1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "Thumb2InstrInfo.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/PseudoSourceValue.h"
24 #include "llvm/ADT/SmallVector.h"
25 #include "llvm/Support/CommandLine.h"
30 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
31 cl::desc("Use old-style Thumb2 if-conversion heuristics"),
34 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
35 : ARMBaseInstrInfo(STI), RI(*this, STI) {
38 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
44 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
45 MachineBasicBlock *NewDest) const {
46 MachineBasicBlock *MBB = Tail->getParent();
47 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
48 if (!AFI->hasITBlocks()) {
49 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
53 // If the first instruction of Tail is predicated, we may have to update
54 // the IT instruction.
56 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
57 MachineBasicBlock::iterator MBBI = Tail;
59 // Expecting at least the t2IT instruction before it.
62 // Actually replace the tail.
63 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
66 if (CC != ARMCC::AL) {
67 MachineBasicBlock::iterator E = MBB->begin();
68 unsigned Count = 4; // At most 4 instructions in an IT block.
69 while (Count && MBBI != E) {
70 if (MBBI->isDebugValue()) {
74 if (MBBI->getOpcode() == ARM::t2IT) {
75 unsigned Mask = MBBI->getOperand(1).getImm();
77 MBBI->eraseFromParent();
79 unsigned MaskOn = 1 << Count;
80 unsigned MaskOff = ~(MaskOn - 1);
81 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
89 // Ctrl flow can reach here if branch folding is run before IT block
95 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
96 MachineBasicBlock::iterator MBBI) const {
97 while (MBBI->isDebugValue()) {
99 if (MBBI == MBB.end())
103 unsigned PredReg = 0;
104 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
107 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator I, DebugLoc DL,
109 unsigned DestReg, unsigned SrcReg,
110 bool KillSrc) const {
111 // Handle SPR, DPR, and QPR copies.
112 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
113 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
115 bool tDest = ARM::tGPRRegClass.contains(DestReg);
116 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
117 unsigned Opc = ARM::tMOVgpr2gpr;
121 Opc = ARM::tMOVtgpr2gpr;
123 Opc = ARM::tMOVgpr2tgpr;
125 BuildMI(MBB, I, DL, get(Opc), DestReg)
126 .addReg(SrcReg, getKillRegState(KillSrc));
129 void Thumb2InstrInfo::
130 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
131 unsigned SrcReg, bool isKill, int FI,
132 const TargetRegisterClass *RC,
133 const TargetRegisterInfo *TRI) const {
134 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
135 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
137 if (I != MBB.end()) DL = I->getDebugLoc();
139 MachineFunction &MF = *MBB.getParent();
140 MachineFrameInfo &MFI = *MF.getFrameInfo();
141 MachineMemOperand *MMO =
142 MF.getMachineMemOperand(
143 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
144 MachineMemOperand::MOStore,
145 MFI.getObjectSize(FI),
146 MFI.getObjectAlignment(FI));
147 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
148 .addReg(SrcReg, getKillRegState(isKill))
149 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
153 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
156 void Thumb2InstrInfo::
157 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
158 unsigned DestReg, int FI,
159 const TargetRegisterClass *RC,
160 const TargetRegisterInfo *TRI) const {
161 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
162 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
164 if (I != MBB.end()) DL = I->getDebugLoc();
166 MachineFunction &MF = *MBB.getParent();
167 MachineFrameInfo &MFI = *MF.getFrameInfo();
168 MachineMemOperand *MMO =
169 MF.getMachineMemOperand(
170 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
171 MachineMemOperand::MOLoad,
172 MFI.getObjectSize(FI),
173 MFI.getObjectAlignment(FI));
174 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
175 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
179 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
182 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
183 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
184 unsigned DestReg, unsigned BaseReg, int NumBytes,
185 ARMCC::CondCodes Pred, unsigned PredReg,
186 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
187 bool isSub = NumBytes < 0;
188 if (isSub) NumBytes = -NumBytes;
190 // If profitable, use a movw or movt to materialize the offset.
191 // FIXME: Use the scavenger to grab a scratch register.
192 if (DestReg != ARM::SP && DestReg != BaseReg &&
194 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
196 if (NumBytes < 65536) {
197 // Use a movw to materialize the 16-bit constant.
198 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
200 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
202 } else if ((NumBytes & 0xffff) == 0) {
203 // Use a movt to materialize the 32-bit constant.
204 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
206 .addImm(NumBytes >> 16)
207 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
213 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
214 .addReg(BaseReg, RegState::Kill)
215 .addReg(DestReg, RegState::Kill)
216 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
217 .setMIFlags(MIFlags);
219 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
220 .addReg(DestReg, RegState::Kill)
221 .addReg(BaseReg, RegState::Kill)
222 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
223 .setMIFlags(MIFlags);
230 unsigned ThisVal = NumBytes;
232 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
233 // mov sp, rn. Note t2MOVr cannot be used.
234 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg)
235 .addReg(BaseReg).setMIFlags(MIFlags);
240 bool HasCCOut = true;
241 if (BaseReg == ARM::SP) {
243 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
244 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
245 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
246 // FIXME: Fix Thumb1 immediate encoding.
247 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
248 .addReg(BaseReg).addImm(ThisVal/4).setMIFlags(MIFlags);
253 // sub rd, sp, so_imm
254 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
255 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
258 // FIXME: Move this to ARMAddressingModes.h?
259 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
260 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
261 NumBytes &= ~ThisVal;
262 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
263 "Bit extraction didn't work?");
266 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
267 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
268 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
270 } else if (ThisVal < 4096) {
271 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
275 // FIXME: Move this to ARMAddressingModes.h?
276 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
277 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
278 NumBytes &= ~ThisVal;
279 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
280 "Bit extraction didn't work?");
284 // Build the new ADD / SUB.
285 MachineInstrBuilder MIB =
286 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
287 .addReg(BaseReg, RegState::Kill)
288 .addImm(ThisVal)).setMIFlags(MIFlags);
297 negativeOffsetOpcode(unsigned opcode)
300 case ARM::t2LDRi12: return ARM::t2LDRi8;
301 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
302 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
303 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
304 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
305 case ARM::t2STRi12: return ARM::t2STRi8;
306 case ARM::t2STRBi12: return ARM::t2STRBi8;
307 case ARM::t2STRHi12: return ARM::t2STRHi8;
327 positiveOffsetOpcode(unsigned opcode)
330 case ARM::t2LDRi8: return ARM::t2LDRi12;
331 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
332 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
333 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
334 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
335 case ARM::t2STRi8: return ARM::t2STRi12;
336 case ARM::t2STRBi8: return ARM::t2STRBi12;
337 case ARM::t2STRHi8: return ARM::t2STRHi12;
342 case ARM::t2LDRSHi12:
343 case ARM::t2LDRSBi12:
357 immediateOffsetOpcode(unsigned opcode)
360 case ARM::t2LDRs: return ARM::t2LDRi12;
361 case ARM::t2LDRHs: return ARM::t2LDRHi12;
362 case ARM::t2LDRBs: return ARM::t2LDRBi12;
363 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
364 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
365 case ARM::t2STRs: return ARM::t2STRi12;
366 case ARM::t2STRBs: return ARM::t2STRBi12;
367 case ARM::t2STRHs: return ARM::t2STRHi12;
372 case ARM::t2LDRSHi12:
373 case ARM::t2LDRSBi12:
394 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
395 unsigned FrameReg, int &Offset,
396 const ARMBaseInstrInfo &TII) {
397 unsigned Opcode = MI.getOpcode();
398 const MCInstrDesc &Desc = MI.getDesc();
399 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
402 // Memory operands in inline assembly always use AddrModeT2_i12.
403 if (Opcode == ARM::INLINEASM)
404 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
406 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
407 Offset += MI.getOperand(FrameRegIdx+1).getImm();
410 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
411 // Turn it into a move.
412 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
413 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
414 // Remove offset and remaining explicit predicate operands.
415 do MI.RemoveOperand(FrameRegIdx+1);
416 while (MI.getNumOperands() > FrameRegIdx+1 &&
417 (!MI.getOperand(FrameRegIdx+1).isReg() ||
418 !MI.getOperand(FrameRegIdx+1).isImm()));
422 bool isSP = FrameReg == ARM::SP;
423 bool HasCCOut = Opcode != ARM::t2ADDri12;
428 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
430 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
433 // Common case: small offset, fits into instruction.
434 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
435 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
436 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
437 // Add cc_out operand if the original instruction did not have one.
439 MI.addOperand(MachineOperand::CreateReg(0, false));
443 // Another common case: imm12.
445 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
446 unsigned NewOpc = isSP
447 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
448 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
449 MI.setDesc(TII.get(NewOpc));
450 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
451 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
452 // Remove the cc_out operand.
454 MI.RemoveOperand(MI.getNumOperands()-1);
459 // Otherwise, extract 8 adjacent bits from the immediate into this
461 unsigned RotAmt = CountLeadingZeros_32(Offset);
462 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
464 // We will handle these bits from offset, clear them.
465 Offset &= ~ThisImmVal;
467 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
468 "Bit extraction didn't work?");
469 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
470 // Add cc_out operand if the original instruction did not have one.
472 MI.addOperand(MachineOperand::CreateReg(0, false));
476 // AddrMode4 and AddrMode6 cannot handle any offset.
477 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
480 // AddrModeT2_so cannot handle any offset. If there is no offset
481 // register then we change to an immediate version.
482 unsigned NewOpc = Opcode;
483 if (AddrMode == ARMII::AddrModeT2_so) {
484 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
485 if (OffsetReg != 0) {
486 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
490 MI.RemoveOperand(FrameRegIdx+1);
491 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
492 NewOpc = immediateOffsetOpcode(Opcode);
493 AddrMode = ARMII::AddrModeT2_i12;
496 unsigned NumBits = 0;
498 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
499 // i8 supports only negative, and i12 supports only positive, so
500 // based on Offset sign convert Opcode to the appropriate
502 Offset += MI.getOperand(FrameRegIdx+1).getImm();
504 NewOpc = negativeOffsetOpcode(Opcode);
509 NewOpc = positiveOffsetOpcode(Opcode);
512 } else if (AddrMode == ARMII::AddrMode5) {
514 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
515 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
516 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
520 Offset += InstrOffs * 4;
521 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
527 llvm_unreachable("Unsupported addressing mode!");
530 if (NewOpc != Opcode)
531 MI.setDesc(TII.get(NewOpc));
533 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
535 // Attempt to fold address computation
536 // Common case: small offset, fits into instruction.
537 int ImmedOffset = Offset / Scale;
538 unsigned Mask = (1 << NumBits) - 1;
539 if ((unsigned)Offset <= Mask * Scale) {
540 // Replace the FrameIndex with fp/sp
541 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
543 if (AddrMode == ARMII::AddrMode5)
544 // FIXME: Not consistent.
545 ImmedOffset |= 1 << NumBits;
547 ImmedOffset = -ImmedOffset;
549 ImmOp.ChangeToImmediate(ImmedOffset);
554 // Otherwise, offset doesn't fit. Pull in what we can to simplify
555 ImmedOffset = ImmedOffset & Mask;
557 if (AddrMode == ARMII::AddrMode5)
558 // FIXME: Not consistent.
559 ImmedOffset |= 1 << NumBits;
561 ImmedOffset = -ImmedOffset;
562 if (ImmedOffset == 0)
563 // Change the opcode back if the encoded offset is zero.
564 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
567 ImmOp.ChangeToImmediate(ImmedOffset);
568 Offset &= ~(Mask*Scale);
571 Offset = (isSub) ? -Offset : Offset;
575 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
576 /// two-addrss instruction inserted by two-address pass.
578 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
580 const TargetRegisterInfo &TRI) const {
581 if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
582 SrcMI->getOperand(1).isKill())
585 unsigned PredReg = 0;
586 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
587 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
590 // Schedule the copy so it doesn't come between previous instructions
591 // and UseMI which can form an IT block.
592 unsigned SrcReg = SrcMI->getOperand(1).getReg();
593 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
594 MachineBasicBlock *MBB = UseMI->getParent();
595 MachineBasicBlock::iterator MBBI = SrcMI;
596 unsigned NumInsts = 0;
597 while (--MBBI != MBB->begin()) {
598 if (MBBI->isDebugValue())
601 MachineInstr *NMI = &*MBBI;
602 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
603 if (!(NCC == CC || NCC == OCC) ||
604 NMI->modifiesRegister(SrcReg, &TRI) ||
605 NMI->definesRegister(ARM::CPSR))
608 // Too many in a row!
614 MBB->insert(++MBBI, SrcMI);
619 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
620 unsigned Opc = MI->getOpcode();
621 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
623 return llvm::getInstrPredicate(MI, PredReg);