1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "Thumb2InstrInfo.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineMemOperand.h"
24 #include "llvm/CodeGen/PseudoSourceValue.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/Support/CommandLine.h"
31 OldT2IfCvt("old-thumb2-ifcvt", cl::Hidden,
32 cl::desc("Use old-style Thumb2 if-conversion heuristics"),
35 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
36 : ARMBaseInstrInfo(STI), RI(*this, STI) {
39 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
45 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
46 MachineBasicBlock *NewDest) const {
47 MachineBasicBlock *MBB = Tail->getParent();
48 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
49 if (!AFI->hasITBlocks()) {
50 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
54 // If the first instruction of Tail is predicated, we may have to update
55 // the IT instruction.
57 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
58 MachineBasicBlock::iterator MBBI = Tail;
60 // Expecting at least the t2IT instruction before it.
63 // Actually replace the tail.
64 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
67 if (CC != ARMCC::AL) {
68 MachineBasicBlock::iterator E = MBB->begin();
69 unsigned Count = 4; // At most 4 instructions in an IT block.
70 while (Count && MBBI != E) {
71 if (MBBI->isDebugValue()) {
75 if (MBBI->getOpcode() == ARM::t2IT) {
76 unsigned Mask = MBBI->getOperand(1).getImm();
78 MBBI->eraseFromParent();
80 unsigned MaskOn = 1 << Count;
81 unsigned MaskOff = ~(MaskOn - 1);
82 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
90 // Ctrl flow can reach here if branch folding is run before IT block
96 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
97 MachineBasicBlock::iterator MBBI) const {
98 while (MBBI->isDebugValue())
101 unsigned PredReg = 0;
102 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
105 void Thumb2InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
106 MachineBasicBlock::iterator I, DebugLoc DL,
107 unsigned DestReg, unsigned SrcReg,
108 bool KillSrc) const {
109 // Handle SPR, DPR, and QPR copies.
110 if (!ARM::GPRRegClass.contains(DestReg, SrcReg))
111 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc);
113 bool tDest = ARM::tGPRRegClass.contains(DestReg);
114 bool tSrc = ARM::tGPRRegClass.contains(SrcReg);
115 unsigned Opc = ARM::tMOVgpr2gpr;
119 Opc = ARM::tMOVtgpr2gpr;
121 Opc = ARM::tMOVgpr2tgpr;
123 BuildMI(MBB, I, DL, get(Opc), DestReg)
124 .addReg(SrcReg, getKillRegState(KillSrc));
127 void Thumb2InstrInfo::
128 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
129 unsigned SrcReg, bool isKill, int FI,
130 const TargetRegisterClass *RC,
131 const TargetRegisterInfo *TRI) const {
132 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
133 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
135 if (I != MBB.end()) DL = I->getDebugLoc();
137 MachineFunction &MF = *MBB.getParent();
138 MachineFrameInfo &MFI = *MF.getFrameInfo();
139 MachineMemOperand *MMO =
140 MF.getMachineMemOperand(
141 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
142 MachineMemOperand::MOStore,
143 MFI.getObjectSize(FI),
144 MFI.getObjectAlignment(FI));
145 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
146 .addReg(SrcReg, getKillRegState(isKill))
147 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
151 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
154 void Thumb2InstrInfo::
155 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
156 unsigned DestReg, int FI,
157 const TargetRegisterClass *RC,
158 const TargetRegisterInfo *TRI) const {
159 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
160 RC == ARM::tcGPRRegisterClass || RC == ARM::rGPRRegisterClass) {
162 if (I != MBB.end()) DL = I->getDebugLoc();
164 MachineFunction &MF = *MBB.getParent();
165 MachineFrameInfo &MFI = *MF.getFrameInfo();
166 MachineMemOperand *MMO =
167 MF.getMachineMemOperand(
168 MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
169 MachineMemOperand::MOLoad,
170 MFI.getObjectSize(FI),
171 MFI.getObjectAlignment(FI));
172 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
173 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
177 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
180 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
181 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
182 unsigned DestReg, unsigned BaseReg, int NumBytes,
183 ARMCC::CondCodes Pred, unsigned PredReg,
184 const ARMBaseInstrInfo &TII) {
185 bool isSub = NumBytes < 0;
186 if (isSub) NumBytes = -NumBytes;
188 // If profitable, use a movw or movt to materialize the offset.
189 // FIXME: Use the scavenger to grab a scratch register.
190 if (DestReg != ARM::SP && DestReg != BaseReg &&
192 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
194 if (NumBytes < 65536) {
195 // Use a movw to materialize the 16-bit constant.
196 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
198 .addImm((unsigned)Pred).addReg(PredReg);
200 } else if ((NumBytes & 0xffff) == 0) {
201 // Use a movt to materialize the 32-bit constant.
202 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
204 .addImm(NumBytes >> 16)
205 .addImm((unsigned)Pred).addReg(PredReg);
211 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
212 .addReg(BaseReg, RegState::Kill)
213 .addReg(DestReg, RegState::Kill)
214 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
216 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
217 .addReg(DestReg, RegState::Kill)
218 .addReg(BaseReg, RegState::Kill)
219 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
226 unsigned ThisVal = NumBytes;
228 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
229 // mov sp, rn. Note t2MOVr cannot be used.
230 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
235 bool HasCCOut = true;
236 if (BaseReg == ARM::SP) {
238 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
239 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
240 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
241 // FIXME: Fix Thumb1 immediate encoding.
242 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
243 .addReg(BaseReg).addImm(ThisVal/4);
248 // sub rd, sp, so_imm
249 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
250 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
253 // FIXME: Move this to ARMAddressingModes.h?
254 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
255 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
256 NumBytes &= ~ThisVal;
257 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
258 "Bit extraction didn't work?");
261 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
262 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
263 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
265 } else if (ThisVal < 4096) {
266 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
270 // FIXME: Move this to ARMAddressingModes.h?
271 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
272 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
273 NumBytes &= ~ThisVal;
274 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
275 "Bit extraction didn't work?");
279 // Build the new ADD / SUB.
280 MachineInstrBuilder MIB =
281 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
282 .addReg(BaseReg, RegState::Kill)
292 negativeOffsetOpcode(unsigned opcode)
295 case ARM::t2LDRi12: return ARM::t2LDRi8;
296 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
297 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
298 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
299 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
300 case ARM::t2STRi12: return ARM::t2STRi8;
301 case ARM::t2STRBi12: return ARM::t2STRBi8;
302 case ARM::t2STRHi12: return ARM::t2STRHi8;
322 positiveOffsetOpcode(unsigned opcode)
325 case ARM::t2LDRi8: return ARM::t2LDRi12;
326 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
327 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
328 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
329 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
330 case ARM::t2STRi8: return ARM::t2STRi12;
331 case ARM::t2STRBi8: return ARM::t2STRBi12;
332 case ARM::t2STRHi8: return ARM::t2STRHi12;
337 case ARM::t2LDRSHi12:
338 case ARM::t2LDRSBi12:
352 immediateOffsetOpcode(unsigned opcode)
355 case ARM::t2LDRs: return ARM::t2LDRi12;
356 case ARM::t2LDRHs: return ARM::t2LDRHi12;
357 case ARM::t2LDRBs: return ARM::t2LDRBi12;
358 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
359 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
360 case ARM::t2STRs: return ARM::t2STRi12;
361 case ARM::t2STRBs: return ARM::t2STRBi12;
362 case ARM::t2STRHs: return ARM::t2STRHi12;
367 case ARM::t2LDRSHi12:
368 case ARM::t2LDRSBi12:
389 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
390 unsigned FrameReg, int &Offset,
391 const ARMBaseInstrInfo &TII) {
392 unsigned Opcode = MI.getOpcode();
393 const TargetInstrDesc &Desc = MI.getDesc();
394 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
397 // Memory operands in inline assembly always use AddrModeT2_i12.
398 if (Opcode == ARM::INLINEASM)
399 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
401 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
402 Offset += MI.getOperand(FrameRegIdx+1).getImm();
405 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
406 // Turn it into a move.
407 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
408 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
409 // Remove offset and remaining explicit predicate operands.
410 do MI.RemoveOperand(FrameRegIdx+1);
411 while (MI.getNumOperands() > FrameRegIdx+1 &&
412 (!MI.getOperand(FrameRegIdx+1).isReg() ||
413 !MI.getOperand(FrameRegIdx+1).isImm()));
417 bool isSP = FrameReg == ARM::SP;
418 bool HasCCOut = Opcode != ARM::t2ADDri12;
423 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
425 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
428 // Common case: small offset, fits into instruction.
429 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
430 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
431 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
432 // Add cc_out operand if the original instruction did not have one.
434 MI.addOperand(MachineOperand::CreateReg(0, false));
438 // Another common case: imm12.
440 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
441 unsigned NewOpc = isSP
442 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
443 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
444 MI.setDesc(TII.get(NewOpc));
445 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
446 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
447 // Remove the cc_out operand.
449 MI.RemoveOperand(MI.getNumOperands()-1);
454 // Otherwise, extract 8 adjacent bits from the immediate into this
456 unsigned RotAmt = CountLeadingZeros_32(Offset);
457 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
459 // We will handle these bits from offset, clear them.
460 Offset &= ~ThisImmVal;
462 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
463 "Bit extraction didn't work?");
464 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
465 // Add cc_out operand if the original instruction did not have one.
467 MI.addOperand(MachineOperand::CreateReg(0, false));
471 // AddrMode4 and AddrMode6 cannot handle any offset.
472 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
475 // AddrModeT2_so cannot handle any offset. If there is no offset
476 // register then we change to an immediate version.
477 unsigned NewOpc = Opcode;
478 if (AddrMode == ARMII::AddrModeT2_so) {
479 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
480 if (OffsetReg != 0) {
481 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
485 MI.RemoveOperand(FrameRegIdx+1);
486 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
487 NewOpc = immediateOffsetOpcode(Opcode);
488 AddrMode = ARMII::AddrModeT2_i12;
491 unsigned NumBits = 0;
493 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
494 // i8 supports only negative, and i12 supports only positive, so
495 // based on Offset sign convert Opcode to the appropriate
497 Offset += MI.getOperand(FrameRegIdx+1).getImm();
499 NewOpc = negativeOffsetOpcode(Opcode);
504 NewOpc = positiveOffsetOpcode(Opcode);
507 } else if (AddrMode == ARMII::AddrMode5) {
509 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
510 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
511 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
515 Offset += InstrOffs * 4;
516 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
522 llvm_unreachable("Unsupported addressing mode!");
525 if (NewOpc != Opcode)
526 MI.setDesc(TII.get(NewOpc));
528 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
530 // Attempt to fold address computation
531 // Common case: small offset, fits into instruction.
532 int ImmedOffset = Offset / Scale;
533 unsigned Mask = (1 << NumBits) - 1;
534 if ((unsigned)Offset <= Mask * Scale) {
535 // Replace the FrameIndex with fp/sp
536 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
538 if (AddrMode == ARMII::AddrMode5)
539 // FIXME: Not consistent.
540 ImmedOffset |= 1 << NumBits;
542 ImmedOffset = -ImmedOffset;
544 ImmOp.ChangeToImmediate(ImmedOffset);
549 // Otherwise, offset doesn't fit. Pull in what we can to simplify
550 ImmedOffset = ImmedOffset & Mask;
552 if (AddrMode == ARMII::AddrMode5)
553 // FIXME: Not consistent.
554 ImmedOffset |= 1 << NumBits;
556 ImmedOffset = -ImmedOffset;
557 if (ImmedOffset == 0)
558 // Change the opcode back if the encoded offset is zero.
559 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
562 ImmOp.ChangeToImmediate(ImmedOffset);
563 Offset &= ~(Mask*Scale);
566 Offset = (isSub) ? -Offset : Offset;
570 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
571 /// two-addrss instruction inserted by two-address pass.
573 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
575 const TargetRegisterInfo &TRI) const {
576 if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
577 SrcMI->getOperand(1).isKill())
580 unsigned PredReg = 0;
581 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
582 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
585 // Schedule the copy so it doesn't come between previous instructions
586 // and UseMI which can form an IT block.
587 unsigned SrcReg = SrcMI->getOperand(1).getReg();
588 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
589 MachineBasicBlock *MBB = UseMI->getParent();
590 MachineBasicBlock::iterator MBBI = SrcMI;
591 unsigned NumInsts = 0;
592 while (--MBBI != MBB->begin()) {
593 if (MBBI->isDebugValue())
596 MachineInstr *NMI = &*MBBI;
597 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
598 if (!(NCC == CC || NCC == OCC) ||
599 NMI->modifiesRegister(SrcReg, &TRI) ||
600 NMI->definesRegister(ARM::CPSR))
603 // Too many in a row!
609 MBB->insert(++MBBI, SrcMI);
614 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
615 unsigned Opc = MI->getOpcode();
616 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
618 return llvm::getInstrPredicate(MI, PredReg);