1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMInstrInfo.h"
16 #include "ARMGenInstrInfo.inc"
17 #include "ARMMachineFunctionInfo.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/ADT/SmallVector.h"
21 #include "Thumb2InstrInfo.h"
25 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
26 : ARMBaseInstrInfo(STI), RI(*this, STI) {
29 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
34 unsigned Thumb2InstrInfo::getOpcode(ARMII::Op Op) const {
36 case ARMII::ADDri: return ARM::t2ADDri;
37 case ARMII::ADDrs: return ARM::t2ADDrs;
38 case ARMII::ADDrr: return ARM::t2ADDrr;
39 case ARMII::B: return ARM::t2B;
40 case ARMII::Bcc: return ARM::t2Bcc;
41 case ARMII::BX_RET: return ARM::tBX_RET;
42 case ARMII::LDRri: return ARM::t2LDRi12;
43 case ARMII::MOVr: return ARM::t2MOVr;
44 case ARMII::STRri: return ARM::t2STRi12;
45 case ARMII::SUBri: return ARM::t2SUBri;
46 case ARMII::SUBrs: return ARM::t2SUBrs;
47 case ARMII::SUBrr: return ARM::t2SUBrr;
56 Thumb2InstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
57 if (MBB.empty()) return false;
59 switch (MBB.back().getOpcode()) {
61 case ARM::t2B: // Uncond branch.
62 case ARM::t2BR_JT: // Jumptable branch.
63 case ARM::tBR_JTr: // Jumptable branch (16-bit version).
65 case ARM::tBX_RET_vararg:
77 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator I,
79 unsigned DestReg, unsigned SrcReg,
80 const TargetRegisterClass *DestRC,
81 const TargetRegisterClass *SrcRC) const {
82 DebugLoc DL = DebugLoc::getUnknownLoc();
83 if (I != MBB.end()) DL = I->getDebugLoc();
85 if (DestRC == ARM::GPRRegisterClass &&
86 SrcRC == ARM::GPRRegisterClass) {
87 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2MOVr),
88 DestReg).addReg(SrcReg)));
90 } else if (DestRC == ARM::GPRRegisterClass &&
91 SrcRC == ARM::tGPRRegisterClass) {
92 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
94 } else if (DestRC == ARM::tGPRRegisterClass &&
95 SrcRC == ARM::GPRRegisterClass) {
96 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
100 // Handle SPR, DPR, and QPR copies.
101 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC, SrcRC);
104 void Thumb2InstrInfo::
105 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
106 unsigned SrcReg, bool isKill, int FI,
107 const TargetRegisterClass *RC) const {
108 DebugLoc DL = DebugLoc::getUnknownLoc();
109 if (I != MBB.end()) DL = I->getDebugLoc();
111 if (RC == ARM::GPRRegisterClass) {
112 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
113 .addReg(SrcReg, getKillRegState(isKill))
114 .addFrameIndex(FI).addImm(0));
118 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC);
121 void Thumb2InstrInfo::
122 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
123 unsigned DestReg, int FI,
124 const TargetRegisterClass *RC) const {
125 DebugLoc DL = DebugLoc::getUnknownLoc();
126 if (I != MBB.end()) DL = I->getDebugLoc();
128 if (RC == ARM::GPRRegisterClass) {
129 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
130 .addFrameIndex(FI).addImm(0));
134 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC);