1 //===- Thumb2InstrInfo.cpp - Thumb-2 Instruction Information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "Thumb2InstrInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMAddressingModes.h"
18 #include "ARMGenInstrInfo.inc"
19 #include "ARMMachineFunctionInfo.h"
20 #include "Thumb2HazardRecognizer.h"
21 #include "Thumb2InstrInfo.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineMemOperand.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/Support/CommandLine.h"
31 static cl::opt<unsigned>
32 IfCvtLimit("thumb2-ifcvt-limit", cl::Hidden,
33 cl::desc("Thumb2 if-conversion limit (default 3)"),
36 static cl::opt<unsigned>
37 IfCvtDiamondLimit("thumb2-ifcvt-diamond-limit", cl::Hidden,
38 cl::desc("Thumb2 diamond if-conversion limit (default 3)"),
41 Thumb2InstrInfo::Thumb2InstrInfo(const ARMSubtarget &STI)
42 : ARMBaseInstrInfo(STI), RI(*this, STI) {
45 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const {
51 Thumb2InstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
52 MachineBasicBlock *NewDest) const {
53 MachineBasicBlock *MBB = Tail->getParent();
54 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
55 if (!AFI->hasITBlocks()) {
56 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
60 // If the first instruction of Tail is predicated, we may have to update
61 // the IT instruction.
63 ARMCC::CondCodes CC = llvm::getInstrPredicate(Tail, PredReg);
64 MachineBasicBlock::iterator MBBI = Tail;
66 // Expecting at least the t2IT instruction before it.
69 // Actually replace the tail.
70 TargetInstrInfoImpl::ReplaceTailWithBranchTo(Tail, NewDest);
73 if (CC != ARMCC::AL) {
74 MachineBasicBlock::iterator E = MBB->begin();
75 unsigned Count = 4; // At most 4 instructions in an IT block.
76 while (Count && MBBI != E) {
77 if (MBBI->isDebugValue()) {
81 if (MBBI->getOpcode() == ARM::t2IT) {
82 unsigned Mask = MBBI->getOperand(1).getImm();
84 MBBI->eraseFromParent();
86 unsigned MaskOn = 1 << Count;
87 unsigned MaskOff = ~(MaskOn - 1);
88 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
96 // Ctrl flow can reach here if branch folding is run before IT block
102 Thumb2InstrInfo::isLegalToSplitMBBAt(MachineBasicBlock &MBB,
103 MachineBasicBlock::iterator MBBI) const {
104 unsigned PredReg = 0;
105 return llvm::getITInstrPredicate(MBBI, PredReg) == ARMCC::AL;
108 bool Thumb2InstrInfo::isProfitableToIfCvt(MachineBasicBlock &MBB,
109 unsigned NumInstrs) const {
110 return NumInstrs && NumInstrs <= IfCvtLimit;
113 bool Thumb2InstrInfo::
114 isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
115 MachineBasicBlock &FMBB, unsigned NumF) const {
116 // FIXME: Catch optimization such as:
119 return NumT && NumF &&
120 NumT <= (IfCvtDiamondLimit) && NumF <= (IfCvtDiamondLimit);
124 Thumb2InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
125 MachineBasicBlock::iterator I,
126 unsigned DestReg, unsigned SrcReg,
127 const TargetRegisterClass *DestRC,
128 const TargetRegisterClass *SrcRC,
130 if (DestRC == ARM::GPRRegisterClass || DestRC == ARM::tcGPRRegisterClass) {
131 if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
132 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2gpr), DestReg).addReg(SrcReg);
134 } else if (SrcRC == ARM::tGPRRegisterClass) {
135 BuildMI(MBB, I, DL, get(ARM::tMOVtgpr2gpr), DestReg).addReg(SrcReg);
138 } else if (DestRC == ARM::tGPRRegisterClass) {
139 if (SrcRC == ARM::GPRRegisterClass || SrcRC == ARM::tcGPRRegisterClass) {
140 BuildMI(MBB, I, DL, get(ARM::tMOVgpr2tgpr), DestReg).addReg(SrcReg);
142 } else if (SrcRC == ARM::tGPRRegisterClass) {
143 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg).addReg(SrcReg);
148 // Handle SPR, DPR, and QPR copies.
149 return ARMBaseInstrInfo::copyRegToReg(MBB, I, DestReg, SrcReg, DestRC,
153 void Thumb2InstrInfo::
154 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
155 unsigned SrcReg, bool isKill, int FI,
156 const TargetRegisterClass *RC,
157 const TargetRegisterInfo *TRI) const {
158 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
159 RC == ARM::tcGPRRegisterClass) {
161 if (I != MBB.end()) DL = I->getDebugLoc();
163 MachineFunction &MF = *MBB.getParent();
164 MachineFrameInfo &MFI = *MF.getFrameInfo();
165 MachineMemOperand *MMO =
166 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
167 MachineMemOperand::MOStore, 0,
168 MFI.getObjectSize(FI),
169 MFI.getObjectAlignment(FI));
170 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2STRi12))
171 .addReg(SrcReg, getKillRegState(isKill))
172 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
176 ARMBaseInstrInfo::storeRegToStackSlot(MBB, I, SrcReg, isKill, FI, RC, TRI);
179 void Thumb2InstrInfo::
180 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
181 unsigned DestReg, int FI,
182 const TargetRegisterClass *RC,
183 const TargetRegisterInfo *TRI) const {
184 if (RC == ARM::GPRRegisterClass || RC == ARM::tGPRRegisterClass ||
185 RC == ARM::tcGPRRegisterClass) {
187 if (I != MBB.end()) DL = I->getDebugLoc();
189 MachineFunction &MF = *MBB.getParent();
190 MachineFrameInfo &MFI = *MF.getFrameInfo();
191 MachineMemOperand *MMO =
192 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FI),
193 MachineMemOperand::MOLoad, 0,
194 MFI.getObjectSize(FI),
195 MFI.getObjectAlignment(FI));
196 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
197 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
201 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI);
204 ScheduleHazardRecognizer *Thumb2InstrInfo::
205 CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const {
206 return (ScheduleHazardRecognizer *)new Thumb2HazardRecognizer(II);
209 void llvm::emitT2RegPlusImmediate(MachineBasicBlock &MBB,
210 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
211 unsigned DestReg, unsigned BaseReg, int NumBytes,
212 ARMCC::CondCodes Pred, unsigned PredReg,
213 const ARMBaseInstrInfo &TII) {
214 bool isSub = NumBytes < 0;
215 if (isSub) NumBytes = -NumBytes;
217 // If profitable, use a movw or movt to materialize the offset.
218 // FIXME: Use the scavenger to grab a scratch register.
219 if (DestReg != ARM::SP && DestReg != BaseReg &&
221 ARM_AM::getT2SOImmVal(NumBytes) == -1) {
223 if (NumBytes < 65536) {
224 // Use a movw to materialize the 16-bit constant.
225 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
227 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
229 } else if ((NumBytes & 0xffff) == 0) {
230 // Use a movt to materialize the 32-bit constant.
231 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
233 .addImm(NumBytes >> 16)
234 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
240 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
241 .addReg(BaseReg, RegState::Kill)
242 .addReg(DestReg, RegState::Kill)
243 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
245 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
246 .addReg(DestReg, RegState::Kill)
247 .addReg(BaseReg, RegState::Kill)
248 .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
255 unsigned ThisVal = NumBytes;
257 if (DestReg == ARM::SP && BaseReg != ARM::SP) {
258 // mov sp, rn. Note t2MOVr cannot be used.
259 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVgpr2gpr),DestReg).addReg(BaseReg);
264 bool HasCCOut = true;
265 if (BaseReg == ARM::SP) {
267 if (DestReg == ARM::SP && (ThisVal < ((1 << 7)-1) * 4)) {
268 assert((ThisVal & 3) == 0 && "Stack update is not multiple of 4?");
269 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
270 // FIXME: Fix Thumb1 immediate encoding.
271 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
272 .addReg(BaseReg).addImm(ThisVal/4);
277 // sub rd, sp, so_imm
278 Opc = isSub ? ARM::t2SUBrSPi : ARM::t2ADDrSPi;
279 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
282 // FIXME: Move this to ARMAddressingModes.h?
283 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
284 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
285 NumBytes &= ~ThisVal;
286 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
287 "Bit extraction didn't work?");
290 assert(DestReg != ARM::SP && BaseReg != ARM::SP);
291 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri;
292 if (ARM_AM::getT2SOImmVal(NumBytes) != -1) {
294 } else if (ThisVal < 4096) {
295 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12;
299 // FIXME: Move this to ARMAddressingModes.h?
300 unsigned RotAmt = CountLeadingZeros_32(ThisVal);
301 ThisVal = ThisVal & ARM_AM::rotr32(0xff000000U, RotAmt);
302 NumBytes &= ~ThisVal;
303 assert(ARM_AM::getT2SOImmVal(ThisVal) != -1 &&
304 "Bit extraction didn't work?");
308 // Build the new ADD / SUB.
309 MachineInstrBuilder MIB =
310 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
311 .addReg(BaseReg, RegState::Kill)
321 negativeOffsetOpcode(unsigned opcode)
324 case ARM::t2LDRi12: return ARM::t2LDRi8;
325 case ARM::t2LDRHi12: return ARM::t2LDRHi8;
326 case ARM::t2LDRBi12: return ARM::t2LDRBi8;
327 case ARM::t2LDRSHi12: return ARM::t2LDRSHi8;
328 case ARM::t2LDRSBi12: return ARM::t2LDRSBi8;
329 case ARM::t2STRi12: return ARM::t2STRi8;
330 case ARM::t2STRBi12: return ARM::t2STRBi8;
331 case ARM::t2STRHi12: return ARM::t2STRHi8;
351 positiveOffsetOpcode(unsigned opcode)
354 case ARM::t2LDRi8: return ARM::t2LDRi12;
355 case ARM::t2LDRHi8: return ARM::t2LDRHi12;
356 case ARM::t2LDRBi8: return ARM::t2LDRBi12;
357 case ARM::t2LDRSHi8: return ARM::t2LDRSHi12;
358 case ARM::t2LDRSBi8: return ARM::t2LDRSBi12;
359 case ARM::t2STRi8: return ARM::t2STRi12;
360 case ARM::t2STRBi8: return ARM::t2STRBi12;
361 case ARM::t2STRHi8: return ARM::t2STRHi12;
366 case ARM::t2LDRSHi12:
367 case ARM::t2LDRSBi12:
381 immediateOffsetOpcode(unsigned opcode)
384 case ARM::t2LDRs: return ARM::t2LDRi12;
385 case ARM::t2LDRHs: return ARM::t2LDRHi12;
386 case ARM::t2LDRBs: return ARM::t2LDRBi12;
387 case ARM::t2LDRSHs: return ARM::t2LDRSHi12;
388 case ARM::t2LDRSBs: return ARM::t2LDRSBi12;
389 case ARM::t2STRs: return ARM::t2STRi12;
390 case ARM::t2STRBs: return ARM::t2STRBi12;
391 case ARM::t2STRHs: return ARM::t2STRHi12;
396 case ARM::t2LDRSHi12:
397 case ARM::t2LDRSBi12:
418 bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
419 unsigned FrameReg, int &Offset,
420 const ARMBaseInstrInfo &TII) {
421 unsigned Opcode = MI.getOpcode();
422 const TargetInstrDesc &Desc = MI.getDesc();
423 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
426 // Memory operands in inline assembly always use AddrModeT2_i12.
427 if (Opcode == ARM::INLINEASM)
428 AddrMode = ARMII::AddrModeT2_i12; // FIXME. mode for thumb2?
430 if (Opcode == ARM::t2ADDri || Opcode == ARM::t2ADDri12) {
431 Offset += MI.getOperand(FrameRegIdx+1).getImm();
434 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) {
435 // Turn it into a move.
436 MI.setDesc(TII.get(ARM::tMOVgpr2gpr));
437 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
438 // Remove offset and remaining explicit predicate operands.
439 do MI.RemoveOperand(FrameRegIdx+1);
440 while (MI.getNumOperands() > FrameRegIdx+1 &&
441 (!MI.getOperand(FrameRegIdx+1).isReg() ||
442 !MI.getOperand(FrameRegIdx+1).isImm()));
446 bool isSP = FrameReg == ARM::SP;
447 bool HasCCOut = Opcode != ARM::t2ADDri12;
452 MI.setDesc(TII.get(isSP ? ARM::t2SUBrSPi : ARM::t2SUBri));
454 MI.setDesc(TII.get(isSP ? ARM::t2ADDrSPi : ARM::t2ADDri));
457 // Common case: small offset, fits into instruction.
458 if (ARM_AM::getT2SOImmVal(Offset) != -1) {
459 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
460 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
461 // Add cc_out operand if the original instruction did not have one.
463 MI.addOperand(MachineOperand::CreateReg(0, false));
467 // Another common case: imm12.
469 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
470 unsigned NewOpc = isSP
471 ? (isSub ? ARM::t2SUBrSPi12 : ARM::t2ADDrSPi12)
472 : (isSub ? ARM::t2SUBri12 : ARM::t2ADDri12);
473 MI.setDesc(TII.get(NewOpc));
474 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
475 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
476 // Remove the cc_out operand.
478 MI.RemoveOperand(MI.getNumOperands()-1);
483 // Otherwise, extract 8 adjacent bits from the immediate into this
485 unsigned RotAmt = CountLeadingZeros_32(Offset);
486 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xff000000U, RotAmt);
488 // We will handle these bits from offset, clear them.
489 Offset &= ~ThisImmVal;
491 assert(ARM_AM::getT2SOImmVal(ThisImmVal) != -1 &&
492 "Bit extraction didn't work?");
493 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
494 // Add cc_out operand if the original instruction did not have one.
496 MI.addOperand(MachineOperand::CreateReg(0, false));
500 // AddrMode4 and AddrMode6 cannot handle any offset.
501 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
504 // AddrModeT2_so cannot handle any offset. If there is no offset
505 // register then we change to an immediate version.
506 unsigned NewOpc = Opcode;
507 if (AddrMode == ARMII::AddrModeT2_so) {
508 unsigned OffsetReg = MI.getOperand(FrameRegIdx+1).getReg();
509 if (OffsetReg != 0) {
510 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
514 MI.RemoveOperand(FrameRegIdx+1);
515 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(0);
516 NewOpc = immediateOffsetOpcode(Opcode);
517 AddrMode = ARMII::AddrModeT2_i12;
520 unsigned NumBits = 0;
522 if (AddrMode == ARMII::AddrModeT2_i8 || AddrMode == ARMII::AddrModeT2_i12) {
523 // i8 supports only negative, and i12 supports only positive, so
524 // based on Offset sign convert Opcode to the appropriate
526 Offset += MI.getOperand(FrameRegIdx+1).getImm();
528 NewOpc = negativeOffsetOpcode(Opcode);
533 NewOpc = positiveOffsetOpcode(Opcode);
536 } else if (AddrMode == ARMII::AddrMode5) {
538 const MachineOperand &OffOp = MI.getOperand(FrameRegIdx+1);
539 int InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
540 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
544 Offset += InstrOffs * 4;
545 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
551 llvm_unreachable("Unsupported addressing mode!");
554 if (NewOpc != Opcode)
555 MI.setDesc(TII.get(NewOpc));
557 MachineOperand &ImmOp = MI.getOperand(FrameRegIdx+1);
559 // Attempt to fold address computation
560 // Common case: small offset, fits into instruction.
561 int ImmedOffset = Offset / Scale;
562 unsigned Mask = (1 << NumBits) - 1;
563 if ((unsigned)Offset <= Mask * Scale) {
564 // Replace the FrameIndex with fp/sp
565 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
567 if (AddrMode == ARMII::AddrMode5)
568 // FIXME: Not consistent.
569 ImmedOffset |= 1 << NumBits;
571 ImmedOffset = -ImmedOffset;
573 ImmOp.ChangeToImmediate(ImmedOffset);
578 // Otherwise, offset doesn't fit. Pull in what we can to simplify
579 ImmedOffset = ImmedOffset & Mask;
581 if (AddrMode == ARMII::AddrMode5)
582 // FIXME: Not consistent.
583 ImmedOffset |= 1 << NumBits;
585 ImmedOffset = -ImmedOffset;
586 if (ImmedOffset == 0)
587 // Change the opcode back if the encoded offset is zero.
588 MI.setDesc(TII.get(positiveOffsetOpcode(NewOpc)));
591 ImmOp.ChangeToImmediate(ImmedOffset);
592 Offset &= ~(Mask*Scale);
595 Offset = (isSub) ? -Offset : Offset;
599 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
600 /// two-addrss instruction inserted by two-address pass.
602 Thumb2InstrInfo::scheduleTwoAddrSource(MachineInstr *SrcMI,
604 const TargetRegisterInfo &TRI) const {
605 if (SrcMI->getOpcode() != ARM::tMOVgpr2gpr ||
606 SrcMI->getOperand(1).isKill())
609 unsigned PredReg = 0;
610 ARMCC::CondCodes CC = llvm::getInstrPredicate(UseMI, PredReg);
611 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
614 // Schedule the copy so it doesn't come between previous instructions
615 // and UseMI which can form an IT block.
616 unsigned SrcReg = SrcMI->getOperand(1).getReg();
617 ARMCC::CondCodes OCC = ARMCC::getOppositeCondition(CC);
618 MachineBasicBlock *MBB = UseMI->getParent();
619 MachineBasicBlock::iterator MBBI = SrcMI;
620 unsigned NumInsts = 0;
621 while (--MBBI != MBB->begin()) {
622 if (MBBI->isDebugValue())
625 MachineInstr *NMI = &*MBBI;
626 ARMCC::CondCodes NCC = llvm::getInstrPredicate(NMI, PredReg);
627 if (!(NCC == CC || NCC == OCC) ||
628 NMI->modifiesRegister(SrcReg, &TRI) ||
629 NMI->definesRegister(ARM::CPSR))
632 // Too many in a row!
638 MBB->insert(++MBBI, SrcMI);
643 llvm::getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
644 unsigned Opc = MI->getOpcode();
645 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc)
647 return llvm::getInstrPredicate(MI, PredReg);