lib/Target/ARM/Thumb2InstrInfo.h

   1 //===- Thumb2InstrInfo.h - Thumb-2 Instruction Information ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 #ifndef THUMB2INSTRUCTIONINFO_H
  15 #define THUMB2INSTRUCTIONINFO_H
  16
  17 #include "llvm/Target/TargetInstrInfo.h"
  18 #include "ARM.h"
  19 #include "ARMInstrInfo.h"
  20 #include "Thumb2RegisterInfo.h"
  21
  22 namespace llvm {
  23 class ARMSubtarget;
  24 class ScheduleHazardRecognizer;
  25
  26 class Thumb2InstrInfo : public ARMBaseInstrInfo {
  27   Thumb2RegisterInfo RI;
  28 public:
  29   explicit Thumb2InstrInfo(const ARMSubtarget &STI);
  30
  31   // Return the non-pre/post incrementing version of 'Opc'. Return 0
  32   // if there is not such an opcode.
  33   unsigned getUnindexedOpcode(unsigned Opc) const;
  34
  35   void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
  36                                MachineBasicBlock *NewDest) const;
  37
  38   bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
  39                            MachineBasicBlock::iterator MBBI) const;
  40
  41   bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumInstrs) const;
  42
  43   bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumTInstrs,
  44                            MachineBasicBlock &FMBB, unsigned NumFInstrs) const;
  45
  46   bool copyRegToReg(MachineBasicBlock &MBB,
  47                     MachineBasicBlock::iterator I,
  48                     unsigned DestReg, unsigned SrcReg,
  49                     const TargetRegisterClass *DestRC,
  50                     const TargetRegisterClass *SrcRC,
  51                     DebugLoc DL) const;
  52
  53   void storeRegToStackSlot(MachineBasicBlock &MBB,
  54                            MachineBasicBlock::iterator MBBI,
  55                            unsigned SrcReg, bool isKill, int FrameIndex,
  56                            const TargetRegisterClass *RC,
  57                            const TargetRegisterInfo *TRI) const;
  58
  59   void loadRegFromStackSlot(MachineBasicBlock &MBB,
  60                             MachineBasicBlock::iterator MBBI,
  61                             unsigned DestReg, int FrameIndex,
  62                             const TargetRegisterClass *RC,
  63                             const TargetRegisterInfo *TRI) const;
  64
  65   /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
  66   /// two-addrss instruction inserted by two-address pass.
  67   void scheduleTwoAddrSource(MachineInstr *SrcMI, MachineInstr *UseMI,
  68                              const TargetRegisterInfo &TRI) const;
  69
  70   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
  71   /// such, whenever a client has an instance of instruction info, it should
  72   /// always be able to get register info as well (through this method).
  73   ///
  74   const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
  75
  76   ScheduleHazardRecognizer *
  77   CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const;
  78 };
  79
  80 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
  81 /// to llvm::getInstrPredicate except it returns AL for conditional branch
  82 /// instructions which are "predicated", but are not in IT blocks.
  83 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
  84
  85
  86 }
  87
  88 #endif // THUMB2INSTRUCTIONINFO_H