1 //===- Thumb2InstrInfo.h - Thumb-2 Instruction Information ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Thumb-2 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef THUMB2INSTRUCTIONINFO_H
15 #define THUMB2INSTRUCTIONINFO_H
17 #include "llvm/Target/TargetInstrInfo.h"
19 #include "ARMInstrInfo.h"
20 #include "Thumb2RegisterInfo.h"
24 class ScheduleHazardRecognizer;
26 class Thumb2InstrInfo : public ARMBaseInstrInfo {
27 Thumb2RegisterInfo RI;
29 explicit Thumb2InstrInfo(const ARMSubtarget &STI);
31 // Return the non-pre/post incrementing version of 'Opc'. Return 0
32 // if there is not such an opcode.
33 unsigned getUnindexedOpcode(unsigned Opc) const;
35 void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
36 MachineBasicBlock *NewDest) const;
38 bool isLegalToSplitMBBAt(MachineBasicBlock &MBB,
39 MachineBasicBlock::iterator MBBI) const;
41 bool copyRegToReg(MachineBasicBlock &MBB,
42 MachineBasicBlock::iterator I,
43 unsigned DestReg, unsigned SrcReg,
44 const TargetRegisterClass *DestRC,
45 const TargetRegisterClass *SrcRC,
48 void storeRegToStackSlot(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator MBBI,
50 unsigned SrcReg, bool isKill, int FrameIndex,
51 const TargetRegisterClass *RC,
52 const TargetRegisterInfo *TRI) const;
54 void loadRegFromStackSlot(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator MBBI,
56 unsigned DestReg, int FrameIndex,
57 const TargetRegisterClass *RC,
58 const TargetRegisterInfo *TRI) const;
60 /// scheduleTwoAddrSource - Schedule the copy / re-mat of the source of the
61 /// two-addrss instruction inserted by two-address pass.
62 void scheduleTwoAddrSource(MachineInstr *SrcMI, MachineInstr *UseMI,
63 const TargetRegisterInfo &TRI) const;
65 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
66 /// such, whenever a client has an instance of instruction info, it should
67 /// always be able to get register info as well (through this method).
69 const Thumb2RegisterInfo &getRegisterInfo() const { return RI; }
71 ScheduleHazardRecognizer *
72 CreateTargetPostRAHazardRecognizer(const InstrItineraryData &II) const;
75 /// getITInstrPredicate - Valid only in Thumb2 mode. This function is identical
76 /// to llvm::getInstrPredicate except it returns AL for conditional branch
77 /// instructions which are "predicated", but are not in IT blocks.
78 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
83 #endif // THUMB2INSTRUCTIONINFO_H