Use common code for both ARM and Thumb-2 instruction and register info.
[oota-llvm.git] / lib / Target / ARM / Thumb2RegisterInfo.cpp
1 //===- Thumb2RegisterInfo.cpp - Thumb-2 Register Information -------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Thumb-2 implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "ARM.h"
15 #include "ARMAddressingModes.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMMachineFunctionInfo.h"
18 #include "ARMSubtarget.h"
19 #include "Thumb2InstrInfo.h"
20 #include "Thumb2RegisterInfo.h"
21 #include "llvm/Constants.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLocation.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/Target/TargetFrameInfo.h"
30 #include "llvm/Target/TargetMachine.h"
31 #include "llvm/ADT/BitVector.h"
32 #include "llvm/ADT/SmallVector.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 using namespace llvm;
36
37 Thumb2RegisterInfo::Thumb2RegisterInfo(const ARMBaseInstrInfo &tii,
38                                        const ARMSubtarget &sti)
39   : ARMBaseRegisterInfo(tii, sti) {
40 }
41
42 /// emitLoadConstPool - Emits a load from constpool to materialize the
43 /// specified immediate.
44 void Thumb2RegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
45                                            MachineBasicBlock::iterator &MBBI,
46                                            DebugLoc dl,
47                                            unsigned DestReg, int Val,
48                                            ARMCC::CondCodes Pred,
49                                            unsigned PredReg) const {
50   MachineFunction &MF = *MBB.getParent();
51   MachineConstantPool *ConstantPool = MF.getConstantPool();
52   Constant *C = ConstantInt::get(Type::Int32Ty, Val);
53   unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
54
55   BuildMI(MBB, MBBI, dl, TII.get(ARM::t2LDRpci), DestReg)
56     .addConstantPoolIndex(Idx).addImm((int64_t)ARMCC::AL).addReg(0);
57 }
58
59 bool Thumb2RegisterInfo::
60 requiresRegisterScavenging(const MachineFunction &MF) const {
61   // FIXME
62   return false;
63 }