1 //===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "t2-reduce-size"
12 #include "ARMAddressingModes.h"
13 #include "ARMBaseRegisterInfo.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "Thumb2InstrInfo.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/Statistic.h"
26 STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
27 STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
28 STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
30 static cl::opt<int> ReduceLimit("t2-reduce-limit",
31 cl::init(-1), cl::Hidden);
32 static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
33 cl::init(-1), cl::Hidden);
34 static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
35 cl::init(-1), cl::Hidden);
38 /// ReduceTable - A static table with information on mapping from wide
41 unsigned WideOpc; // Wide opcode
42 unsigned NarrowOpc1; // Narrow opcode to transform to
43 unsigned NarrowOpc2; // Narrow opcode when it's two-address
44 uint8_t Imm1Limit; // Limit of immediate field (bits)
45 uint8_t Imm2Limit; // Limit of immediate field when it's two-address
46 unsigned LowRegs1 : 1; // Only possible if low-registers are used
47 unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
48 unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa.
50 // 2 - Always set CPSR.
52 unsigned Special : 1; // Needs to be dealt with specially
55 static const ReduceEntry ReduceTable[] = {
56 // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, S
57 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0 },
58 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0 },
59 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0 },
60 // Note: immediate scale is 4.
61 { ARM::t2ADDrSPi,ARM::tADDrSPi,0, 8, 0, 1, 0, 1,0, 0 },
62 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 1 },
63 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 1 },
64 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 0 },
65 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 0 },
66 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 0 },
67 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 0 },
68 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
69 //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0 },
70 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0 },
71 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0 },
72 { ARM::t2CMPzri,ARM::tCMPzi8, 0, 8, 0, 1, 0, 2,0, 0 },
73 { ARM::t2CMPzrr,ARM::tCMPzhir,0, 0, 0, 0, 0, 2,0, 0 },
74 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 0 },
75 // FIXME: adr.n immediate offset must be multiple of 4.
76 //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0 },
77 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 0 },
78 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 0 },
79 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 0 },
80 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 0 },
81 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0 },
82 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1 },
83 // FIXME: Do we need the 16-bit 'S' variant?
84 { ARM::t2MOVr,ARM::tMOVgpr2gpr,0, 0, 0, 0, 0, 1,0, 0 },
85 { ARM::t2MOVCCr,0, ARM::tMOVCCr, 0, 0, 0, 0, 0,1, 0 },
86 { ARM::t2MOVCCi,0, ARM::tMOVCCi, 0, 8, 0, 1, 0,1, 0 },
87 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 0 },
88 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0 },
89 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 0 },
90 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0 },
91 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0 },
92 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0 },
93 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 0 },
94 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 1 },
95 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 1 },
96 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0 },
97 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0 },
98 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0 },
99 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0 },
100 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0 },
101 { ARM::t2SXTBr, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0 },
102 { ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0 },
103 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0 },
104 { ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0 },
105 { ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0 },
107 // FIXME: Clean this up after splitting each Thumb load / store opcode
108 // into multiple ones.
109 { ARM::t2LDRi12,ARM::tLDR, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 1 },
110 { ARM::t2LDRs, ARM::tLDR, 0, 0, 0, 1, 0, 0,0, 1 },
111 { ARM::t2LDRBi12,ARM::tLDRB, 0, 5, 0, 1, 0, 0,0, 1 },
112 { ARM::t2LDRBs, ARM::tLDRB, 0, 0, 0, 1, 0, 0,0, 1 },
113 { ARM::t2LDRHi12,ARM::tLDRH, 0, 5, 0, 1, 0, 0,0, 1 },
114 { ARM::t2LDRHs, ARM::tLDRH, 0, 0, 0, 1, 0, 0,0, 1 },
115 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 1 },
116 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 1 },
117 { ARM::t2STRi12,ARM::tSTR, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 1 },
118 { ARM::t2STRs, ARM::tSTR, 0, 0, 0, 1, 0, 0,0, 1 },
119 { ARM::t2STRBi12,ARM::tSTRB, 0, 5, 0, 1, 0, 0,0, 1 },
120 { ARM::t2STRBs, ARM::tSTRB, 0, 0, 0, 1, 0, 0,0, 1 },
121 { ARM::t2STRHi12,ARM::tSTRH, 0, 5, 0, 1, 0, 0,0, 1 },
122 { ARM::t2STRHs, ARM::tSTRH, 0, 0, 0, 1, 0, 0,0, 1 },
124 { ARM::t2LDM_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 1 },
125 { ARM::t2LDM, ARM::tLDM, ARM::tPOP, 0, 0, 1, 1, 1,1, 1 },
126 { ARM::t2STM, ARM::tSTM, ARM::tPUSH, 0, 0, 1, 1, 1,1, 1 },
129 class Thumb2SizeReduce : public MachineFunctionPass {
134 const Thumb2InstrInfo *TII;
136 virtual bool runOnMachineFunction(MachineFunction &MF);
138 virtual const char *getPassName() const {
139 return "Thumb2 instruction size reduction pass";
143 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
144 DenseMap<unsigned, unsigned> ReduceOpcodeMap;
146 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
147 bool is2Addr, ARMCC::CondCodes Pred,
148 bool LiveCPSR, bool &HasCC, bool &CCDead);
150 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
151 const ReduceEntry &Entry);
153 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
154 const ReduceEntry &Entry, bool LiveCPSR);
156 /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
158 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
159 const ReduceEntry &Entry,
162 /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
163 /// non-two-address instruction.
164 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
165 const ReduceEntry &Entry,
168 /// ReduceMBB - Reduce width of instructions in the specified basic block.
169 bool ReduceMBB(MachineBasicBlock &MBB);
171 char Thumb2SizeReduce::ID = 0;
174 Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(&ID) {
175 for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
176 unsigned FromOpc = ReduceTable[i].WideOpc;
177 if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
178 assert(false && "Duplicated entries?");
182 static bool HasImplicitCPSRDef(const TargetInstrDesc &TID) {
183 for (const unsigned *Regs = TID.ImplicitDefs; *Regs; ++Regs)
184 if (*Regs == ARM::CPSR)
190 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
191 bool is2Addr, ARMCC::CondCodes Pred,
192 bool LiveCPSR, bool &HasCC, bool &CCDead) {
193 if ((is2Addr && Entry.PredCC2 == 0) ||
194 (!is2Addr && Entry.PredCC1 == 0)) {
195 if (Pred == ARMCC::AL) {
196 // Not predicated, must set CPSR.
198 // Original instruction was not setting CPSR, but CPSR is not
199 // currently live anyway. It's ok to set it. The CPSR def is
209 // Predicated, must not set CPSR.
213 } else if ((is2Addr && Entry.PredCC2 == 2) ||
214 (!is2Addr && Entry.PredCC1 == 2)) {
215 /// Old opcode has an optional def of CPSR.
218 // If both old opcode does not implicit CPSR def, then it's not ok since
219 // these new opcodes CPSR def is not meant to be thrown away. e.g. CMP.
220 if (!HasImplicitCPSRDef(MI->getDesc()))
224 // 16-bit instruction does not set CPSR.
232 static bool VerifyLowRegs(MachineInstr *MI) {
233 unsigned Opc = MI->getOpcode();
234 bool isPCOk = (Opc == ARM::t2LDM_RET) || (Opc == ARM::t2LDM);
235 bool isLROk = (Opc == ARM::t2STM);
236 bool isSPOk = isPCOk || isLROk || (Opc == ARM::t2ADDrSPi);
237 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
238 const MachineOperand &MO = MI->getOperand(i);
239 if (!MO.isReg() || MO.isImplicit())
241 unsigned Reg = MO.getReg();
242 if (Reg == 0 || Reg == ARM::CPSR)
244 if (isPCOk && Reg == ARM::PC)
246 if (isLROk && Reg == ARM::LR)
248 if (Reg == ARM::SP) {
251 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
252 // Special case for these ldr / str with sp as base register.
255 if (!isARMLowRegister(Reg))
262 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
263 const ReduceEntry &Entry) {
264 if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
268 bool HasImmOffset = false;
269 bool HasShift = false;
270 bool HasOffReg = true;
271 bool isLdStMul = false;
272 unsigned Opc = Entry.NarrowOpc1;
273 unsigned OpNum = 3; // First 'rest' of operands.
274 uint8_t ImmLimit = Entry.Imm1Limit;
275 switch (Entry.WideOpc) {
277 llvm_unreachable("Unexpected Thumb2 load / store opcode!");
279 case ARM::t2STRi12: {
280 unsigned BaseReg = MI->getOperand(1).getReg();
281 if (BaseReg == ARM::SP) {
282 Opc = Entry.NarrowOpc2;
283 ImmLimit = Entry.Imm2Limit;
314 unsigned BaseReg = MI->getOperand(0).getReg();
315 unsigned Mode = MI->getOperand(1).getImm();
316 if (BaseReg == ARM::SP && ARM_AM::getAM4WBFlag(Mode)) {
317 Opc = Entry.NarrowOpc2;
319 } else if (Entry.WideOpc == ARM::t2LDM_RET ||
320 !isARMLowRegister(BaseReg) ||
321 !ARM_AM::getAM4WBFlag(Mode) ||
322 ARM_AM::getAM4SubMode(Mode) != ARM_AM::ia) {
330 unsigned OffsetReg = 0;
331 bool OffsetKill = false;
333 OffsetReg = MI->getOperand(2).getReg();
334 OffsetKill = MI->getOperand(2).isKill();
335 if (MI->getOperand(3).getImm())
336 // Thumb1 addressing mode doesn't support shift.
340 unsigned OffsetImm = 0;
342 OffsetImm = MI->getOperand(2).getImm();
343 unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
344 if ((OffsetImm & (Scale-1)) || OffsetImm > MaxOffset)
345 // Make sure the immediate field fits.
349 // Add the 16-bit load / store instruction.
350 // FIXME: Thumb1 addressing mode encode both immediate and register offset.
351 DebugLoc dl = MI->getDebugLoc();
352 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
354 MIB.addOperand(MI->getOperand(0)).addOperand(MI->getOperand(1));
355 if (Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) {
356 // tLDRSB and tLDRSH do not have an immediate offset field. On the other
357 // hand, it must have an offset register.
358 // FIXME: Remove this special case.
359 MIB.addImm(OffsetImm/Scale);
361 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
364 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
367 // Transfer the rest of operands.
368 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
369 MIB.addOperand(MI->getOperand(OpNum));
371 // Transfer memoperands.
372 (*MIB).setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
374 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
382 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
383 const ReduceEntry &Entry,
385 if (Entry.LowRegs1 && !VerifyLowRegs(MI))
388 const TargetInstrDesc &TID = MI->getDesc();
389 if (TID.mayLoad() || TID.mayStore())
390 return ReduceLoadStore(MBB, MI, Entry);
392 unsigned Opc = MI->getOpcode();
396 case ARM::t2ADDSrr: {
397 unsigned PredReg = 0;
398 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
401 case ARM::t2ADDSri: {
402 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR))
407 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
414 if (MI->getOperand(2).getImm() == 0)
415 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
418 // Can convert only 'pure' immediate operands, not immediates obtained as
419 // globals' addresses.
420 if (MI->getOperand(1).isImm())
421 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
428 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
429 const ReduceEntry &Entry,
432 if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
435 const TargetInstrDesc &TID = MI->getDesc();
436 unsigned Reg0 = MI->getOperand(0).getReg();
437 unsigned Reg1 = MI->getOperand(1).getReg();
440 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
442 if (Entry.Imm2Limit) {
443 unsigned Imm = MI->getOperand(2).getImm();
444 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
448 unsigned Reg2 = MI->getOperand(2).getReg();
449 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
453 // Check if it's possible / necessary to transfer the predicate.
454 const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc2);
455 unsigned PredReg = 0;
456 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
457 bool SkipPred = false;
458 if (Pred != ARMCC::AL) {
459 if (!NewTID.isPredicable())
460 // Can't transfer predicate, fail.
463 SkipPred = !NewTID.isPredicable();
468 if (TID.hasOptionalDef()) {
469 unsigned NumOps = TID.getNumOperands();
470 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
471 if (HasCC && MI->getOperand(NumOps-1).isDead())
474 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
477 // Add the 16-bit instruction.
478 DebugLoc dl = MI->getDebugLoc();
479 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
480 MIB.addOperand(MI->getOperand(0));
481 if (NewTID.hasOptionalDef()) {
483 AddDefaultT1CC(MIB, CCDead);
488 // Transfer the rest of operands.
489 unsigned NumOps = TID.getNumOperands();
490 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
491 if (i < NumOps && TID.OpInfo[i].isOptionalDef())
493 if (SkipPred && TID.OpInfo[i].isPredicate())
495 MIB.addOperand(MI->getOperand(i));
498 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
506 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
507 const ReduceEntry &Entry,
509 if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
512 unsigned Limit = ~0U;
513 unsigned Scale = (Entry.WideOpc == ARM::t2ADDrSPi) ? 4 : 1;
515 Limit = ((1 << Entry.Imm1Limit) - 1) * Scale;
517 const TargetInstrDesc &TID = MI->getDesc();
518 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
519 if (TID.OpInfo[i].isPredicate())
521 const MachineOperand &MO = MI->getOperand(i);
523 unsigned Reg = MO.getReg();
524 if (!Reg || Reg == ARM::CPSR)
526 if (Entry.WideOpc == ARM::t2ADDrSPi && Reg == ARM::SP)
528 if (Entry.LowRegs1 && !isARMLowRegister(Reg))
530 } else if (MO.isImm() &&
531 !TID.OpInfo[i].isPredicate()) {
532 if (((unsigned)MO.getImm()) > Limit || (MO.getImm() & (Scale-1)) != 0)
537 // Check if it's possible / necessary to transfer the predicate.
538 const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc1);
539 unsigned PredReg = 0;
540 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
541 bool SkipPred = false;
542 if (Pred != ARMCC::AL) {
543 if (!NewTID.isPredicable())
544 // Can't transfer predicate, fail.
547 SkipPred = !NewTID.isPredicable();
552 if (TID.hasOptionalDef()) {
553 unsigned NumOps = TID.getNumOperands();
554 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
555 if (HasCC && MI->getOperand(NumOps-1).isDead())
558 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
561 // Add the 16-bit instruction.
562 DebugLoc dl = MI->getDebugLoc();
563 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
564 MIB.addOperand(MI->getOperand(0));
565 if (NewTID.hasOptionalDef()) {
567 AddDefaultT1CC(MIB, CCDead);
572 // Transfer the rest of operands.
573 unsigned NumOps = TID.getNumOperands();
574 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
575 if (i < NumOps && TID.OpInfo[i].isOptionalDef())
577 if ((TID.getOpcode() == ARM::t2RSBSri ||
578 TID.getOpcode() == ARM::t2RSBri) && i == 2)
579 // Skip the zero immediate operand, it's now implicit.
581 bool isPred = (i < NumOps && TID.OpInfo[i].isPredicate());
582 if (SkipPred && isPred)
584 const MachineOperand &MO = MI->getOperand(i);
585 if (Scale > 1 && !isPred && MO.isImm())
586 MIB.addImm(MO.getImm() / Scale);
588 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
589 // Skip implicit def of CPSR. Either it's modeled as an optional
590 // def now or it's already an implicit def on the new instruction.
595 if (!TID.isPredicable() && NewTID.isPredicable())
598 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
605 static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR) {
607 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
608 const MachineOperand &MO = MI.getOperand(i);
609 if (!MO.isReg() || MO.isUndef() || MO.isUse())
611 if (MO.getReg() != ARM::CPSR)
617 return HasDef || LiveCPSR;
620 static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
621 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
622 const MachineOperand &MO = MI.getOperand(i);
623 if (!MO.isReg() || MO.isUndef() || MO.isDef())
625 if (MO.getReg() != ARM::CPSR)
627 assert(LiveCPSR && "CPSR liveness tracking is wrong!");
637 bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
638 bool Modified = false;
640 bool LiveCPSR = false;
641 // Yes, CPSR could be livein.
642 for (MachineBasicBlock::const_livein_iterator I = MBB.livein_begin(),
643 E = MBB.livein_end(); I != E; ++I) {
644 if (*I == ARM::CPSR) {
650 MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
651 MachineBasicBlock::iterator NextMII;
652 for (; MII != E; MII = NextMII) {
653 NextMII = llvm::next(MII);
655 MachineInstr *MI = &*MII;
656 LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
658 unsigned Opcode = MI->getOpcode();
659 DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
660 if (OPI != ReduceOpcodeMap.end()) {
661 const ReduceEntry &Entry = ReduceTable[OPI->second];
662 // Ignore "special" cases for now.
664 if (ReduceSpecial(MBB, MI, Entry, LiveCPSR)) {
666 MachineBasicBlock::iterator I = prior(NextMII);
672 // Try to transform to a 16-bit two-address instruction.
673 if (Entry.NarrowOpc2 && ReduceTo2Addr(MBB, MI, Entry, LiveCPSR)) {
675 MachineBasicBlock::iterator I = prior(NextMII);
680 // Try to transform ro a 16-bit non-two-address instruction.
681 if (Entry.NarrowOpc1 && ReduceToNarrow(MBB, MI, Entry, LiveCPSR)) {
683 MachineBasicBlock::iterator I = prior(NextMII);
689 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR);
695 bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
696 const TargetMachine &TM = MF.getTarget();
697 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
699 bool Modified = false;
700 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
701 Modified |= ReduceMBB(*I);
705 /// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
707 FunctionPass *llvm::createThumb2SizeReductionPass() {
708 return new Thumb2SizeReduce();