1 //===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "t2-reduce-size"
12 #include "ARMAddressingModes.h"
13 #include "ARMBaseRegisterInfo.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "Thumb2InstrInfo.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/Statistic.h"
26 STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
27 STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
28 STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
30 static cl::opt<int> ReduceLimit("t2-reduce-limit",
31 cl::init(-1), cl::Hidden);
32 static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
33 cl::init(-1), cl::Hidden);
34 static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
35 cl::init(-1), cl::Hidden);
38 /// ReduceTable - A static table with information on mapping from wide
41 unsigned WideOpc; // Wide opcode
42 unsigned NarrowOpc1; // Narrow opcode to transform to
43 unsigned NarrowOpc2; // Narrow opcode when it's two-address
44 uint8_t Imm1Limit; // Limit of immediate field (bits)
45 uint8_t Imm2Limit; // Limit of immediate field when it's two-address
46 unsigned LowRegs1 : 1; // Only possible if low-registers are used
47 unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
48 unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa.
50 // 2 - Always set CPSR.
52 unsigned Special : 1; // Needs to be dealt with specially
55 static const ReduceEntry ReduceTable[] = {
56 // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, S
57 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0 },
58 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0 },
59 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0 },
60 // Note: immediate scale is 4.
61 { ARM::t2ADDrSPi,ARM::tADDrSPi,0, 8, 0, 1, 0, 1,0, 0 },
62 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 1 },
63 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 1 },
64 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 0 },
65 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 0 },
66 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 0 },
67 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 0 },
68 { ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0 },
69 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0 },
70 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0 },
71 { ARM::t2CMPzri,ARM::tCMPzi8, 0, 8, 0, 1, 0, 2,0, 0 },
72 { ARM::t2CMPzrr,ARM::tCMPzhir,0, 0, 0, 0, 0, 2,0, 0 },
73 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 0 },
74 // FIXME: adr.n immediate offset must be multiple of 4.
75 //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0 },
76 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 0 },
77 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 0 },
78 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 0 },
79 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 0 },
80 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0 },
81 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0 },
82 // FIXME: Do we need the 16-bit 'S' variant?
83 { ARM::t2MOVr,ARM::tMOVgpr2gpr,0, 0, 0, 0, 0, 1,0, 0 },
84 { ARM::t2MOVCCr,0, ARM::tMOVCCr, 0, 0, 0, 0, 0,1, 0 },
85 { ARM::t2MOVCCi,0, ARM::tMOVCCi, 0, 8, 0, 0, 0,1, 0 },
86 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 0 },
87 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0 },
88 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 0 },
89 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0 },
90 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0 },
91 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0 },
92 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 0 },
93 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 1 },
94 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 1 },
95 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0 },
96 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0 },
97 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0 },
98 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0 },
99 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0 },
100 { ARM::t2SXTBr, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0 },
101 { ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0 },
102 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0 },
103 { ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0 },
104 { ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0 },
106 // FIXME: Clean this up after splitting each Thumb load / store opcode
107 // into multiple ones.
108 { ARM::t2LDRi12,ARM::tLDR, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 1 },
109 { ARM::t2LDRs, ARM::tLDR, 0, 0, 0, 1, 0, 0,0, 1 },
110 { ARM::t2LDRBi12,ARM::tLDRB, 0, 5, 0, 1, 0, 0,0, 1 },
111 { ARM::t2LDRBs, ARM::tLDRB, 0, 0, 0, 1, 0, 0,0, 1 },
112 { ARM::t2LDRHi12,ARM::tLDRH, 0, 5, 0, 1, 0, 0,0, 1 },
113 { ARM::t2LDRHs, ARM::tLDRH, 0, 0, 0, 1, 0, 0,0, 1 },
114 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 1 },
115 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 1 },
116 { ARM::t2STRi12,ARM::tSTR, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 1 },
117 { ARM::t2STRs, ARM::tSTR, 0, 0, 0, 1, 0, 0,0, 1 },
118 { ARM::t2STRBi12,ARM::tSTRB, 0, 5, 0, 1, 0, 0,0, 1 },
119 { ARM::t2STRBs, ARM::tSTRB, 0, 0, 0, 1, 0, 0,0, 1 },
120 { ARM::t2STRHi12,ARM::tSTRH, 0, 5, 0, 1, 0, 0,0, 1 },
121 { ARM::t2STRHs, ARM::tSTRH, 0, 0, 0, 1, 0, 0,0, 1 },
123 { ARM::t2LDM_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 1 },
124 { ARM::t2LDM, ARM::tLDM, ARM::tPOP, 0, 0, 1, 1, 1,1, 1 },
125 { ARM::t2STM, ARM::tSTM, ARM::tPUSH, 0, 0, 1, 1, 1,1, 1 },
128 class Thumb2SizeReduce : public MachineFunctionPass {
133 const Thumb2InstrInfo *TII;
135 virtual bool runOnMachineFunction(MachineFunction &MF);
137 virtual const char *getPassName() const {
138 return "Thumb2 instruction size reduction pass";
142 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
143 DenseMap<unsigned, unsigned> ReduceOpcodeMap;
145 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
146 bool is2Addr, ARMCC::CondCodes Pred,
147 bool LiveCPSR, bool &HasCC, bool &CCDead);
149 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
150 const ReduceEntry &Entry);
152 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
153 const ReduceEntry &Entry, bool LiveCPSR);
155 /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
157 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
158 const ReduceEntry &Entry,
161 /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
162 /// non-two-address instruction.
163 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
164 const ReduceEntry &Entry,
167 /// ReduceMBB - Reduce width of instructions in the specified basic block.
168 bool ReduceMBB(MachineBasicBlock &MBB);
170 char Thumb2SizeReduce::ID = 0;
173 Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(&ID) {
174 for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
175 unsigned FromOpc = ReduceTable[i].WideOpc;
176 if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
177 assert(false && "Duplicated entries?");
181 static bool HasImplicitCPSRDef(const TargetInstrDesc &TID) {
182 for (const unsigned *Regs = TID.ImplicitDefs; *Regs; ++Regs)
183 if (*Regs == ARM::CPSR)
189 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
190 bool is2Addr, ARMCC::CondCodes Pred,
191 bool LiveCPSR, bool &HasCC, bool &CCDead) {
192 if ((is2Addr && Entry.PredCC2 == 0) ||
193 (!is2Addr && Entry.PredCC1 == 0)) {
194 if (Pred == ARMCC::AL) {
195 // Not predicated, must set CPSR.
197 // Original instruction was not setting CPSR, but CPSR is not
198 // currently live anyway. It's ok to set it. The CPSR def is
208 // Predicated, must not set CPSR.
212 } else if ((is2Addr && Entry.PredCC2 == 2) ||
213 (!is2Addr && Entry.PredCC1 == 2)) {
214 /// Old opcode has an optional def of CPSR.
217 // If both old opcode does not implicit CPSR def, then it's not ok since
218 // these new opcodes CPSR def is not meant to be thrown away. e.g. CMP.
219 if (!HasImplicitCPSRDef(MI->getDesc()))
223 // 16-bit instruction does not set CPSR.
231 static bool VerifyLowRegs(MachineInstr *MI) {
232 unsigned Opc = MI->getOpcode();
233 bool isPCOk = (Opc == ARM::t2LDM_RET) || (Opc == ARM::t2LDM);
234 bool isLROk = (Opc == ARM::t2STM);
235 bool isSPOk = isPCOk || isLROk || (Opc == ARM::t2ADDrSPi);
236 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
237 const MachineOperand &MO = MI->getOperand(i);
238 if (!MO.isReg() || MO.isImplicit())
240 unsigned Reg = MO.getReg();
241 if (Reg == 0 || Reg == ARM::CPSR)
243 if (isPCOk && Reg == ARM::PC)
245 if (isLROk && Reg == ARM::LR)
247 if (Reg == ARM::SP) {
250 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
251 // Special case for these ldr / str with sp as base register.
254 if (!isARMLowRegister(Reg))
261 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
262 const ReduceEntry &Entry) {
263 if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
267 bool HasImmOffset = false;
268 bool HasShift = false;
269 bool HasOffReg = true;
270 bool isLdStMul = false;
271 unsigned Opc = Entry.NarrowOpc1;
272 unsigned OpNum = 3; // First 'rest' of operands.
273 uint8_t ImmLimit = Entry.Imm1Limit;
274 switch (Entry.WideOpc) {
276 llvm_unreachable("Unexpected Thumb2 load / store opcode!");
278 case ARM::t2STRi12: {
279 unsigned BaseReg = MI->getOperand(1).getReg();
280 if (BaseReg == ARM::SP) {
281 Opc = Entry.NarrowOpc2;
282 ImmLimit = Entry.Imm2Limit;
313 unsigned BaseReg = MI->getOperand(0).getReg();
314 unsigned Mode = MI->getOperand(1).getImm();
315 if (BaseReg == ARM::SP && ARM_AM::getAM4WBFlag(Mode)) {
316 Opc = Entry.NarrowOpc2;
318 } else if (Entry.WideOpc == ARM::t2LDM_RET ||
319 !isARMLowRegister(BaseReg) ||
320 !ARM_AM::getAM4WBFlag(Mode) ||
321 ARM_AM::getAM4SubMode(Mode) != ARM_AM::ia) {
329 unsigned OffsetReg = 0;
330 bool OffsetKill = false;
332 OffsetReg = MI->getOperand(2).getReg();
333 OffsetKill = MI->getOperand(2).isKill();
334 if (MI->getOperand(3).getImm())
335 // Thumb1 addressing mode doesn't support shift.
339 unsigned OffsetImm = 0;
341 OffsetImm = MI->getOperand(2).getImm();
342 unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
343 if ((OffsetImm & (Scale-1)) || OffsetImm > MaxOffset)
344 // Make sure the immediate field fits.
348 // Add the 16-bit load / store instruction.
349 // FIXME: Thumb1 addressing mode encode both immediate and register offset.
350 DebugLoc dl = MI->getDebugLoc();
351 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
353 MIB.addOperand(MI->getOperand(0)).addOperand(MI->getOperand(1));
354 if (Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) {
355 // tLDRSB and tLDRSH do not have an immediate offset field. On the other
356 // hand, it must have an offset register.
357 // FIXME: Remove this special case.
358 MIB.addImm(OffsetImm/Scale);
360 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
363 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
366 // Transfer the rest of operands.
367 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
368 MIB.addOperand(MI->getOperand(OpNum));
370 // Transfer memoperands.
371 (*MIB).setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
373 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
381 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
382 const ReduceEntry &Entry,
384 if (Entry.LowRegs1 && !VerifyLowRegs(MI))
387 const TargetInstrDesc &TID = MI->getDesc();
388 if (TID.mayLoad() || TID.mayStore())
389 return ReduceLoadStore(MBB, MI, Entry);
391 unsigned Opc = MI->getOpcode();
395 case ARM::t2ADDSrr: {
396 unsigned PredReg = 0;
397 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
400 case ARM::t2ADDSri: {
401 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR))
406 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
413 if (MI->getOperand(2).getImm() == 0)
414 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
421 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
422 const ReduceEntry &Entry,
425 if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
428 const TargetInstrDesc &TID = MI->getDesc();
429 unsigned Reg0 = MI->getOperand(0).getReg();
430 unsigned Reg1 = MI->getOperand(1).getReg();
433 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
435 if (Entry.Imm2Limit) {
436 unsigned Imm = MI->getOperand(2).getImm();
437 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
441 unsigned Reg2 = MI->getOperand(2).getReg();
442 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
446 // Check if it's possible / necessary to transfer the predicate.
447 const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc2);
448 unsigned PredReg = 0;
449 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
450 bool SkipPred = false;
451 if (Pred != ARMCC::AL) {
452 if (!NewTID.isPredicable())
453 // Can't transfer predicate, fail.
456 SkipPred = !NewTID.isPredicable();
461 if (TID.hasOptionalDef()) {
462 unsigned NumOps = TID.getNumOperands();
463 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
464 if (HasCC && MI->getOperand(NumOps-1).isDead())
467 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
470 // Add the 16-bit instruction.
471 DebugLoc dl = MI->getDebugLoc();
472 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
473 MIB.addOperand(MI->getOperand(0));
474 if (NewTID.hasOptionalDef()) {
476 AddDefaultT1CC(MIB, CCDead);
481 // Transfer the rest of operands.
482 unsigned NumOps = TID.getNumOperands();
483 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
484 if (i < NumOps && TID.OpInfo[i].isOptionalDef())
486 if (SkipPred && TID.OpInfo[i].isPredicate())
488 MIB.addOperand(MI->getOperand(i));
491 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
499 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
500 const ReduceEntry &Entry,
502 if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
505 unsigned Limit = ~0U;
506 unsigned Scale = (Entry.WideOpc == ARM::t2ADDrSPi) ? 4 : 1;
508 Limit = ((1 << Entry.Imm1Limit) - 1) * Scale;
510 const TargetInstrDesc &TID = MI->getDesc();
511 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
512 if (TID.OpInfo[i].isPredicate())
514 const MachineOperand &MO = MI->getOperand(i);
516 unsigned Reg = MO.getReg();
517 if (!Reg || Reg == ARM::CPSR)
519 if (Entry.WideOpc == ARM::t2ADDrSPi && Reg == ARM::SP)
521 if (Entry.LowRegs1 && !isARMLowRegister(Reg))
523 } else if (MO.isImm() &&
524 !TID.OpInfo[i].isPredicate()) {
525 if (((unsigned)MO.getImm()) > Limit || (MO.getImm() & (Scale-1)) != 0)
530 // Check if it's possible / necessary to transfer the predicate.
531 const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc1);
532 unsigned PredReg = 0;
533 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
534 bool SkipPred = false;
535 if (Pred != ARMCC::AL) {
536 if (!NewTID.isPredicable())
537 // Can't transfer predicate, fail.
540 SkipPred = !NewTID.isPredicable();
545 if (TID.hasOptionalDef()) {
546 unsigned NumOps = TID.getNumOperands();
547 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
548 if (HasCC && MI->getOperand(NumOps-1).isDead())
551 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
554 // Add the 16-bit instruction.
555 DebugLoc dl = MI->getDebugLoc();
556 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
557 MIB.addOperand(MI->getOperand(0));
558 if (NewTID.hasOptionalDef()) {
560 AddDefaultT1CC(MIB, CCDead);
565 // Transfer the rest of operands.
566 unsigned NumOps = TID.getNumOperands();
567 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
568 if (i < NumOps && TID.OpInfo[i].isOptionalDef())
570 if ((TID.getOpcode() == ARM::t2RSBSri ||
571 TID.getOpcode() == ARM::t2RSBri) && i == 2)
572 // Skip the zero immediate operand, it's now implicit.
574 bool isPred = (i < NumOps && TID.OpInfo[i].isPredicate());
575 if (SkipPred && isPred)
577 const MachineOperand &MO = MI->getOperand(i);
578 if (Scale > 1 && !isPred && MO.isImm())
579 MIB.addImm(MO.getImm() / Scale);
581 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
582 // Skip implicit def of CPSR. Either it's modeled as an optional
583 // def now or it's already an implicit def on the new instruction.
588 if (!TID.isPredicable() && NewTID.isPredicable())
591 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
598 static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR) {
600 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
601 const MachineOperand &MO = MI.getOperand(i);
602 if (!MO.isReg() || MO.isUndef() || MO.isUse())
604 if (MO.getReg() != ARM::CPSR)
610 return HasDef || LiveCPSR;
613 static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
614 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
615 const MachineOperand &MO = MI.getOperand(i);
616 if (!MO.isReg() || MO.isUndef() || MO.isDef())
618 if (MO.getReg() != ARM::CPSR)
620 assert(LiveCPSR && "CPSR liveness tracking is wrong!");
630 bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
631 bool Modified = false;
633 bool LiveCPSR = false;
634 // Yes, CPSR could be livein.
635 for (MachineBasicBlock::const_livein_iterator I = MBB.livein_begin(),
636 E = MBB.livein_end(); I != E; ++I) {
637 if (*I == ARM::CPSR) {
643 MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
644 MachineBasicBlock::iterator NextMII;
645 for (; MII != E; MII = NextMII) {
648 MachineInstr *MI = &*MII;
649 LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
651 unsigned Opcode = MI->getOpcode();
652 DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
653 if (OPI != ReduceOpcodeMap.end()) {
654 const ReduceEntry &Entry = ReduceTable[OPI->second];
655 // Ignore "special" cases for now.
657 if (ReduceSpecial(MBB, MI, Entry, LiveCPSR)) {
659 MachineBasicBlock::iterator I = prior(NextMII);
665 // Try to transform to a 16-bit two-address instruction.
666 if (Entry.NarrowOpc2 && ReduceTo2Addr(MBB, MI, Entry, LiveCPSR)) {
668 MachineBasicBlock::iterator I = prior(NextMII);
673 // Try to transform ro a 16-bit non-two-address instruction.
674 if (Entry.NarrowOpc1 && ReduceToNarrow(MBB, MI, Entry, LiveCPSR)) {
676 MachineBasicBlock::iterator I = prior(NextMII);
682 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR);
688 bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
689 const TargetMachine &TM = MF.getTarget();
690 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
692 bool Modified = false;
693 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
694 Modified |= ReduceMBB(*I);
698 /// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
700 FunctionPass *llvm::createThumb2SizeReductionPass() {
701 return new Thumb2SizeReduce();