1 //===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "t2-reduce-size"
12 #include "ARMAddressingModes.h"
13 #include "ARMBaseRegisterInfo.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMSubtarget.h"
16 #include "Thumb2InstrInfo.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/Statistic.h"
27 STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
28 STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
29 STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
31 static cl::opt<int> ReduceLimit("t2-reduce-limit",
32 cl::init(-1), cl::Hidden);
33 static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
34 cl::init(-1), cl::Hidden);
35 static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
36 cl::init(-1), cl::Hidden);
39 /// ReduceTable - A static table with information on mapping from wide
42 unsigned WideOpc; // Wide opcode
43 unsigned NarrowOpc1; // Narrow opcode to transform to
44 unsigned NarrowOpc2; // Narrow opcode when it's two-address
45 uint8_t Imm1Limit; // Limit of immediate field (bits)
46 uint8_t Imm2Limit; // Limit of immediate field when it's two-address
47 unsigned LowRegs1 : 1; // Only possible if low-registers are used
48 unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
49 unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa.
51 // 2 - Always set CPSR.
53 unsigned PartFlag : 1; // 16-bit instruction does partial flag update
54 unsigned Special : 1; // Needs to be dealt with specially
57 static const ReduceEntry ReduceTable[] = {
58 // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, PF, S
59 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0 },
60 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,0 },
61 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0 },
62 // Note: immediate scale is 4.
63 { ARM::t2ADDrSPi,ARM::tADDrSPi,0, 8, 0, 1, 0, 1,0, 0,1 },
64 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1 },
65 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1 },
66 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0 },
67 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0 },
68 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0 },
69 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0 },
70 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
71 //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0,0 },
72 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0 },
73 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1 },
74 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0 },
75 // FIXME: adr.n immediate offset must be multiple of 4.
76 //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0,0 },
77 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0 },
78 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0 },
79 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0 },
80 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0 },
81 // FIXME: tMOVi8 and tMVN also partially update CPSR but they are less
82 // likely to cause issue in the loop. As a size / performance workaround,
83 // they are not marked as such.
84 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0,0 },
85 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0,1 },
86 // FIXME: Do we need the 16-bit 'S' variant?
87 { ARM::t2MOVr,ARM::tMOVgpr2gpr,0, 0, 0, 0, 0, 1,0, 0,0 },
88 { ARM::t2MOVCCr,0, ARM::tMOVCCr, 0, 0, 0, 0, 0,1, 0,0 },
89 { ARM::t2MOVCCi,0, ARM::tMOVCCi, 0, 8, 0, 1, 0,1, 0,0 },
90 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0 },
91 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0 },
92 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0 },
93 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0 },
94 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0 },
95 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0 },
96 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0 },
97 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1 },
98 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1 },
99 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0 },
100 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0 },
101 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0 },
102 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0 },
103 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0 },
104 { ARM::t2SXTBr, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,0 },
105 { ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,0 },
106 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0 },
107 { ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,0 },
108 { ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,0 },
110 // FIXME: Clean this up after splitting each Thumb load / store opcode
111 // into multiple ones.
112 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1 },
113 { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1 },
114 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1 },
115 { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1 },
116 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1 },
117 { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1 },
118 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1 },
119 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1 },
120 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1 },
121 { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1 },
122 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1 },
123 { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1 },
124 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1 },
125 { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1 },
127 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1 },
128 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1 },
129 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1 },
130 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
131 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1 },
132 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1 },
135 class Thumb2SizeReduce : public MachineFunctionPass {
140 const Thumb2InstrInfo *TII;
141 const ARMSubtarget *STI;
143 virtual bool runOnMachineFunction(MachineFunction &MF);
145 virtual const char *getPassName() const {
146 return "Thumb2 instruction size reduction pass";
150 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
151 DenseMap<unsigned, unsigned> ReduceOpcodeMap;
153 bool canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use);
155 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
156 bool is2Addr, ARMCC::CondCodes Pred,
157 bool LiveCPSR, bool &HasCC, bool &CCDead);
159 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
160 const ReduceEntry &Entry);
162 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
163 const ReduceEntry &Entry, bool LiveCPSR,
164 MachineInstr *CPSRDef);
166 /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
168 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
169 const ReduceEntry &Entry,
170 bool LiveCPSR, MachineInstr *CPSRDef);
172 /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
173 /// non-two-address instruction.
174 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
175 const ReduceEntry &Entry,
176 bool LiveCPSR, MachineInstr *CPSRDef);
178 /// ReduceMBB - Reduce width of instructions in the specified basic block.
179 bool ReduceMBB(MachineBasicBlock &MBB);
181 char Thumb2SizeReduce::ID = 0;
184 Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(ID) {
185 for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
186 unsigned FromOpc = ReduceTable[i].WideOpc;
187 if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
188 assert(false && "Duplicated entries?");
192 static bool HasImplicitCPSRDef(const TargetInstrDesc &TID) {
193 for (const unsigned *Regs = TID.ImplicitDefs; *Regs; ++Regs)
194 if (*Regs == ARM::CPSR)
199 /// canAddPseudoFlagDep - For A9 (and other out-of-order) implementations,
200 /// the 's' 16-bit instruction partially update CPSR. Abort the
201 /// transformation to avoid adding false dependency on last CPSR setting
202 /// instruction which hurts the ability for out-of-order execution engine
203 /// to do register renaming magic.
204 /// This function checks if there is a read-of-write dependency between the
205 /// last instruction that defines the CPSR and the current instruction. If there
206 /// is, then there is no harm done since the instruction cannot be retired
207 /// before the CPSR setting instruction anyway.
208 /// Note, we are not doing full dependency analysis here for the sake of compile
209 /// time. We're not looking for cases like:
211 /// r1 = add.w r0, ...
214 /// In this case it would have been ok to narrow the mul.w to muls since there
215 /// are indirect RAW dependency between the muls and the mul.w
217 Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use) {
218 if (!Def || !STI->avoidCPSRPartialUpdate())
221 SmallSet<unsigned, 2> Defs;
222 for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) {
223 const MachineOperand &MO = Def->getOperand(i);
224 if (!MO.isReg() || MO.isUndef() || MO.isUse())
226 unsigned Reg = MO.getReg();
227 if (Reg == 0 || Reg == ARM::CPSR)
232 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
233 const MachineOperand &MO = Use->getOperand(i);
234 if (!MO.isReg() || MO.isUndef() || MO.isDef())
236 unsigned Reg = MO.getReg();
241 // No read-after-write dependency. The narrowing will add false dependency.
246 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
247 bool is2Addr, ARMCC::CondCodes Pred,
248 bool LiveCPSR, bool &HasCC, bool &CCDead) {
249 if ((is2Addr && Entry.PredCC2 == 0) ||
250 (!is2Addr && Entry.PredCC1 == 0)) {
251 if (Pred == ARMCC::AL) {
252 // Not predicated, must set CPSR.
254 // Original instruction was not setting CPSR, but CPSR is not
255 // currently live anyway. It's ok to set it. The CPSR def is
265 // Predicated, must not set CPSR.
269 } else if ((is2Addr && Entry.PredCC2 == 2) ||
270 (!is2Addr && Entry.PredCC1 == 2)) {
271 /// Old opcode has an optional def of CPSR.
274 // If old opcode does not implicitly define CPSR, then it's not ok since
275 // these new opcodes' CPSR def is not meant to be thrown away. e.g. CMP.
276 if (!HasImplicitCPSRDef(MI->getDesc()))
280 // 16-bit instruction does not set CPSR.
288 static bool VerifyLowRegs(MachineInstr *MI) {
289 unsigned Opc = MI->getOpcode();
290 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA ||
291 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD ||
292 Opc == ARM::t2LDMDB_UPD);
293 bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD);
294 bool isSPOk = isPCOk || isLROk || (Opc == ARM::t2ADDrSPi);
295 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
296 const MachineOperand &MO = MI->getOperand(i);
297 if (!MO.isReg() || MO.isImplicit())
299 unsigned Reg = MO.getReg();
300 if (Reg == 0 || Reg == ARM::CPSR)
302 if (isPCOk && Reg == ARM::PC)
304 if (isLROk && Reg == ARM::LR)
306 if (Reg == ARM::SP) {
309 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
310 // Special case for these ldr / str with sp as base register.
313 if (!isARMLowRegister(Reg))
320 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
321 const ReduceEntry &Entry) {
322 if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
326 bool HasImmOffset = false;
327 bool HasShift = false;
328 bool HasOffReg = true;
329 bool isLdStMul = false;
330 unsigned Opc = Entry.NarrowOpc1;
331 unsigned OpNum = 3; // First 'rest' of operands.
332 uint8_t ImmLimit = Entry.Imm1Limit;
334 switch (Entry.WideOpc) {
336 llvm_unreachable("Unexpected Thumb2 load / store opcode!");
339 if (MI->getOperand(1).getReg() == ARM::SP) {
340 Opc = Entry.NarrowOpc2;
341 ImmLimit = Entry.Imm2Limit;
373 unsigned BaseReg = MI->getOperand(0).getReg();
374 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
377 // For the non-writeback version (this one), the base register must be
378 // one of the registers being loaded.
380 for (unsigned i = 4; i < MI->getNumOperands(); ++i) {
381 if (MI->getOperand(i).getReg() == BaseReg) {
394 case ARM::t2LDMIA_RET: {
395 unsigned BaseReg = MI->getOperand(1).getReg();
396 if (BaseReg != ARM::SP)
398 Opc = Entry.NarrowOpc2; // tPOP_RET
403 case ARM::t2LDMIA_UPD:
404 case ARM::t2LDMDB_UPD:
405 case ARM::t2STMIA_UPD:
406 case ARM::t2STMDB_UPD: {
409 unsigned BaseReg = MI->getOperand(1).getReg();
410 if (BaseReg == ARM::SP &&
411 (Entry.WideOpc == ARM::t2LDMIA_UPD ||
412 Entry.WideOpc == ARM::t2STMDB_UPD)) {
413 Opc = Entry.NarrowOpc2; // tPOP or tPUSH
415 } else if (!isARMLowRegister(BaseReg) ||
416 (Entry.WideOpc != ARM::t2LDMIA_UPD &&
417 Entry.WideOpc != ARM::t2STMIA_UPD)) {
426 unsigned OffsetReg = 0;
427 bool OffsetKill = false;
429 OffsetReg = MI->getOperand(2).getReg();
430 OffsetKill = MI->getOperand(2).isKill();
432 if (MI->getOperand(3).getImm())
433 // Thumb1 addressing mode doesn't support shift.
437 unsigned OffsetImm = 0;
439 OffsetImm = MI->getOperand(2).getImm();
440 unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
442 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
443 // Make sure the immediate field fits.
447 // Add the 16-bit load / store instruction.
448 DebugLoc dl = MI->getDebugLoc();
449 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
451 MIB.addOperand(MI->getOperand(0));
452 MIB.addOperand(MI->getOperand(1));
455 MIB.addImm(OffsetImm / Scale);
457 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
460 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
463 // Transfer the rest of operands.
464 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
465 MIB.addOperand(MI->getOperand(OpNum));
467 // Transfer memoperands.
468 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
470 // Transfer MI flags.
471 MIB.setMIFlags(MI->getFlags());
473 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
481 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
482 const ReduceEntry &Entry,
483 bool LiveCPSR, MachineInstr *CPSRDef) {
484 if (Entry.LowRegs1 && !VerifyLowRegs(MI))
487 const TargetInstrDesc &TID = MI->getDesc();
488 if (TID.mayLoad() || TID.mayStore())
489 return ReduceLoadStore(MBB, MI, Entry);
491 unsigned Opc = MI->getOpcode();
495 case ARM::t2ADDSrr: {
496 unsigned PredReg = 0;
497 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
500 case ARM::t2ADDSri: {
501 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef))
506 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
513 if (MI->getOperand(2).getImm() == 0)
514 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
517 // Can convert only 'pure' immediate operands, not immediates obtained as
518 // globals' addresses.
519 if (MI->getOperand(1).isImm())
520 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
523 // Try to reduce to the lo-reg only version first. Why there are two
524 // versions of the instruction is a mystery.
525 // It would be nice to just have two entries in the master table that
526 // are prioritized, but the table assumes a unique entry for each
527 // source insn opcode. So for now, we hack a local entry record to use.
528 static const ReduceEntry NarrowEntry =
529 { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1 };
530 if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef))
532 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
534 case ARM::t2ADDrSPi: {
535 static const ReduceEntry NarrowEntry =
536 { ARM::t2ADDrSPi,ARM::tADDspi, 0, 7, 0, 1, 0, 1, 0, 0,1 };
537 if (MI->getOperand(0).getReg() == ARM::SP)
538 return ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef);
539 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef);
546 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
547 const ReduceEntry &Entry,
548 bool LiveCPSR, MachineInstr *CPSRDef) {
550 if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
553 unsigned Reg0 = MI->getOperand(0).getReg();
554 unsigned Reg1 = MI->getOperand(1).getReg();
556 // Try to commute the operands to make it a 2-address instruction.
557 unsigned CommOpIdx1, CommOpIdx2;
558 if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) ||
559 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
561 MachineInstr *CommutedMI = TII->commuteInstruction(MI);
565 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
567 if (Entry.Imm2Limit) {
568 unsigned Imm = MI->getOperand(2).getImm();
569 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
573 unsigned Reg2 = MI->getOperand(2).getReg();
574 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
578 // Check if it's possible / necessary to transfer the predicate.
579 const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc2);
580 unsigned PredReg = 0;
581 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
582 bool SkipPred = false;
583 if (Pred != ARMCC::AL) {
584 if (!NewTID.isPredicable())
585 // Can't transfer predicate, fail.
588 SkipPred = !NewTID.isPredicable();
593 const TargetInstrDesc &TID = MI->getDesc();
594 if (TID.hasOptionalDef()) {
595 unsigned NumOps = TID.getNumOperands();
596 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
597 if (HasCC && MI->getOperand(NumOps-1).isDead())
600 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
603 // Avoid adding a false dependency on partial flag update by some 16-bit
604 // instructions which has the 's' bit set.
605 if (Entry.PartFlag && NewTID.hasOptionalDef() && HasCC &&
606 canAddPseudoFlagDep(CPSRDef, MI))
609 // Add the 16-bit instruction.
610 DebugLoc dl = MI->getDebugLoc();
611 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
612 MIB.addOperand(MI->getOperand(0));
613 if (NewTID.hasOptionalDef()) {
615 AddDefaultT1CC(MIB, CCDead);
620 // Transfer the rest of operands.
621 unsigned NumOps = TID.getNumOperands();
622 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
623 if (i < NumOps && TID.OpInfo[i].isOptionalDef())
625 if (SkipPred && TID.OpInfo[i].isPredicate())
627 MIB.addOperand(MI->getOperand(i));
630 // Transfer MI flags.
631 MIB.setMIFlags(MI->getFlags());
633 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
641 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
642 const ReduceEntry &Entry,
643 bool LiveCPSR, MachineInstr *CPSRDef) {
644 if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
647 unsigned Limit = ~0U;
648 unsigned Scale = (Entry.WideOpc == ARM::t2ADDrSPi) ? 4 : 1;
650 Limit = ((1 << Entry.Imm1Limit) - 1) * Scale;
652 const TargetInstrDesc &TID = MI->getDesc();
653 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
654 if (TID.OpInfo[i].isPredicate())
656 const MachineOperand &MO = MI->getOperand(i);
658 unsigned Reg = MO.getReg();
659 if (!Reg || Reg == ARM::CPSR)
661 if (Entry.WideOpc == ARM::t2ADDrSPi && Reg == ARM::SP)
663 if (Entry.LowRegs1 && !isARMLowRegister(Reg))
665 } else if (MO.isImm() &&
666 !TID.OpInfo[i].isPredicate()) {
667 if (((unsigned)MO.getImm()) > Limit || (MO.getImm() & (Scale-1)) != 0)
672 // Check if it's possible / necessary to transfer the predicate.
673 const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc1);
674 unsigned PredReg = 0;
675 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
676 bool SkipPred = false;
677 if (Pred != ARMCC::AL) {
678 if (!NewTID.isPredicable())
679 // Can't transfer predicate, fail.
682 SkipPred = !NewTID.isPredicable();
687 if (TID.hasOptionalDef()) {
688 unsigned NumOps = TID.getNumOperands();
689 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
690 if (HasCC && MI->getOperand(NumOps-1).isDead())
693 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
696 // Avoid adding a false dependency on partial flag update by some 16-bit
697 // instructions which has the 's' bit set.
698 if (Entry.PartFlag && NewTID.hasOptionalDef() && HasCC &&
699 canAddPseudoFlagDep(CPSRDef, MI))
702 // Add the 16-bit instruction.
703 DebugLoc dl = MI->getDebugLoc();
704 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
705 MIB.addOperand(MI->getOperand(0));
706 if (NewTID.hasOptionalDef()) {
708 AddDefaultT1CC(MIB, CCDead);
713 // Transfer the rest of operands.
714 unsigned NumOps = TID.getNumOperands();
715 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
716 if (i < NumOps && TID.OpInfo[i].isOptionalDef())
718 if ((TID.getOpcode() == ARM::t2RSBSri ||
719 TID.getOpcode() == ARM::t2RSBri) && i == 2)
720 // Skip the zero immediate operand, it's now implicit.
722 bool isPred = (i < NumOps && TID.OpInfo[i].isPredicate());
723 if (SkipPred && isPred)
725 const MachineOperand &MO = MI->getOperand(i);
726 if (Scale > 1 && !isPred && MO.isImm())
727 MIB.addImm(MO.getImm() / Scale);
729 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
730 // Skip implicit def of CPSR. Either it's modeled as an optional
731 // def now or it's already an implicit def on the new instruction.
736 if (!TID.isPredicable() && NewTID.isPredicable())
739 // Transfer MI flags.
740 MIB.setMIFlags(MI->getFlags());
742 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
749 static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR) {
751 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
752 const MachineOperand &MO = MI.getOperand(i);
753 if (!MO.isReg() || MO.isUndef() || MO.isUse())
755 if (MO.getReg() != ARM::CPSR)
763 return HasDef || LiveCPSR;
766 static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
767 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
768 const MachineOperand &MO = MI.getOperand(i);
769 if (!MO.isReg() || MO.isUndef() || MO.isDef())
771 if (MO.getReg() != ARM::CPSR)
773 assert(LiveCPSR && "CPSR liveness tracking is wrong!");
783 bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
784 bool Modified = false;
786 // Yes, CPSR could be livein.
787 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
788 MachineInstr *CPSRDef = 0;
790 MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
791 MachineBasicBlock::iterator NextMII;
792 for (; MII != E; MII = NextMII) {
793 NextMII = llvm::next(MII);
795 MachineInstr *MI = &*MII;
796 LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
798 unsigned Opcode = MI->getOpcode();
799 DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
800 if (OPI != ReduceOpcodeMap.end()) {
801 const ReduceEntry &Entry = ReduceTable[OPI->second];
802 // Ignore "special" cases for now.
804 if (ReduceSpecial(MBB, MI, Entry, LiveCPSR, CPSRDef)) {
806 MachineBasicBlock::iterator I = prior(NextMII);
812 // Try to transform to a 16-bit two-address instruction.
813 if (Entry.NarrowOpc2 &&
814 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef)) {
816 MachineBasicBlock::iterator I = prior(NextMII);
821 // Try to transform to a 16-bit non-two-address instruction.
822 if (Entry.NarrowOpc1 &&
823 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef)) {
825 MachineBasicBlock::iterator I = prior(NextMII);
831 bool DefCPSR = false;
832 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR);
833 if (MI->getDesc().isCall())
834 // Calls don't really set CPSR.
837 // This is the last CPSR defining instruction.
844 bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
845 const TargetMachine &TM = MF.getTarget();
846 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
847 STI = &TM.getSubtarget<ARMSubtarget>();
849 bool Modified = false;
850 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
851 Modified |= ReduceMBB(*I);
855 /// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
857 FunctionPass *llvm::createThumb2SizeReductionPass() {
858 return new Thumb2SizeReduce();