1 //===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "t2-reduce-size"
12 #include "ARMBaseRegisterInfo.h"
13 #include "ARMBaseInstrInfo.h"
14 #include "ARMSubtarget.h"
15 #include "Thumb2InstrInfo.h"
16 #include "MCTargetDesc/ARMAddressingModes.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
20 #include "llvm/Support/CommandLine.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/Statistic.h"
27 STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
28 STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
29 STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
31 static cl::opt<int> ReduceLimit("t2-reduce-limit",
32 cl::init(-1), cl::Hidden);
33 static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
34 cl::init(-1), cl::Hidden);
35 static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
36 cl::init(-1), cl::Hidden);
39 /// ReduceTable - A static table with information on mapping from wide
42 unsigned WideOpc; // Wide opcode
43 unsigned NarrowOpc1; // Narrow opcode to transform to
44 unsigned NarrowOpc2; // Narrow opcode when it's two-address
45 uint8_t Imm1Limit; // Limit of immediate field (bits)
46 uint8_t Imm2Limit; // Limit of immediate field when it's two-address
47 unsigned LowRegs1 : 1; // Only possible if low-registers are used
48 unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
49 unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa.
51 // 2 - Always set CPSR.
53 unsigned PartFlag : 1; // 16-bit instruction does partial flag update
54 unsigned Special : 1; // Needs to be dealt with specially
57 static const ReduceEntry ReduceTable[] = {
58 // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, PF, S
59 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0 },
60 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1 },
61 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0 },
62 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1 },
63 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1 },
64 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0 },
65 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0 },
66 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0 },
67 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0 },
68 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
69 //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0,0 },
70 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0 },
71 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1 },
72 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0 },
73 // FIXME: adr.n immediate offset must be multiple of 4.
74 //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0,0 },
75 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0 },
76 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0 },
77 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0 },
78 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0 },
79 // FIXME: tMOVi8 and tMVN also partially update CPSR but they are less
80 // likely to cause issue in the loop. As a size / performance workaround,
81 // they are not marked as such.
82 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0,0 },
83 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0,1 },
84 // FIXME: Do we need the 16-bit 'S' variant?
85 { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0 },
86 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0 },
87 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0 },
88 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0 },
89 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0 },
90 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0 },
91 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0 },
92 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0 },
93 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1 },
94 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1 },
95 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0 },
96 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0 },
97 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0 },
98 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0 },
99 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0 },
100 { ARM::t2SXTB, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,1 },
101 { ARM::t2SXTH, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,1 },
102 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0 },
103 { ARM::t2UXTB, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,1 },
104 { ARM::t2UXTH, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,1 },
106 // FIXME: Clean this up after splitting each Thumb load / store opcode
107 // into multiple ones.
108 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1 },
109 { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1 },
110 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1 },
111 { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1 },
112 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1 },
113 { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1 },
114 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1 },
115 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1 },
116 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1 },
117 { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1 },
118 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1 },
119 { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1 },
120 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1 },
121 { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1 },
123 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1 },
124 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1 },
125 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1 },
126 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
127 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1 },
128 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1 },
131 class Thumb2SizeReduce : public MachineFunctionPass {
136 const Thumb2InstrInfo *TII;
137 const ARMSubtarget *STI;
139 virtual bool runOnMachineFunction(MachineFunction &MF);
141 virtual const char *getPassName() const {
142 return "Thumb2 instruction size reduction pass";
146 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
147 DenseMap<unsigned, unsigned> ReduceOpcodeMap;
149 bool canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use,
152 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
153 bool is2Addr, ARMCC::CondCodes Pred,
154 bool LiveCPSR, bool &HasCC, bool &CCDead);
156 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
157 const ReduceEntry &Entry);
159 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
160 const ReduceEntry &Entry, bool LiveCPSR,
161 MachineInstr *CPSRDef, bool IsSelfLoop);
163 /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
165 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
166 const ReduceEntry &Entry,
167 bool LiveCPSR, MachineInstr *CPSRDef,
170 /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
171 /// non-two-address instruction.
172 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
173 const ReduceEntry &Entry,
174 bool LiveCPSR, MachineInstr *CPSRDef,
177 /// ReduceMBB - Reduce width of instructions in the specified basic block.
178 bool ReduceMBB(MachineBasicBlock &MBB);
180 char Thumb2SizeReduce::ID = 0;
183 Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(ID) {
184 for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
185 unsigned FromOpc = ReduceTable[i].WideOpc;
186 if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
187 assert(false && "Duplicated entries?");
191 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
192 for (const unsigned *Regs = MCID.ImplicitDefs; *Regs; ++Regs)
193 if (*Regs == ARM::CPSR)
198 /// canAddPseudoFlagDep - For A9 (and other out-of-order) implementations,
199 /// the 's' 16-bit instruction partially update CPSR. Abort the
200 /// transformation to avoid adding false dependency on last CPSR setting
201 /// instruction which hurts the ability for out-of-order execution engine
202 /// to do register renaming magic.
203 /// This function checks if there is a read-of-write dependency between the
204 /// last instruction that defines the CPSR and the current instruction. If there
205 /// is, then there is no harm done since the instruction cannot be retired
206 /// before the CPSR setting instruction anyway.
207 /// Note, we are not doing full dependency analysis here for the sake of compile
208 /// time. We're not looking for cases like:
210 /// r1 = add.w r0, ...
213 /// In this case it would have been ok to narrow the mul.w to muls since there
214 /// are indirect RAW dependency between the muls and the mul.w
216 Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Def, MachineInstr *Use,
217 bool FirstInSelfLoop) {
218 // FIXME: Disable check for -Oz (aka OptimizeForSizeHarder).
219 if (!STI->avoidCPSRPartialUpdate())
223 // If this BB loops back to itself, conservatively avoid narrowing the
224 // first instruction that does partial flag update.
225 return FirstInSelfLoop;
227 SmallSet<unsigned, 2> Defs;
228 for (unsigned i = 0, e = Def->getNumOperands(); i != e; ++i) {
229 const MachineOperand &MO = Def->getOperand(i);
230 if (!MO.isReg() || MO.isUndef() || MO.isUse())
232 unsigned Reg = MO.getReg();
233 if (Reg == 0 || Reg == ARM::CPSR)
238 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) {
239 const MachineOperand &MO = Use->getOperand(i);
240 if (!MO.isReg() || MO.isUndef() || MO.isDef())
242 unsigned Reg = MO.getReg();
247 // No read-after-write dependency. The narrowing will add false dependency.
252 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
253 bool is2Addr, ARMCC::CondCodes Pred,
254 bool LiveCPSR, bool &HasCC, bool &CCDead) {
255 if ((is2Addr && Entry.PredCC2 == 0) ||
256 (!is2Addr && Entry.PredCC1 == 0)) {
257 if (Pred == ARMCC::AL) {
258 // Not predicated, must set CPSR.
260 // Original instruction was not setting CPSR, but CPSR is not
261 // currently live anyway. It's ok to set it. The CPSR def is
271 // Predicated, must not set CPSR.
275 } else if ((is2Addr && Entry.PredCC2 == 2) ||
276 (!is2Addr && Entry.PredCC1 == 2)) {
277 /// Old opcode has an optional def of CPSR.
280 // If old opcode does not implicitly define CPSR, then it's not ok since
281 // these new opcodes' CPSR def is not meant to be thrown away. e.g. CMP.
282 if (!HasImplicitCPSRDef(MI->getDesc()))
286 // 16-bit instruction does not set CPSR.
294 static bool VerifyLowRegs(MachineInstr *MI) {
295 unsigned Opc = MI->getOpcode();
296 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA ||
297 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD ||
298 Opc == ARM::t2LDMDB_UPD);
299 bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD);
300 bool isSPOk = isPCOk || isLROk;
301 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
302 const MachineOperand &MO = MI->getOperand(i);
303 if (!MO.isReg() || MO.isImplicit())
305 unsigned Reg = MO.getReg();
306 if (Reg == 0 || Reg == ARM::CPSR)
308 if (isPCOk && Reg == ARM::PC)
310 if (isLROk && Reg == ARM::LR)
312 if (Reg == ARM::SP) {
315 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
316 // Special case for these ldr / str with sp as base register.
319 if (!isARMLowRegister(Reg))
326 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
327 const ReduceEntry &Entry) {
328 if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
332 bool HasImmOffset = false;
333 bool HasShift = false;
334 bool HasOffReg = true;
335 bool isLdStMul = false;
336 unsigned Opc = Entry.NarrowOpc1;
337 unsigned OpNum = 3; // First 'rest' of operands.
338 uint8_t ImmLimit = Entry.Imm1Limit;
340 switch (Entry.WideOpc) {
342 llvm_unreachable("Unexpected Thumb2 load / store opcode!");
345 if (MI->getOperand(1).getReg() == ARM::SP) {
346 Opc = Entry.NarrowOpc2;
347 ImmLimit = Entry.Imm2Limit;
379 unsigned BaseReg = MI->getOperand(0).getReg();
380 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
383 // For the non-writeback version (this one), the base register must be
384 // one of the registers being loaded.
386 for (unsigned i = 4; i < MI->getNumOperands(); ++i) {
387 if (MI->getOperand(i).getReg() == BaseReg) {
400 case ARM::t2LDMIA_RET: {
401 unsigned BaseReg = MI->getOperand(1).getReg();
402 if (BaseReg != ARM::SP)
404 Opc = Entry.NarrowOpc2; // tPOP_RET
409 case ARM::t2LDMIA_UPD:
410 case ARM::t2LDMDB_UPD:
411 case ARM::t2STMIA_UPD:
412 case ARM::t2STMDB_UPD: {
415 unsigned BaseReg = MI->getOperand(1).getReg();
416 if (BaseReg == ARM::SP &&
417 (Entry.WideOpc == ARM::t2LDMIA_UPD ||
418 Entry.WideOpc == ARM::t2STMDB_UPD)) {
419 Opc = Entry.NarrowOpc2; // tPOP or tPUSH
421 } else if (!isARMLowRegister(BaseReg) ||
422 (Entry.WideOpc != ARM::t2LDMIA_UPD &&
423 Entry.WideOpc != ARM::t2STMIA_UPD)) {
432 unsigned OffsetReg = 0;
433 bool OffsetKill = false;
435 OffsetReg = MI->getOperand(2).getReg();
436 OffsetKill = MI->getOperand(2).isKill();
438 if (MI->getOperand(3).getImm())
439 // Thumb1 addressing mode doesn't support shift.
443 unsigned OffsetImm = 0;
445 OffsetImm = MI->getOperand(2).getImm();
446 unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
448 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
449 // Make sure the immediate field fits.
453 // Add the 16-bit load / store instruction.
454 DebugLoc dl = MI->getDebugLoc();
455 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
457 MIB.addOperand(MI->getOperand(0));
458 MIB.addOperand(MI->getOperand(1));
461 MIB.addImm(OffsetImm / Scale);
463 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
466 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
469 // Transfer the rest of operands.
470 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
471 MIB.addOperand(MI->getOperand(OpNum));
473 // Transfer memoperands.
474 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
476 // Transfer MI flags.
477 MIB.setMIFlags(MI->getFlags());
479 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
487 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
488 const ReduceEntry &Entry,
489 bool LiveCPSR, MachineInstr *CPSRDef,
491 unsigned Opc = MI->getOpcode();
492 if (Opc == ARM::t2ADDri) {
493 // If the source register is SP, try to reduce to tADDrSPi, otherwise
494 // it's a normal reduce.
495 if (MI->getOperand(1).getReg() != ARM::SP) {
496 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop))
498 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
500 // Try to reduce to tADDrSPi.
501 unsigned Imm = MI->getOperand(2).getImm();
502 // The immediate must be in range, the destination register must be a low
503 // reg, the predicate must be "always" and the condition flags must not
505 if (Imm & 3 || Imm > 1020)
507 if (!isARMLowRegister(MI->getOperand(0).getReg()))
509 if (MI->getOperand(3).getImm() != ARMCC::AL)
511 const MCInstrDesc &MCID = MI->getDesc();
512 if (MCID.hasOptionalDef() &&
513 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
516 MachineInstrBuilder MIB = BuildMI(MBB, *MI, MI->getDebugLoc(),
517 TII->get(ARM::tADDrSPi))
518 .addOperand(MI->getOperand(0))
519 .addOperand(MI->getOperand(1))
520 .addImm(Imm / 4); // The tADDrSPi has an implied scale by four.
523 // Transfer MI flags.
524 MIB.setMIFlags(MI->getFlags());
526 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB);
533 if (Entry.LowRegs1 && !VerifyLowRegs(MI))
536 const MCInstrDesc &MCID = MI->getDesc();
537 if (MCID.mayLoad() || MCID.mayStore())
538 return ReduceLoadStore(MBB, MI, Entry);
543 case ARM::t2ADDSrr: {
544 unsigned PredReg = 0;
545 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
548 case ARM::t2ADDSri: {
549 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop))
554 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
565 if (MI->getOperand(2).getImm() == 0)
566 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
569 // Can convert only 'pure' immediate operands, not immediates obtained as
570 // globals' addresses.
571 if (MI->getOperand(1).isImm())
572 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
575 // Try to reduce to the lo-reg only version first. Why there are two
576 // versions of the instruction is a mystery.
577 // It would be nice to just have two entries in the master table that
578 // are prioritized, but the table assumes a unique entry for each
579 // source insn opcode. So for now, we hack a local entry record to use.
580 static const ReduceEntry NarrowEntry =
581 { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1 };
582 if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, CPSRDef, IsSelfLoop))
584 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop);
591 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
592 const ReduceEntry &Entry,
593 bool LiveCPSR, MachineInstr *CPSRDef,
596 if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
599 unsigned Reg0 = MI->getOperand(0).getReg();
600 unsigned Reg1 = MI->getOperand(1).getReg();
602 // Try to commute the operands to make it a 2-address instruction.
603 unsigned CommOpIdx1, CommOpIdx2;
604 if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) ||
605 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
607 MachineInstr *CommutedMI = TII->commuteInstruction(MI);
611 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
613 if (Entry.Imm2Limit) {
614 unsigned Imm = MI->getOperand(2).getImm();
615 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
619 unsigned Reg2 = MI->getOperand(2).getReg();
620 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
624 // Check if it's possible / necessary to transfer the predicate.
625 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
626 unsigned PredReg = 0;
627 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
628 bool SkipPred = false;
629 if (Pred != ARMCC::AL) {
630 if (!NewMCID.isPredicable())
631 // Can't transfer predicate, fail.
634 SkipPred = !NewMCID.isPredicable();
639 const MCInstrDesc &MCID = MI->getDesc();
640 if (MCID.hasOptionalDef()) {
641 unsigned NumOps = MCID.getNumOperands();
642 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
643 if (HasCC && MI->getOperand(NumOps-1).isDead())
646 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
649 // Avoid adding a false dependency on partial flag update by some 16-bit
650 // instructions which has the 's' bit set.
651 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
652 canAddPseudoFlagDep(CPSRDef, MI, IsSelfLoop))
655 // Add the 16-bit instruction.
656 DebugLoc dl = MI->getDebugLoc();
657 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewMCID);
658 MIB.addOperand(MI->getOperand(0));
659 if (NewMCID.hasOptionalDef()) {
661 AddDefaultT1CC(MIB, CCDead);
666 // Transfer the rest of operands.
667 unsigned NumOps = MCID.getNumOperands();
668 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
669 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
671 if (SkipPred && MCID.OpInfo[i].isPredicate())
673 MIB.addOperand(MI->getOperand(i));
676 // Transfer MI flags.
677 MIB.setMIFlags(MI->getFlags());
679 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
687 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
688 const ReduceEntry &Entry,
689 bool LiveCPSR, MachineInstr *CPSRDef,
691 if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
694 unsigned Limit = ~0U;
696 Limit = (1 << Entry.Imm1Limit) - 1;
698 const MCInstrDesc &MCID = MI->getDesc();
699 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
700 if (MCID.OpInfo[i].isPredicate())
702 const MachineOperand &MO = MI->getOperand(i);
704 unsigned Reg = MO.getReg();
705 if (!Reg || Reg == ARM::CPSR)
707 if (Entry.LowRegs1 && !isARMLowRegister(Reg))
709 } else if (MO.isImm() &&
710 !MCID.OpInfo[i].isPredicate()) {
711 if (((unsigned)MO.getImm()) > Limit)
716 // Check if it's possible / necessary to transfer the predicate.
717 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
718 unsigned PredReg = 0;
719 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
720 bool SkipPred = false;
721 if (Pred != ARMCC::AL) {
722 if (!NewMCID.isPredicable())
723 // Can't transfer predicate, fail.
726 SkipPred = !NewMCID.isPredicable();
731 if (MCID.hasOptionalDef()) {
732 unsigned NumOps = MCID.getNumOperands();
733 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
734 if (HasCC && MI->getOperand(NumOps-1).isDead())
737 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
740 // Avoid adding a false dependency on partial flag update by some 16-bit
741 // instructions which has the 's' bit set.
742 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
743 canAddPseudoFlagDep(CPSRDef, MI, IsSelfLoop))
746 // Add the 16-bit instruction.
747 DebugLoc dl = MI->getDebugLoc();
748 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewMCID);
749 MIB.addOperand(MI->getOperand(0));
750 if (NewMCID.hasOptionalDef()) {
752 AddDefaultT1CC(MIB, CCDead);
757 // Transfer the rest of operands.
758 unsigned NumOps = MCID.getNumOperands();
759 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
760 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
762 if ((MCID.getOpcode() == ARM::t2RSBSri ||
763 MCID.getOpcode() == ARM::t2RSBri ||
764 MCID.getOpcode() == ARM::t2SXTB ||
765 MCID.getOpcode() == ARM::t2SXTH ||
766 MCID.getOpcode() == ARM::t2UXTB ||
767 MCID.getOpcode() == ARM::t2UXTH) && i == 2)
768 // Skip the zero immediate operand, it's now implicit.
770 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
771 if (SkipPred && isPred)
773 const MachineOperand &MO = MI->getOperand(i);
774 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
775 // Skip implicit def of CPSR. Either it's modeled as an optional
776 // def now or it's already an implicit def on the new instruction.
780 if (!MCID.isPredicable() && NewMCID.isPredicable())
783 // Transfer MI flags.
784 MIB.setMIFlags(MI->getFlags());
786 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
793 static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR) {
795 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
796 const MachineOperand &MO = MI.getOperand(i);
797 if (!MO.isReg() || MO.isUndef() || MO.isUse())
799 if (MO.getReg() != ARM::CPSR)
807 return HasDef || LiveCPSR;
810 static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
811 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
812 const MachineOperand &MO = MI.getOperand(i);
813 if (!MO.isReg() || MO.isUndef() || MO.isDef())
815 if (MO.getReg() != ARM::CPSR)
817 assert(LiveCPSR && "CPSR liveness tracking is wrong!");
827 bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
828 bool Modified = false;
830 // Yes, CPSR could be livein.
831 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
832 MachineInstr *CPSRDef = 0;
834 // If this BB loops back to itself, conservatively avoid narrowing the
835 // first instruction that does partial flag update.
836 bool IsSelfLoop = MBB.isSuccessor(&MBB);
837 MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
838 MachineBasicBlock::iterator NextMII;
839 for (; MII != E; MII = NextMII) {
840 NextMII = llvm::next(MII);
842 MachineInstr *MI = &*MII;
843 LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
845 unsigned Opcode = MI->getOpcode();
846 DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
847 if (OPI != ReduceOpcodeMap.end()) {
848 const ReduceEntry &Entry = ReduceTable[OPI->second];
849 // Ignore "special" cases for now.
851 if (ReduceSpecial(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) {
853 MachineBasicBlock::iterator I = prior(NextMII);
859 // Try to transform to a 16-bit two-address instruction.
860 if (Entry.NarrowOpc2 &&
861 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) {
863 MachineBasicBlock::iterator I = prior(NextMII);
868 // Try to transform to a 16-bit non-two-address instruction.
869 if (Entry.NarrowOpc1 &&
870 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, CPSRDef, IsSelfLoop)) {
872 MachineBasicBlock::iterator I = prior(NextMII);
878 bool DefCPSR = false;
879 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR);
880 if (MI->getDesc().isCall()) {
881 // Calls don't really set CPSR.
884 } else if (DefCPSR) {
885 // This is the last CPSR defining instruction.
894 bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
895 const TargetMachine &TM = MF.getTarget();
896 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
897 STI = &TM.getSubtarget<ARMSubtarget>();
899 bool Modified = false;
900 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
901 Modified |= ReduceMBB(*I);
905 /// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
907 FunctionPass *llvm::createThumb2SizeReductionPass() {
908 return new Thumb2SizeReduce();