1 //===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #define DEBUG_TYPE "t2-reduce-size"
12 #include "ARMAddressingModes.h"
13 #include "ARMBaseRegisterInfo.h"
14 #include "ARMBaseInstrInfo.h"
15 #include "Thumb2InstrInfo.h"
16 #include "llvm/CodeGen/MachineInstr.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/Support/CommandLine.h"
20 #include "llvm/Support/Debug.h"
21 #include "llvm/Support/raw_ostream.h"
22 #include "llvm/ADT/DenseMap.h"
23 #include "llvm/ADT/Statistic.h"
26 STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
27 STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
28 STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
30 static cl::opt<int> ReduceLimit("t2-reduce-limit",
31 cl::init(-1), cl::Hidden);
32 static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
33 cl::init(-1), cl::Hidden);
34 static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
35 cl::init(-1), cl::Hidden);
38 /// ReduceTable - A static table with information on mapping from wide
41 unsigned WideOpc; // Wide opcode
42 unsigned NarrowOpc1; // Narrow opcode to transform to
43 unsigned NarrowOpc2; // Narrow opcode when it's two-address
44 uint8_t Imm1Limit; // Limit of immediate field (bits)
45 uint8_t Imm2Limit; // Limit of immediate field when it's two-address
46 unsigned LowRegs1 : 1; // Only possible if low-registers are used
47 unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
48 unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa.
50 // 2 - Always set CPSR.
52 unsigned Special : 1; // Needs to be dealt with specially
55 static const ReduceEntry ReduceTable[] = {
56 // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, S
57 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0 },
58 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0 },
59 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0 },
60 // Note: immediate scale is 4.
61 { ARM::t2ADDrSPi,ARM::tADDrSPi,0, 8, 0, 1, 0, 1,0, 1 },
62 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 1 },
63 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 1 },
64 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 0 },
65 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 0 },
66 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 0 },
67 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 0 },
68 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
69 //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0 },
70 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0 },
71 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0 },
72 { ARM::t2CMPzri,ARM::tCMPzi8, 0, 8, 0, 1, 0, 2,0, 0 },
73 { ARM::t2CMPzrr,ARM::tCMPzhir,0, 0, 0, 0, 0, 2,0, 1 },
74 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 0 },
75 // FIXME: adr.n immediate offset must be multiple of 4.
76 //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0 },
77 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 0 },
78 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 0 },
79 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 0 },
80 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 0 },
81 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0 },
82 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1 },
83 // FIXME: Do we need the 16-bit 'S' variant?
84 { ARM::t2MOVr,ARM::tMOVgpr2gpr,0, 0, 0, 0, 0, 1,0, 0 },
85 { ARM::t2MOVCCr,0, ARM::tMOVCCr, 0, 0, 0, 0, 0,1, 0 },
86 { ARM::t2MOVCCi,0, ARM::tMOVCCi, 0, 8, 0, 1, 0,1, 0 },
87 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 0 },
88 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0 },
89 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 0 },
90 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0 },
91 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0 },
92 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0 },
93 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 0 },
94 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 1 },
95 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 1 },
96 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0 },
97 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0 },
98 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0 },
99 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0 },
100 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0 },
101 { ARM::t2SXTBr, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0 },
102 { ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0 },
103 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0 },
104 { ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0 },
105 { ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0 },
107 // FIXME: Clean this up after splitting each Thumb load / store opcode
108 // into multiple ones.
109 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 1 },
110 { ARM::t2LDRs, ARM::tLDR, 0, 0, 0, 1, 0, 0,0, 1 },
111 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 1 },
112 { ARM::t2LDRBs, ARM::tLDRB, 0, 0, 0, 1, 0, 0,0, 1 },
113 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 1 },
114 { ARM::t2LDRHs, ARM::tLDRH, 0, 0, 0, 1, 0, 0,0, 1 },
115 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 1 },
116 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 1 },
117 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 1 },
118 { ARM::t2STRs, ARM::tSTR, 0, 0, 0, 1, 0, 0,0, 1 },
119 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 1 },
120 { ARM::t2STRBs, ARM::tSTRB, 0, 0, 0, 1, 0, 0,0, 1 },
121 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 1 },
122 { ARM::t2STRHs, ARM::tSTRH, 0, 0, 0, 1, 0, 0,0, 1 },
124 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 1 },
125 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 1 },
126 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 1 },
127 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
128 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 1 },
129 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 1 },
132 class Thumb2SizeReduce : public MachineFunctionPass {
137 const Thumb2InstrInfo *TII;
139 virtual bool runOnMachineFunction(MachineFunction &MF);
141 virtual const char *getPassName() const {
142 return "Thumb2 instruction size reduction pass";
146 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
147 DenseMap<unsigned, unsigned> ReduceOpcodeMap;
149 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
150 bool is2Addr, ARMCC::CondCodes Pred,
151 bool LiveCPSR, bool &HasCC, bool &CCDead);
153 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
154 const ReduceEntry &Entry);
156 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
157 const ReduceEntry &Entry, bool LiveCPSR);
159 /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
161 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
162 const ReduceEntry &Entry,
165 /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
166 /// non-two-address instruction.
167 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
168 const ReduceEntry &Entry,
171 /// ReduceMBB - Reduce width of instructions in the specified basic block.
172 bool ReduceMBB(MachineBasicBlock &MBB);
174 char Thumb2SizeReduce::ID = 0;
177 Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(ID) {
178 for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
179 unsigned FromOpc = ReduceTable[i].WideOpc;
180 if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
181 assert(false && "Duplicated entries?");
185 static bool HasImplicitCPSRDef(const TargetInstrDesc &TID) {
186 for (const unsigned *Regs = TID.ImplicitDefs; *Regs; ++Regs)
187 if (*Regs == ARM::CPSR)
193 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
194 bool is2Addr, ARMCC::CondCodes Pred,
195 bool LiveCPSR, bool &HasCC, bool &CCDead) {
196 if ((is2Addr && Entry.PredCC2 == 0) ||
197 (!is2Addr && Entry.PredCC1 == 0)) {
198 if (Pred == ARMCC::AL) {
199 // Not predicated, must set CPSR.
201 // Original instruction was not setting CPSR, but CPSR is not
202 // currently live anyway. It's ok to set it. The CPSR def is
212 // Predicated, must not set CPSR.
216 } else if ((is2Addr && Entry.PredCC2 == 2) ||
217 (!is2Addr && Entry.PredCC1 == 2)) {
218 /// Old opcode has an optional def of CPSR.
221 // If old opcode does not implicitly define CPSR, then it's not ok since
222 // these new opcodes' CPSR def is not meant to be thrown away. e.g. CMP.
223 if (!HasImplicitCPSRDef(MI->getDesc()))
227 // 16-bit instruction does not set CPSR.
235 static bool VerifyLowRegs(MachineInstr *MI) {
236 unsigned Opc = MI->getOpcode();
237 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA ||
238 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD ||
239 Opc == ARM::t2LDMDB_UPD || Opc == ARM::t2LDRi12);
240 bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD);
241 bool isSPOk = isPCOk || isLROk || (Opc == ARM::t2ADDrSPi);
242 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
243 const MachineOperand &MO = MI->getOperand(i);
244 if (!MO.isReg() || MO.isImplicit())
246 unsigned Reg = MO.getReg();
247 if (Reg == 0 || Reg == ARM::CPSR)
249 if (isPCOk && Reg == ARM::PC)
251 if (isLROk && Reg == ARM::LR)
253 if (Reg == ARM::SP) {
256 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
257 // Special case for these ldr / str with sp as base register.
260 if (!isARMLowRegister(Reg))
267 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
268 const ReduceEntry &Entry) {
269 if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
273 bool HasBaseReg = true;
274 bool HasImmOffset = false;
275 bool HasShift = false;
276 bool HasOffReg = true;
277 bool isLdStMul = false;
278 bool InsertImmOffset = true;
279 unsigned Opc = Entry.NarrowOpc1;
280 unsigned OpNum = 3; // First 'rest' of operands.
281 uint8_t ImmLimit = Entry.Imm1Limit;
283 switch (Entry.WideOpc) {
285 llvm_unreachable("Unexpected Thumb2 load / store opcode!");
287 case ARM::t2STRi12: {
288 unsigned BaseReg = MI->getOperand(1).getReg();
289 if (BaseReg == ARM::SP) {
290 Opc = Entry.NarrowOpc2;
291 ImmLimit = Entry.Imm2Limit;
295 if (MI->getOperand(2).isImm())
298 if (Entry.WideOpc == ARM::t2LDRi12) {
302 HasImmOffset = false;
303 InsertImmOffset = false;
311 if (MI->getOperand(2).isImm())
314 if (Entry.WideOpc == ARM::t2LDRBi12) {
318 HasImmOffset = false;
319 InsertImmOffset = false;
327 if (MI->getOperand(2).isImm())
330 if (Entry.WideOpc == ARM::t2LDRHi12) {
334 HasImmOffset = false;
335 InsertImmOffset = false;
353 unsigned BaseReg = MI->getOperand(0).getReg();
354 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA)
356 // For the non-writeback version (this one), the base register must be
357 // one of the registers being loaded.
359 for (unsigned i = 4; i < MI->getNumOperands(); ++i) {
360 if (MI->getOperand(i).getReg() == BaseReg) {
372 case ARM::t2LDMIA_RET: {
373 unsigned BaseReg = MI->getOperand(1).getReg();
374 if (BaseReg != ARM::SP)
376 Opc = Entry.NarrowOpc2; // tPOP_RET
381 case ARM::t2LDMIA_UPD:
382 case ARM::t2LDMDB_UPD:
383 case ARM::t2STMIA_UPD:
384 case ARM::t2STMDB_UPD: {
386 unsigned BaseReg = MI->getOperand(1).getReg();
387 if (BaseReg == ARM::SP &&
388 (Entry.WideOpc == ARM::t2LDMIA_UPD ||
389 Entry.WideOpc == ARM::t2STMDB_UPD)) {
390 Opc = Entry.NarrowOpc2; // tPOP or tPUSH
392 } else if (!isARMLowRegister(BaseReg) ||
393 (Entry.WideOpc != ARM::t2LDMIA_UPD &&
394 Entry.WideOpc != ARM::t2STMIA_UPD)) {
402 unsigned OffsetReg = 0;
403 bool OffsetKill = false;
405 OffsetReg = MI->getOperand(2).getReg();
406 OffsetKill = MI->getOperand(2).isKill();
407 if (MI->getOperand(3).getImm())
408 // Thumb1 addressing mode doesn't support shift.
412 unsigned OffsetImm = 0;
414 OffsetImm = MI->getOperand(2).getImm();
415 unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
416 if ((OffsetImm & (Scale-1)) || OffsetImm > MaxOffset)
417 // Make sure the immediate field fits.
421 // Add the 16-bit load / store instruction.
422 // FIXME: Thumb1 addressing mode encode both immediate and register offset.
423 DebugLoc dl = MI->getDebugLoc();
424 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc));
426 MIB.addOperand(MI->getOperand(0));
427 if (HasBaseReg) MIB.addOperand(MI->getOperand(1));
428 if (InsertImmOffset && Opc != ARM::tLDRSB && Opc != ARM::tLDRSH) {
429 // tLDRSB and tLDRSH do not have an immediate offset field. On the other
430 // hand, it must have an offset register.
431 // FIXME: Remove this special case.
432 MIB.addImm(OffsetImm/Scale);
434 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
437 MIB.addReg(OffsetReg, getKillRegState(OffsetKill));
440 // Transfer the rest of operands.
441 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
442 MIB.addOperand(MI->getOperand(OpNum));
444 // Transfer memoperands.
445 (*MIB).setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
447 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
455 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
456 const ReduceEntry &Entry,
458 if (Entry.LowRegs1 && !VerifyLowRegs(MI))
461 const TargetInstrDesc &TID = MI->getDesc();
462 if (TID.mayLoad() || TID.mayStore())
463 return ReduceLoadStore(MBB, MI, Entry);
465 unsigned Opc = MI->getOpcode();
469 case ARM::t2ADDSrr: {
470 unsigned PredReg = 0;
471 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
474 case ARM::t2ADDSri: {
475 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR))
480 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
487 if (MI->getOperand(2).getImm() == 0)
488 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
491 // Can convert only 'pure' immediate operands, not immediates obtained as
492 // globals' addresses.
493 if (MI->getOperand(1).isImm())
494 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
496 case ARM::t2CMPzrr: {
497 // Try to reduce to the lo-reg only version first. Why there are two
498 // versions of the instruction is a mystery.
499 // It would be nice to just have two entries in the master table that
500 // are prioritized, but the table assumes a unique entry for each
501 // source insn opcode. So for now, we hack a local entry record to use.
502 static const ReduceEntry NarrowEntry =
503 { ARM::t2CMPzrr,ARM::tCMPzr, 0, 0, 0, 1, 1,2, 0, 1 };
504 if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR))
506 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
508 case ARM::t2ADDrSPi: {
509 static const ReduceEntry NarrowEntry =
510 { ARM::t2ADDrSPi,ARM::tADDspi, 0, 7, 0, 1, 0, 1, 0, 1 };
511 if (MI->getOperand(0).getReg() == ARM::SP)
512 return ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR);
513 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR);
520 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
521 const ReduceEntry &Entry,
524 if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
527 unsigned Reg0 = MI->getOperand(0).getReg();
528 unsigned Reg1 = MI->getOperand(1).getReg();
530 // Try to commute the operands to make it a 2-address instruction.
531 unsigned CommOpIdx1, CommOpIdx2;
532 if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) ||
533 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
535 MachineInstr *CommutedMI = TII->commuteInstruction(MI);
539 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
541 if (Entry.Imm2Limit) {
542 unsigned Imm = MI->getOperand(2).getImm();
543 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
547 unsigned Reg2 = MI->getOperand(2).getReg();
548 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
552 // Check if it's possible / necessary to transfer the predicate.
553 const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc2);
554 unsigned PredReg = 0;
555 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
556 bool SkipPred = false;
557 if (Pred != ARMCC::AL) {
558 if (!NewTID.isPredicable())
559 // Can't transfer predicate, fail.
562 SkipPred = !NewTID.isPredicable();
567 const TargetInstrDesc &TID = MI->getDesc();
568 if (TID.hasOptionalDef()) {
569 unsigned NumOps = TID.getNumOperands();
570 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
571 if (HasCC && MI->getOperand(NumOps-1).isDead())
574 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
577 // Add the 16-bit instruction.
578 DebugLoc dl = MI->getDebugLoc();
579 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
580 MIB.addOperand(MI->getOperand(0));
581 if (NewTID.hasOptionalDef()) {
583 AddDefaultT1CC(MIB, CCDead);
588 // Transfer the rest of operands.
589 unsigned NumOps = TID.getNumOperands();
590 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
591 if (i < NumOps && TID.OpInfo[i].isOptionalDef())
593 if (SkipPred && TID.OpInfo[i].isPredicate())
595 MIB.addOperand(MI->getOperand(i));
598 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
606 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
607 const ReduceEntry &Entry,
609 if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
612 unsigned Limit = ~0U;
613 unsigned Scale = (Entry.WideOpc == ARM::t2ADDrSPi) ? 4 : 1;
615 Limit = ((1 << Entry.Imm1Limit) - 1) * Scale;
617 const TargetInstrDesc &TID = MI->getDesc();
618 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) {
619 if (TID.OpInfo[i].isPredicate())
621 const MachineOperand &MO = MI->getOperand(i);
623 unsigned Reg = MO.getReg();
624 if (!Reg || Reg == ARM::CPSR)
626 if (Entry.WideOpc == ARM::t2ADDrSPi && Reg == ARM::SP)
628 if (Entry.LowRegs1 && !isARMLowRegister(Reg))
630 } else if (MO.isImm() &&
631 !TID.OpInfo[i].isPredicate()) {
632 if (((unsigned)MO.getImm()) > Limit || (MO.getImm() & (Scale-1)) != 0)
637 // Check if it's possible / necessary to transfer the predicate.
638 const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc1);
639 unsigned PredReg = 0;
640 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
641 bool SkipPred = false;
642 if (Pred != ARMCC::AL) {
643 if (!NewTID.isPredicable())
644 // Can't transfer predicate, fail.
647 SkipPred = !NewTID.isPredicable();
652 if (TID.hasOptionalDef()) {
653 unsigned NumOps = TID.getNumOperands();
654 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
655 if (HasCC && MI->getOperand(NumOps-1).isDead())
658 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
661 // Add the 16-bit instruction.
662 DebugLoc dl = MI->getDebugLoc();
663 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID);
664 MIB.addOperand(MI->getOperand(0));
665 if (NewTID.hasOptionalDef()) {
667 AddDefaultT1CC(MIB, CCDead);
672 // Transfer the rest of operands.
673 unsigned NumOps = TID.getNumOperands();
674 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
675 if (i < NumOps && TID.OpInfo[i].isOptionalDef())
677 if ((TID.getOpcode() == ARM::t2RSBSri ||
678 TID.getOpcode() == ARM::t2RSBri) && i == 2)
679 // Skip the zero immediate operand, it's now implicit.
681 bool isPred = (i < NumOps && TID.OpInfo[i].isPredicate());
682 if (SkipPred && isPred)
684 const MachineOperand &MO = MI->getOperand(i);
685 if (Scale > 1 && !isPred && MO.isImm())
686 MIB.addImm(MO.getImm() / Scale);
688 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
689 // Skip implicit def of CPSR. Either it's modeled as an optional
690 // def now or it's already an implicit def on the new instruction.
695 if (!TID.isPredicable() && NewTID.isPredicable())
698 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
705 static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR) {
707 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
708 const MachineOperand &MO = MI.getOperand(i);
709 if (!MO.isReg() || MO.isUndef() || MO.isUse())
711 if (MO.getReg() != ARM::CPSR)
717 return HasDef || LiveCPSR;
720 static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
721 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
722 const MachineOperand &MO = MI.getOperand(i);
723 if (!MO.isReg() || MO.isUndef() || MO.isDef())
725 if (MO.getReg() != ARM::CPSR)
727 assert(LiveCPSR && "CPSR liveness tracking is wrong!");
737 bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
738 bool Modified = false;
740 // Yes, CPSR could be livein.
741 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
743 MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
744 MachineBasicBlock::iterator NextMII;
745 for (; MII != E; MII = NextMII) {
746 NextMII = llvm::next(MII);
748 MachineInstr *MI = &*MII;
749 LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
751 unsigned Opcode = MI->getOpcode();
752 DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
753 if (OPI != ReduceOpcodeMap.end()) {
754 const ReduceEntry &Entry = ReduceTable[OPI->second];
755 // Ignore "special" cases for now.
757 if (ReduceSpecial(MBB, MI, Entry, LiveCPSR)) {
759 MachineBasicBlock::iterator I = prior(NextMII);
765 // Try to transform to a 16-bit two-address instruction.
766 if (Entry.NarrowOpc2 && ReduceTo2Addr(MBB, MI, Entry, LiveCPSR)) {
768 MachineBasicBlock::iterator I = prior(NextMII);
773 // Try to transform to a 16-bit non-two-address instruction.
774 if (Entry.NarrowOpc1 && ReduceToNarrow(MBB, MI, Entry, LiveCPSR)) {
776 MachineBasicBlock::iterator I = prior(NextMII);
782 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR);
788 bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
789 const TargetMachine &TM = MF.getTarget();
790 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo());
792 bool Modified = false;
793 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
794 Modified |= ReduceMBB(*I);
798 /// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
800 FunctionPass *llvm::createThumb2SizeReductionPass() {
801 return new Thumb2SizeReduce();