1 //===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARMBaseInstrInfo.h"
12 #include "ARMSubtarget.h"
13 #include "MCTargetDesc/ARMAddressingModes.h"
14 #include "Thumb2InstrInfo.h"
15 #include "llvm/ADT/DenseMap.h"
16 #include "llvm/ADT/PostOrderIterator.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineInstr.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/IR/Function.h" // To access Function attributes
22 #include "llvm/Support/CommandLine.h"
23 #include "llvm/Support/Debug.h"
24 #include "llvm/Support/raw_ostream.h"
25 #include "llvm/Target/TargetMachine.h"
28 #define DEBUG_TYPE "t2-reduce-size"
30 STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones");
31 STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones");
32 STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones");
34 static cl::opt<int> ReduceLimit("t2-reduce-limit",
35 cl::init(-1), cl::Hidden);
36 static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2",
37 cl::init(-1), cl::Hidden);
38 static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3",
39 cl::init(-1), cl::Hidden);
42 /// ReduceTable - A static table with information on mapping from wide
45 uint16_t WideOpc; // Wide opcode
46 uint16_t NarrowOpc1; // Narrow opcode to transform to
47 uint16_t NarrowOpc2; // Narrow opcode when it's two-address
48 uint8_t Imm1Limit; // Limit of immediate field (bits)
49 uint8_t Imm2Limit; // Limit of immediate field when it's two-address
50 unsigned LowRegs1 : 1; // Only possible if low-registers are used
51 unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr)
52 unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa.
54 // 2 - Always set CPSR.
56 unsigned PartFlag : 1; // 16-bit instruction does partial flag update
57 unsigned Special : 1; // Needs to be dealt with specially
58 unsigned AvoidMovs: 1; // Avoid movs with shifter operand (for Swift)
61 static const ReduceEntry ReduceTable[] = {
62 // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C,PF,S,AM
63 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0,0,0 },
64 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0,1,0 },
65 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0,0,0 },
66 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 0,1,0 },
67 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
68 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 1,0,0 },
69 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
70 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
71 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 1,0,0 },
72 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
73 //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
74 { ARM::t2CMNzrr, ARM::tCMNz, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
75 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0,0,0 },
76 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 0,1,0 },
77 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 1,0,0 },
78 // FIXME: adr.n immediate offset must be multiple of 4.
79 //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
80 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
81 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 1,0,1 },
82 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 1,0,1 },
83 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 1,0,1 },
84 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,0,0 },
85 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1,1,0 },
86 // FIXME: Do we need the 16-bit 'S' variant?
87 { ARM::t2MOVr,ARM::tMOVr, 0, 0, 0, 0, 0, 1,0, 0,0,0 },
88 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 1,0,0 },
89 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
90 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 1,0,0 },
91 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
92 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
93 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0,0,0 },
94 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 1,0,0 },
95 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
96 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 0,1,0 },
97 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0,0,0 },
98 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0,0,0 },
99 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0,0,0 },
100 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0,0,0 },
101 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
102 { ARM::t2SXTB, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
103 { ARM::t2SXTH, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
104 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0,0,0 },
105 { ARM::t2UXTB, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
106 { ARM::t2UXTH, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0,1,0 },
108 // FIXME: Clean this up after splitting each Thumb load / store opcode
109 // into multiple ones.
110 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
111 { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
112 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
113 { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
114 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
115 { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
116 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
117 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
118 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 0,1,0 },
119 { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
120 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
121 { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
122 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 0,1,0 },
123 { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 0,1,0 },
125 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
126 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 0,1,0 },
127 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 0,1,0 },
128 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent
129 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 0,1,0 },
130 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 0,1,0 }
133 class Thumb2SizeReduce : public MachineFunctionPass {
136 Thumb2SizeReduce(std::function<bool(const Function &)> Ftor);
138 const Thumb2InstrInfo *TII;
139 const ARMSubtarget *STI;
141 bool runOnMachineFunction(MachineFunction &MF) override;
143 const char *getPassName() const override {
144 return "Thumb2 instruction size reduction pass";
148 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable.
149 DenseMap<unsigned, unsigned> ReduceOpcodeMap;
151 bool canAddPseudoFlagDep(MachineInstr *Use, bool IsSelfLoop);
153 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
154 bool is2Addr, ARMCC::CondCodes Pred,
155 bool LiveCPSR, bool &HasCC, bool &CCDead);
157 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
158 const ReduceEntry &Entry);
160 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
161 const ReduceEntry &Entry, bool LiveCPSR, bool IsSelfLoop);
163 /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address
165 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
166 const ReduceEntry &Entry, bool LiveCPSR,
169 /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit
170 /// non-two-address instruction.
171 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
172 const ReduceEntry &Entry, bool LiveCPSR,
175 /// ReduceMI - Attempt to reduce MI, return true on success.
176 bool ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI,
177 bool LiveCPSR, bool IsSelfLoop);
179 /// ReduceMBB - Reduce width of instructions in the specified basic block.
180 bool ReduceMBB(MachineBasicBlock &MBB);
185 // Last instruction to define CPSR in the current block.
186 MachineInstr *CPSRDef;
187 // Was CPSR last defined by a high latency instruction?
188 // When CPSRDef is null, this refers to CPSR defs in predecessors.
189 bool HighLatencyCPSR;
192 // The flags leaving this block have high latency.
193 bool HighLatencyCPSR;
194 // Has this block been visited yet?
197 MBBInfo() : HighLatencyCPSR(false), Visited(false) {}
200 SmallVector<MBBInfo, 8> BlockInfo;
202 std::function<bool(const Function &)> PredicateFtor;
204 char Thumb2SizeReduce::ID = 0;
207 Thumb2SizeReduce::Thumb2SizeReduce(std::function<bool(const Function &)> Ftor)
208 : MachineFunctionPass(ID), PredicateFtor(Ftor) {
209 OptimizeSize = MinimizeSize = false;
210 for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) {
211 unsigned FromOpc = ReduceTable[i].WideOpc;
212 if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second)
213 assert(false && "Duplicated entries?");
217 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) {
218 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs)
219 if (*Regs == ARM::CPSR)
224 // Check for a likely high-latency flag def.
225 static bool isHighLatencyCPSR(MachineInstr *Def) {
226 switch(Def->getOpcode()) {
234 /// canAddPseudoFlagDep - For A9 (and other out-of-order) implementations,
235 /// the 's' 16-bit instruction partially update CPSR. Abort the
236 /// transformation to avoid adding false dependency on last CPSR setting
237 /// instruction which hurts the ability for out-of-order execution engine
238 /// to do register renaming magic.
239 /// This function checks if there is a read-of-write dependency between the
240 /// last instruction that defines the CPSR and the current instruction. If there
241 /// is, then there is no harm done since the instruction cannot be retired
242 /// before the CPSR setting instruction anyway.
243 /// Note, we are not doing full dependency analysis here for the sake of compile
244 /// time. We're not looking for cases like:
246 /// r1 = add.w r0, ...
249 /// In this case it would have been ok to narrow the mul.w to muls since there
250 /// are indirect RAW dependency between the muls and the mul.w
252 Thumb2SizeReduce::canAddPseudoFlagDep(MachineInstr *Use, bool FirstInSelfLoop) {
253 // Disable the check for -Oz (aka OptimizeForSizeHarder).
254 if (MinimizeSize || !STI->avoidCPSRPartialUpdate())
258 // If this BB loops back to itself, conservatively avoid narrowing the
259 // first instruction that does partial flag update.
260 return HighLatencyCPSR || FirstInSelfLoop;
262 SmallSet<unsigned, 2> Defs;
263 for (const MachineOperand &MO : CPSRDef->operands()) {
264 if (!MO.isReg() || MO.isUndef() || MO.isUse())
266 unsigned Reg = MO.getReg();
267 if (Reg == 0 || Reg == ARM::CPSR)
272 for (const MachineOperand &MO : Use->operands()) {
273 if (!MO.isReg() || MO.isUndef() || MO.isDef())
275 unsigned Reg = MO.getReg();
280 // If the current CPSR has high latency, try to avoid the false dependency.
284 // tMOVi8 usually doesn't start long dependency chains, and there are a lot
285 // of them, so always shrink them when CPSR doesn't have high latency.
286 if (Use->getOpcode() == ARM::t2MOVi ||
287 Use->getOpcode() == ARM::t2MOVi16)
290 // No read-after-write dependency. The narrowing will add false dependency.
295 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
296 bool is2Addr, ARMCC::CondCodes Pred,
297 bool LiveCPSR, bool &HasCC, bool &CCDead) {
298 if ((is2Addr && Entry.PredCC2 == 0) ||
299 (!is2Addr && Entry.PredCC1 == 0)) {
300 if (Pred == ARMCC::AL) {
301 // Not predicated, must set CPSR.
303 // Original instruction was not setting CPSR, but CPSR is not
304 // currently live anyway. It's ok to set it. The CPSR def is
314 // Predicated, must not set CPSR.
318 } else if ((is2Addr && Entry.PredCC2 == 2) ||
319 (!is2Addr && Entry.PredCC1 == 2)) {
320 /// Old opcode has an optional def of CPSR.
323 // If old opcode does not implicitly define CPSR, then it's not ok since
324 // these new opcodes' CPSR def is not meant to be thrown away. e.g. CMP.
325 if (!HasImplicitCPSRDef(MI->getDesc()))
329 // 16-bit instruction does not set CPSR.
337 static bool VerifyLowRegs(MachineInstr *MI) {
338 unsigned Opc = MI->getOpcode();
339 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA_UPD);
340 bool isLROk = (Opc == ARM::t2STMDB_UPD);
341 bool isSPOk = isPCOk || isLROk;
342 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
343 const MachineOperand &MO = MI->getOperand(i);
344 if (!MO.isReg() || MO.isImplicit())
346 unsigned Reg = MO.getReg();
347 if (Reg == 0 || Reg == ARM::CPSR)
349 if (isPCOk && Reg == ARM::PC)
351 if (isLROk && Reg == ARM::LR)
353 if (Reg == ARM::SP) {
356 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12))
357 // Special case for these ldr / str with sp as base register.
360 if (!isARMLowRegister(Reg))
367 Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
368 const ReduceEntry &Entry) {
369 if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt))
373 bool HasImmOffset = false;
374 bool HasShift = false;
375 bool HasOffReg = true;
376 bool isLdStMul = false;
377 unsigned Opc = Entry.NarrowOpc1;
378 unsigned OpNum = 3; // First 'rest' of operands.
379 uint8_t ImmLimit = Entry.Imm1Limit;
381 switch (Entry.WideOpc) {
383 llvm_unreachable("Unexpected Thumb2 load / store opcode!");
386 if (MI->getOperand(1).getReg() == ARM::SP) {
387 Opc = Entry.NarrowOpc2;
388 ImmLimit = Entry.Imm2Limit;
418 unsigned BaseReg = MI->getOperand(0).getReg();
419 assert(isARMLowRegister(BaseReg));
421 // For the non-writeback version (this one), the base register must be
422 // one of the registers being loaded.
424 for (unsigned i = 3; i < MI->getNumOperands(); ++i) {
425 if (MI->getOperand(i).getReg() == BaseReg) {
438 case ARM::t2LDMIA_RET: {
439 unsigned BaseReg = MI->getOperand(1).getReg();
440 if (BaseReg != ARM::SP)
442 Opc = Entry.NarrowOpc2; // tPOP_RET
447 case ARM::t2LDMIA_UPD:
448 case ARM::t2STMIA_UPD:
449 case ARM::t2STMDB_UPD: {
452 unsigned BaseReg = MI->getOperand(1).getReg();
453 if (BaseReg == ARM::SP &&
454 (Entry.WideOpc == ARM::t2LDMIA_UPD ||
455 Entry.WideOpc == ARM::t2STMDB_UPD)) {
456 Opc = Entry.NarrowOpc2; // tPOP or tPUSH
458 } else if (!isARMLowRegister(BaseReg) ||
459 (Entry.WideOpc != ARM::t2LDMIA_UPD &&
460 Entry.WideOpc != ARM::t2STMIA_UPD)) {
469 unsigned OffsetReg = 0;
470 bool OffsetKill = false;
471 bool OffsetInternal = false;
473 OffsetReg = MI->getOperand(2).getReg();
474 OffsetKill = MI->getOperand(2).isKill();
475 OffsetInternal = MI->getOperand(2).isInternalRead();
477 if (MI->getOperand(3).getImm())
478 // Thumb1 addressing mode doesn't support shift.
482 unsigned OffsetImm = 0;
484 OffsetImm = MI->getOperand(2).getImm();
485 unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale;
487 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset)
488 // Make sure the immediate field fits.
492 // Add the 16-bit load / store instruction.
493 DebugLoc dl = MI->getDebugLoc();
494 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
496 MIB.addOperand(MI->getOperand(0));
497 MIB.addOperand(MI->getOperand(1));
500 MIB.addImm(OffsetImm / Scale);
502 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!");
505 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
506 getInternalReadRegState(OffsetInternal));
509 // Transfer the rest of operands.
510 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum)
511 MIB.addOperand(MI->getOperand(OpNum));
513 // Transfer memoperands.
514 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
516 // Transfer MI flags.
517 MIB.setMIFlags(MI->getFlags());
519 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
527 Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
528 const ReduceEntry &Entry,
529 bool LiveCPSR, bool IsSelfLoop) {
530 unsigned Opc = MI->getOpcode();
531 if (Opc == ARM::t2ADDri) {
532 // If the source register is SP, try to reduce to tADDrSPi, otherwise
533 // it's a normal reduce.
534 if (MI->getOperand(1).getReg() != ARM::SP) {
535 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
537 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
539 // Try to reduce to tADDrSPi.
540 unsigned Imm = MI->getOperand(2).getImm();
541 // The immediate must be in range, the destination register must be a low
542 // reg, the predicate must be "always" and the condition flags must not
544 if (Imm & 3 || Imm > 1020)
546 if (!isARMLowRegister(MI->getOperand(0).getReg()))
548 if (MI->getOperand(3).getImm() != ARMCC::AL)
550 const MCInstrDesc &MCID = MI->getDesc();
551 if (MCID.hasOptionalDef() &&
552 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
555 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(),
556 TII->get(ARM::tADDrSPi))
557 .addOperand(MI->getOperand(0))
558 .addOperand(MI->getOperand(1))
559 .addImm(Imm / 4); // The tADDrSPi has an implied scale by four.
562 // Transfer MI flags.
563 MIB.setMIFlags(MI->getFlags());
565 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " <<*MIB);
572 if (Entry.LowRegs1 && !VerifyLowRegs(MI))
575 if (MI->mayLoadOrStore())
576 return ReduceLoadStore(MBB, MI, Entry);
581 case ARM::t2ADDSrr: {
582 unsigned PredReg = 0;
583 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) {
586 case ARM::t2ADDSri: {
587 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
592 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
603 if (MI->getOperand(2).getImm() == 0)
604 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
607 // Can convert only 'pure' immediate operands, not immediates obtained as
608 // globals' addresses.
609 if (MI->getOperand(1).isImm())
610 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
613 // Try to reduce to the lo-reg only version first. Why there are two
614 // versions of the instruction is a mystery.
615 // It would be nice to just have two entries in the master table that
616 // are prioritized, but the table assumes a unique entry for each
617 // source insn opcode. So for now, we hack a local entry record to use.
618 static const ReduceEntry NarrowEntry =
619 { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 0,1,0 };
620 if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR, IsSelfLoop))
622 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
629 Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
630 const ReduceEntry &Entry,
631 bool LiveCPSR, bool IsSelfLoop) {
633 if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr))
636 if (!MinimizeSize && !OptimizeSize && Entry.AvoidMovs &&
637 STI->avoidMOVsShifterOperand())
638 // Don't issue movs with shifter operand for some CPUs unless we
639 // are optimizing / minimizing for size.
642 unsigned Reg0 = MI->getOperand(0).getReg();
643 unsigned Reg1 = MI->getOperand(1).getReg();
644 // t2MUL is "special". The tied source operand is second, not first.
645 if (MI->getOpcode() == ARM::t2MUL) {
646 unsigned Reg2 = MI->getOperand(2).getReg();
647 // Early exit if the regs aren't all low regs.
648 if (!isARMLowRegister(Reg0) || !isARMLowRegister(Reg1)
649 || !isARMLowRegister(Reg2))
652 // If the other operand also isn't the same as the destination, we
656 // Try to commute the operands to make it a 2-address instruction.
657 MachineInstr *CommutedMI = TII->commuteInstruction(MI);
661 } else if (Reg0 != Reg1) {
662 // Try to commute the operands to make it a 2-address instruction.
663 unsigned CommOpIdx1, CommOpIdx2;
664 if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) ||
665 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0)
667 MachineInstr *CommutedMI = TII->commuteInstruction(MI);
671 if (Entry.LowRegs2 && !isARMLowRegister(Reg0))
673 if (Entry.Imm2Limit) {
674 unsigned Imm = MI->getOperand(2).getImm();
675 unsigned Limit = (1 << Entry.Imm2Limit) - 1;
679 unsigned Reg2 = MI->getOperand(2).getReg();
680 if (Entry.LowRegs2 && !isARMLowRegister(Reg2))
684 // Check if it's possible / necessary to transfer the predicate.
685 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2);
686 unsigned PredReg = 0;
687 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
688 bool SkipPred = false;
689 if (Pred != ARMCC::AL) {
690 if (!NewMCID.isPredicable())
691 // Can't transfer predicate, fail.
694 SkipPred = !NewMCID.isPredicable();
699 const MCInstrDesc &MCID = MI->getDesc();
700 if (MCID.hasOptionalDef()) {
701 unsigned NumOps = MCID.getNumOperands();
702 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
703 if (HasCC && MI->getOperand(NumOps-1).isDead())
706 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead))
709 // Avoid adding a false dependency on partial flag update by some 16-bit
710 // instructions which has the 's' bit set.
711 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
712 canAddPseudoFlagDep(MI, IsSelfLoop))
715 // Add the 16-bit instruction.
716 DebugLoc dl = MI->getDebugLoc();
717 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
718 MIB.addOperand(MI->getOperand(0));
719 if (NewMCID.hasOptionalDef()) {
721 AddDefaultT1CC(MIB, CCDead);
726 // Transfer the rest of operands.
727 unsigned NumOps = MCID.getNumOperands();
728 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
729 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
731 if (SkipPred && MCID.OpInfo[i].isPredicate())
733 MIB.addOperand(MI->getOperand(i));
736 // Transfer MI flags.
737 MIB.setMIFlags(MI->getFlags());
739 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
747 Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
748 const ReduceEntry &Entry,
749 bool LiveCPSR, bool IsSelfLoop) {
750 if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit))
753 if (!MinimizeSize && !OptimizeSize && Entry.AvoidMovs &&
754 STI->avoidMOVsShifterOperand())
755 // Don't issue movs with shifter operand for some CPUs unless we
756 // are optimizing / minimizing for size.
759 unsigned Limit = ~0U;
761 Limit = (1 << Entry.Imm1Limit) - 1;
763 const MCInstrDesc &MCID = MI->getDesc();
764 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) {
765 if (MCID.OpInfo[i].isPredicate())
767 const MachineOperand &MO = MI->getOperand(i);
769 unsigned Reg = MO.getReg();
770 if (!Reg || Reg == ARM::CPSR)
772 if (Entry.LowRegs1 && !isARMLowRegister(Reg))
774 } else if (MO.isImm() &&
775 !MCID.OpInfo[i].isPredicate()) {
776 if (((unsigned)MO.getImm()) > Limit)
781 // Check if it's possible / necessary to transfer the predicate.
782 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1);
783 unsigned PredReg = 0;
784 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
785 bool SkipPred = false;
786 if (Pred != ARMCC::AL) {
787 if (!NewMCID.isPredicable())
788 // Can't transfer predicate, fail.
791 SkipPred = !NewMCID.isPredicable();
796 if (MCID.hasOptionalDef()) {
797 unsigned NumOps = MCID.getNumOperands();
798 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
799 if (HasCC && MI->getOperand(NumOps-1).isDead())
802 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead))
805 // Avoid adding a false dependency on partial flag update by some 16-bit
806 // instructions which has the 's' bit set.
807 if (Entry.PartFlag && NewMCID.hasOptionalDef() && HasCC &&
808 canAddPseudoFlagDep(MI, IsSelfLoop))
811 // Add the 16-bit instruction.
812 DebugLoc dl = MI->getDebugLoc();
813 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
814 MIB.addOperand(MI->getOperand(0));
815 if (NewMCID.hasOptionalDef()) {
817 AddDefaultT1CC(MIB, CCDead);
822 // Transfer the rest of operands.
823 unsigned NumOps = MCID.getNumOperands();
824 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
825 if (i < NumOps && MCID.OpInfo[i].isOptionalDef())
827 if ((MCID.getOpcode() == ARM::t2RSBSri ||
828 MCID.getOpcode() == ARM::t2RSBri ||
829 MCID.getOpcode() == ARM::t2SXTB ||
830 MCID.getOpcode() == ARM::t2SXTH ||
831 MCID.getOpcode() == ARM::t2UXTB ||
832 MCID.getOpcode() == ARM::t2UXTH) && i == 2)
833 // Skip the zero immediate operand, it's now implicit.
835 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate());
836 if (SkipPred && isPred)
838 const MachineOperand &MO = MI->getOperand(i);
839 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
840 // Skip implicit def of CPSR. Either it's modeled as an optional
841 // def now or it's already an implicit def on the new instruction.
845 if (!MCID.isPredicable() && NewMCID.isPredicable())
848 // Transfer MI flags.
849 MIB.setMIFlags(MI->getFlags());
851 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB);
858 static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR, bool &DefCPSR) {
860 for (const MachineOperand &MO : MI.operands()) {
861 if (!MO.isReg() || MO.isUndef() || MO.isUse())
863 if (MO.getReg() != ARM::CPSR)
871 return HasDef || LiveCPSR;
874 static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) {
875 for (const MachineOperand &MO : MI.operands()) {
876 if (!MO.isReg() || MO.isUndef() || MO.isDef())
878 if (MO.getReg() != ARM::CPSR)
880 assert(LiveCPSR && "CPSR liveness tracking is wrong!");
890 bool Thumb2SizeReduce::ReduceMI(MachineBasicBlock &MBB, MachineInstr *MI,
891 bool LiveCPSR, bool IsSelfLoop) {
892 unsigned Opcode = MI->getOpcode();
893 DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode);
894 if (OPI == ReduceOpcodeMap.end())
896 const ReduceEntry &Entry = ReduceTable[OPI->second];
898 // Don't attempt normal reductions on "special" cases for now.
900 return ReduceSpecial(MBB, MI, Entry, LiveCPSR, IsSelfLoop);
902 // Try to transform to a 16-bit two-address instruction.
903 if (Entry.NarrowOpc2 &&
904 ReduceTo2Addr(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
907 // Try to transform to a 16-bit non-two-address instruction.
908 if (Entry.NarrowOpc1 &&
909 ReduceToNarrow(MBB, MI, Entry, LiveCPSR, IsSelfLoop))
915 bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) {
916 bool Modified = false;
918 // Yes, CPSR could be livein.
919 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR);
920 MachineInstr *BundleMI = nullptr;
923 HighLatencyCPSR = false;
925 // Check predecessors for the latest CPSRDef.
926 for (auto *Pred : MBB.predecessors()) {
927 const MBBInfo &PInfo = BlockInfo[Pred->getNumber()];
928 if (!PInfo.Visited) {
929 // Since blocks are visited in RPO, this must be a back-edge.
932 if (PInfo.HighLatencyCPSR) {
933 HighLatencyCPSR = true;
938 // If this BB loops back to itself, conservatively avoid narrowing the
939 // first instruction that does partial flag update.
940 bool IsSelfLoop = MBB.isSuccessor(&MBB);
941 MachineBasicBlock::instr_iterator MII = MBB.instr_begin(),E = MBB.instr_end();
942 MachineBasicBlock::instr_iterator NextMII;
943 for (; MII != E; MII = NextMII) {
944 NextMII = std::next(MII);
946 MachineInstr *MI = &*MII;
947 if (MI->isBundle()) {
951 if (MI->isDebugValue())
954 LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR);
956 // Does NextMII belong to the same bundle as MI?
957 bool NextInSameBundle = NextMII != E && NextMII->isBundledWithPred();
959 if (ReduceMI(MBB, MI, LiveCPSR, IsSelfLoop)) {
961 MachineBasicBlock::instr_iterator I = std::prev(NextMII);
963 // Removing and reinserting the first instruction in a bundle will break
964 // up the bundle. Fix the bundling if it was broken.
965 if (NextInSameBundle && !NextMII->isBundledWithPred())
966 NextMII->bundleWithPred();
969 if (!NextInSameBundle && MI->isInsideBundle()) {
970 // FIXME: Since post-ra scheduler operates on bundles, the CPSR kill
971 // marker is only on the BUNDLE instruction. Process the BUNDLE
972 // instruction as we finish with the bundled instruction to work around
973 // the inconsistency.
974 if (BundleMI->killsRegister(ARM::CPSR))
976 MachineOperand *MO = BundleMI->findRegisterDefOperand(ARM::CPSR);
977 if (MO && !MO->isDead())
979 MO = BundleMI->findRegisterUseOperand(ARM::CPSR);
980 if (MO && !MO->isKill())
984 bool DefCPSR = false;
985 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR, DefCPSR);
987 // Calls don't really set CPSR.
989 HighLatencyCPSR = false;
991 } else if (DefCPSR) {
992 // This is the last CPSR defining instruction.
994 HighLatencyCPSR = isHighLatencyCPSR(CPSRDef);
999 MBBInfo &Info = BlockInfo[MBB.getNumber()];
1000 Info.HighLatencyCPSR = HighLatencyCPSR;
1001 Info.Visited = true;
1005 bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) {
1006 if (PredicateFtor && !PredicateFtor(*MF.getFunction()))
1009 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1010 if (STI->isThumb1Only() || STI->prefers32BitThumb())
1013 TII = static_cast<const Thumb2InstrInfo *>(STI->getInstrInfo());
1015 // Optimizing / minimizing size?
1016 OptimizeSize = MF.getFunction()->hasFnAttribute(Attribute::OptimizeForSize);
1017 MinimizeSize = MF.getFunction()->hasFnAttribute(Attribute::MinSize);
1020 BlockInfo.resize(MF.getNumBlockIDs());
1022 // Visit blocks in reverse post-order so LastCPSRDef is known for all
1024 ReversePostOrderTraversal<MachineFunction*> RPOT(&MF);
1025 bool Modified = false;
1026 for (ReversePostOrderTraversal<MachineFunction*>::rpo_iterator
1027 I = RPOT.begin(), E = RPOT.end(); I != E; ++I)
1028 Modified |= ReduceMBB(**I);
1032 /// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size
1034 FunctionPass *llvm::createThumb2SizeReductionPass(
1035 std::function<bool(const Function &)> Ftor) {
1036 return new Thumb2SizeReduce(Ftor);