1 //===- ARM64.td - Describe the ARM64 Target Machine --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM64 Subtarget features.
23 /// Cyclone has register move instructions which are "free".
24 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
25 "Has zereo-cycle register moves">;
27 /// Cyclone has instructions which zero registers for "free".
28 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
29 "Has zero-cycle zeroing instructions">;
31 //===----------------------------------------------------------------------===//
32 // Register File Description
33 //===----------------------------------------------------------------------===//
35 include "ARM64RegisterInfo.td"
36 include "ARM64CallingConvention.td"
38 //===----------------------------------------------------------------------===//
39 // Instruction Descriptions
40 //===----------------------------------------------------------------------===//
42 include "ARM64Schedule.td"
43 include "ARM64InstrInfo.td"
45 def ARM64InstrInfo : InstrInfo;
47 //===----------------------------------------------------------------------===//
48 // ARM64 Processors supported.
50 include "ARM64SchedCyclone.td"
52 def : ProcessorModel<"arm64-generic", NoSchedModel, []>;
54 def : ProcessorModel<"cyclone", CycloneModel, [FeatureZCRegMove, FeatureZCZeroing]>;
56 //===----------------------------------------------------------------------===//
58 //===----------------------------------------------------------------------===//
60 def GenericAsmParserVariant : AsmParserVariant {
62 string Name = "generic";
65 def AppleAsmParserVariant : AsmParserVariant {
67 string Name = "apple-neon";
70 //===----------------------------------------------------------------------===//
72 //===----------------------------------------------------------------------===//
73 // ARM64 Uses the MC printer for asm output, so make sure the TableGen
74 // AsmWriter bits get associated with the correct class.
75 def GenericAsmWriter : AsmWriter {
76 string AsmWriterClassName = "InstPrinter";
78 bit isMCAsmWriter = 1;
81 def AppleAsmWriter : AsmWriter {
82 let AsmWriterClassName = "AppleInstPrinter";
84 int isMCAsmWriter = 1;
87 //===----------------------------------------------------------------------===//
89 //===----------------------------------------------------------------------===//
92 let InstructionSet = ARM64InstrInfo;
93 let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
94 let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];