lib/Target/ARM64/ARM64.td

   1 //===- ARM64.td - Describe the ARM64 Target Machine --------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM64 Subtarget features.
  21 //
  22
  23 /// Cyclone has register move instructions which are "free".
  24 def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true",
  25                                         "Has zereo-cycle register moves">;
  26
  27 /// Cyclone has instructions which zero registers for "free".
  28 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
  29                                         "Has zero-cycle zeroing instructions">;
  30
  31 //===----------------------------------------------------------------------===//
  32 // Register File Description
  33 //===----------------------------------------------------------------------===//
  34
  35 include "ARM64RegisterInfo.td"
  36 include "ARM64CallingConvention.td"
  37
  38 //===----------------------------------------------------------------------===//
  39 // Instruction Descriptions
  40 //===----------------------------------------------------------------------===//
  41
  42 include "ARM64Schedule.td"
  43 include "ARM64InstrInfo.td"
  44
  45 def ARM64InstrInfo : InstrInfo;
  46
  47 //===----------------------------------------------------------------------===//
  48 // ARM64 Processors supported.
  49 //
  50 include "ARM64SchedCyclone.td"
  51
  52 def : ProcessorModel<"arm64-generic", NoSchedModel, []>;
  53
  54 def : ProcessorModel<"cyclone", CycloneModel, [FeatureZCRegMove, FeatureZCZeroing]>;
  55
  56 //===----------------------------------------------------------------------===//
  57 // Assembly parser
  58 //===----------------------------------------------------------------------===//
  59
  60 def GenericAsmParserVariant : AsmParserVariant {
  61   int Variant = 0;
  62   string Name = "generic";
  63 }
  64
  65 def AppleAsmParserVariant : AsmParserVariant {
  66   int Variant = 1;
  67   string Name = "apple-neon";
  68 }
  69
  70 //===----------------------------------------------------------------------===//
  71 // Assembly printer
  72 //===----------------------------------------------------------------------===//
  73 // ARM64 Uses the MC printer for asm output, so make sure the TableGen
  74 // AsmWriter bits get associated with the correct class.
  75 def GenericAsmWriter : AsmWriter {
  76   string AsmWriterClassName  = "InstPrinter";
  77   int Variant = 0;
  78   bit isMCAsmWriter = 1;
  79 }
  80
  81 def AppleAsmWriter : AsmWriter {
  82   let AsmWriterClassName = "AppleInstPrinter";
  83   int Variant = 1;
  84   int isMCAsmWriter = 1;
  85 }
  86
  87 //===----------------------------------------------------------------------===//
  88 // Target Declaration
  89 //===----------------------------------------------------------------------===//
  90
  91 def ARM64 : Target {
  92   let InstructionSet = ARM64InstrInfo;
  93   let AssemblyParserVariants = [GenericAsmParserVariant, AppleAsmParserVariant];
  94   let AssemblyWriters = [GenericAsmWriter, AppleAsmWriter];
  95 }