1 //===-- ARM64AsmPrinter.cpp - ARM64 LLVM assembly writer ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to the ARM64 assembly language.
13 //===----------------------------------------------------------------------===//
16 #include "ARM64MachineFunctionInfo.h"
17 #include "ARM64MCInstLower.h"
18 #include "ARM64RegisterInfo.h"
19 #include "ARM64Subtarget.h"
20 #include "InstPrinter/ARM64InstPrinter.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Twine.h"
24 #include "llvm/CodeGen/AsmPrinter.h"
25 #include "llvm/CodeGen/MachineInstr.h"
26 #include "llvm/CodeGen/StackMaps.h"
27 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/DataLayout.h"
30 #include "llvm/IR/DebugInfo.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCContext.h"
33 #include "llvm/MC/MCInst.h"
34 #include "llvm/MC/MCInstBuilder.h"
35 #include "llvm/MC/MCLinkerOptimizationHint.h"
36 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/Support/Debug.h"
38 #include "llvm/Support/TargetRegistry.h"
41 #define DEBUG_TYPE "asm-printer"
45 class ARM64AsmPrinter : public AsmPrinter {
46 /// Subtarget - Keep a pointer to the ARM64Subtarget around so that we can
47 /// make the right decision when printing asm code for different targets.
48 const ARM64Subtarget *Subtarget;
50 ARM64MCInstLower MCInstLowering;
54 ARM64AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
55 : AsmPrinter(TM, Streamer), Subtarget(&TM.getSubtarget<ARM64Subtarget>()),
56 MCInstLowering(OutContext, *Mang, *this), SM(*this), ARM64FI(NULL),
59 virtual const char *getPassName() const { return "ARM64 Assembly Printer"; }
61 /// \brief Wrapper for MCInstLowering.lowerOperand() for the
62 /// tblgen'erated pseudo lowering.
63 bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
64 return MCInstLowering.lowerOperand(MO, MCOp);
67 void LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
68 const MachineInstr &MI);
69 void LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
70 const MachineInstr &MI);
71 /// \brief tblgen'erated driver function for lowering simple MI->MC
72 /// pseudo instructions.
73 bool emitPseudoExpansionLowering(MCStreamer &OutStreamer,
74 const MachineInstr *MI);
76 void EmitInstruction(const MachineInstr *MI);
78 void getAnalysisUsage(AnalysisUsage &AU) const {
79 AsmPrinter::getAnalysisUsage(AU);
83 bool runOnMachineFunction(MachineFunction &F) {
84 ARM64FI = F.getInfo<ARM64FunctionInfo>();
85 return AsmPrinter::runOnMachineFunction(F);
89 MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
90 void printOperand(const MachineInstr *MI, unsigned OpNum, raw_ostream &O);
91 bool printAsmMRegister(const MachineOperand &MO, char Mode, raw_ostream &O);
92 bool printAsmRegInClass(const MachineOperand &MO,
93 const TargetRegisterClass *RC, bool isVector,
96 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
97 unsigned AsmVariant, const char *ExtraCode,
99 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
100 unsigned AsmVariant, const char *ExtraCode,
103 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
105 void EmitFunctionBodyEnd();
107 MCSymbol *GetCPISymbol(unsigned CPID) const;
108 void EmitEndOfAsmFile(Module &M);
109 ARM64FunctionInfo *ARM64FI;
111 /// \brief Emit the LOHs contained in ARM64FI.
114 typedef std::map<const MachineInstr *, MCSymbol *> MInstToMCSymbol;
115 MInstToMCSymbol LOHInstToLabel;
116 unsigned LOHLabelCounter;
119 } // end of anonymous namespace
121 //===----------------------------------------------------------------------===//
123 void ARM64AsmPrinter::EmitEndOfAsmFile(Module &M) {
124 if (Subtarget->isTargetMachO()) {
125 // Funny Darwin hack: This flag tells the linker that no global symbols
126 // contain code that falls through to other global symbols (e.g. the obvious
127 // implementation of multiple entry points). If this doesn't occur, the
128 // linker can safely perform dead code stripping. Since LLVM never
129 // generates code that does this, it is always safe to set.
130 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
131 SM.serializeToStackMapSection();
134 // Emit a .data.rel section containing any stubs that were created.
135 if (Subtarget->isTargetELF()) {
136 const TargetLoweringObjectFileELF &TLOFELF =
137 static_cast<const TargetLoweringObjectFileELF &>(getObjFileLowering());
139 MachineModuleInfoELF &MMIELF = MMI->getObjFileInfo<MachineModuleInfoELF>();
141 // Output stubs for external and common global variables.
142 MachineModuleInfoELF::SymbolListTy Stubs = MMIELF.GetGVStubList();
143 if (!Stubs.empty()) {
144 OutStreamer.SwitchSection(TLOFELF.getDataRelSection());
145 const DataLayout *TD = TM.getDataLayout();
147 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
148 OutStreamer.EmitLabel(Stubs[i].first);
149 OutStreamer.EmitSymbolValue(Stubs[i].second.getPointer(),
150 TD->getPointerSize(0));
159 ARM64AsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
160 MachineLocation Location;
161 assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
162 // Frame address. Currently handles register +- offset only.
163 if (MI->getOperand(0).isReg() && MI->getOperand(1).isImm())
164 Location.set(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
166 DEBUG(dbgs() << "DBG_VALUE instruction ignored! " << *MI << "\n");
171 void ARM64AsmPrinter::EmitLOHs() {
172 SmallVector<MCSymbol *, 3> MCArgs;
174 for (const auto &D : ARM64FI->getLOHContainer()) {
175 for (const MachineInstr *MI : D.getArgs()) {
176 MInstToMCSymbol::iterator LabelIt = LOHInstToLabel.find(MI);
177 assert(LabelIt != LOHInstToLabel.end() &&
178 "Label hasn't been inserted for LOH related instruction");
179 MCArgs.push_back(LabelIt->second);
181 OutStreamer.EmitLOHDirective(D.getKind(), MCArgs);
186 void ARM64AsmPrinter::EmitFunctionBodyEnd() {
187 if (!ARM64FI->getLOHRelated().empty())
191 /// GetCPISymbol - Return the symbol for the specified constant pool entry.
192 MCSymbol *ARM64AsmPrinter::GetCPISymbol(unsigned CPID) const {
193 // Darwin uses a linker-private symbol name for constant-pools (to
194 // avoid addends on the relocation?), ELF has no such concept and
195 // uses a normal private symbol.
196 if (getDataLayout().getLinkerPrivateGlobalPrefix()[0])
197 return OutContext.GetOrCreateSymbol(
198 Twine(getDataLayout().getLinkerPrivateGlobalPrefix()) + "CPI" +
199 Twine(getFunctionNumber()) + "_" + Twine(CPID));
201 return OutContext.GetOrCreateSymbol(
202 Twine(getDataLayout().getPrivateGlobalPrefix()) + "CPI" +
203 Twine(getFunctionNumber()) + "_" + Twine(CPID));
206 void ARM64AsmPrinter::printOperand(const MachineInstr *MI, unsigned OpNum,
208 const MachineOperand &MO = MI->getOperand(OpNum);
209 switch (MO.getType()) {
211 assert(0 && "<unknown operand type>");
212 case MachineOperand::MO_Register: {
213 unsigned Reg = MO.getReg();
214 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
215 assert(!MO.getSubReg() && "Subregs should be eliminated!");
216 O << ARM64InstPrinter::getRegisterName(Reg);
219 case MachineOperand::MO_Immediate: {
220 int64_t Imm = MO.getImm();
227 bool ARM64AsmPrinter::printAsmMRegister(const MachineOperand &MO, char Mode,
229 unsigned Reg = MO.getReg();
232 return true; // Unknown mode.
234 Reg = getWRegFromXReg(Reg);
237 Reg = getXRegFromWReg(Reg);
241 O << ARM64InstPrinter::getRegisterName(Reg);
245 // Prints the register in MO using class RC using the offset in the
246 // new register class. This should not be used for cross class
248 bool ARM64AsmPrinter::printAsmRegInClass(const MachineOperand &MO,
249 const TargetRegisterClass *RC,
250 bool isVector, raw_ostream &O) {
251 assert(MO.isReg() && "Should only get here with a register!");
252 const ARM64RegisterInfo *RI =
253 static_cast<const ARM64RegisterInfo *>(TM.getRegisterInfo());
254 unsigned Reg = MO.getReg();
255 unsigned RegToPrint = RC->getRegister(RI->getEncodingValue(Reg));
256 assert(RI->regsOverlap(RegToPrint, Reg));
257 O << ARM64InstPrinter::getRegisterName(
258 RegToPrint, isVector ? ARM64::vreg : ARM64::NoRegAltName);
262 bool ARM64AsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
264 const char *ExtraCode, raw_ostream &O) {
265 const MachineOperand &MO = MI->getOperand(OpNum);
266 // Does this asm operand have a single letter operand modifier?
267 if (ExtraCode && ExtraCode[0]) {
268 if (ExtraCode[1] != 0)
269 return true; // Unknown modifier.
271 switch (ExtraCode[0]) {
273 return true; // Unknown modifier.
274 case 'w': // Print W register
275 case 'x': // Print X register
277 return printAsmMRegister(MO, ExtraCode[0], O);
278 if (MO.isImm() && MO.getImm() == 0) {
279 unsigned Reg = ExtraCode[0] == 'w' ? ARM64::WZR : ARM64::XZR;
280 O << ARM64InstPrinter::getRegisterName(Reg);
283 printOperand(MI, OpNum, O);
285 case 'b': // Print B register.
286 case 'h': // Print H register.
287 case 's': // Print S register.
288 case 'd': // Print D register.
289 case 'q': // Print Q register.
291 const TargetRegisterClass *RC;
292 switch (ExtraCode[0]) {
294 RC = &ARM64::FPR8RegClass;
297 RC = &ARM64::FPR16RegClass;
300 RC = &ARM64::FPR32RegClass;
303 RC = &ARM64::FPR64RegClass;
306 RC = &ARM64::FPR128RegClass;
311 return printAsmRegInClass(MO, RC, false /* vector */, O);
313 printOperand(MI, OpNum, O);
318 // According to ARM, we should emit x and v registers unless we have a
321 unsigned Reg = MO.getReg();
323 // If this is a w or x register, print an x register.
324 if (ARM64::GPR32allRegClass.contains(Reg) ||
325 ARM64::GPR64allRegClass.contains(Reg))
326 return printAsmMRegister(MO, 'x', O);
328 // If this is a b, h, s, d, or q register, print it as a v register.
329 return printAsmRegInClass(MO, &ARM64::FPR128RegClass, true /* vector */, O);
332 printOperand(MI, OpNum, O);
336 bool ARM64AsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
337 unsigned OpNum, unsigned AsmVariant,
338 const char *ExtraCode,
340 if (ExtraCode && ExtraCode[0])
341 return true; // Unknown modifier.
343 const MachineOperand &MO = MI->getOperand(OpNum);
344 assert(MO.isReg() && "unexpected inline asm memory operand");
345 O << "[" << ARM64InstPrinter::getRegisterName(MO.getReg()) << "]";
349 void ARM64AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
351 unsigned NOps = MI->getNumOperands();
353 OS << '\t' << MAI->getCommentString() << "DEBUG_VALUE: ";
354 // cast away const; DIetc do not take const operands for some reason.
355 DIVariable V(const_cast<MDNode *>(MI->getOperand(NOps - 1).getMetadata()));
358 // Frame address. Currently handles register +- offset only.
359 assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm());
361 printOperand(MI, 0, OS);
363 printOperand(MI, 1, OS);
366 printOperand(MI, NOps - 2, OS);
369 void ARM64AsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM,
370 const MachineInstr &MI) {
371 unsigned NumNOPBytes = MI.getOperand(1).getImm();
373 SM.recordStackMap(MI);
375 assert(NumNOPBytes % 4 == 0 && "Invalid number of NOP bytes requested!");
376 for (unsigned i = 0; i < NumNOPBytes; i += 4)
377 EmitToStreamer(OutStreamer, MCInstBuilder(ARM64::HINT).addImm(0));
380 // Lower a patchpoint of the form:
381 // [<def>], <id>, <numBytes>, <target>, <numArgs>
382 void ARM64AsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM,
383 const MachineInstr &MI) {
384 SM.recordPatchPoint(MI);
386 PatchPointOpers Opers(&MI);
388 int64_t CallTarget = Opers.getMetaOper(PatchPointOpers::TargetPos).getImm();
389 unsigned EncodedBytes = 0;
391 assert((CallTarget & 0xFFFFFFFFFFFF) == CallTarget &&
392 "High 16 bits of call target should be zero.");
393 unsigned ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
395 // Materialize the jump address:
396 EmitToStreamer(OutStreamer, MCInstBuilder(ARM64::MOVZWi)
398 .addImm((CallTarget >> 32) & 0xFFFF)
400 EmitToStreamer(OutStreamer, MCInstBuilder(ARM64::MOVKWi)
403 .addImm((CallTarget >> 16) & 0xFFFF)
405 EmitToStreamer(OutStreamer, MCInstBuilder(ARM64::MOVKWi)
408 .addImm(CallTarget & 0xFFFF)
410 EmitToStreamer(OutStreamer, MCInstBuilder(ARM64::BLR).addReg(ScratchReg));
413 unsigned NumBytes = Opers.getMetaOper(PatchPointOpers::NBytesPos).getImm();
414 assert(NumBytes >= EncodedBytes &&
415 "Patchpoint can't request size less than the length of a call.");
416 assert((NumBytes - EncodedBytes) % 4 == 0 &&
417 "Invalid number of NOP bytes requested!");
418 for (unsigned i = EncodedBytes; i < NumBytes; i += 4)
419 EmitToStreamer(OutStreamer, MCInstBuilder(ARM64::HINT).addImm(0));
422 // Simple pseudo-instructions have their lowering (with expansion to real
423 // instructions) auto-generated.
424 #include "ARM64GenMCPseudoLowering.inc"
426 static unsigned getRealIndexedOpcode(unsigned Opc) {
428 case ARM64::LDRXpre_isel: return ARM64::LDRXpre;
429 case ARM64::LDRWpre_isel: return ARM64::LDRWpre;
430 case ARM64::LDRDpre_isel: return ARM64::LDRDpre;
431 case ARM64::LDRSpre_isel: return ARM64::LDRSpre;
432 case ARM64::LDRBBpre_isel: return ARM64::LDRBBpre;
433 case ARM64::LDRHHpre_isel: return ARM64::LDRHHpre;
434 case ARM64::LDRSBWpre_isel: return ARM64::LDRSBWpre;
435 case ARM64::LDRSBXpre_isel: return ARM64::LDRSBXpre;
436 case ARM64::LDRSHWpre_isel: return ARM64::LDRSHWpre;
437 case ARM64::LDRSHXpre_isel: return ARM64::LDRSHXpre;
438 case ARM64::LDRSWpre_isel: return ARM64::LDRSWpre;
440 case ARM64::LDRDpost_isel: return ARM64::LDRDpost;
441 case ARM64::LDRSpost_isel: return ARM64::LDRSpost;
442 case ARM64::LDRXpost_isel: return ARM64::LDRXpost;
443 case ARM64::LDRWpost_isel: return ARM64::LDRWpost;
444 case ARM64::LDRHHpost_isel: return ARM64::LDRHHpost;
445 case ARM64::LDRBBpost_isel: return ARM64::LDRBBpost;
446 case ARM64::LDRSWpost_isel: return ARM64::LDRSWpost;
447 case ARM64::LDRSHWpost_isel: return ARM64::LDRSHWpost;
448 case ARM64::LDRSHXpost_isel: return ARM64::LDRSHXpost;
449 case ARM64::LDRSBWpost_isel: return ARM64::LDRSBWpost;
450 case ARM64::LDRSBXpost_isel: return ARM64::LDRSBXpost;
452 case ARM64::STRXpre_isel: return ARM64::STRXpre;
453 case ARM64::STRWpre_isel: return ARM64::STRWpre;
454 case ARM64::STRHHpre_isel: return ARM64::STRHHpre;
455 case ARM64::STRBBpre_isel: return ARM64::STRBBpre;
456 case ARM64::STRDpre_isel: return ARM64::STRDpre;
457 case ARM64::STRSpre_isel: return ARM64::STRSpre;
459 llvm_unreachable("Unexpected pre-indexed opcode!");
462 void ARM64AsmPrinter::EmitInstruction(const MachineInstr *MI) {
463 // Do any auto-generated pseudo lowerings.
464 if (emitPseudoExpansionLowering(OutStreamer, MI))
467 if (ARM64FI->getLOHRelated().count(MI)) {
468 // Generate a label for LOH related instruction
469 MCSymbol *LOHLabel = GetTempSymbol("loh", LOHLabelCounter++);
470 // Associate the instruction with the label
471 LOHInstToLabel[MI] = LOHLabel;
472 OutStreamer.EmitLabel(LOHLabel);
475 // Do any manual lowerings.
476 switch (MI->getOpcode()) {
479 case ARM64::DBG_VALUE: {
480 if (isVerbose() && OutStreamer.hasRawTextSupport()) {
481 SmallString<128> TmpStr;
482 raw_svector_ostream OS(TmpStr);
483 PrintDebugValueComment(MI, OS);
484 OutStreamer.EmitRawText(StringRef(OS.str()));
488 // Indexed loads and stores use a pseudo to handle complex operand
489 // tricks and writeback to the base register. We strip off the writeback
490 // operand and switch the opcode here. Post-indexed stores were handled by the
491 // tablegen'erated pseudos above. (The complex operand <--> simple
492 // operand isel is beyond tablegen's ability, so we do these manually).
493 case ARM64::LDRHHpre_isel:
494 case ARM64::LDRBBpre_isel:
495 case ARM64::LDRXpre_isel:
496 case ARM64::LDRWpre_isel:
497 case ARM64::LDRDpre_isel:
498 case ARM64::LDRSpre_isel:
499 case ARM64::LDRSBWpre_isel:
500 case ARM64::LDRSBXpre_isel:
501 case ARM64::LDRSHWpre_isel:
502 case ARM64::LDRSHXpre_isel:
503 case ARM64::LDRSWpre_isel:
504 case ARM64::LDRDpost_isel:
505 case ARM64::LDRSpost_isel:
506 case ARM64::LDRXpost_isel:
507 case ARM64::LDRWpost_isel:
508 case ARM64::LDRHHpost_isel:
509 case ARM64::LDRBBpost_isel:
510 case ARM64::LDRSWpost_isel:
511 case ARM64::LDRSHWpost_isel:
512 case ARM64::LDRSHXpost_isel:
513 case ARM64::LDRSBWpost_isel:
514 case ARM64::LDRSBXpost_isel: {
516 // For loads, the writeback operand to be skipped is the second.
517 TmpInst.setOpcode(getRealIndexedOpcode(MI->getOpcode()));
518 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
519 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(2).getReg()));
520 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
521 EmitToStreamer(OutStreamer, TmpInst);
524 case ARM64::STRXpre_isel:
525 case ARM64::STRWpre_isel:
526 case ARM64::STRHHpre_isel:
527 case ARM64::STRBBpre_isel:
528 case ARM64::STRDpre_isel:
529 case ARM64::STRSpre_isel: {
531 // For loads, the writeback operand to be skipped is the first.
532 TmpInst.setOpcode(getRealIndexedOpcode(MI->getOpcode()));
533 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
534 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(2).getReg()));
535 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(3).getImm()));
536 EmitToStreamer(OutStreamer, TmpInst);
540 // Tail calls use pseudo instructions so they have the proper code-gen
541 // attributes (isCall, isReturn, etc.). We lower them to the real
543 case ARM64::TCRETURNri: {
545 TmpInst.setOpcode(ARM64::BR);
546 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
547 EmitToStreamer(OutStreamer, TmpInst);
550 case ARM64::TCRETURNdi: {
552 MCInstLowering.lowerOperand(MI->getOperand(0), Dest);
554 TmpInst.setOpcode(ARM64::B);
555 TmpInst.addOperand(Dest);
556 EmitToStreamer(OutStreamer, TmpInst);
559 case ARM64::TLSDESC_BLR: {
560 MCOperand Callee, Sym;
561 MCInstLowering.lowerOperand(MI->getOperand(0), Callee);
562 MCInstLowering.lowerOperand(MI->getOperand(1), Sym);
564 // First emit a relocation-annotation. This expands to no code, but requests
565 // the following instruction gets an R_AARCH64_TLSDESC_CALL.
567 TLSDescCall.setOpcode(ARM64::TLSDESCCALL);
568 TLSDescCall.addOperand(Sym);
569 EmitToStreamer(OutStreamer, TLSDescCall);
571 // Other than that it's just a normal indirect call to the function loaded
572 // from the descriptor.
574 BLR.setOpcode(ARM64::BLR);
575 BLR.addOperand(Callee);
576 EmitToStreamer(OutStreamer, BLR);
581 case TargetOpcode::STACKMAP:
582 return LowerSTACKMAP(OutStreamer, SM, *MI);
584 case TargetOpcode::PATCHPOINT:
585 return LowerPATCHPOINT(OutStreamer, SM, *MI);
588 // Finally, do the automated lowerings for everything else.
590 MCInstLowering.Lower(MI, TmpInst);
591 EmitToStreamer(OutStreamer, TmpInst);
594 // Force static initialization.
595 extern "C" void LLVMInitializeARM64AsmPrinter() {
596 RegisterAsmPrinter<ARM64AsmPrinter> X(TheARM64leTarget);
597 RegisterAsmPrinter<ARM64AsmPrinter> Y(TheARM64beTarget);