1 //===- ARM64CallingConv.td - Calling Conventions for ARM64 -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This describes the calling conventions for ARM64 architecture.
12 //===----------------------------------------------------------------------===//
14 /// CCIfAlign - Match of the original alignment of the arg
15 class CCIfAlign<string Align, CCAction A> :
16 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
18 //===----------------------------------------------------------------------===//
19 // ARM AAPCS64 Calling Convention
20 //===----------------------------------------------------------------------===//
22 def CC_ARM64_AAPCS : CallingConv<[
23 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
24 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
26 // An SRet is passed in X8, not X0 like a normal pointer parameter.
27 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
29 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
30 // up to eight each of GPR and FPR.
31 CCIfType<[i1, i8, i16], CCCustom<"CC_ARM64_Custom_i1i8i16_Reg">>,
32 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
33 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
34 // i128 is split to two i64s, we can't fit half to register X7.
35 CCIfType<[i64], CCIfSplit<CCAssignToRegWithShadow<[X0, X2, X4, X6],
38 // i128 is split to two i64s, and its stack alignment is 16 bytes.
39 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>,
41 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
42 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
43 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
44 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
45 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
46 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
47 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32],
48 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
49 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
50 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
51 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
53 // If more than will fit in registers, pass them on the stack instead.
54 CCIfType<[i1, i8, i16], CCAssignToStack<8, 8>>,
55 CCIfType<[i32, f32], CCAssignToStack<8, 8>>,
56 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8],
57 CCAssignToStack<8, 8>>,
58 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64], CCAssignToStack<16, 16>>
61 def RetCC_ARM64_AAPCS : CallingConv<[
62 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
63 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
65 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
66 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
67 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
68 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
69 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
70 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
71 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
72 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
73 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32],
74 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
75 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
76 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
77 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
81 // Darwin uses a calling convention which differs in only two ways
82 // from the standard one at this level:
83 // + i128s (i.e. split i64s) don't need even registers.
84 // + Stack slots are sized as needed rather than being at least 64-bit.
85 def CC_ARM64_DarwinPCS : CallingConv<[
86 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
87 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
89 // An SRet is passed in X8, not X0 like a normal pointer parameter.
90 CCIfSRet<CCIfType<[i64], CCAssignToRegWithShadow<[X8], [W8]>>>,
92 // Handle i1, i8, i16, i32, i64, f32, f64 and v2f64 by passing in registers,
93 // up to eight each of GPR and FPR.
94 CCIfType<[i1, i8, i16], CCCustom<"CC_ARM64_Custom_i1i8i16_Reg">>,
95 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
96 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
97 // i128 is split to two i64s, we can't fit half to register X7.
99 CCIfSplit<CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6],
100 [W0, W1, W2, W3, W4, W5, W6]>>>,
101 // i128 is split to two i64s, and its stack alignment is 16 bytes.
102 CCIfType<[i64], CCIfSplit<CCAssignToStackWithShadow<8, 16, [X7]>>>,
104 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
105 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
106 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
107 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
108 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
109 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
110 CCIfType<[v1i64, v2i32, v4i16, v8i8, v1f64, v2f32],
111 CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
112 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
113 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64],
114 CCAssignToReg<[Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
116 // If more than will fit in registers, pass them on the stack instead.
117 CCIfType<[i1, i8, i16], CCCustom<"CC_ARM64_Custom_i1i8i16_Stack">>,
118 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
119 CCIfType<[i64, f64, v1f64, v2f32, v1i64, v2i32, v4i16, v8i8],
120 CCAssignToStack<8, 8>>,
121 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64], CCAssignToStack<16, 16>>
124 def CC_ARM64_DarwinPCS_VarArg : CallingConv<[
125 CCIfType<[v2f32], CCBitConvertToType<v2i32>>,
126 CCIfType<[v2f64, v4f32, f128], CCBitConvertToType<v2i64>>,
128 // Handle all scalar types as either i64 or f64.
129 CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
130 CCIfType<[f32], CCPromoteToType<f64>>,
132 // Everything is on the stack.
133 // i128 is split to two i64s, and its stack alignment is 16 bytes.
134 CCIfType<[i64], CCIfSplit<CCAssignToStack<8, 16>>>,
135 CCIfType<[i64, f64, v1i64, v2i32, v4i16, v8i8, v1f64, v2f32], CCAssignToStack<8, 8>>,
136 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32, v2f64], CCAssignToStack<16, 16>>
139 // The WebKit_JS calling convention only passes the first argument (the callee)
140 // in register and the remaining arguments on stack. We allow 32bit stack slots,
141 // so that WebKit can write partial values in the stack and define the other
142 // 32bit quantity as undef.
143 def CC_ARM64_WebKit_JS : CallingConv<[
144 // Handle i1, i8, i16, i32, and i64 passing in register X0 (W0).
145 CCIfType<[i1, i8, i16], CCCustom<"CC_ARM64_WebKit_JS_i1i8i16_Reg">>,
146 CCIfType<[i32], CCAssignToRegWithShadow<[W0], [X0]>>,
147 CCIfType<[i64], CCAssignToRegWithShadow<[X0], [W0]>>,
149 // Pass the remaining arguments on the stack instead.
150 CCIfType<[i1, i8, i16], CCAssignToStack<4, 4>>,
151 CCIfType<[i32, f32], CCAssignToStack<4, 4>>,
152 CCIfType<[i64, f64], CCAssignToStack<8, 8>>
155 def RetCC_ARM64_WebKit_JS : CallingConv<[
156 CCIfType<[i32], CCAssignToRegWithShadow<[W0, W1, W2, W3, W4, W5, W6, W7],
157 [X0, X1, X2, X3, X4, X5, X6, X7]>>,
158 CCIfType<[i64], CCAssignToRegWithShadow<[X0, X1, X2, X3, X4, X5, X6, X7],
159 [W0, W1, W2, W3, W4, W5, W6, W7]>>,
160 CCIfType<[f32], CCAssignToRegWithShadow<[S0, S1, S2, S3, S4, S5, S6, S7],
161 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>,
162 CCIfType<[f64], CCAssignToRegWithShadow<[D0, D1, D2, D3, D4, D5, D6, D7],
163 [Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7]>>
166 // FIXME: LR is only callee-saved in the sense that *we* preserve it and are
167 // presumably a callee to someone. External functions may not do so, but this
168 // is currently safe since BL has LR as an implicit-def and what happens after a
169 // tail call doesn't matter.
171 // It would be better to model its preservation semantics properly (create a
172 // vreg on entry, use it in RET & tail call generation; make that vreg def if we
173 // end up saving LR as part of a call frame). Watch this space...
174 def CSR_ARM64_AAPCS : CalleeSavedRegs<(add LR, FP, X19, X20, X21, X22,
175 X23, X24, X25, X26, X27, X28,
177 D12, D13, D14, D15)>;
179 // Constructors and destructors return 'this' in the iOS 64-bit C++ ABI; since
180 // 'this' and the pointer return value are both passed in X0 in these cases,
181 // this can be partially modelled by treating X0 as a callee-saved register;
182 // only the resulting RegMask is used; the SaveList is ignored
184 // (For generic ARM 64-bit ABI code, clang will not generate constructors or
185 // destructors with 'this' returns, so this RegMask will not be used in that
187 def CSR_ARM64_AAPCS_ThisReturn : CalleeSavedRegs<(add CSR_ARM64_AAPCS, X0)>;
189 // The function used by Darwin to obtain the address of a thread-local variable
190 // guarantees more than a normal AAPCS function. x16 and x17 are used on the
191 // fast path for calculation, but other registers except X0 (argument/return)
192 // and LR (it is a call, after all) are preserved.
193 def CSR_ARM64_TLS_Darwin
194 : CalleeSavedRegs<(add (sub (sequence "X%u", 1, 28), X16, X17),
196 (sequence "Q%u", 0, 31))>;
198 // The ELF stub used for TLS-descriptor access saves every feasible
199 // register. Only X0 and LR are clobbered.
200 def CSR_ARM64_TLS_ELF
201 : CalleeSavedRegs<(add (sequence "X%u", 1, 28), FP,
202 (sequence "Q%u", 0, 31))>;
204 def CSR_ARM64_AllRegs
205 : CalleeSavedRegs<(add (sequence "W%u", 0, 30), WSP,
206 (sequence "X%u", 0, 28), FP, LR, SP,
207 (sequence "B%u", 0, 31), (sequence "H%u", 0, 31),
208 (sequence "S%u", 0, 31), (sequence "D%u", 0, 31),
209 (sequence "Q%u", 0, 31))>;