1 //===-- ARM64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // When allowed by the instruction, replace a dead definition of a GPR with
10 // the zero register. This makes the code a bit friendlier towards the
11 // hardware's register renamer.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm64-dead-defs"
16 #include "ARM64RegisterInfo.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
25 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
28 class ARM64DeadRegisterDefinitions : public MachineFunctionPass {
30 bool processMachineBasicBlock(MachineBasicBlock *MBB);
33 static char ID; // Pass identification, replacement for typeid.
34 explicit ARM64DeadRegisterDefinitions() : MachineFunctionPass(ID) {}
36 virtual bool runOnMachineFunction(MachineFunction &F);
38 const char *getPassName() const { return "Dead register definitions"; }
40 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
42 MachineFunctionPass::getAnalysisUsage(AU);
45 char ARM64DeadRegisterDefinitions::ID = 0;
46 } // end anonymous namespace
49 ARM64DeadRegisterDefinitions::processMachineBasicBlock(MachineBasicBlock *MBB) {
51 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
54 for (int i = 0, e = MI->getDesc().getNumDefs(); i != e; ++i) {
55 MachineOperand &MO = MI->getOperand(i);
56 if (MO.isReg() && MO.isDead() && MO.isDef()) {
57 assert(!MO.isImplicit() && "Unexpected implicit def!");
58 DEBUG(dbgs() << " Dead def operand #" << i << " in:\n ";
60 // Be careful not to change the register if it's a tied operand.
61 if (MI->isRegTiedToUseOperand(i)) {
62 DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
65 // Make sure the instruction take a register class that contains
66 // the zero register and replace it if so.
68 switch (MI->getDesc().OpInfo[i].RegClass) {
70 DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
72 case ARM64::GPR32RegClassID:
75 case ARM64::GPR64RegClassID:
79 DEBUG(dbgs() << " Replacing with zero register. New:\n ");
81 DEBUG(MI->print(dbgs()));
82 ++NumDeadDefsReplaced;
89 // Scan the function for instructions that have a dead definition of a
90 // register. Replace that register with the zero register when possible.
91 bool ARM64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &mf) {
92 MachineFunction *MF = &mf;
94 DEBUG(dbgs() << "***** ARM64DeadRegisterDefinitions *****\n");
96 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I)
97 if (processMachineBasicBlock(I))
102 FunctionPass *llvm::createARM64DeadRegisterDefinitions() {
103 return new ARM64DeadRegisterDefinitions();