1 //===-- ARM64DeadRegisterDefinitions.cpp - Replace dead defs w/ zero reg --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // When allowed by the instruction, replace a dead definition of a GPR with
10 // the zero register. This makes the code a bit friendlier towards the
11 // hardware's register renamer.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm64-dead-defs"
16 #include "ARM64RegisterInfo.h"
17 #include "llvm/ADT/Statistic.h"
18 #include "llvm/CodeGen/MachineFunctionPass.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/raw_ostream.h"
25 STATISTIC(NumDeadDefsReplaced, "Number of dead definitions replaced");
28 class ARM64DeadRegisterDefinitions : public MachineFunctionPass {
30 const TargetRegisterInfo *TRI;
31 bool implicitlyDefinesSubReg(unsigned Reg, const MachineInstr *MI);
32 bool processMachineBasicBlock(MachineBasicBlock *MBB);
35 static char ID; // Pass identification, replacement for typeid.
36 explicit ARM64DeadRegisterDefinitions() : MachineFunctionPass(ID) {}
38 virtual bool runOnMachineFunction(MachineFunction &F);
40 const char *getPassName() const { return "Dead register definitions"; }
42 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
44 MachineFunctionPass::getAnalysisUsage(AU);
47 char ARM64DeadRegisterDefinitions::ID = 0;
48 } // end anonymous namespace
50 bool ARM64DeadRegisterDefinitions::implicitlyDefinesSubReg(
52 const MachineInstr *MI) {
53 for (const MachineOperand &MO : MI->implicit_operands())
54 if (MO.isReg() && MO.isDef())
55 if (TRI->isSubRegister(Reg, MO.getReg()))
61 ARM64DeadRegisterDefinitions::processMachineBasicBlock(MachineBasicBlock *MBB) {
63 for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
66 for (int i = 0, e = MI->getDesc().getNumDefs(); i != e; ++i) {
67 MachineOperand &MO = MI->getOperand(i);
68 if (MO.isReg() && MO.isDead() && MO.isDef()) {
69 assert(!MO.isImplicit() && "Unexpected implicit def!");
70 DEBUG(dbgs() << " Dead def operand #" << i << " in:\n ";
72 // Be careful not to change the register if it's a tied operand.
73 if (MI->isRegTiedToUseOperand(i)) {
74 DEBUG(dbgs() << " Ignoring, def is tied operand.\n");
77 // Don't change the register if there's an implicit def of a subreg.
78 if (implicitlyDefinesSubReg(MO.getReg(), MI)) {
79 DEBUG(dbgs() << " Ignoring, implicitly defines subregister.\n");
82 // Make sure the instruction take a register class that contains
83 // the zero register and replace it if so.
85 switch (MI->getDesc().OpInfo[i].RegClass) {
87 DEBUG(dbgs() << " Ignoring, register is not a GPR.\n");
89 case ARM64::GPR32RegClassID:
92 case ARM64::GPR64RegClassID:
96 DEBUG(dbgs() << " Replacing with zero register. New:\n ");
98 DEBUG(MI->print(dbgs()));
99 ++NumDeadDefsReplaced;
106 // Scan the function for instructions that have a dead definition of a
107 // register. Replace that register with the zero register when possible.
108 bool ARM64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &mf) {
109 MachineFunction *MF = &mf;
110 TRI = MF->getTarget().getRegisterInfo();
111 bool Changed = false;
112 DEBUG(dbgs() << "***** ARM64DeadRegisterDefinitions *****\n");
114 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I)
115 if (processMachineBasicBlock(I))
120 FunctionPass *llvm::createARM64DeadRegisterDefinitions() {
121 return new ARM64DeadRegisterDefinitions();