1 //===-- ARM64ISelDAGToDAG.cpp - A dag to dag inst selector for ARM64 ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the ARM64 target.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "arm64-isel"
15 #include "ARM64TargetMachine.h"
16 #include "MCTargetDesc/ARM64AddressingModes.h"
17 #include "llvm/CodeGen/SelectionDAGISel.h"
18 #include "llvm/IR/Function.h" // To access function attributes.
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/IR/Intrinsics.h"
21 #include "llvm/Support/Debug.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/raw_ostream.h"
28 //===--------------------------------------------------------------------===//
29 /// ARM64DAGToDAGISel - ARM64 specific code to select ARM64 machine
30 /// instructions for SelectionDAG operations.
34 class ARM64DAGToDAGISel : public SelectionDAGISel {
35 ARM64TargetMachine &TM;
37 /// Subtarget - Keep a pointer to the ARM64Subtarget around so that we can
38 /// make the right decision when generating code for different targets.
39 const ARM64Subtarget *Subtarget;
44 explicit ARM64DAGToDAGISel(ARM64TargetMachine &tm, CodeGenOpt::Level OptLevel)
45 : SelectionDAGISel(tm, OptLevel), TM(tm),
46 Subtarget(&TM.getSubtarget<ARM64Subtarget>()), ForCodeSize(false) {}
48 virtual const char *getPassName() const {
49 return "ARM64 Instruction Selection";
52 virtual bool runOnMachineFunction(MachineFunction &MF) {
53 AttributeSet FnAttrs = MF.getFunction()->getAttributes();
55 FnAttrs.hasAttribute(AttributeSet::FunctionIndex,
56 Attribute::OptimizeForSize) ||
57 FnAttrs.hasAttribute(AttributeSet::FunctionIndex, Attribute::MinSize);
58 return SelectionDAGISel::runOnMachineFunction(MF);
61 SDNode *Select(SDNode *Node);
63 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
64 /// inline asm expressions.
65 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
67 std::vector<SDValue> &OutOps);
69 SDNode *SelectMLAV64LaneV128(SDNode *N);
70 SDNode *SelectMULLV64LaneV128(unsigned IntNo, SDNode *N);
71 bool SelectArithExtendedRegister(SDValue N, SDValue &Reg, SDValue &Shift);
72 bool SelectArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
73 bool SelectNegArithImmed(SDValue N, SDValue &Val, SDValue &Shift);
74 bool SelectArithShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
75 return SelectShiftedRegister(N, false, Reg, Shift);
77 bool SelectLogicalShiftedRegister(SDValue N, SDValue &Reg, SDValue &Shift) {
78 return SelectShiftedRegister(N, true, Reg, Shift);
80 bool SelectAddrModeIndexed8(SDValue N, SDValue &Base, SDValue &OffImm) {
81 return SelectAddrModeIndexed(N, 1, Base, OffImm);
83 bool SelectAddrModeIndexed16(SDValue N, SDValue &Base, SDValue &OffImm) {
84 return SelectAddrModeIndexed(N, 2, Base, OffImm);
86 bool SelectAddrModeIndexed32(SDValue N, SDValue &Base, SDValue &OffImm) {
87 return SelectAddrModeIndexed(N, 4, Base, OffImm);
89 bool SelectAddrModeIndexed64(SDValue N, SDValue &Base, SDValue &OffImm) {
90 return SelectAddrModeIndexed(N, 8, Base, OffImm);
92 bool SelectAddrModeIndexed128(SDValue N, SDValue &Base, SDValue &OffImm) {
93 return SelectAddrModeIndexed(N, 16, Base, OffImm);
95 bool SelectAddrModeUnscaled8(SDValue N, SDValue &Base, SDValue &OffImm) {
96 return SelectAddrModeUnscaled(N, 1, Base, OffImm);
98 bool SelectAddrModeUnscaled16(SDValue N, SDValue &Base, SDValue &OffImm) {
99 return SelectAddrModeUnscaled(N, 2, Base, OffImm);
101 bool SelectAddrModeUnscaled32(SDValue N, SDValue &Base, SDValue &OffImm) {
102 return SelectAddrModeUnscaled(N, 4, Base, OffImm);
104 bool SelectAddrModeUnscaled64(SDValue N, SDValue &Base, SDValue &OffImm) {
105 return SelectAddrModeUnscaled(N, 8, Base, OffImm);
107 bool SelectAddrModeUnscaled128(SDValue N, SDValue &Base, SDValue &OffImm) {
108 return SelectAddrModeUnscaled(N, 16, Base, OffImm);
111 bool SelectAddrModeRO8(SDValue N, SDValue &Base, SDValue &Offset,
113 return SelectAddrModeRO(N, 1, Base, Offset, Imm);
115 bool SelectAddrModeRO16(SDValue N, SDValue &Base, SDValue &Offset,
117 return SelectAddrModeRO(N, 2, Base, Offset, Imm);
119 bool SelectAddrModeRO32(SDValue N, SDValue &Base, SDValue &Offset,
121 return SelectAddrModeRO(N, 4, Base, Offset, Imm);
123 bool SelectAddrModeRO64(SDValue N, SDValue &Base, SDValue &Offset,
125 return SelectAddrModeRO(N, 8, Base, Offset, Imm);
127 bool SelectAddrModeRO128(SDValue N, SDValue &Base, SDValue &Offset,
129 return SelectAddrModeRO(N, 16, Base, Offset, Imm);
131 bool SelectAddrModeNoIndex(SDValue N, SDValue &Val);
133 /// Form sequences of consecutive 64/128-bit registers for use in NEON
134 /// instructions making use of a vector-list (e.g. ldN, tbl). Vecs must have
135 /// between 1 and 4 elements. If it contains a single element that is returned
136 /// unchanged; otherwise a REG_SEQUENCE value is returned.
137 SDValue createDTuple(ArrayRef<SDValue> Vecs);
138 SDValue createQTuple(ArrayRef<SDValue> Vecs);
140 /// Generic helper for the createDTuple/createQTuple
141 /// functions. Those should almost always be called instead.
142 SDValue createTuple(ArrayRef<SDValue> Vecs, unsigned RegClassIDs[],
145 SDNode *SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
147 SDNode *SelectIndexedLoad(SDNode *N, bool &Done);
149 SDNode *SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
151 SDNode *SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
153 SDNode *SelectStore(SDNode *N, unsigned NumVecs, unsigned Opc);
154 SDNode *SelectStoreLane(SDNode *N, unsigned NumVecs, unsigned Opc);
156 SDNode *SelectSIMDAddSubNarrowing(unsigned IntNo, SDNode *Node);
157 SDNode *SelectSIMDXtnNarrowing(unsigned IntNo, SDNode *Node);
159 SDNode *SelectAtomic(SDNode *Node, unsigned Op8, unsigned Op16, unsigned Op32,
162 SDNode *SelectBitfieldExtractOp(SDNode *N);
163 SDNode *SelectBitfieldInsertOp(SDNode *N);
165 SDNode *SelectLIBM(SDNode *N);
167 // Include the pieces autogenerated from the target description.
168 #include "ARM64GenDAGISel.inc"
171 bool SelectShiftedRegister(SDValue N, bool AllowROR, SDValue &Reg,
173 bool SelectAddrModeIndexed(SDValue N, unsigned Size, SDValue &Base,
175 bool SelectAddrModeUnscaled(SDValue N, unsigned Size, SDValue &Base,
177 bool SelectAddrModeRO(SDValue N, unsigned Size, SDValue &Base,
178 SDValue &Offset, SDValue &Imm);
179 bool isWorthFolding(SDValue V) const;
180 bool SelectExtendedSHL(SDValue N, unsigned Size, SDValue &Offset,
183 } // end anonymous namespace
185 /// isIntImmediate - This method tests to see if the node is a constant
186 /// operand. If so Imm will receive the 32-bit value.
187 static bool isIntImmediate(const SDNode *N, uint64_t &Imm) {
188 if (const ConstantSDNode *C = dyn_cast<const ConstantSDNode>(N)) {
189 Imm = C->getZExtValue();
195 // isIntImmediate - This method tests to see if a constant operand.
196 // If so Imm will receive the value.
197 static bool isIntImmediate(SDValue N, uint64_t &Imm) {
198 return isIntImmediate(N.getNode(), Imm);
201 // isOpcWithIntImmediate - This method tests to see if the node is a specific
202 // opcode and that it has a immediate integer right operand.
203 // If so Imm will receive the 32 bit value.
204 static bool isOpcWithIntImmediate(const SDNode *N, unsigned Opc,
206 return N->getOpcode() == Opc &&
207 isIntImmediate(N->getOperand(1).getNode(), Imm);
210 bool ARM64DAGToDAGISel::SelectAddrModeNoIndex(SDValue N, SDValue &Val) {
211 EVT ValTy = N.getValueType();
212 if (ValTy != MVT::i64)
218 bool ARM64DAGToDAGISel::SelectInlineAsmMemoryOperand(
219 const SDValue &Op, char ConstraintCode, std::vector<SDValue> &OutOps) {
220 assert(ConstraintCode == 'm' && "unexpected asm memory constraint");
221 // Require the address to be in a register. That is safe for all ARM64
222 // variants and it is hard to do anything much smarter without knowing
223 // how the operand is used.
224 OutOps.push_back(Op);
228 /// SelectArithImmed - Select an immediate value that can be represented as
229 /// a 12-bit value shifted left by either 0 or 12. If so, return true with
230 /// Val set to the 12-bit value and Shift set to the shifter operand.
231 bool ARM64DAGToDAGISel::SelectArithImmed(SDValue N, SDValue &Val,
233 // This function is called from the addsub_shifted_imm ComplexPattern,
234 // which lists [imm] as the list of opcode it's interested in, however
235 // we still need to check whether the operand is actually an immediate
236 // here because the ComplexPattern opcode list is only used in
237 // root-level opcode matching.
238 if (!isa<ConstantSDNode>(N.getNode()))
241 uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
244 if (Immed >> 12 == 0) {
246 } else if ((Immed & 0xfff) == 0 && Immed >> 24 == 0) {
252 unsigned ShVal = ARM64_AM::getShifterImm(ARM64_AM::LSL, ShiftAmt);
253 Val = CurDAG->getTargetConstant(Immed, MVT::i32);
254 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
258 /// SelectNegArithImmed - As above, but negates the value before trying to
260 bool ARM64DAGToDAGISel::SelectNegArithImmed(SDValue N, SDValue &Val,
262 // This function is called from the addsub_shifted_imm ComplexPattern,
263 // which lists [imm] as the list of opcode it's interested in, however
264 // we still need to check whether the operand is actually an immediate
265 // here because the ComplexPattern opcode list is only used in
266 // root-level opcode matching.
267 if (!isa<ConstantSDNode>(N.getNode()))
270 // The immediate operand must be a 24-bit zero-extended immediate.
271 uint64_t Immed = cast<ConstantSDNode>(N.getNode())->getZExtValue();
273 // This negation is almost always valid, but "cmp wN, #0" and "cmn wN, #0"
274 // have the opposite effect on the C flag, so this pattern mustn't match under
275 // those circumstances.
279 if (N.getValueType() == MVT::i32)
280 Immed = ~((uint32_t)Immed) + 1;
282 Immed = ~Immed + 1ULL;
283 if (Immed & 0xFFFFFFFFFF000000ULL)
286 Immed &= 0xFFFFFFULL;
287 return SelectArithImmed(CurDAG->getConstant(Immed, MVT::i32), Val, Shift);
290 /// getShiftTypeForNode - Translate a shift node to the corresponding
292 static ARM64_AM::ShiftType getShiftTypeForNode(SDValue N) {
293 switch (N.getOpcode()) {
295 return ARM64_AM::InvalidShift;
297 return ARM64_AM::LSL;
299 return ARM64_AM::LSR;
301 return ARM64_AM::ASR;
303 return ARM64_AM::ROR;
307 /// \brief Determine wether it is worth to fold V into an extended register.
308 bool ARM64DAGToDAGISel::isWorthFolding(SDValue V) const {
309 // it hurts if the a value is used at least twice, unless we are optimizing
311 if (ForCodeSize || V.hasOneUse())
316 /// SelectShiftedRegister - Select a "shifted register" operand. If the value
317 /// is not shifted, set the Shift operand to default of "LSL 0". The logical
318 /// instructions allow the shifted register to be rotated, but the arithmetic
319 /// instructions do not. The AllowROR parameter specifies whether ROR is
321 bool ARM64DAGToDAGISel::SelectShiftedRegister(SDValue N, bool AllowROR,
322 SDValue &Reg, SDValue &Shift) {
323 ARM64_AM::ShiftType ShType = getShiftTypeForNode(N);
324 if (ShType == ARM64_AM::InvalidShift)
326 if (!AllowROR && ShType == ARM64_AM::ROR)
329 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
330 unsigned BitSize = N.getValueType().getSizeInBits();
331 unsigned Val = RHS->getZExtValue() & (BitSize - 1);
332 unsigned ShVal = ARM64_AM::getShifterImm(ShType, Val);
334 Reg = N.getOperand(0);
335 Shift = CurDAG->getTargetConstant(ShVal, MVT::i32);
336 return isWorthFolding(N);
342 /// getExtendTypeForNode - Translate an extend node to the corresponding
343 /// ExtendType value.
344 static ARM64_AM::ExtendType getExtendTypeForNode(SDValue N,
345 bool IsLoadStore = false) {
346 if (N.getOpcode() == ISD::SIGN_EXTEND ||
347 N.getOpcode() == ISD::SIGN_EXTEND_INREG) {
349 if (N.getOpcode() == ISD::SIGN_EXTEND_INREG)
350 SrcVT = cast<VTSDNode>(N.getOperand(1))->getVT();
352 SrcVT = N.getOperand(0).getValueType();
354 if (!IsLoadStore && SrcVT == MVT::i8)
355 return ARM64_AM::SXTB;
356 else if (!IsLoadStore && SrcVT == MVT::i16)
357 return ARM64_AM::SXTH;
358 else if (SrcVT == MVT::i32)
359 return ARM64_AM::SXTW;
360 else if (SrcVT == MVT::i64)
361 return ARM64_AM::SXTX;
363 return ARM64_AM::InvalidExtend;
364 } else if (N.getOpcode() == ISD::ZERO_EXTEND ||
365 N.getOpcode() == ISD::ANY_EXTEND) {
366 EVT SrcVT = N.getOperand(0).getValueType();
367 if (!IsLoadStore && SrcVT == MVT::i8)
368 return ARM64_AM::UXTB;
369 else if (!IsLoadStore && SrcVT == MVT::i16)
370 return ARM64_AM::UXTH;
371 else if (SrcVT == MVT::i32)
372 return ARM64_AM::UXTW;
373 else if (SrcVT == MVT::i64)
374 return ARM64_AM::UXTX;
376 return ARM64_AM::InvalidExtend;
377 } else if (N.getOpcode() == ISD::AND) {
378 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
380 return ARM64_AM::InvalidExtend;
381 uint64_t AndMask = CSD->getZExtValue();
385 return ARM64_AM::InvalidExtend;
387 return !IsLoadStore ? ARM64_AM::UXTB : ARM64_AM::InvalidExtend;
389 return !IsLoadStore ? ARM64_AM::UXTH : ARM64_AM::InvalidExtend;
391 return ARM64_AM::UXTW;
395 return ARM64_AM::InvalidExtend;
398 // Helper for SelectMLAV64LaneV128 - Recognize high lane extracts.
399 static bool checkHighLaneIndex(SDNode *DL, SDValue &LaneOp, int &LaneIdx) {
400 if (DL->getOpcode() != ARM64ISD::DUPLANE16 &&
401 DL->getOpcode() != ARM64ISD::DUPLANE32)
404 SDValue SV = DL->getOperand(0);
405 if (SV.getOpcode() != ISD::INSERT_SUBVECTOR)
408 SDValue EV = SV.getOperand(1);
409 if (EV.getOpcode() != ISD::EXTRACT_SUBVECTOR)
412 ConstantSDNode *DLidx = cast<ConstantSDNode>(DL->getOperand(1).getNode());
413 ConstantSDNode *EVidx = cast<ConstantSDNode>(EV.getOperand(1).getNode());
414 LaneIdx = DLidx->getSExtValue() + EVidx->getSExtValue();
415 LaneOp = EV.getOperand(0);
420 // Helper for SelectOpcV64LaneV128 - Recogzine operatinos where one operand is a
421 // high lane extract.
422 static bool checkV64LaneV128(SDValue Op0, SDValue Op1, SDValue &StdOp,
423 SDValue &LaneOp, int &LaneIdx) {
425 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx)) {
427 if (!checkHighLaneIndex(Op0.getNode(), LaneOp, LaneIdx))
434 /// SelectMLAV64LaneV128 - ARM64 supports vector MLAs where one multiplicand is
435 /// a lane in the upper half of a 128-bit vector. Recognize and select this so
436 /// that we don't emit unnecessary lane extracts.
437 SDNode *ARM64DAGToDAGISel::SelectMLAV64LaneV128(SDNode *N) {
438 SDValue Op0 = N->getOperand(0);
439 SDValue Op1 = N->getOperand(1);
440 SDValue MLAOp1; // Will hold ordinary multiplicand for MLA.
441 SDValue MLAOp2; // Will hold lane-accessed multiplicand for MLA.
442 int LaneIdx = -1; // Will hold the lane index.
444 if (Op1.getOpcode() != ISD::MUL ||
445 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
448 if (Op1.getOpcode() != ISD::MUL ||
449 !checkV64LaneV128(Op1.getOperand(0), Op1.getOperand(1), MLAOp1, MLAOp2,
454 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, MVT::i64);
456 SDValue Ops[] = { Op0, MLAOp1, MLAOp2, LaneIdxVal };
458 unsigned MLAOpc = ~0U;
460 switch (N->getSimpleValueType(0).SimpleTy) {
462 llvm_unreachable("Unrecognized MLA.");
464 MLAOpc = ARM64::MLAv4i16_indexed;
467 MLAOpc = ARM64::MLAv8i16_indexed;
470 MLAOpc = ARM64::MLAv2i32_indexed;
473 MLAOpc = ARM64::MLAv4i32_indexed;
477 return CurDAG->getMachineNode(MLAOpc, SDLoc(N), N->getValueType(0), Ops);
480 SDNode *ARM64DAGToDAGISel::SelectMULLV64LaneV128(unsigned IntNo, SDNode *N) {
485 if (!checkV64LaneV128(N->getOperand(1), N->getOperand(2), SMULLOp0, SMULLOp1,
489 SDValue LaneIdxVal = CurDAG->getTargetConstant(LaneIdx, MVT::i64);
491 SDValue Ops[] = { SMULLOp0, SMULLOp1, LaneIdxVal };
493 unsigned SMULLOpc = ~0U;
495 if (IntNo == Intrinsic::arm64_neon_smull) {
496 switch (N->getSimpleValueType(0).SimpleTy) {
498 llvm_unreachable("Unrecognized SMULL.");
500 SMULLOpc = ARM64::SMULLv4i16_indexed;
503 SMULLOpc = ARM64::SMULLv2i32_indexed;
506 } else if (IntNo == Intrinsic::arm64_neon_umull) {
507 switch (N->getSimpleValueType(0).SimpleTy) {
509 llvm_unreachable("Unrecognized SMULL.");
511 SMULLOpc = ARM64::UMULLv4i16_indexed;
514 SMULLOpc = ARM64::UMULLv2i32_indexed;
518 llvm_unreachable("Unrecognized intrinsic.");
520 return CurDAG->getMachineNode(SMULLOpc, SDLoc(N), N->getValueType(0), Ops);
523 /// SelectArithExtendedRegister - Select a "extended register" operand. This
524 /// operand folds in an extend followed by an optional left shift.
525 bool ARM64DAGToDAGISel::SelectArithExtendedRegister(SDValue N, SDValue &Reg,
527 unsigned ShiftVal = 0;
528 ARM64_AM::ExtendType Ext;
530 if (N.getOpcode() == ISD::SHL) {
531 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
534 ShiftVal = CSD->getZExtValue();
535 if ((ShiftVal & 0x3) != ShiftVal)
538 Ext = getExtendTypeForNode(N.getOperand(0));
539 if (Ext == ARM64_AM::InvalidExtend)
542 Reg = N.getOperand(0).getOperand(0);
544 Ext = getExtendTypeForNode(N);
545 if (Ext == ARM64_AM::InvalidExtend)
548 Reg = N.getOperand(0);
551 // ARM64 mandates that the RHS of the operation must use the smallest
552 // register classs that could contain the size being extended from. Thus,
553 // if we're folding a (sext i8), we need the RHS to be a GPR32, even though
554 // there might not be an actual 32-bit value in the program. We can
555 // (harmlessly) synthesize one by injected an EXTRACT_SUBREG here.
556 if (Reg.getValueType() == MVT::i64 && Ext != ARM64_AM::UXTX &&
557 Ext != ARM64_AM::SXTX) {
558 SDValue SubReg = CurDAG->getTargetConstant(ARM64::sub_32, MVT::i32);
559 MachineSDNode *Node = CurDAG->getMachineNode(
560 TargetOpcode::EXTRACT_SUBREG, SDLoc(N), MVT::i32, Reg, SubReg);
561 Reg = SDValue(Node, 0);
564 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), MVT::i32);
565 return isWorthFolding(N);
568 /// SelectAddrModeIndexed - Select a "register plus scaled unsigned 12-bit
569 /// immediate" address. The "Size" argument is the size in bytes of the memory
570 /// reference, which determines the scale.
571 bool ARM64DAGToDAGISel::SelectAddrModeIndexed(SDValue N, unsigned Size,
572 SDValue &Base, SDValue &OffImm) {
573 const TargetLowering *TLI = getTargetLowering();
574 if (N.getOpcode() == ISD::FrameIndex) {
575 int FI = cast<FrameIndexSDNode>(N)->getIndex();
576 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
577 OffImm = CurDAG->getTargetConstant(0, MVT::i64);
581 if (N.getOpcode() == ARM64ISD::ADDlow) {
582 GlobalAddressSDNode *GAN =
583 dyn_cast<GlobalAddressSDNode>(N.getOperand(1).getNode());
584 Base = N.getOperand(0);
585 OffImm = N.getOperand(1);
589 const GlobalValue *GV = GAN->getGlobal();
590 unsigned Alignment = GV->getAlignment();
591 const DataLayout *DL = TLI->getDataLayout();
592 if (Alignment == 0 && !Subtarget->isTargetDarwin())
593 Alignment = DL->getABITypeAlignment(GV->getType()->getElementType());
595 if (Alignment >= Size)
599 if (CurDAG->isBaseWithConstantOffset(N)) {
600 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
601 int64_t RHSC = (int64_t)RHS->getZExtValue();
602 unsigned Scale = Log2_32(Size);
603 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 && RHSC < (0x1000 << Scale)) {
604 Base = N.getOperand(0);
605 if (Base.getOpcode() == ISD::FrameIndex) {
606 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
607 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
609 OffImm = CurDAG->getTargetConstant(RHSC >> Scale, MVT::i64);
615 // Before falling back to our general case, check if the unscaled
616 // instructions can handle this. If so, that's preferable.
617 if (SelectAddrModeUnscaled(N, Size, Base, OffImm))
620 // Base only. The address will be materialized into a register before
621 // the memory is accessed.
622 // add x0, Xbase, #offset
625 OffImm = CurDAG->getTargetConstant(0, MVT::i64);
629 /// SelectAddrModeUnscaled - Select a "register plus unscaled signed 9-bit
630 /// immediate" address. This should only match when there is an offset that
631 /// is not valid for a scaled immediate addressing mode. The "Size" argument
632 /// is the size in bytes of the memory reference, which is needed here to know
633 /// what is valid for a scaled immediate.
634 bool ARM64DAGToDAGISel::SelectAddrModeUnscaled(SDValue N, unsigned Size,
635 SDValue &Base, SDValue &OffImm) {
636 if (!CurDAG->isBaseWithConstantOffset(N))
638 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
639 int64_t RHSC = RHS->getSExtValue();
640 // If the offset is valid as a scaled immediate, don't match here.
641 if ((RHSC & (Size - 1)) == 0 && RHSC >= 0 &&
642 RHSC < (0x1000 << Log2_32(Size)))
644 if (RHSC >= -256 && RHSC < 256) {
645 Base = N.getOperand(0);
646 if (Base.getOpcode() == ISD::FrameIndex) {
647 int FI = cast<FrameIndexSDNode>(Base)->getIndex();
648 const TargetLowering *TLI = getTargetLowering();
649 Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
651 OffImm = CurDAG->getTargetConstant(RHSC, MVT::i64);
658 static SDValue Widen(SelectionDAG *CurDAG, SDValue N) {
659 SDValue SubReg = CurDAG->getTargetConstant(ARM64::sub_32, MVT::i32);
660 SDValue ImpDef = SDValue(
661 CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, SDLoc(N), MVT::i64),
663 MachineSDNode *Node = CurDAG->getMachineNode(
664 TargetOpcode::INSERT_SUBREG, SDLoc(N), MVT::i64, ImpDef, N, SubReg);
665 return SDValue(Node, 0);
668 static SDValue WidenIfNeeded(SelectionDAG *CurDAG, SDValue N) {
669 if (N.getValueType() == MVT::i32) {
670 return Widen(CurDAG, N);
676 /// \brief Check if the given SHL node (\p N), can be used to form an
677 /// extended register for an addressing mode.
678 bool ARM64DAGToDAGISel::SelectExtendedSHL(SDValue N, unsigned Size,
679 SDValue &Offset, SDValue &Imm) {
680 assert(N.getOpcode() == ISD::SHL && "Invalid opcode.");
681 ConstantSDNode *CSD = dyn_cast<ConstantSDNode>(N.getOperand(1));
682 if (CSD && (CSD->getZExtValue() & 0x7) == CSD->getZExtValue()) {
684 ARM64_AM::ExtendType Ext = getExtendTypeForNode(N.getOperand(0), true);
685 if (Ext == ARM64_AM::InvalidExtend) {
686 Ext = ARM64_AM::UXTX;
687 Offset = WidenIfNeeded(CurDAG, N.getOperand(0));
689 Offset = WidenIfNeeded(CurDAG, N.getOperand(0).getOperand(0));
692 unsigned LegalShiftVal = Log2_32(Size);
693 unsigned ShiftVal = CSD->getZExtValue();
695 if (ShiftVal != 0 && ShiftVal != LegalShiftVal)
698 Imm = CurDAG->getTargetConstant(
699 ARM64_AM::getMemExtendImm(Ext, ShiftVal != 0), MVT::i32);
700 if (isWorthFolding(N))
706 bool ARM64DAGToDAGISel::SelectAddrModeRO(SDValue N, unsigned Size,
707 SDValue &Base, SDValue &Offset,
709 if (N.getOpcode() != ISD::ADD)
711 SDValue LHS = N.getOperand(0);
712 SDValue RHS = N.getOperand(1);
714 // We don't want to match immediate adds here, because they are better lowered
715 // to the register-immediate addressing modes.
716 if (isa<ConstantSDNode>(LHS) || isa<ConstantSDNode>(RHS))
719 // Check if this particular node is reused in any non-memory related
720 // operation. If yes, do not try to fold this node into the address
721 // computation, since the computation will be kept.
722 const SDNode *Node = N.getNode();
723 for (SDNode::use_iterator UI = Node->use_begin(), UE = Node->use_end();
725 if (!isa<MemSDNode>(*UI))
729 // Remember if it is worth folding N when it produces extended register.
730 bool IsExtendedRegisterWorthFolding = isWorthFolding(N);
732 // Try to match a shifted extend on the RHS.
733 if (IsExtendedRegisterWorthFolding && RHS.getOpcode() == ISD::SHL &&
734 SelectExtendedSHL(RHS, Size, Offset, Imm)) {
739 // Try to match a shifted extend on the LHS.
740 if (IsExtendedRegisterWorthFolding && LHS.getOpcode() == ISD::SHL &&
741 SelectExtendedSHL(LHS, Size, Offset, Imm)) {
746 ARM64_AM::ExtendType Ext = ARM64_AM::UXTX;
747 // Try to match an unshifted extend on the LHS.
748 if (IsExtendedRegisterWorthFolding &&
749 (Ext = getExtendTypeForNode(LHS, true)) != ARM64_AM::InvalidExtend) {
751 Offset = WidenIfNeeded(CurDAG, LHS.getOperand(0));
752 Imm = CurDAG->getTargetConstant(ARM64_AM::getMemExtendImm(Ext, false),
754 if (isWorthFolding(LHS))
758 // Try to match an unshifted extend on the RHS.
759 if (IsExtendedRegisterWorthFolding &&
760 (Ext = getExtendTypeForNode(RHS, true)) != ARM64_AM::InvalidExtend) {
762 Offset = WidenIfNeeded(CurDAG, RHS.getOperand(0));
763 Imm = CurDAG->getTargetConstant(ARM64_AM::getMemExtendImm(Ext, false),
765 if (isWorthFolding(RHS))
769 // Match any non-shifted, non-extend, non-immediate add expression.
771 Offset = WidenIfNeeded(CurDAG, RHS);
772 Ext = ARM64_AM::UXTX;
773 Imm = CurDAG->getTargetConstant(ARM64_AM::getMemExtendImm(Ext, false),
775 // Reg1 + Reg2 is free: no check needed.
779 SDValue ARM64DAGToDAGISel::createDTuple(ArrayRef<SDValue> Regs) {
780 static unsigned RegClassIDs[] = { ARM64::DDRegClassID, ARM64::DDDRegClassID,
781 ARM64::DDDDRegClassID };
782 static unsigned SubRegs[] = { ARM64::dsub0, ARM64::dsub1,
783 ARM64::dsub2, ARM64::dsub3 };
785 return createTuple(Regs, RegClassIDs, SubRegs);
788 SDValue ARM64DAGToDAGISel::createQTuple(ArrayRef<SDValue> Regs) {
789 static unsigned RegClassIDs[] = { ARM64::QQRegClassID, ARM64::QQQRegClassID,
790 ARM64::QQQQRegClassID };
791 static unsigned SubRegs[] = { ARM64::qsub0, ARM64::qsub1,
792 ARM64::qsub2, ARM64::qsub3 };
794 return createTuple(Regs, RegClassIDs, SubRegs);
797 SDValue ARM64DAGToDAGISel::createTuple(ArrayRef<SDValue> Regs,
798 unsigned RegClassIDs[],
799 unsigned SubRegs[]) {
800 // There's no special register-class for a vector-list of 1 element: it's just
802 if (Regs.size() == 1)
805 assert(Regs.size() >= 2 && Regs.size() <= 4);
807 SDLoc DL(Regs[0].getNode());
809 SmallVector<SDValue, 4> Ops;
811 // First operand of REG_SEQUENCE is the desired RegClass.
813 CurDAG->getTargetConstant(RegClassIDs[Regs.size() - 2], MVT::i32));
815 // Then we get pairs of source & subregister-position for the components.
816 for (unsigned i = 0; i < Regs.size(); ++i) {
817 Ops.push_back(Regs[i]);
818 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], MVT::i32));
822 CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::Untyped, Ops);
823 return SDValue(N, 0);
826 SDNode *ARM64DAGToDAGISel::SelectTable(SDNode *N, unsigned NumVecs,
827 unsigned Opc, bool isExt) {
829 EVT VT = N->getValueType(0);
831 unsigned ExtOff = isExt;
833 // Form a REG_SEQUENCE to force register allocation.
834 unsigned Vec0Off = ExtOff + 1;
835 SmallVector<SDValue, 4> Regs(N->op_begin() + Vec0Off,
836 N->op_begin() + Vec0Off + NumVecs);
837 SDValue RegSeq = createQTuple(Regs);
839 SmallVector<SDValue, 6> Ops;
841 Ops.push_back(N->getOperand(1));
842 Ops.push_back(RegSeq);
843 Ops.push_back(N->getOperand(NumVecs + ExtOff + 1));
844 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
847 SDNode *ARM64DAGToDAGISel::SelectIndexedLoad(SDNode *N, bool &Done) {
848 LoadSDNode *LD = cast<LoadSDNode>(N);
849 if (LD->isUnindexed())
851 EVT VT = LD->getMemoryVT();
852 EVT DstVT = N->getValueType(0);
853 ISD::MemIndexedMode AM = LD->getAddressingMode();
854 bool IsPre = AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
856 // We're not doing validity checking here. That was done when checking
857 // if we should mark the load as indexed or not. We're just selecting
858 // the right instruction.
861 ISD::LoadExtType ExtType = LD->getExtensionType();
862 bool InsertTo64 = false;
864 Opcode = IsPre ? ARM64::LDRXpre_isel : ARM64::LDRXpost_isel;
865 else if (VT == MVT::i32) {
866 if (ExtType == ISD::NON_EXTLOAD)
867 Opcode = IsPre ? ARM64::LDRWpre_isel : ARM64::LDRWpost_isel;
868 else if (ExtType == ISD::SEXTLOAD)
869 Opcode = IsPre ? ARM64::LDRSWpre_isel : ARM64::LDRSWpost_isel;
871 Opcode = IsPre ? ARM64::LDRWpre_isel : ARM64::LDRWpost_isel;
873 // The result of the load is only i32. It's the subreg_to_reg that makes
877 } else if (VT == MVT::i16) {
878 if (ExtType == ISD::SEXTLOAD) {
879 if (DstVT == MVT::i64)
880 Opcode = IsPre ? ARM64::LDRSHXpre_isel : ARM64::LDRSHXpost_isel;
882 Opcode = IsPre ? ARM64::LDRSHWpre_isel : ARM64::LDRSHWpost_isel;
884 Opcode = IsPre ? ARM64::LDRHHpre_isel : ARM64::LDRHHpost_isel;
885 InsertTo64 = DstVT == MVT::i64;
886 // The result of the load is only i32. It's the subreg_to_reg that makes
890 } else if (VT == MVT::i8) {
891 if (ExtType == ISD::SEXTLOAD) {
892 if (DstVT == MVT::i64)
893 Opcode = IsPre ? ARM64::LDRSBXpre_isel : ARM64::LDRSBXpost_isel;
895 Opcode = IsPre ? ARM64::LDRSBWpre_isel : ARM64::LDRSBWpost_isel;
897 Opcode = IsPre ? ARM64::LDRBBpre_isel : ARM64::LDRBBpost_isel;
898 InsertTo64 = DstVT == MVT::i64;
899 // The result of the load is only i32. It's the subreg_to_reg that makes
903 } else if (VT == MVT::f32) {
904 Opcode = IsPre ? ARM64::LDRSpre_isel : ARM64::LDRSpost_isel;
905 } else if (VT == MVT::f64) {
906 Opcode = IsPre ? ARM64::LDRDpre_isel : ARM64::LDRDpost_isel;
909 SDValue Chain = LD->getChain();
910 SDValue Base = LD->getBasePtr();
911 ConstantSDNode *OffsetOp = cast<ConstantSDNode>(LD->getOffset());
912 int OffsetVal = (int)OffsetOp->getZExtValue();
913 SDValue Offset = CurDAG->getTargetConstant(OffsetVal, MVT::i64);
914 SDValue Ops[] = { Base, Offset, Chain };
915 SDNode *Res = CurDAG->getMachineNode(Opcode, SDLoc(N), DstVT, MVT::i64,
917 // Either way, we're replacing the node, so tell the caller that.
920 SDValue SubReg = CurDAG->getTargetConstant(ARM64::sub_32, MVT::i32);
921 SDNode *Sub = CurDAG->getMachineNode(
922 ARM64::SUBREG_TO_REG, SDLoc(N), MVT::i64,
923 CurDAG->getTargetConstant(0, MVT::i64), SDValue(Res, 0), SubReg);
924 ReplaceUses(SDValue(N, 0), SDValue(Sub, 0));
925 ReplaceUses(SDValue(N, 1), SDValue(Res, 1));
926 ReplaceUses(SDValue(N, 2), SDValue(Res, 2));
932 SDNode *ARM64DAGToDAGISel::SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
933 unsigned SubRegIdx) {
935 EVT VT = N->getValueType(0);
936 SDValue Chain = N->getOperand(0);
938 SmallVector<SDValue, 6> Ops;
939 Ops.push_back(N->getOperand(2)); // Mem operand;
940 Ops.push_back(Chain);
942 std::vector<EVT> ResTys;
943 ResTys.push_back(MVT::Untyped);
944 ResTys.push_back(MVT::Other);
946 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
947 SDValue SuperReg = SDValue(Ld, 0);
949 // MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
950 // MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
951 // cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
955 ReplaceUses(SDValue(N, 3), CurDAG->getTargetExtractSubreg(SubRegIdx + 3, dl,
959 ReplaceUses(SDValue(N, 2), CurDAG->getTargetExtractSubreg(SubRegIdx + 2, dl,
963 ReplaceUses(SDValue(N, 1), CurDAG->getTargetExtractSubreg(SubRegIdx + 1, dl,
965 ReplaceUses(SDValue(N, 0),
966 CurDAG->getTargetExtractSubreg(SubRegIdx, dl, VT, SuperReg));
969 ReplaceUses(SDValue(N, 0), SuperReg);
973 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
978 SDNode *ARM64DAGToDAGISel::SelectStore(SDNode *N, unsigned NumVecs,
981 EVT VT = N->getOperand(2)->getValueType(0);
983 // Form a REG_SEQUENCE to force register allocation.
984 bool Is128Bit = VT.getSizeInBits() == 128;
985 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
986 SDValue RegSeq = Is128Bit ? createQTuple(Regs) : createDTuple(Regs);
988 SmallVector<SDValue, 6> Ops;
989 Ops.push_back(RegSeq);
990 Ops.push_back(N->getOperand(NumVecs + 2));
991 Ops.push_back(N->getOperand(0));
992 SDNode *St = CurDAG->getMachineNode(Opc, dl, N->getValueType(0), Ops);
997 /// WidenVector - Given a value in the V64 register class, produce the
998 /// equivalent value in the V128 register class.
1003 WidenVector(SelectionDAG &DAG) : DAG(DAG) {}
1005 SDValue operator()(SDValue V64Reg) {
1006 EVT VT = V64Reg.getValueType();
1007 unsigned NarrowSize = VT.getVectorNumElements();
1008 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1009 MVT WideTy = MVT::getVectorVT(EltTy, 2 * NarrowSize);
1013 SDValue(DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, WideTy), 0);
1014 return DAG.getTargetInsertSubreg(ARM64::dsub, DL, WideTy, Undef, V64Reg);
1018 /// NarrowVector - Given a value in the V128 register class, produce the
1019 /// equivalent value in the V64 register class.
1020 static SDValue NarrowVector(SDValue V128Reg, SelectionDAG &DAG) {
1021 EVT VT = V128Reg.getValueType();
1022 unsigned WideSize = VT.getVectorNumElements();
1023 MVT EltTy = VT.getVectorElementType().getSimpleVT();
1024 MVT NarrowTy = MVT::getVectorVT(EltTy, WideSize / 2);
1026 return DAG.getTargetExtractSubreg(ARM64::dsub, SDLoc(V128Reg), NarrowTy,
1030 SDNode *ARM64DAGToDAGISel::SelectLoadLane(SDNode *N, unsigned NumVecs,
1033 EVT VT = N->getValueType(0);
1034 bool Narrow = VT.getSizeInBits() == 64;
1036 // Form a REG_SEQUENCE to force register allocation.
1037 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1040 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1041 WidenVector(*CurDAG));
1043 SDValue RegSeq = createQTuple(Regs);
1045 std::vector<EVT> ResTys;
1046 ResTys.push_back(MVT::Untyped);
1047 ResTys.push_back(MVT::Other);
1050 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1052 SmallVector<SDValue, 6> Ops;
1053 Ops.push_back(RegSeq);
1054 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1055 Ops.push_back(N->getOperand(NumVecs + 3));
1056 Ops.push_back(N->getOperand(0));
1057 SDNode *Ld = CurDAG->getMachineNode(Opc, dl, ResTys, Ops);
1058 SDValue SuperReg = SDValue(Ld, 0);
1060 EVT WideVT = RegSeq.getOperand(1)->getValueType(0);
1064 CurDAG->getTargetExtractSubreg(ARM64::qsub3, dl, WideVT, SuperReg);
1066 ReplaceUses(SDValue(N, 3), NarrowVector(NV3, *CurDAG));
1068 ReplaceUses(SDValue(N, 3), NV3);
1073 CurDAG->getTargetExtractSubreg(ARM64::qsub2, dl, WideVT, SuperReg);
1075 ReplaceUses(SDValue(N, 2), NarrowVector(NV2, *CurDAG));
1077 ReplaceUses(SDValue(N, 2), NV2);
1082 CurDAG->getTargetExtractSubreg(ARM64::qsub1, dl, WideVT, SuperReg);
1084 CurDAG->getTargetExtractSubreg(ARM64::qsub0, dl, WideVT, SuperReg);
1086 ReplaceUses(SDValue(N, 1), NarrowVector(NV1, *CurDAG));
1087 ReplaceUses(SDValue(N, 0), NarrowVector(NV0, *CurDAG));
1089 ReplaceUses(SDValue(N, 1), NV1);
1090 ReplaceUses(SDValue(N, 0), NV0);
1096 ReplaceUses(SDValue(N, NumVecs), SDValue(Ld, 1));
1101 SDNode *ARM64DAGToDAGISel::SelectStoreLane(SDNode *N, unsigned NumVecs,
1104 EVT VT = N->getOperand(2)->getValueType(0);
1105 bool Narrow = VT.getSizeInBits() == 64;
1107 // Form a REG_SEQUENCE to force register allocation.
1108 SmallVector<SDValue, 4> Regs(N->op_begin() + 2, N->op_begin() + 2 + NumVecs);
1111 std::transform(Regs.begin(), Regs.end(), Regs.begin(),
1112 WidenVector(*CurDAG));
1114 SDValue RegSeq = createQTuple(Regs);
1117 cast<ConstantSDNode>(N->getOperand(NumVecs + 2))->getZExtValue();
1119 SmallVector<SDValue, 6> Ops;
1120 Ops.push_back(RegSeq);
1121 Ops.push_back(CurDAG->getTargetConstant(LaneNo, MVT::i64));
1122 Ops.push_back(N->getOperand(NumVecs + 3));
1123 Ops.push_back(N->getOperand(0));
1124 SDNode *St = CurDAG->getMachineNode(Opc, dl, MVT::Other, Ops);
1126 // Transfer memoperands.
1127 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1128 MemOp[0] = cast<MemIntrinsicSDNode>(N)->getMemOperand();
1129 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1134 SDNode *ARM64DAGToDAGISel::SelectAtomic(SDNode *Node, unsigned Op8,
1135 unsigned Op16, unsigned Op32,
1137 // Mostly direct translation to the given operations, except that we preserve
1138 // the AtomicOrdering for use later on.
1139 AtomicSDNode *AN = cast<AtomicSDNode>(Node);
1140 EVT VT = AN->getMemoryVT();
1145 else if (VT == MVT::i16)
1147 else if (VT == MVT::i32)
1149 else if (VT == MVT::i64)
1152 llvm_unreachable("Unexpected atomic operation");
1154 SmallVector<SDValue, 4> Ops;
1155 for (unsigned i = 1; i < AN->getNumOperands(); ++i)
1156 Ops.push_back(AN->getOperand(i));
1158 Ops.push_back(CurDAG->getTargetConstant(AN->getOrdering(), MVT::i32));
1159 Ops.push_back(AN->getOperand(0)); // Chain moves to the end
1161 return CurDAG->SelectNodeTo(Node, Op, AN->getValueType(0), MVT::Other,
1162 &Ops[0], Ops.size());
1165 static bool isBitfieldExtractOpFromAnd(SelectionDAG *CurDAG, SDNode *N,
1166 unsigned &Opc, SDValue &Opd0,
1167 unsigned &LSB, unsigned &MSB,
1168 unsigned NumberOfIgnoredLowBits,
1169 bool BiggerPattern) {
1170 assert(N->getOpcode() == ISD::AND &&
1171 "N must be a AND operation to call this function");
1173 EVT VT = N->getValueType(0);
1175 // Here we can test the type of VT and return false when the type does not
1176 // match, but since it is done prior to that call in the current context
1177 // we turned that into an assert to avoid redundant code.
1178 assert((VT == MVT::i32 || VT == MVT::i64) &&
1179 "Type checking must have been done before calling this function");
1181 // FIXME: simplify-demanded-bits in DAGCombine will probably have
1182 // changed the AND node to a 32-bit mask operation. We'll have to
1183 // undo that as part of the transform here if we want to catch all
1184 // the opportunities.
1185 // Currently the NumberOfIgnoredLowBits argument helps to recover
1186 // form these situations when matching bigger pattern (bitfield insert).
1188 // For unsigned extracts, check for a shift right and mask
1189 uint64_t And_imm = 0;
1190 if (!isOpcWithIntImmediate(N, ISD::AND, And_imm))
1193 const SDNode *Op0 = N->getOperand(0).getNode();
1195 // Because of simplify-demanded-bits in DAGCombine, the mask may have been
1196 // simplified. Try to undo that
1197 And_imm |= (1 << NumberOfIgnoredLowBits) - 1;
1199 // The immediate is a mask of the low bits iff imm & (imm+1) == 0
1200 if (And_imm & (And_imm + 1))
1203 bool ClampMSB = false;
1204 uint64_t Srl_imm = 0;
1205 // Handle the SRL + ANY_EXTEND case.
1206 if (VT == MVT::i64 && Op0->getOpcode() == ISD::ANY_EXTEND &&
1207 isOpcWithIntImmediate(Op0->getOperand(0).getNode(), ISD::SRL, Srl_imm)) {
1208 // Extend the incoming operand of the SRL to 64-bit.
1209 Opd0 = Widen(CurDAG, Op0->getOperand(0).getOperand(0));
1210 // Make sure to clamp the MSB so that we preserve the semantics of the
1211 // original operations.
1213 } else if (isOpcWithIntImmediate(Op0, ISD::SRL, Srl_imm)) {
1214 Opd0 = Op0->getOperand(0);
1215 } else if (BiggerPattern) {
1216 // Let's pretend a 0 shift right has been performed.
1217 // The resulting code will be at least as good as the original one
1218 // plus it may expose more opportunities for bitfield insert pattern.
1219 // FIXME: Currently we limit this to the bigger pattern, because
1220 // some optimizations expect AND and not UBFM
1221 Opd0 = N->getOperand(0);
1225 assert((BiggerPattern || (Srl_imm > 0 && Srl_imm < VT.getSizeInBits())) &&
1226 "bad amount in shift node!");
1229 MSB = Srl_imm + (VT == MVT::i32 ? CountTrailingOnes_32(And_imm)
1230 : CountTrailingOnes_64(And_imm)) -
1233 // Since we're moving the extend before the right shift operation, we need
1234 // to clamp the MSB to make sure we don't shift in undefined bits instead of
1235 // the zeros which would get shifted in with the original right shift
1237 MSB = MSB > 31 ? 31 : MSB;
1239 Opc = VT == MVT::i32 ? ARM64::UBFMWri : ARM64::UBFMXri;
1243 static bool isOneBitExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
1244 unsigned &LSB, unsigned &MSB) {
1245 // We are looking for the following pattern which basically extracts a single
1246 // bit from the source value and places it in the LSB of the destination
1247 // value, all other bits of the destination value or set to zero:
1249 // Value2 = AND Value, MaskImm
1250 // SRL Value2, ShiftImm
1252 // with MaskImm >> ShiftImm == 1.
1254 // This gets selected into a single UBFM:
1256 // UBFM Value, ShiftImm, ShiftImm
1259 if (N->getOpcode() != ISD::SRL)
1262 uint64_t And_mask = 0;
1263 if (!isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::AND, And_mask))
1266 Opd0 = N->getOperand(0).getOperand(0);
1268 uint64_t Srl_imm = 0;
1269 if (!isIntImmediate(N->getOperand(1), Srl_imm))
1272 // Check whether we really have a one bit extract here.
1273 if (And_mask >> Srl_imm == 0x1) {
1274 if (N->getValueType(0) == MVT::i32)
1275 Opc = ARM64::UBFMWri;
1277 Opc = ARM64::UBFMXri;
1279 LSB = MSB = Srl_imm;
1287 static bool isBitfieldExtractOpFromShr(SDNode *N, unsigned &Opc, SDValue &Opd0,
1288 unsigned &LSB, unsigned &MSB,
1289 bool BiggerPattern) {
1290 assert((N->getOpcode() == ISD::SRA || N->getOpcode() == ISD::SRL) &&
1291 "N must be a SHR/SRA operation to call this function");
1293 EVT VT = N->getValueType(0);
1295 // Here we can test the type of VT and return false when the type does not
1296 // match, but since it is done prior to that call in the current context
1297 // we turned that into an assert to avoid redundant code.
1298 assert((VT == MVT::i32 || VT == MVT::i64) &&
1299 "Type checking must have been done before calling this function");
1301 // Check for AND + SRL doing a one bit extract.
1302 if (isOneBitExtractOpFromShr(N, Opc, Opd0, LSB, MSB))
1305 // we're looking for a shift of a shift
1306 uint64_t Shl_imm = 0;
1307 if (isOpcWithIntImmediate(N->getOperand(0).getNode(), ISD::SHL, Shl_imm)) {
1308 Opd0 = N->getOperand(0).getOperand(0);
1309 } else if (BiggerPattern) {
1310 // Let's pretend a 0 shift left has been performed.
1311 // FIXME: Currently we limit this to the bigger pattern case,
1312 // because some optimizations expect AND and not UBFM
1313 Opd0 = N->getOperand(0);
1317 assert(Shl_imm < VT.getSizeInBits() && "bad amount in shift node!");
1318 uint64_t Srl_imm = 0;
1319 if (!isIntImmediate(N->getOperand(1), Srl_imm))
1322 assert(Srl_imm > 0 && Srl_imm < VT.getSizeInBits() &&
1323 "bad amount in shift node!");
1324 // Note: The width operand is encoded as width-1.
1325 unsigned Width = VT.getSizeInBits() - Srl_imm - 1;
1326 int sLSB = Srl_imm - Shl_imm;
1331 // SRA requires a signed extraction
1333 Opc = N->getOpcode() == ISD::SRA ? ARM64::SBFMWri : ARM64::UBFMWri;
1335 Opc = N->getOpcode() == ISD::SRA ? ARM64::SBFMXri : ARM64::UBFMXri;
1339 static bool isBitfieldExtractOp(SelectionDAG *CurDAG, SDNode *N, unsigned &Opc,
1340 SDValue &Opd0, unsigned &LSB, unsigned &MSB,
1341 unsigned NumberOfIgnoredLowBits = 0,
1342 bool BiggerPattern = false) {
1343 if (N->getValueType(0) != MVT::i32 && N->getValueType(0) != MVT::i64)
1346 switch (N->getOpcode()) {
1348 if (!N->isMachineOpcode())
1352 return isBitfieldExtractOpFromAnd(CurDAG, N, Opc, Opd0, LSB, MSB,
1353 NumberOfIgnoredLowBits, BiggerPattern);
1356 return isBitfieldExtractOpFromShr(N, Opc, Opd0, LSB, MSB, BiggerPattern);
1359 unsigned NOpc = N->getMachineOpcode();
1363 case ARM64::SBFMWri:
1364 case ARM64::UBFMWri:
1365 case ARM64::SBFMXri:
1366 case ARM64::UBFMXri:
1368 Opd0 = N->getOperand(0);
1369 LSB = cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue();
1370 MSB = cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue();
1377 SDNode *ARM64DAGToDAGISel::SelectBitfieldExtractOp(SDNode *N) {
1378 unsigned Opc, LSB, MSB;
1380 if (!isBitfieldExtractOp(CurDAG, N, Opc, Opd0, LSB, MSB))
1383 EVT VT = N->getValueType(0);
1384 SDValue Ops[] = { Opd0, CurDAG->getTargetConstant(LSB, VT),
1385 CurDAG->getTargetConstant(MSB, VT) };
1386 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 3);
1389 // Is mask a i32 or i64 binary sequence 1..10..0 and
1390 // CountTrailingZeros(mask) == ExpectedTrailingZeros
1391 static bool isHighMask(uint64_t Mask, unsigned ExpectedTrailingZeros,
1392 unsigned NumberOfIgnoredHighBits, EVT VT) {
1393 assert((VT == MVT::i32 || VT == MVT::i64) &&
1394 "i32 or i64 mask type expected!");
1396 uint64_t ExpectedMask;
1397 if (VT == MVT::i32) {
1398 uint32_t ExpectedMaski32 = ~0 << ExpectedTrailingZeros;
1399 ExpectedMask = ExpectedMaski32;
1400 if (NumberOfIgnoredHighBits) {
1401 uint32_t highMask = ~0 << (32 - NumberOfIgnoredHighBits);
1405 ExpectedMask = ((uint64_t) ~0) << ExpectedTrailingZeros;
1406 if (NumberOfIgnoredHighBits)
1407 Mask |= ((uint64_t) ~0) << (64 - NumberOfIgnoredHighBits);
1410 return Mask == ExpectedMask;
1413 // Look for bits that will be useful for later uses.
1414 // A bit is consider useless as soon as it is dropped and never used
1415 // before it as been dropped.
1416 // E.g., looking for useful bit of x
1419 // After #1, x useful bits are 0x7, then the useful bits of x, live through
1421 // After #2, the useful bits of x are 0x4.
1422 // However, if x is used on an unpredicatable instruction, then all its bits
1428 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth = 0);
1430 static void getUsefulBitsFromAndWithImmediate(SDValue Op, APInt &UsefulBits,
1433 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1434 Imm = ARM64_AM::decodeLogicalImmediate(Imm, UsefulBits.getBitWidth());
1435 UsefulBits &= APInt(UsefulBits.getBitWidth(), Imm);
1436 getUsefulBits(Op, UsefulBits, Depth + 1);
1439 static void getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits,
1440 uint64_t Imm, uint64_t MSB,
1442 // inherit the bitwidth value
1443 APInt OpUsefulBits(UsefulBits);
1447 OpUsefulBits = OpUsefulBits.shl(MSB - Imm + 1);
1449 // The interesting part will be in the lower part of the result
1450 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1451 // The interesting part was starting at Imm in the argument
1452 OpUsefulBits = OpUsefulBits.shl(Imm);
1454 OpUsefulBits = OpUsefulBits.shl(MSB + 1);
1456 // The interesting part will be shifted in the result
1457 OpUsefulBits = OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm);
1458 getUsefulBits(Op, OpUsefulBits, Depth + 1);
1459 // The interesting part was at zero in the argument
1460 OpUsefulBits = OpUsefulBits.lshr(OpUsefulBits.getBitWidth() - Imm);
1463 UsefulBits &= OpUsefulBits;
1466 static void getUsefulBitsFromUBFM(SDValue Op, APInt &UsefulBits,
1469 cast<const ConstantSDNode>(Op.getOperand(1).getNode())->getZExtValue();
1471 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1473 getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
1476 static void getUsefulBitsFromOrWithShiftedReg(SDValue Op, APInt &UsefulBits,
1478 uint64_t ShiftTypeAndValue =
1479 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1480 APInt Mask(UsefulBits);
1481 Mask.clearAllBits();
1484 if (ARM64_AM::getShiftType(ShiftTypeAndValue) == ARM64_AM::LSL) {
1486 uint64_t ShiftAmt = ARM64_AM::getShiftValue(ShiftTypeAndValue);
1487 Mask = Mask.shl(ShiftAmt);
1488 getUsefulBits(Op, Mask, Depth + 1);
1489 Mask = Mask.lshr(ShiftAmt);
1490 } else if (ARM64_AM::getShiftType(ShiftTypeAndValue) == ARM64_AM::LSR) {
1492 // We do not handle ARM64_AM::ASR, because the sign will change the
1493 // number of useful bits
1494 uint64_t ShiftAmt = ARM64_AM::getShiftValue(ShiftTypeAndValue);
1495 Mask = Mask.lshr(ShiftAmt);
1496 getUsefulBits(Op, Mask, Depth + 1);
1497 Mask = Mask.shl(ShiftAmt);
1504 static void getUsefulBitsFromBFM(SDValue Op, SDValue Orig, APInt &UsefulBits,
1507 cast<const ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue();
1509 cast<const ConstantSDNode>(Op.getOperand(3).getNode())->getZExtValue();
1511 if (Op.getOperand(1) == Orig)
1512 return getUsefulBitsFromBitfieldMoveOpd(Op, UsefulBits, Imm, MSB, Depth);
1514 APInt OpUsefulBits(UsefulBits);
1518 OpUsefulBits = OpUsefulBits.shl(MSB - Imm + 1);
1520 UsefulBits &= ~OpUsefulBits;
1521 getUsefulBits(Op, UsefulBits, Depth + 1);
1523 OpUsefulBits = OpUsefulBits.shl(MSB + 1);
1525 UsefulBits = ~(OpUsefulBits.shl(OpUsefulBits.getBitWidth() - Imm));
1526 getUsefulBits(Op, UsefulBits, Depth + 1);
1530 static void getUsefulBitsForUse(SDNode *UserNode, APInt &UsefulBits,
1531 SDValue Orig, unsigned Depth) {
1533 // Users of this node should have already been instruction selected
1534 // FIXME: Can we turn that into an assert?
1535 if (!UserNode->isMachineOpcode())
1538 switch (UserNode->getMachineOpcode()) {
1541 case ARM64::ANDSWri:
1542 case ARM64::ANDSXri:
1545 // We increment Depth only when we call the getUsefulBits
1546 return getUsefulBitsFromAndWithImmediate(SDValue(UserNode, 0), UsefulBits,
1548 case ARM64::UBFMWri:
1549 case ARM64::UBFMXri:
1550 return getUsefulBitsFromUBFM(SDValue(UserNode, 0), UsefulBits, Depth);
1554 if (UserNode->getOperand(1) != Orig)
1556 return getUsefulBitsFromOrWithShiftedReg(SDValue(UserNode, 0), UsefulBits,
1560 return getUsefulBitsFromBFM(SDValue(UserNode, 0), Orig, UsefulBits, Depth);
1564 static void getUsefulBits(SDValue Op, APInt &UsefulBits, unsigned Depth) {
1567 // Initialize UsefulBits
1569 unsigned Bitwidth = Op.getValueType().getScalarType().getSizeInBits();
1570 // At the beginning, assume every produced bits is useful
1571 UsefulBits = APInt(Bitwidth, 0);
1572 UsefulBits.flipAllBits();
1574 APInt UsersUsefulBits(UsefulBits.getBitWidth(), 0);
1576 for (SDNode::use_iterator UseIt = Op.getNode()->use_begin(),
1577 UseEnd = Op.getNode()->use_end();
1578 UseIt != UseEnd; ++UseIt) {
1579 // A use cannot produce useful bits
1580 APInt UsefulBitsForUse = APInt(UsefulBits);
1581 getUsefulBitsForUse(*UseIt, UsefulBitsForUse, Op, Depth);
1582 UsersUsefulBits |= UsefulBitsForUse;
1584 // UsefulBits contains the produced bits that are meaningful for the
1585 // current definition, thus a user cannot make a bit meaningful at
1587 UsefulBits &= UsersUsefulBits;
1590 // Given a OR operation, check if we have the following pattern
1591 // ubfm c, b, imm, imm2 (or something that does the same jobs, see
1592 // isBitfieldExtractOp)
1593 // d = e & mask2 ; where mask is a binary sequence of 1..10..0 and
1594 // countTrailingZeros(mask2) == imm2 - imm + 1
1596 // if yes, given reference arguments will be update so that one can replace
1597 // the OR instruction with:
1598 // f = Opc Opd0, Opd1, LSB, MSB ; where Opc is a BFM, LSB = imm, and MSB = imm2
1599 static bool isBitfieldInsertOpFromOr(SDNode *N, unsigned &Opc, SDValue &Opd0,
1600 SDValue &Opd1, unsigned &LSB,
1601 unsigned &MSB, SelectionDAG *CurDAG) {
1602 assert(N->getOpcode() == ISD::OR && "Expect a OR operation");
1605 EVT VT = N->getValueType(0);
1607 Opc = ARM64::BFMWri;
1608 else if (VT == MVT::i64)
1609 Opc = ARM64::BFMXri;
1613 // Because of simplify-demanded-bits in DAGCombine, involved masks may not
1614 // have the expected shape. Try to undo that.
1616 getUsefulBits(SDValue(N, 0), UsefulBits);
1618 unsigned NumberOfIgnoredLowBits = UsefulBits.countTrailingZeros();
1619 unsigned NumberOfIgnoredHighBits = UsefulBits.countLeadingZeros();
1621 // OR is commutative, check both possibilities (does llvm provide a
1622 // way to do that directely, e.g., via code matcher?)
1623 SDValue OrOpd1Val = N->getOperand(1);
1624 SDNode *OrOpd0 = N->getOperand(0).getNode();
1625 SDNode *OrOpd1 = N->getOperand(1).getNode();
1626 for (int i = 0; i < 2;
1627 ++i, std::swap(OrOpd0, OrOpd1), OrOpd1Val = N->getOperand(0)) {
1629 // Set Opd1, LSB and MSB arguments by looking for
1630 // c = ubfm b, imm, imm2
1631 if (!isBitfieldExtractOp(CurDAG, OrOpd0, BFXOpc, Opd1, LSB, MSB,
1632 NumberOfIgnoredLowBits, true))
1635 // Check that the returned opcode is compatible with the pattern,
1636 // i.e., same type and zero extended (U and not S)
1637 if ((BFXOpc != ARM64::UBFMXri && VT == MVT::i64) ||
1638 (BFXOpc != ARM64::UBFMWri && VT == MVT::i32))
1641 // Compute the width of the bitfield insertion
1642 int sMSB = MSB - LSB + 1;
1643 // FIXME: This constraints is to catch bitfield insertion we may
1644 // want to widen the pattern if we want to grab general bitfied
1649 // Check the second part of the pattern
1650 EVT VT = OrOpd1->getValueType(0);
1651 if (VT != MVT::i32 && VT != MVT::i64)
1654 // Compute the Known Zero for the candidate of the first operand.
1655 // This allows to catch more general case than just looking for
1656 // AND with imm. Indeed, simplify-demanded-bits may have removed
1657 // the AND instruction because it proves it was useless.
1658 APInt KnownZero, KnownOne;
1659 CurDAG->ComputeMaskedBits(OrOpd1Val, KnownZero, KnownOne);
1661 // Check if there is enough room for the second operand to appear
1663 if (KnownZero.countTrailingOnes() < (unsigned)sMSB)
1666 // Set the first operand
1668 if (isOpcWithIntImmediate(OrOpd1, ISD::AND, Imm) &&
1669 isHighMask(Imm, sMSB, NumberOfIgnoredHighBits, VT))
1670 // In that case, we can eliminate the AND
1671 Opd0 = OrOpd1->getOperand(0);
1673 // Maybe the AND has been removed by simplify-demanded-bits
1674 // or is useful because it discards more bits
1684 SDNode *ARM64DAGToDAGISel::SelectBitfieldInsertOp(SDNode *N) {
1685 if (N->getOpcode() != ISD::OR)
1692 if (!isBitfieldInsertOpFromOr(N, Opc, Opd0, Opd1, LSB, MSB, CurDAG))
1695 EVT VT = N->getValueType(0);
1696 SDValue Ops[] = { Opd0,
1698 CurDAG->getTargetConstant(LSB, VT),
1699 CurDAG->getTargetConstant(MSB, VT) };
1700 return CurDAG->SelectNodeTo(N, Opc, VT, Ops, 4);
1703 SDNode *ARM64DAGToDAGISel::SelectLIBM(SDNode *N) {
1704 EVT VT = N->getValueType(0);
1707 unsigned FRINTXOpcs[] = { ARM64::FRINTXSr, ARM64::FRINTXDr };
1709 if (VT == MVT::f32) {
1711 } else if (VT == MVT::f64) {
1714 return 0; // Unrecognized argument type. Fall back on default codegen.
1716 // Pick the FRINTX variant needed to set the flags.
1717 unsigned FRINTXOpc = FRINTXOpcs[Variant];
1719 switch (N->getOpcode()) {
1721 return 0; // Unrecognized libm ISD node. Fall back on default codegen.
1723 unsigned FRINTPOpcs[] = { ARM64::FRINTPSr, ARM64::FRINTPDr };
1724 Opc = FRINTPOpcs[Variant];
1728 unsigned FRINTMOpcs[] = { ARM64::FRINTMSr, ARM64::FRINTMDr };
1729 Opc = FRINTMOpcs[Variant];
1733 unsigned FRINTZOpcs[] = { ARM64::FRINTZSr, ARM64::FRINTZDr };
1734 Opc = FRINTZOpcs[Variant];
1738 unsigned FRINTAOpcs[] = { ARM64::FRINTASr, ARM64::FRINTADr };
1739 Opc = FRINTAOpcs[Variant];
1745 SDValue In = N->getOperand(0);
1746 SmallVector<SDValue, 2> Ops;
1749 if (!TM.Options.UnsafeFPMath) {
1750 SDNode *FRINTX = CurDAG->getMachineNode(FRINTXOpc, dl, VT, MVT::Glue, In);
1751 Ops.push_back(SDValue(FRINTX, 1));
1754 return CurDAG->getMachineNode(Opc, dl, VT, Ops);
1757 SDNode *ARM64DAGToDAGISel::Select(SDNode *Node) {
1758 // Dump information about the Node being selected
1759 DEBUG(errs() << "Selecting: ");
1760 DEBUG(Node->dump(CurDAG));
1761 DEBUG(errs() << "\n");
1763 // If we have a custom node, we already have selected!
1764 if (Node->isMachineOpcode()) {
1765 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
1766 Node->setNodeId(-1);
1770 // Few custom selection stuff.
1771 SDNode *ResNode = 0;
1772 EVT VT = Node->getValueType(0);
1774 switch (Node->getOpcode()) {
1779 if (SDNode *I = SelectMLAV64LaneV128(Node))
1783 case ISD::ATOMIC_LOAD_ADD:
1784 return SelectAtomic(Node, ARM64::ATOMIC_LOAD_ADD_I8,
1785 ARM64::ATOMIC_LOAD_ADD_I16, ARM64::ATOMIC_LOAD_ADD_I32,
1786 ARM64::ATOMIC_LOAD_ADD_I64);
1787 case ISD::ATOMIC_LOAD_SUB:
1788 return SelectAtomic(Node, ARM64::ATOMIC_LOAD_SUB_I8,
1789 ARM64::ATOMIC_LOAD_SUB_I16, ARM64::ATOMIC_LOAD_SUB_I32,
1790 ARM64::ATOMIC_LOAD_SUB_I64);
1791 case ISD::ATOMIC_LOAD_AND:
1792 return SelectAtomic(Node, ARM64::ATOMIC_LOAD_AND_I8,
1793 ARM64::ATOMIC_LOAD_AND_I16, ARM64::ATOMIC_LOAD_AND_I32,
1794 ARM64::ATOMIC_LOAD_AND_I64);
1795 case ISD::ATOMIC_LOAD_OR:
1796 return SelectAtomic(Node, ARM64::ATOMIC_LOAD_OR_I8,
1797 ARM64::ATOMIC_LOAD_OR_I16, ARM64::ATOMIC_LOAD_OR_I32,
1798 ARM64::ATOMIC_LOAD_OR_I64);
1799 case ISD::ATOMIC_LOAD_XOR:
1800 return SelectAtomic(Node, ARM64::ATOMIC_LOAD_XOR_I8,
1801 ARM64::ATOMIC_LOAD_XOR_I16, ARM64::ATOMIC_LOAD_XOR_I32,
1802 ARM64::ATOMIC_LOAD_XOR_I64);
1803 case ISD::ATOMIC_LOAD_NAND:
1804 return SelectAtomic(
1805 Node, ARM64::ATOMIC_LOAD_NAND_I8, ARM64::ATOMIC_LOAD_NAND_I16,
1806 ARM64::ATOMIC_LOAD_NAND_I32, ARM64::ATOMIC_LOAD_NAND_I64);
1807 case ISD::ATOMIC_LOAD_MIN:
1808 return SelectAtomic(Node, ARM64::ATOMIC_LOAD_MIN_I8,
1809 ARM64::ATOMIC_LOAD_MIN_I16, ARM64::ATOMIC_LOAD_MIN_I32,
1810 ARM64::ATOMIC_LOAD_MIN_I64);
1811 case ISD::ATOMIC_LOAD_MAX:
1812 return SelectAtomic(Node, ARM64::ATOMIC_LOAD_MAX_I8,
1813 ARM64::ATOMIC_LOAD_MAX_I16, ARM64::ATOMIC_LOAD_MAX_I32,
1814 ARM64::ATOMIC_LOAD_MAX_I64);
1815 case ISD::ATOMIC_LOAD_UMIN:
1816 return SelectAtomic(
1817 Node, ARM64::ATOMIC_LOAD_UMIN_I8, ARM64::ATOMIC_LOAD_UMIN_I16,
1818 ARM64::ATOMIC_LOAD_UMIN_I32, ARM64::ATOMIC_LOAD_UMIN_I64);
1819 case ISD::ATOMIC_LOAD_UMAX:
1820 return SelectAtomic(
1821 Node, ARM64::ATOMIC_LOAD_UMAX_I8, ARM64::ATOMIC_LOAD_UMAX_I16,
1822 ARM64::ATOMIC_LOAD_UMAX_I32, ARM64::ATOMIC_LOAD_UMAX_I64);
1823 case ISD::ATOMIC_SWAP:
1824 return SelectAtomic(Node, ARM64::ATOMIC_SWAP_I8, ARM64::ATOMIC_SWAP_I16,
1825 ARM64::ATOMIC_SWAP_I32, ARM64::ATOMIC_SWAP_I64);
1826 case ISD::ATOMIC_CMP_SWAP:
1827 return SelectAtomic(Node, ARM64::ATOMIC_CMP_SWAP_I8,
1828 ARM64::ATOMIC_CMP_SWAP_I16, ARM64::ATOMIC_CMP_SWAP_I32,
1829 ARM64::ATOMIC_CMP_SWAP_I64);
1832 // Try to select as an indexed load. Fall through to normal processing
1835 SDNode *I = SelectIndexedLoad(Node, Done);
1844 if (SDNode *I = SelectBitfieldExtractOp(Node))
1849 if (SDNode *I = SelectBitfieldInsertOp(Node))
1853 case ISD::EXTRACT_VECTOR_ELT: {
1854 // Extracting lane zero is a special case where we can just use a plain
1855 // EXTRACT_SUBREG instruction, which will become FMOV. This is easier for
1856 // the rest of the compiler, especially the register allocator and copyi
1857 // propagation, to reason about, so is preferred when it's possible to
1859 ConstantSDNode *LaneNode = cast<ConstantSDNode>(Node->getOperand(1));
1860 // Bail and use the default Select() for non-zero lanes.
1861 if (LaneNode->getZExtValue() != 0)
1863 // If the element type is not the same as the result type, likewise
1864 // bail and use the default Select(), as there's more to do than just
1865 // a cross-class COPY. This catches extracts of i8 and i16 elements
1866 // since they will need an explicit zext.
1867 if (VT != Node->getOperand(0).getValueType().getVectorElementType())
1870 switch (Node->getOperand(0)
1872 .getVectorElementType()
1875 assert(0 && "Unexpected vector element type!");
1877 SubReg = ARM64::dsub;
1880 SubReg = ARM64::ssub;
1882 case 16: // FALLTHROUGH
1884 llvm_unreachable("unexpected zext-requiring extract element!");
1886 SDValue Extract = CurDAG->getTargetExtractSubreg(SubReg, SDLoc(Node), VT,
1887 Node->getOperand(0));
1888 DEBUG(dbgs() << "ISEL: Custom selection!\n=> ");
1889 DEBUG(Extract->dumpr(CurDAG));
1890 DEBUG(dbgs() << "\n");
1891 return Extract.getNode();
1893 case ISD::Constant: {
1894 // Materialize zero constants as copies from WZR/XZR. This allows
1895 // the coalescer to propagate these into other instructions.
1896 ConstantSDNode *ConstNode = cast<ConstantSDNode>(Node);
1897 if (ConstNode->isNullValue()) {
1899 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
1900 ARM64::WZR, MVT::i32).getNode();
1901 else if (VT == MVT::i64)
1902 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node),
1903 ARM64::XZR, MVT::i64).getNode();
1908 case ISD::FrameIndex: {
1909 // Selects to ADDXri FI, 0 which in turn will become ADDXri SP, imm.
1910 int FI = cast<FrameIndexSDNode>(Node)->getIndex();
1911 unsigned Shifter = ARM64_AM::getShifterImm(ARM64_AM::LSL, 0);
1912 const TargetLowering *TLI = getTargetLowering();
1913 SDValue TFI = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy());
1914 SDValue Ops[] = { TFI, CurDAG->getTargetConstant(0, MVT::i32),
1915 CurDAG->getTargetConstant(Shifter, MVT::i32) };
1916 return CurDAG->SelectNodeTo(Node, ARM64::ADDXri, MVT::i64, Ops, 3);
1918 case ISD::INTRINSIC_W_CHAIN: {
1919 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
1923 case Intrinsic::arm64_ldxp: {
1924 SDValue MemAddr = Node->getOperand(2);
1926 SDValue Chain = Node->getOperand(0);
1928 SDNode *Ld = CurDAG->getMachineNode(ARM64::LDXPX, DL, MVT::i64, MVT::i64,
1929 MVT::Other, MemAddr, Chain);
1931 // Transfer memoperands.
1932 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1933 MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
1934 cast<MachineSDNode>(Ld)->setMemRefs(MemOp, MemOp + 1);
1937 case Intrinsic::arm64_stxp: {
1939 SDValue Chain = Node->getOperand(0);
1940 SDValue ValLo = Node->getOperand(2);
1941 SDValue ValHi = Node->getOperand(3);
1942 SDValue MemAddr = Node->getOperand(4);
1944 // Place arguments in the right order.
1945 SmallVector<SDValue, 7> Ops;
1946 Ops.push_back(ValLo);
1947 Ops.push_back(ValHi);
1948 Ops.push_back(MemAddr);
1949 Ops.push_back(Chain);
1952 CurDAG->getMachineNode(ARM64::STXPX, DL, MVT::i32, MVT::Other, Ops);
1953 // Transfer memoperands.
1954 MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1);
1955 MemOp[0] = cast<MemIntrinsicSDNode>(Node)->getMemOperand();
1956 cast<MachineSDNode>(St)->setMemRefs(MemOp, MemOp + 1);
1960 case Intrinsic::arm64_neon_ld1x2:
1961 if (VT == MVT::v8i8)
1962 return SelectLoad(Node, 2, ARM64::LD1Twov8b, ARM64::dsub0);
1963 else if (VT == MVT::v16i8)
1964 return SelectLoad(Node, 2, ARM64::LD1Twov16b, ARM64::qsub0);
1965 else if (VT == MVT::v4i16)
1966 return SelectLoad(Node, 2, ARM64::LD1Twov4h, ARM64::dsub0);
1967 else if (VT == MVT::v8i16)
1968 return SelectLoad(Node, 2, ARM64::LD1Twov8h, ARM64::qsub0);
1969 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
1970 return SelectLoad(Node, 2, ARM64::LD1Twov2s, ARM64::dsub0);
1971 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
1972 return SelectLoad(Node, 2, ARM64::LD1Twov4s, ARM64::qsub0);
1973 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
1974 return SelectLoad(Node, 2, ARM64::LD1Twov1d, ARM64::dsub0);
1975 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
1976 return SelectLoad(Node, 2, ARM64::LD1Twov2d, ARM64::qsub0);
1978 case Intrinsic::arm64_neon_ld1x3:
1979 if (VT == MVT::v8i8)
1980 return SelectLoad(Node, 3, ARM64::LD1Threev8b, ARM64::dsub0);
1981 else if (VT == MVT::v16i8)
1982 return SelectLoad(Node, 3, ARM64::LD1Threev16b, ARM64::qsub0);
1983 else if (VT == MVT::v4i16)
1984 return SelectLoad(Node, 3, ARM64::LD1Threev4h, ARM64::dsub0);
1985 else if (VT == MVT::v8i16)
1986 return SelectLoad(Node, 3, ARM64::LD1Threev8h, ARM64::qsub0);
1987 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
1988 return SelectLoad(Node, 3, ARM64::LD1Threev2s, ARM64::dsub0);
1989 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
1990 return SelectLoad(Node, 3, ARM64::LD1Threev4s, ARM64::qsub0);
1991 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
1992 return SelectLoad(Node, 3, ARM64::LD1Threev1d, ARM64::dsub0);
1993 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
1994 return SelectLoad(Node, 3, ARM64::LD1Threev2d, ARM64::qsub0);
1996 case Intrinsic::arm64_neon_ld1x4:
1997 if (VT == MVT::v8i8)
1998 return SelectLoad(Node, 4, ARM64::LD1Fourv8b, ARM64::dsub0);
1999 else if (VT == MVT::v16i8)
2000 return SelectLoad(Node, 4, ARM64::LD1Fourv16b, ARM64::qsub0);
2001 else if (VT == MVT::v4i16)
2002 return SelectLoad(Node, 4, ARM64::LD1Fourv4h, ARM64::dsub0);
2003 else if (VT == MVT::v8i16)
2004 return SelectLoad(Node, 4, ARM64::LD1Fourv8h, ARM64::qsub0);
2005 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2006 return SelectLoad(Node, 4, ARM64::LD1Fourv2s, ARM64::dsub0);
2007 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2008 return SelectLoad(Node, 4, ARM64::LD1Fourv4s, ARM64::qsub0);
2009 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2010 return SelectLoad(Node, 4, ARM64::LD1Fourv1d, ARM64::dsub0);
2011 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2012 return SelectLoad(Node, 4, ARM64::LD1Fourv2d, ARM64::qsub0);
2014 case Intrinsic::arm64_neon_ld2:
2015 if (VT == MVT::v8i8)
2016 return SelectLoad(Node, 2, ARM64::LD2Twov8b, ARM64::dsub0);
2017 else if (VT == MVT::v16i8)
2018 return SelectLoad(Node, 2, ARM64::LD2Twov16b, ARM64::qsub0);
2019 else if (VT == MVT::v4i16)
2020 return SelectLoad(Node, 2, ARM64::LD2Twov4h, ARM64::dsub0);
2021 else if (VT == MVT::v8i16)
2022 return SelectLoad(Node, 2, ARM64::LD2Twov8h, ARM64::qsub0);
2023 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2024 return SelectLoad(Node, 2, ARM64::LD2Twov2s, ARM64::dsub0);
2025 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2026 return SelectLoad(Node, 2, ARM64::LD2Twov4s, ARM64::qsub0);
2027 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2028 return SelectLoad(Node, 2, ARM64::LD1Twov1d, ARM64::dsub0);
2029 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2030 return SelectLoad(Node, 2, ARM64::LD2Twov2d, ARM64::qsub0);
2032 case Intrinsic::arm64_neon_ld3:
2033 if (VT == MVT::v8i8)
2034 return SelectLoad(Node, 3, ARM64::LD3Threev8b, ARM64::dsub0);
2035 else if (VT == MVT::v16i8)
2036 return SelectLoad(Node, 3, ARM64::LD3Threev16b, ARM64::qsub0);
2037 else if (VT == MVT::v4i16)
2038 return SelectLoad(Node, 3, ARM64::LD3Threev4h, ARM64::dsub0);
2039 else if (VT == MVT::v8i16)
2040 return SelectLoad(Node, 3, ARM64::LD3Threev8h, ARM64::qsub0);
2041 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2042 return SelectLoad(Node, 3, ARM64::LD3Threev2s, ARM64::dsub0);
2043 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2044 return SelectLoad(Node, 3, ARM64::LD3Threev4s, ARM64::qsub0);
2045 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2046 return SelectLoad(Node, 3, ARM64::LD1Threev1d, ARM64::dsub0);
2047 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2048 return SelectLoad(Node, 3, ARM64::LD3Threev2d, ARM64::qsub0);
2050 case Intrinsic::arm64_neon_ld4:
2051 if (VT == MVT::v8i8)
2052 return SelectLoad(Node, 4, ARM64::LD4Fourv8b, ARM64::dsub0);
2053 else if (VT == MVT::v16i8)
2054 return SelectLoad(Node, 4, ARM64::LD4Fourv16b, ARM64::qsub0);
2055 else if (VT == MVT::v4i16)
2056 return SelectLoad(Node, 4, ARM64::LD4Fourv4h, ARM64::dsub0);
2057 else if (VT == MVT::v8i16)
2058 return SelectLoad(Node, 4, ARM64::LD4Fourv8h, ARM64::qsub0);
2059 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2060 return SelectLoad(Node, 4, ARM64::LD4Fourv2s, ARM64::dsub0);
2061 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2062 return SelectLoad(Node, 4, ARM64::LD4Fourv4s, ARM64::qsub0);
2063 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2064 return SelectLoad(Node, 4, ARM64::LD1Fourv1d, ARM64::dsub0);
2065 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2066 return SelectLoad(Node, 4, ARM64::LD4Fourv2d, ARM64::qsub0);
2068 case Intrinsic::arm64_neon_ld2r:
2069 if (VT == MVT::v8i8)
2070 return SelectLoad(Node, 2, ARM64::LD2Rv8b, ARM64::dsub0);
2071 else if (VT == MVT::v16i8)
2072 return SelectLoad(Node, 2, ARM64::LD2Rv16b, ARM64::qsub0);
2073 else if (VT == MVT::v4i16)
2074 return SelectLoad(Node, 2, ARM64::LD2Rv4h, ARM64::dsub0);
2075 else if (VT == MVT::v8i16)
2076 return SelectLoad(Node, 2, ARM64::LD2Rv8h, ARM64::qsub0);
2077 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2078 return SelectLoad(Node, 2, ARM64::LD2Rv2s, ARM64::dsub0);
2079 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2080 return SelectLoad(Node, 2, ARM64::LD2Rv4s, ARM64::qsub0);
2081 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2082 return SelectLoad(Node, 2, ARM64::LD2Rv1d, ARM64::dsub0);
2083 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2084 return SelectLoad(Node, 2, ARM64::LD2Rv2d, ARM64::qsub0);
2086 case Intrinsic::arm64_neon_ld3r:
2087 if (VT == MVT::v8i8)
2088 return SelectLoad(Node, 3, ARM64::LD3Rv8b, ARM64::dsub0);
2089 else if (VT == MVT::v16i8)
2090 return SelectLoad(Node, 3, ARM64::LD3Rv16b, ARM64::qsub0);
2091 else if (VT == MVT::v4i16)
2092 return SelectLoad(Node, 3, ARM64::LD3Rv4h, ARM64::dsub0);
2093 else if (VT == MVT::v8i16)
2094 return SelectLoad(Node, 3, ARM64::LD3Rv8h, ARM64::qsub0);
2095 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2096 return SelectLoad(Node, 3, ARM64::LD3Rv2s, ARM64::dsub0);
2097 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2098 return SelectLoad(Node, 3, ARM64::LD3Rv4s, ARM64::qsub0);
2099 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2100 return SelectLoad(Node, 3, ARM64::LD3Rv1d, ARM64::dsub0);
2101 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2102 return SelectLoad(Node, 3, ARM64::LD3Rv2d, ARM64::qsub0);
2104 case Intrinsic::arm64_neon_ld4r:
2105 if (VT == MVT::v8i8)
2106 return SelectLoad(Node, 4, ARM64::LD4Rv8b, ARM64::dsub0);
2107 else if (VT == MVT::v16i8)
2108 return SelectLoad(Node, 4, ARM64::LD4Rv16b, ARM64::qsub0);
2109 else if (VT == MVT::v4i16)
2110 return SelectLoad(Node, 4, ARM64::LD4Rv4h, ARM64::dsub0);
2111 else if (VT == MVT::v8i16)
2112 return SelectLoad(Node, 4, ARM64::LD4Rv8h, ARM64::qsub0);
2113 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2114 return SelectLoad(Node, 4, ARM64::LD4Rv2s, ARM64::dsub0);
2115 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2116 return SelectLoad(Node, 4, ARM64::LD4Rv4s, ARM64::qsub0);
2117 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2118 return SelectLoad(Node, 4, ARM64::LD4Rv1d, ARM64::dsub0);
2119 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2120 return SelectLoad(Node, 4, ARM64::LD4Rv2d, ARM64::qsub0);
2122 case Intrinsic::arm64_neon_ld2lane:
2123 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2124 return SelectLoadLane(Node, 2, ARM64::LD2i8);
2125 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2126 return SelectLoadLane(Node, 2, ARM64::LD2i16);
2127 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2129 return SelectLoadLane(Node, 2, ARM64::LD2i32);
2130 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2132 return SelectLoadLane(Node, 2, ARM64::LD2i64);
2134 case Intrinsic::arm64_neon_ld3lane:
2135 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2136 return SelectLoadLane(Node, 3, ARM64::LD3i8);
2137 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2138 return SelectLoadLane(Node, 3, ARM64::LD3i16);
2139 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2141 return SelectLoadLane(Node, 3, ARM64::LD3i32);
2142 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2144 return SelectLoadLane(Node, 3, ARM64::LD3i64);
2146 case Intrinsic::arm64_neon_ld4lane:
2147 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2148 return SelectLoadLane(Node, 4, ARM64::LD4i8);
2149 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2150 return SelectLoadLane(Node, 4, ARM64::LD4i16);
2151 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2153 return SelectLoadLane(Node, 4, ARM64::LD4i32);
2154 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2156 return SelectLoadLane(Node, 4, ARM64::LD4i64);
2160 case ISD::INTRINSIC_WO_CHAIN: {
2161 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue();
2165 case Intrinsic::arm64_neon_tbl2:
2166 return SelectTable(Node, 2, VT == MVT::v8i8 ? ARM64::TBLv8i8Two
2167 : ARM64::TBLv16i8Two,
2169 case Intrinsic::arm64_neon_tbl3:
2170 return SelectTable(Node, 3, VT == MVT::v8i8 ? ARM64::TBLv8i8Three
2171 : ARM64::TBLv16i8Three,
2173 case Intrinsic::arm64_neon_tbl4:
2174 return SelectTable(Node, 4, VT == MVT::v8i8 ? ARM64::TBLv8i8Four
2175 : ARM64::TBLv16i8Four,
2177 case Intrinsic::arm64_neon_tbx2:
2178 return SelectTable(Node, 2, VT == MVT::v8i8 ? ARM64::TBXv8i8Two
2179 : ARM64::TBXv16i8Two,
2181 case Intrinsic::arm64_neon_tbx3:
2182 return SelectTable(Node, 3, VT == MVT::v8i8 ? ARM64::TBXv8i8Three
2183 : ARM64::TBXv16i8Three,
2185 case Intrinsic::arm64_neon_tbx4:
2186 return SelectTable(Node, 4, VT == MVT::v8i8 ? ARM64::TBXv8i8Four
2187 : ARM64::TBXv16i8Four,
2189 case Intrinsic::arm64_neon_smull:
2190 case Intrinsic::arm64_neon_umull:
2191 if (SDNode *N = SelectMULLV64LaneV128(IntNo, Node))
2197 case ISD::INTRINSIC_VOID: {
2198 unsigned IntNo = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue();
2199 if (Node->getNumOperands() >= 3)
2200 VT = Node->getOperand(2)->getValueType(0);
2204 case Intrinsic::arm64_neon_st1x2: {
2205 if (VT == MVT::v8i8)
2206 return SelectStore(Node, 2, ARM64::ST1Twov8b);
2207 else if (VT == MVT::v16i8)
2208 return SelectStore(Node, 2, ARM64::ST1Twov16b);
2209 else if (VT == MVT::v4i16)
2210 return SelectStore(Node, 2, ARM64::ST1Twov4h);
2211 else if (VT == MVT::v8i16)
2212 return SelectStore(Node, 2, ARM64::ST1Twov8h);
2213 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2214 return SelectStore(Node, 2, ARM64::ST1Twov2s);
2215 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2216 return SelectStore(Node, 2, ARM64::ST1Twov4s);
2217 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2218 return SelectStore(Node, 2, ARM64::ST1Twov2d);
2219 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2220 return SelectStore(Node, 2, ARM64::ST1Twov1d);
2223 case Intrinsic::arm64_neon_st1x3: {
2224 if (VT == MVT::v8i8)
2225 return SelectStore(Node, 3, ARM64::ST1Threev8b);
2226 else if (VT == MVT::v16i8)
2227 return SelectStore(Node, 3, ARM64::ST1Threev16b);
2228 else if (VT == MVT::v4i16)
2229 return SelectStore(Node, 3, ARM64::ST1Threev4h);
2230 else if (VT == MVT::v8i16)
2231 return SelectStore(Node, 3, ARM64::ST1Threev8h);
2232 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2233 return SelectStore(Node, 3, ARM64::ST1Threev2s);
2234 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2235 return SelectStore(Node, 3, ARM64::ST1Threev4s);
2236 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2237 return SelectStore(Node, 3, ARM64::ST1Threev2d);
2238 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2239 return SelectStore(Node, 3, ARM64::ST1Threev1d);
2242 case Intrinsic::arm64_neon_st1x4: {
2243 if (VT == MVT::v8i8)
2244 return SelectStore(Node, 4, ARM64::ST1Fourv8b);
2245 else if (VT == MVT::v16i8)
2246 return SelectStore(Node, 4, ARM64::ST1Fourv16b);
2247 else if (VT == MVT::v4i16)
2248 return SelectStore(Node, 4, ARM64::ST1Fourv4h);
2249 else if (VT == MVT::v8i16)
2250 return SelectStore(Node, 4, ARM64::ST1Fourv8h);
2251 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2252 return SelectStore(Node, 4, ARM64::ST1Fourv2s);
2253 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2254 return SelectStore(Node, 4, ARM64::ST1Fourv4s);
2255 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2256 return SelectStore(Node, 4, ARM64::ST1Fourv2d);
2257 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2258 return SelectStore(Node, 4, ARM64::ST1Fourv1d);
2261 case Intrinsic::arm64_neon_st2: {
2262 if (VT == MVT::v8i8)
2263 return SelectStore(Node, 2, ARM64::ST2Twov8b);
2264 else if (VT == MVT::v16i8)
2265 return SelectStore(Node, 2, ARM64::ST2Twov16b);
2266 else if (VT == MVT::v4i16)
2267 return SelectStore(Node, 2, ARM64::ST2Twov4h);
2268 else if (VT == MVT::v8i16)
2269 return SelectStore(Node, 2, ARM64::ST2Twov8h);
2270 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2271 return SelectStore(Node, 2, ARM64::ST2Twov2s);
2272 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2273 return SelectStore(Node, 2, ARM64::ST2Twov4s);
2274 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2275 return SelectStore(Node, 2, ARM64::ST2Twov2d);
2276 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2277 return SelectStore(Node, 2, ARM64::ST1Twov1d);
2280 case Intrinsic::arm64_neon_st3: {
2281 if (VT == MVT::v8i8)
2282 return SelectStore(Node, 3, ARM64::ST3Threev8b);
2283 else if (VT == MVT::v16i8)
2284 return SelectStore(Node, 3, ARM64::ST3Threev16b);
2285 else if (VT == MVT::v4i16)
2286 return SelectStore(Node, 3, ARM64::ST3Threev4h);
2287 else if (VT == MVT::v8i16)
2288 return SelectStore(Node, 3, ARM64::ST3Threev8h);
2289 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2290 return SelectStore(Node, 3, ARM64::ST3Threev2s);
2291 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2292 return SelectStore(Node, 3, ARM64::ST3Threev4s);
2293 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2294 return SelectStore(Node, 3, ARM64::ST3Threev2d);
2295 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2296 return SelectStore(Node, 3, ARM64::ST1Threev1d);
2299 case Intrinsic::arm64_neon_st4: {
2300 if (VT == MVT::v8i8)
2301 return SelectStore(Node, 4, ARM64::ST4Fourv8b);
2302 else if (VT == MVT::v16i8)
2303 return SelectStore(Node, 4, ARM64::ST4Fourv16b);
2304 else if (VT == MVT::v4i16)
2305 return SelectStore(Node, 4, ARM64::ST4Fourv4h);
2306 else if (VT == MVT::v8i16)
2307 return SelectStore(Node, 4, ARM64::ST4Fourv8h);
2308 else if (VT == MVT::v2i32 || VT == MVT::v2f32)
2309 return SelectStore(Node, 4, ARM64::ST4Fourv2s);
2310 else if (VT == MVT::v4i32 || VT == MVT::v4f32)
2311 return SelectStore(Node, 4, ARM64::ST4Fourv4s);
2312 else if (VT == MVT::v2i64 || VT == MVT::v2f64)
2313 return SelectStore(Node, 4, ARM64::ST4Fourv2d);
2314 else if (VT == MVT::v1i64 || VT == MVT::v1f64)
2315 return SelectStore(Node, 4, ARM64::ST1Fourv1d);
2318 case Intrinsic::arm64_neon_st2lane: {
2319 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2320 return SelectStoreLane(Node, 2, ARM64::ST2i8);
2321 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2322 return SelectStoreLane(Node, 2, ARM64::ST2i16);
2323 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2325 return SelectStoreLane(Node, 2, ARM64::ST2i32);
2326 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2328 return SelectStoreLane(Node, 2, ARM64::ST2i64);
2331 case Intrinsic::arm64_neon_st3lane: {
2332 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2333 return SelectStoreLane(Node, 3, ARM64::ST3i8);
2334 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2335 return SelectStoreLane(Node, 3, ARM64::ST3i16);
2336 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2338 return SelectStoreLane(Node, 3, ARM64::ST3i32);
2339 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2341 return SelectStoreLane(Node, 3, ARM64::ST3i64);
2344 case Intrinsic::arm64_neon_st4lane: {
2345 if (VT == MVT::v16i8 || VT == MVT::v8i8)
2346 return SelectStoreLane(Node, 4, ARM64::ST4i8);
2347 else if (VT == MVT::v8i16 || VT == MVT::v4i16)
2348 return SelectStoreLane(Node, 4, ARM64::ST4i16);
2349 else if (VT == MVT::v4i32 || VT == MVT::v2i32 || VT == MVT::v4f32 ||
2351 return SelectStoreLane(Node, 4, ARM64::ST4i32);
2352 else if (VT == MVT::v2i64 || VT == MVT::v1i64 || VT == MVT::v2f64 ||
2354 return SelectStoreLane(Node, 4, ARM64::ST4i64);
2364 if (SDNode *I = SelectLIBM(Node))
2369 // Select the default instruction
2370 ResNode = SelectCode(Node);
2372 DEBUG(errs() << "=> ");
2373 if (ResNode == NULL || ResNode == Node)
2374 DEBUG(Node->dump(CurDAG));
2376 DEBUG(ResNode->dump(CurDAG));
2377 DEBUG(errs() << "\n");
2382 /// createARM64ISelDag - This pass converts a legalized DAG into a
2383 /// ARM64-specific DAG, ready for instruction scheduling.
2384 FunctionPass *llvm::createARM64ISelDag(ARM64TargetMachine &TM,
2385 CodeGenOpt::Level OptLevel) {
2386 return new ARM64DAGToDAGISel(TM, OptLevel);