1 //===- ARM64InstrFormats.td - ARM64 Instruction Formats ------*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe ARM64 instructions format here
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<2> val> {
21 def PseudoFrm : Format<0>;
22 def NormalFrm : Format<1>; // Do we need any others?
24 // ARM64 Instruction Format
25 class ARM64Inst<Format f, string cstr> : Instruction {
26 field bits<32> Inst; // Instruction encoding.
27 // Mask of bits that cause an encoding to be UNPREDICTABLE.
28 // If a bit is set, then if the corresponding bit in the
29 // target encoding differs from its value in the "Inst" field,
30 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
31 field bits<32> Unpredictable = 0;
32 // SoftFail is the generic name for this field, but we alias it so
33 // as to make it more obvious what it means in ARM-land.
34 field bits<32> SoftFail = Unpredictable;
35 let Namespace = "ARM64";
37 bits<2> Form = F.Value;
39 let Constraints = cstr;
42 // Pseudo instructions (don't have encoding information)
43 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
44 : ARM64Inst<PseudoFrm, cstr> {
45 dag OutOperandList = oops;
46 dag InOperandList = iops;
47 let Pattern = pattern;
48 let isCodeGenOnly = 1;
51 // Real instructions (have encoding information)
52 class EncodedI<string cstr, list<dag> pattern> : ARM64Inst<NormalFrm, cstr> {
53 let Pattern = pattern;
57 // Normal instructions
58 class I<dag oops, dag iops, string asm, string operands, string cstr,
60 : EncodedI<cstr, pattern> {
61 dag OutOperandList = oops;
62 dag InOperandList = iops;
63 let AsmString = !strconcat(asm, operands);
66 class TriOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$MHS, node:$RHS), res>;
67 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
68 class UnOpFrag<dag res> : PatFrag<(ops node:$LHS), res>;
70 // Helper fragment for an extract of the high portion of a 128-bit vector.
71 def extract_high_v16i8 :
72 UnOpFrag<(extract_subvector (v16i8 node:$LHS), (i64 8))>;
73 def extract_high_v8i16 :
74 UnOpFrag<(extract_subvector (v8i16 node:$LHS), (i64 4))>;
75 def extract_high_v4i32 :
76 UnOpFrag<(extract_subvector (v4i32 node:$LHS), (i64 2))>;
77 def extract_high_v2i64 :
78 UnOpFrag<(extract_subvector (v2i64 node:$LHS), (i64 1))>;
80 //===----------------------------------------------------------------------===//
81 // Asm Operand Classes.
84 // Shifter operand for arithmetic shifted encodings.
85 def ShifterOperand : AsmOperandClass {
89 // Shifter operand for mov immediate encodings.
90 def MovImm32ShifterOperand : AsmOperandClass {
91 let SuperClasses = [ShifterOperand];
92 let Name = "MovImm32Shifter";
94 def MovImm64ShifterOperand : AsmOperandClass {
95 let SuperClasses = [ShifterOperand];
96 let Name = "MovImm64Shifter";
99 // Shifter operand for arithmetic register shifted encodings.
100 def ArithmeticShifterOperand : AsmOperandClass {
101 let SuperClasses = [ShifterOperand];
102 let Name = "ArithmeticShifter";
105 // Shifter operand for arithmetic shifted encodings for ADD/SUB instructions.
106 def AddSubShifterOperand : AsmOperandClass {
107 let SuperClasses = [ArithmeticShifterOperand];
108 let Name = "AddSubShifter";
111 // Shifter operand for logical vector 128/64-bit shifted encodings.
112 def LogicalVecShifterOperand : AsmOperandClass {
113 let SuperClasses = [ShifterOperand];
114 let Name = "LogicalVecShifter";
116 def LogicalVecHalfWordShifterOperand : AsmOperandClass {
117 let SuperClasses = [LogicalVecShifterOperand];
118 let Name = "LogicalVecHalfWordShifter";
121 // The "MSL" shifter on the vector MOVI instruction.
122 def MoveVecShifterOperand : AsmOperandClass {
123 let SuperClasses = [ShifterOperand];
124 let Name = "MoveVecShifter";
127 // Extend operand for arithmetic encodings.
128 def ExtendOperand : AsmOperandClass { let Name = "Extend"; }
129 def ExtendOperand64 : AsmOperandClass {
130 let SuperClasses = [ExtendOperand];
131 let Name = "Extend64";
133 // 'extend' that's a lsl of a 64-bit register.
134 def ExtendOperandLSL64 : AsmOperandClass {
135 let SuperClasses = [ExtendOperand];
136 let Name = "ExtendLSL64";
139 // 8-bit floating-point immediate encodings.
140 def FPImmOperand : AsmOperandClass {
142 let ParserMethod = "tryParseFPImm";
145 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
146 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
147 // are encoded as the eight bit value 'abcdefgh'.
148 def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
151 //===----------------------------------------------------------------------===//
152 // Operand Definitions.
155 // ADR[P] instruction labels.
156 def AdrpOperand : AsmOperandClass {
157 let Name = "AdrpLabel";
158 let ParserMethod = "tryParseAdrpLabel";
160 def adrplabel : Operand<i64> {
161 let EncoderMethod = "getAdrLabelOpValue";
162 let PrintMethod = "printAdrpLabel";
163 let ParserMatchClass = AdrpOperand;
166 def AdrOperand : AsmOperandClass {
167 let Name = "AdrLabel";
168 let ParserMethod = "tryParseAdrLabel";
170 def adrlabel : Operand<i64> {
171 let EncoderMethod = "getAdrLabelOpValue";
172 let ParserMatchClass = AdrOperand;
175 // simm9 predicate - True if the immediate is in the range [-256, 255].
176 def SImm9Operand : AsmOperandClass {
178 let DiagnosticType = "InvalidMemoryIndexedSImm9";
180 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
181 let ParserMatchClass = SImm9Operand;
184 // simm7s4 predicate - True if the immediate is a multiple of 4 in the range
186 def SImm7s4Operand : AsmOperandClass {
187 let Name = "SImm7s4";
188 let DiagnosticType = "InvalidMemoryIndexed32SImm7";
190 def simm7s4 : Operand<i32> {
191 let ParserMatchClass = SImm7s4Operand;
192 let PrintMethod = "printImmScale4";
195 // simm7s8 predicate - True if the immediate is a multiple of 8 in the range
197 def SImm7s8Operand : AsmOperandClass {
198 let Name = "SImm7s8";
199 let DiagnosticType = "InvalidMemoryIndexed64SImm7";
201 def simm7s8 : Operand<i32> {
202 let ParserMatchClass = SImm7s8Operand;
203 let PrintMethod = "printImmScale8";
206 // simm7s16 predicate - True if the immediate is a multiple of 16 in the range
208 def SImm7s16Operand : AsmOperandClass {
209 let Name = "SImm7s16";
210 let DiagnosticType = "InvalidMemoryIndexed64SImm7";
212 def simm7s16 : Operand<i32> {
213 let ParserMatchClass = SImm7s16Operand;
214 let PrintMethod = "printImmScale16";
217 // imm0_65535 predicate - True if the immediate is in the range [0,65535].
218 def Imm0_65535Operand : AsmOperandClass { let Name = "Imm0_65535"; }
219 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
220 return ((uint32_t)Imm) < 65536;
222 let ParserMatchClass = Imm0_65535Operand;
225 def Imm1_8Operand : AsmOperandClass {
227 let DiagnosticType = "InvalidImm1_8";
229 def Imm1_16Operand : AsmOperandClass {
230 let Name = "Imm1_16";
231 let DiagnosticType = "InvalidImm1_16";
233 def Imm1_32Operand : AsmOperandClass {
234 let Name = "Imm1_32";
235 let DiagnosticType = "InvalidImm1_32";
237 def Imm1_64Operand : AsmOperandClass {
238 let Name = "Imm1_64";
239 let DiagnosticType = "InvalidImm1_64";
242 def MovZSymbolG3AsmOperand : AsmOperandClass {
243 let Name = "MovZSymbolG3";
244 let RenderMethod = "addImmOperands";
247 def movz_symbol_g3 : Operand<i32> {
248 let ParserMatchClass = MovZSymbolG3AsmOperand;
251 def MovZSymbolG2AsmOperand : AsmOperandClass {
252 let Name = "MovZSymbolG2";
253 let RenderMethod = "addImmOperands";
256 def movz_symbol_g2 : Operand<i32> {
257 let ParserMatchClass = MovZSymbolG2AsmOperand;
260 def MovZSymbolG1AsmOperand : AsmOperandClass {
261 let Name = "MovZSymbolG1";
262 let RenderMethod = "addImmOperands";
265 def movz_symbol_g1 : Operand<i32> {
266 let ParserMatchClass = MovZSymbolG1AsmOperand;
269 def MovZSymbolG0AsmOperand : AsmOperandClass {
270 let Name = "MovZSymbolG0";
271 let RenderMethod = "addImmOperands";
274 def movz_symbol_g0 : Operand<i32> {
275 let ParserMatchClass = MovZSymbolG0AsmOperand;
278 def MovKSymbolG2AsmOperand : AsmOperandClass {
279 let Name = "MovKSymbolG2";
280 let RenderMethod = "addImmOperands";
283 def movk_symbol_g2 : Operand<i32> {
284 let ParserMatchClass = MovKSymbolG2AsmOperand;
287 def MovKSymbolG1AsmOperand : AsmOperandClass {
288 let Name = "MovKSymbolG1";
289 let RenderMethod = "addImmOperands";
292 def movk_symbol_g1 : Operand<i32> {
293 let ParserMatchClass = MovKSymbolG1AsmOperand;
296 def MovKSymbolG0AsmOperand : AsmOperandClass {
297 let Name = "MovKSymbolG0";
298 let RenderMethod = "addImmOperands";
301 def movk_symbol_g0 : Operand<i32> {
302 let ParserMatchClass = MovKSymbolG0AsmOperand;
305 def fixedpoint32 : Operand<i32> {
306 let EncoderMethod = "getFixedPointScaleOpValue";
307 let DecoderMethod = "DecodeFixedPointScaleImm";
308 let ParserMatchClass = Imm1_32Operand;
310 def fixedpoint64 : Operand<i64> {
311 let EncoderMethod = "getFixedPointScaleOpValue";
312 let DecoderMethod = "DecodeFixedPointScaleImm";
313 let ParserMatchClass = Imm1_64Operand;
316 def vecshiftR8 : Operand<i32>, ImmLeaf<i32, [{
317 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
319 let EncoderMethod = "getVecShiftR8OpValue";
320 let DecoderMethod = "DecodeVecShiftR8Imm";
321 let ParserMatchClass = Imm1_8Operand;
323 def vecshiftR16 : Operand<i32>, ImmLeaf<i32, [{
324 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
326 let EncoderMethod = "getVecShiftR16OpValue";
327 let DecoderMethod = "DecodeVecShiftR16Imm";
328 let ParserMatchClass = Imm1_16Operand;
330 def vecshiftR16Narrow : Operand<i32>, ImmLeaf<i32, [{
331 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
333 let EncoderMethod = "getVecShiftR16OpValue";
334 let DecoderMethod = "DecodeVecShiftR16ImmNarrow";
335 let ParserMatchClass = Imm1_8Operand;
337 def vecshiftR32 : Operand<i32>, ImmLeaf<i32, [{
338 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
340 let EncoderMethod = "getVecShiftR32OpValue";
341 let DecoderMethod = "DecodeVecShiftR32Imm";
342 let ParserMatchClass = Imm1_32Operand;
344 def vecshiftR32Narrow : Operand<i32>, ImmLeaf<i32, [{
345 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
347 let EncoderMethod = "getVecShiftR32OpValue";
348 let DecoderMethod = "DecodeVecShiftR32ImmNarrow";
349 let ParserMatchClass = Imm1_16Operand;
351 def vecshiftR64 : Operand<i32>, ImmLeaf<i32, [{
352 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
354 let EncoderMethod = "getVecShiftR64OpValue";
355 let DecoderMethod = "DecodeVecShiftR64Imm";
356 let ParserMatchClass = Imm1_64Operand;
358 def vecshiftR64Narrow : Operand<i32>, ImmLeaf<i32, [{
359 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
361 let EncoderMethod = "getVecShiftR64OpValue";
362 let DecoderMethod = "DecodeVecShiftR64ImmNarrow";
363 let ParserMatchClass = Imm1_32Operand;
366 def Imm0_7Operand : AsmOperandClass { let Name = "Imm0_7"; }
367 def Imm0_15Operand : AsmOperandClass { let Name = "Imm0_15"; }
368 def Imm0_31Operand : AsmOperandClass { let Name = "Imm0_31"; }
369 def Imm0_63Operand : AsmOperandClass { let Name = "Imm0_63"; }
371 def vecshiftL8 : Operand<i32>, ImmLeaf<i32, [{
372 return (((uint32_t)Imm) < 8);
374 let EncoderMethod = "getVecShiftL8OpValue";
375 let DecoderMethod = "DecodeVecShiftL8Imm";
376 let ParserMatchClass = Imm0_7Operand;
378 def vecshiftL16 : Operand<i32>, ImmLeaf<i32, [{
379 return (((uint32_t)Imm) < 16);
381 let EncoderMethod = "getVecShiftL16OpValue";
382 let DecoderMethod = "DecodeVecShiftL16Imm";
383 let ParserMatchClass = Imm0_15Operand;
385 def vecshiftL32 : Operand<i32>, ImmLeaf<i32, [{
386 return (((uint32_t)Imm) < 32);
388 let EncoderMethod = "getVecShiftL32OpValue";
389 let DecoderMethod = "DecodeVecShiftL32Imm";
390 let ParserMatchClass = Imm0_31Operand;
392 def vecshiftL64 : Operand<i32>, ImmLeaf<i32, [{
393 return (((uint32_t)Imm) < 64);
395 let EncoderMethod = "getVecShiftL64OpValue";
396 let DecoderMethod = "DecodeVecShiftL64Imm";
397 let ParserMatchClass = Imm0_63Operand;
401 // Crazy immediate formats used by 32-bit and 64-bit logical immediate
402 // instructions for splatting repeating bit patterns across the immediate.
403 def logical_imm32_XFORM : SDNodeXForm<imm, [{
404 uint64_t enc = ARM64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
405 return CurDAG->getTargetConstant(enc, MVT::i32);
407 def logical_imm64_XFORM : SDNodeXForm<imm, [{
408 uint64_t enc = ARM64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
409 return CurDAG->getTargetConstant(enc, MVT::i32);
412 def LogicalImm32Operand : AsmOperandClass { let Name = "LogicalImm32"; }
413 def LogicalImm64Operand : AsmOperandClass { let Name = "LogicalImm64"; }
414 def logical_imm32 : Operand<i32>, PatLeaf<(imm), [{
415 return ARM64_AM::isLogicalImmediate(N->getZExtValue(), 32);
416 }], logical_imm32_XFORM> {
417 let PrintMethod = "printLogicalImm32";
418 let ParserMatchClass = LogicalImm32Operand;
420 def logical_imm64 : Operand<i64>, PatLeaf<(imm), [{
421 return ARM64_AM::isLogicalImmediate(N->getZExtValue(), 64);
422 }], logical_imm64_XFORM> {
423 let PrintMethod = "printLogicalImm64";
424 let ParserMatchClass = LogicalImm64Operand;
427 // imm0_255 predicate - True if the immediate is in the range [0,255].
428 def Imm0_255Operand : AsmOperandClass { let Name = "Imm0_255"; }
429 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
430 return ((uint32_t)Imm) < 256;
432 let ParserMatchClass = Imm0_255Operand;
435 // imm0_127 predicate - True if the immediate is in the range [0,127]
436 def Imm0_127Operand : AsmOperandClass { let Name = "Imm0_127"; }
437 def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
438 return ((uint32_t)Imm) < 128;
440 let ParserMatchClass = Imm0_127Operand;
443 // imm0_63 predicate - True if the immediate is in the range [0,63]
444 // NOTE: This has to be of type i64 because i64 is the shift-amount-size
446 def imm0_63 : Operand<i64>, ImmLeaf<i64, [{
447 return ((uint64_t)Imm) < 64;
449 let ParserMatchClass = Imm0_63Operand;
452 // imm0_31x predicate - True if the immediate is in the range [0,31]
453 // NOTE: This has to be of type i64 because i64 is the shift-amount-size
455 def imm0_31x : Operand<i64>, ImmLeaf<i64, [{
456 return ((uint64_t)Imm) < 32;
458 let ParserMatchClass = Imm0_31Operand;
461 // imm0_15x predicate - True if the immediate is in the range [0,15]
462 def imm0_15x : Operand<i64>, ImmLeaf<i64, [{
463 return ((uint64_t)Imm) < 16;
465 let ParserMatchClass = Imm0_15Operand;
468 // imm0_7x predicate - True if the immediate is in the range [0,7]
469 def imm0_7x : Operand<i64>, ImmLeaf<i64, [{
470 return ((uint64_t)Imm) < 8;
472 let ParserMatchClass = Imm0_7Operand;
475 // imm0_31 predicate - True if the immediate is in the range [0,31]
476 // NOTE: This has to be of type i32 because i32 is the shift-amount-size
478 def imm0_31 : Operand<i32>, ImmLeaf<i32, [{
479 return ((uint32_t)Imm) < 32;
481 let ParserMatchClass = Imm0_31Operand;
484 // imm0_15 predicate - True if the immediate is in the range [0,15]
485 def imm0_15 : Operand<i32>, ImmLeaf<i32, [{
486 return ((uint32_t)Imm) < 16;
488 let ParserMatchClass = Imm0_15Operand;
491 // imm0_7 predicate - True if the immediate is in the range [0,7]
492 def imm0_7 : Operand<i32>, ImmLeaf<i32, [{
493 return ((uint32_t)Imm) < 8;
495 let ParserMatchClass = Imm0_7Operand;
498 // An arithmetic shifter operand:
499 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
501 def arith_shift : Operand<i32> {
502 let PrintMethod = "printShifter";
503 let ParserMatchClass = ArithmeticShifterOperand;
506 class arith_shifted_reg<ValueType Ty, RegisterClass regclass>
508 ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
509 let PrintMethod = "printShiftedRegister";
510 let MIOperandInfo = (ops regclass, arith_shift);
513 def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32>;
514 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64>;
516 // An arithmetic shifter operand:
517 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr, 11 = ror
519 def logical_shift : Operand<i32> {
520 let PrintMethod = "printShifter";
521 let ParserMatchClass = ShifterOperand;
524 class logical_shifted_reg<ValueType Ty, RegisterClass regclass>
526 ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
527 let PrintMethod = "printShiftedRegister";
528 let MIOperandInfo = (ops regclass, logical_shift);
531 def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32>;
532 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64>;
534 // A logical vector shifter operand:
535 // {7-6} - shift type: 00 = lsl
536 // {5-0} - imm6: #0, #8, #16, or #24
537 def logical_vec_shift : Operand<i32> {
538 let PrintMethod = "printShifter";
539 let EncoderMethod = "getVecShifterOpValue";
540 let ParserMatchClass = LogicalVecShifterOperand;
543 // A logical vector half-word shifter operand:
544 // {7-6} - shift type: 00 = lsl
545 // {5-0} - imm6: #0 or #8
546 def logical_vec_hw_shift : Operand<i32> {
547 let PrintMethod = "printShifter";
548 let EncoderMethod = "getVecShifterOpValue";
549 let ParserMatchClass = LogicalVecHalfWordShifterOperand;
552 // A vector move shifter operand:
553 // {0} - imm1: #8 or #16
554 def move_vec_shift : Operand<i32> {
555 let PrintMethod = "printShifter";
556 let EncoderMethod = "getMoveVecShifterOpValue";
557 let ParserMatchClass = MoveVecShifterOperand;
560 // An ADD/SUB immediate shifter operand:
561 // {7-6} - shift type: 00 = lsl
562 // {5-0} - imm6: #0 or #12
563 def addsub_shift : Operand<i32> {
564 let ParserMatchClass = AddSubShifterOperand;
567 class addsub_shifted_imm<ValueType Ty>
568 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectArithImmed", [imm]> {
569 let PrintMethod = "printAddSubImm";
570 let EncoderMethod = "getAddSubImmOpValue";
571 let MIOperandInfo = (ops i32imm, addsub_shift);
574 def addsub_shifted_imm32 : addsub_shifted_imm<i32>;
575 def addsub_shifted_imm64 : addsub_shifted_imm<i64>;
577 class neg_addsub_shifted_imm<ValueType Ty>
578 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
579 let PrintMethod = "printAddSubImm";
580 let EncoderMethod = "getAddSubImmOpValue";
581 let MIOperandInfo = (ops i32imm, addsub_shift);
584 def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm<i32>;
585 def neg_addsub_shifted_imm64 : neg_addsub_shifted_imm<i64>;
587 // An extend operand:
588 // {5-3} - extend type
590 def arith_extend : Operand<i32> {
591 let PrintMethod = "printExtend";
592 let ParserMatchClass = ExtendOperand;
594 def arith_extend64 : Operand<i32> {
595 let PrintMethod = "printExtend";
596 let ParserMatchClass = ExtendOperand64;
599 // 'extend' that's a lsl of a 64-bit register.
600 def arith_extendlsl64 : Operand<i32> {
601 let PrintMethod = "printExtend";
602 let ParserMatchClass = ExtendOperandLSL64;
605 class arith_extended_reg32<ValueType Ty> : Operand<Ty>,
606 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
607 let PrintMethod = "printExtendedRegister";
608 let MIOperandInfo = (ops GPR32, arith_extend);
611 class arith_extended_reg32to64<ValueType Ty> : Operand<Ty>,
612 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
613 let PrintMethod = "printExtendedRegister";
614 let MIOperandInfo = (ops GPR32, arith_extend64);
617 // Floating-point immediate.
618 def fpimm32 : Operand<f32>,
619 PatLeaf<(f32 fpimm), [{
620 return ARM64_AM::getFP32Imm(N->getValueAPF()) != -1;
621 }], SDNodeXForm<fpimm, [{
622 APFloat InVal = N->getValueAPF();
623 uint32_t enc = ARM64_AM::getFP32Imm(InVal);
624 return CurDAG->getTargetConstant(enc, MVT::i32);
626 let ParserMatchClass = FPImmOperand;
627 let PrintMethod = "printFPImmOperand";
629 def fpimm64 : Operand<f64>,
630 PatLeaf<(f64 fpimm), [{
631 return ARM64_AM::getFP64Imm(N->getValueAPF()) != -1;
632 }], SDNodeXForm<fpimm, [{
633 APFloat InVal = N->getValueAPF();
634 uint32_t enc = ARM64_AM::getFP64Imm(InVal);
635 return CurDAG->getTargetConstant(enc, MVT::i32);
637 let ParserMatchClass = FPImmOperand;
638 let PrintMethod = "printFPImmOperand";
641 def fpimm8 : Operand<i32> {
642 let ParserMatchClass = FPImmOperand;
643 let PrintMethod = "printFPImmOperand";
646 def fpimm0 : PatLeaf<(fpimm), [{
647 return N->isExactlyValue(+0.0);
650 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
651 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
652 // are encoded as the eight bit value 'abcdefgh'.
653 def simdimmtype10 : Operand<i32>,
654 PatLeaf<(f64 fpimm), [{
655 return ARM64_AM::isAdvSIMDModImmType10(N->getValueAPF()
658 }], SDNodeXForm<fpimm, [{
659 APFloat InVal = N->getValueAPF();
660 uint32_t enc = ARM64_AM::encodeAdvSIMDModImmType10(N->getValueAPF()
663 return CurDAG->getTargetConstant(enc, MVT::i32);
665 let ParserMatchClass = SIMDImmType10Operand;
666 let PrintMethod = "printSIMDType10Operand";
674 // Base encoding for system instruction operands.
675 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
676 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands>
677 : I<oops, iops, asm, operands, "", []> {
678 let Inst{31-22} = 0b1101010100;
682 // System instructions which do not have an Rt register.
683 class SimpleSystemI<bit L, dag iops, string asm, string operands>
684 : BaseSystemI<L, (outs), iops, asm, operands> {
685 let Inst{4-0} = 0b11111;
688 // System instructions which have an Rt register.
689 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
690 : BaseSystemI<L, oops, iops, asm, operands>,
696 // Hint instructions that take both a CRm and a 3-bit immediate.
697 class HintI<string mnemonic>
698 : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "">,
701 let Inst{20-12} = 0b000110010;
702 let Inst{11-5} = imm;
705 // System instructions taking a single literal operand which encodes into
706 // CRm. op2 differentiates the opcodes.
707 def BarrierAsmOperand : AsmOperandClass {
708 let Name = "Barrier";
709 let ParserMethod = "tryParseBarrierOperand";
711 def barrier_op : Operand<i32> {
712 let PrintMethod = "printBarrierOption";
713 let ParserMatchClass = BarrierAsmOperand;
715 class CRmSystemI<Operand crmtype, bits<3> opc, string asm>
716 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm">,
717 Sched<[WriteBarrier]> {
719 let Inst{20-12} = 0b000110011;
720 let Inst{11-8} = CRm;
724 // MRS/MSR system instructions.
725 def SystemRegisterOperand : AsmOperandClass {
726 let Name = "SystemRegister";
727 let ParserMethod = "tryParseSystemRegister";
729 // concatenation of 1, op0, op1, CRn, CRm, op2. 16-bit immediate.
730 def sysreg_op : Operand<i32> {
731 let ParserMatchClass = SystemRegisterOperand;
732 let DecoderMethod = "DecodeSystemRegister";
733 let PrintMethod = "printSystemRegister";
736 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins sysreg_op:$systemreg),
737 "mrs", "\t$Rt, $systemreg"> {
740 let Inst{19-5} = systemreg;
743 // FIXME: Some of these def CPSR, others don't. Best way to model that?
744 // Explicitly modeling each of the system register as a register class
745 // would do it, but feels like overkill at this point.
746 class MSRI : RtSystemI<0, (outs), (ins sysreg_op:$systemreg, GPR64:$Rt),
747 "msr", "\t$systemreg, $Rt"> {
750 let Inst{19-5} = systemreg;
753 def SystemCPSRFieldOperand : AsmOperandClass {
754 let Name = "SystemCPSRField";
755 let ParserMethod = "tryParseCPSRField";
757 def cpsrfield_op : Operand<i32> {
758 let ParserMatchClass = SystemCPSRFieldOperand;
759 let PrintMethod = "printSystemCPSRField";
763 class MSRcpsrI : SimpleSystemI<0, (ins cpsrfield_op:$cpsr_field, imm0_15:$imm),
764 "msr", "\t$cpsr_field, $imm">,
768 let Inst{20-19} = 0b00;
769 let Inst{18-16} = cpsrfield{5-3};
770 let Inst{15-12} = 0b0100;
771 let Inst{11-8} = imm;
772 let Inst{7-5} = cpsrfield{2-0};
774 let DecoderMethod = "DecodeSystemCPSRInstruction";
777 // SYS and SYSL generic system instructions.
778 def SysCRAsmOperand : AsmOperandClass {
780 let ParserMethod = "tryParseSysCROperand";
783 def sys_cr_op : Operand<i32> {
784 let PrintMethod = "printSysCROperand";
785 let ParserMatchClass = SysCRAsmOperand;
788 class SystemI<bit L, string asm>
790 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
791 asm, "\t$op1, $Cn, $Cm, $op2">,
797 let Inst{20-19} = 0b01;
798 let Inst{18-16} = op1;
799 let Inst{15-12} = Cn;
804 class SystemXtI<bit L, string asm>
805 : RtSystemI<L, (outs),
806 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
807 asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> {
812 let Inst{20-19} = 0b01;
813 let Inst{18-16} = op1;
814 let Inst{15-12} = Cn;
819 class SystemLXtI<bit L, string asm>
820 : RtSystemI<L, (outs),
821 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
822 asm, "\t$Rt, $op1, $Cn, $Cm, $op2"> {
827 let Inst{20-19} = 0b01;
828 let Inst{18-16} = op1;
829 let Inst{15-12} = Cn;
835 // Branch (register) instructions:
843 // otherwise UNDEFINED
844 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
845 string operands, list<dag> pattern>
846 : I<oops, iops, asm, operands, "", pattern>, Sched<[WriteBrReg]> {
847 let Inst{31-25} = 0b1101011;
848 let Inst{24-21} = opc;
849 let Inst{20-16} = 0b11111;
850 let Inst{15-10} = 0b000000;
851 let Inst{4-0} = 0b00000;
854 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
855 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
860 let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in
861 class SpecialReturn<bits<4> opc, string asm>
862 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
863 let Inst{9-5} = 0b11111;
867 // Conditional branch instruction.
869 // Branch condition code.
870 // 4-bit immediate. Pretty-printed as .<cc>
871 def dotCcode : Operand<i32> {
872 let PrintMethod = "printDotCondCode";
875 // Conditional branch target. 19-bit immediate. The low two bits of the target
876 // offset are implied zero and so are not part of the immediate.
877 def BranchTarget19Operand : AsmOperandClass {
878 let Name = "BranchTarget19";
880 def am_brcond : Operand<OtherVT> {
881 let EncoderMethod = "getCondBranchTargetOpValue";
882 let DecoderMethod = "DecodeCondBranchTarget";
883 let PrintMethod = "printAlignedBranchTarget";
884 let ParserMatchClass = BranchTarget19Operand;
887 class BranchCond : I<(outs), (ins dotCcode:$cond, am_brcond:$target),
888 "b", "$cond\t$target", "",
889 [(ARM64brcond bb:$target, imm:$cond, CPSR)]>,
892 let isTerminator = 1;
897 let Inst{31-24} = 0b01010100;
898 let Inst{23-5} = target;
900 let Inst{3-0} = cond;
904 // Compare-and-branch instructions.
906 class BaseCmpBranch<RegisterClass regtype, bit op, string asm, SDNode node>
907 : I<(outs), (ins regtype:$Rt, am_brcond:$target),
908 asm, "\t$Rt, $target", "",
909 [(node regtype:$Rt, bb:$target)]>,
912 let isTerminator = 1;
916 let Inst{30-25} = 0b011010;
918 let Inst{23-5} = target;
922 multiclass CmpBranch<bit op, string asm, SDNode node> {
923 def W : BaseCmpBranch<GPR32, op, asm, node> {
926 def X : BaseCmpBranch<GPR64, op, asm, node> {
932 // Test-bit-and-branch instructions.
934 // Test-and-branch target. 14-bit sign-extended immediate. The low two bits of
935 // the target offset are implied zero and so are not part of the immediate.
936 def BranchTarget14Operand : AsmOperandClass {
937 let Name = "BranchTarget14";
939 def am_tbrcond : Operand<OtherVT> {
940 let EncoderMethod = "getTestBranchTargetOpValue";
941 let PrintMethod = "printAlignedBranchTarget";
942 let ParserMatchClass = BranchTarget14Operand;
945 class TestBranch<bit op, string asm, SDNode node>
946 : I<(outs), (ins GPR64:$Rt, imm0_63:$bit_off, am_tbrcond:$target),
947 asm, "\t$Rt, $bit_off, $target", "",
948 [(node GPR64:$Rt, imm0_63:$bit_off, bb:$target)]>,
951 let isTerminator = 1;
957 let Inst{31} = bit_off{5};
958 let Inst{30-25} = 0b011011;
960 let Inst{23-19} = bit_off{4-0};
961 let Inst{18-5} = target;
964 let DecoderMethod = "DecodeTestAndBranch";
968 // Unconditional branch (immediate) instructions.
970 def BranchTarget26Operand : AsmOperandClass {
971 let Name = "BranchTarget26";
973 def am_b_target : Operand<OtherVT> {
974 let EncoderMethod = "getBranchTargetOpValue";
975 let PrintMethod = "printAlignedBranchTarget";
976 let ParserMatchClass = BranchTarget26Operand;
978 def am_bl_target : Operand<i64> {
979 let EncoderMethod = "getBranchTargetOpValue";
980 let PrintMethod = "printAlignedBranchTarget";
981 let ParserMatchClass = BranchTarget26Operand;
984 class BImm<bit op, dag iops, string asm, list<dag> pattern>
985 : I<(outs), iops, asm, "\t$addr", "", pattern>, Sched<[WriteBr]> {
988 let Inst{30-26} = 0b00101;
989 let Inst{25-0} = addr;
991 let DecoderMethod = "DecodeUnconditionalBranch";
994 class BranchImm<bit op, string asm, list<dag> pattern>
995 : BImm<op, (ins am_b_target:$addr), asm, pattern>;
996 class CallImm<bit op, string asm, list<dag> pattern>
997 : BImm<op, (ins am_bl_target:$addr), asm, pattern>;
1000 // Basic one-operand data processing instructions.
1003 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1004 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
1005 SDPatternOperator node>
1006 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1007 [(set regtype:$Rd, (node regtype:$Rn))]>,
1012 let Inst{30-13} = 0b101101011000000000;
1013 let Inst{12-10} = opc;
1018 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1019 multiclass OneOperandData<bits<3> opc, string asm,
1020 SDPatternOperator node = null_frag> {
1021 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1025 def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
1030 class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
1031 : BaseOneOperandData<opc, GPR32, asm, node> {
1035 class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
1036 : BaseOneOperandData<opc, GPR64, asm, node> {
1041 // Basic two-operand data processing instructions.
1043 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1045 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1046 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1052 let Inst{30} = isSub;
1053 let Inst{28-21} = 0b11010000;
1054 let Inst{20-16} = Rm;
1055 let Inst{15-10} = 0;
1060 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1062 : BaseBaseAddSubCarry<isSub, regtype, asm,
1063 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, CPSR))]>;
1065 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
1067 : BaseBaseAddSubCarry<isSub, regtype, asm,
1068 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, CPSR)),
1073 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
1074 SDNode OpNode, SDNode OpNode_setflags> {
1075 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1079 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1085 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
1090 def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
1097 class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
1098 SDPatternOperator OpNode>
1099 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1100 asm, "\t$Rd, $Rn, $Rm", "",
1101 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1105 let Inst{30-21} = 0b0011010110;
1106 let Inst{20-16} = Rm;
1107 let Inst{15-14} = 0b00;
1108 let Inst{13-10} = opc;
1113 class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
1114 SDPatternOperator OpNode>
1115 : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
1116 let Inst{10} = isSigned;
1119 multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
1120 def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
1121 Sched<[WriteID32]> {
1124 def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
1125 Sched<[WriteID64]> {
1130 class BaseShift<bits<2> shift_type, RegisterClass regtype,
1131 string asm, SDNode OpNode>
1132 : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
1134 let Inst{11-10} = shift_type;
1137 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1138 def Wr : BaseShift<shift_type, GPR32, asm, OpNode> {
1142 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
1147 class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
1148 : InstAlias<asm#" $dst, $src1, $src2",
1149 (inst regtype:$dst, regtype:$src1, regtype:$src2)>;
1151 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
1152 RegisterClass addtype, string asm,
1154 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
1155 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
1160 let Inst{30-24} = 0b0011011;
1161 let Inst{23-21} = opc;
1162 let Inst{20-16} = Rm;
1163 let Inst{15} = isSub;
1164 let Inst{14-10} = Ra;
1169 multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
1170 def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
1171 [(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))]>,
1172 Sched<[WriteIM32]> {
1176 def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
1177 [(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))]>,
1178 Sched<[WriteIM64]> {
1183 class WideMulAccum<bit isSub, bits<3> opc, string asm,
1184 SDNode AccNode, SDNode ExtNode>
1185 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1186 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1187 (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
1188 Sched<[WriteIM32]> {
1192 class MulHi<bits<3> opc, string asm, SDNode OpNode>
1193 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1194 asm, "\t$Rd, $Rn, $Rm", "",
1195 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1196 Sched<[WriteIM64]> {
1200 let Inst{31-24} = 0b10011011;
1201 let Inst{23-21} = opc;
1202 let Inst{20-16} = Rm;
1203 let Inst{15-10} = 0b011111;
1208 class MulAccumWAlias<string asm, Instruction inst>
1209 : InstAlias<asm#" $dst, $src1, $src2",
1210 (inst GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR)>;
1211 class MulAccumXAlias<string asm, Instruction inst>
1212 : InstAlias<asm#" $dst, $src1, $src2",
1213 (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
1214 class WideMulAccumAlias<string asm, Instruction inst>
1215 : InstAlias<asm#" $dst, $src1, $src2",
1216 (inst GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR)>;
1218 class BaseCRC32<bit sf, bits<2> sz, bit C, RegisterClass StreamReg,
1219 SDPatternOperator OpNode, string asm>
1220 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1221 asm, "\t$Rd, $Rn, $Rm", "",
1222 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1223 Sched<[WriteISReg]> {
1229 let Inst{30-21} = 0b0011010110;
1230 let Inst{20-16} = Rm;
1231 let Inst{15-13} = 0b010;
1233 let Inst{11-10} = sz;
1239 // Address generation.
1242 class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
1243 : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "",
1248 let Inst{31} = page;
1249 let Inst{30-29} = label{1-0};
1250 let Inst{28-24} = 0b10000;
1251 let Inst{23-5} = label{20-2};
1254 let DecoderMethod = "DecodeAdrInstruction";
1261 def movimm32_imm : Operand<i32> {
1262 let ParserMatchClass = Imm0_65535Operand;
1263 let EncoderMethod = "getMoveWideImmOpValue";
1265 def movimm32_shift : Operand<i32> {
1266 let PrintMethod = "printShifter";
1267 let ParserMatchClass = MovImm32ShifterOperand;
1269 def movimm64_shift : Operand<i32> {
1270 let PrintMethod = "printShifter";
1271 let ParserMatchClass = MovImm64ShifterOperand;
1273 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1274 class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1276 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1277 asm, "\t$Rd, $imm$shift", "", []>,
1282 let Inst{30-29} = opc;
1283 let Inst{28-23} = 0b100101;
1284 let Inst{22-21} = shift{5-4};
1285 let Inst{20-5} = imm;
1288 let DecoderMethod = "DecodeMoveImmInstruction";
1291 multiclass MoveImmediate<bits<2> opc, string asm> {
1292 def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
1296 def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
1301 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1302 class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1304 : I<(outs regtype:$Rd),
1305 (ins regtype:$src, movimm32_imm:$imm, shifter:$shift),
1306 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
1311 let Inst{30-29} = opc;
1312 let Inst{28-23} = 0b100101;
1313 let Inst{22-21} = shift{5-4};
1314 let Inst{20-5} = imm;
1317 let DecoderMethod = "DecodeMoveImmInstruction";
1320 multiclass InsertImmediate<bits<2> opc, string asm> {
1321 def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
1325 def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
1334 class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
1335 RegisterClass srcRegtype, addsub_shifted_imm immtype,
1336 string asm, SDPatternOperator OpNode>
1337 : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
1338 asm, "\t$Rd, $Rn, $imm", "",
1339 [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
1344 let Inst{30} = isSub;
1345 let Inst{29} = setFlags;
1346 let Inst{28-24} = 0b10001;
1347 let Inst{23-22} = imm{13-12}; // '00' => lsl #0, '01' => lsl #12
1348 let Inst{21-10} = imm{11-0};
1351 let DecoderMethod = "DecodeBaseAddSubImm";
1354 class BaseAddSubRegPseudo<RegisterClass regtype,
1355 SDPatternOperator OpNode>
1356 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1357 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1360 class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
1361 arith_shifted_reg shifted_regtype, string asm,
1362 SDPatternOperator OpNode>
1363 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1364 asm, "\t$Rd, $Rn, $Rm", "",
1365 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
1366 Sched<[WriteISReg]> {
1367 // The operands are in order to match the 'addr' MI operands, so we
1368 // don't need an encoder method and by-name matching. Just use the default
1369 // in-order handling. Since we're using by-order, make sure the names
1375 let Inst{30} = isSub;
1376 let Inst{29} = setFlags;
1377 let Inst{28-24} = 0b01011;
1378 let Inst{23-22} = shift{7-6};
1380 let Inst{20-16} = src2;
1381 let Inst{15-10} = shift{5-0};
1382 let Inst{9-5} = src1;
1383 let Inst{4-0} = dst;
1385 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1388 class BaseAddSubEReg<bit isSub, bit setFlags, RegisterClass dstRegtype,
1389 RegisterClass src1Regtype, Operand src2Regtype,
1390 string asm, SDPatternOperator OpNode>
1391 : I<(outs dstRegtype:$R1),
1392 (ins src1Regtype:$R2, src2Regtype:$R3),
1393 asm, "\t$R1, $R2, $R3", "",
1394 [(set dstRegtype:$R1, (OpNode src1Regtype:$R2, src2Regtype:$R3))]>,
1395 Sched<[WriteIEReg]> {
1400 let Inst{30} = isSub;
1401 let Inst{29} = setFlags;
1402 let Inst{28-24} = 0b01011;
1403 let Inst{23-21} = 0b001;
1404 let Inst{20-16} = Rm;
1405 let Inst{15-13} = ext{5-3};
1406 let Inst{12-10} = ext{2-0};
1410 let DecoderMethod = "DecodeAddSubERegInstruction";
1413 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1414 class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
1415 RegisterClass src1Regtype, RegisterClass src2Regtype,
1416 Operand ext_op, string asm>
1417 : I<(outs dstRegtype:$Rd),
1418 (ins src1Regtype:$Rn, src2Regtype:$Rm, ext_op:$ext),
1419 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
1420 Sched<[WriteIEReg]> {
1425 let Inst{30} = isSub;
1426 let Inst{29} = setFlags;
1427 let Inst{28-24} = 0b01011;
1428 let Inst{23-21} = 0b001;
1429 let Inst{20-16} = Rm;
1430 let Inst{15} = ext{5};
1431 let Inst{12-10} = ext{2-0};
1435 let DecoderMethod = "DecodeAddSubERegInstruction";
1438 // Aliases for register+register add/subtract.
1439 class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
1440 RegisterClass src1Regtype, RegisterClass src2Regtype,
1442 : InstAlias<asm#" $dst, $src1, $src2",
1443 (inst dstRegtype:$dst, src1Regtype:$src1, src2Regtype:$src2,
1446 multiclass AddSub<bit isSub, string mnemonic,
1447 SDPatternOperator OpNode = null_frag> {
1448 let hasSideEffects = 0 in {
1449 // Add/Subtract immediate
1450 def Wri : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
1454 def Xri : BaseAddSubImm<isSub, 0, GPR64sp, GPR64sp, addsub_shifted_imm64,
1459 // Add/Subtract register - Only used for CodeGen
1460 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1461 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1463 // Add/Subtract shifted register
1464 def Wrs : BaseAddSubSReg<isSub, 0, GPR32, arith_shifted_reg32, mnemonic,
1468 def Xrs : BaseAddSubSReg<isSub, 0, GPR64, arith_shifted_reg64, mnemonic,
1474 // Add/Subtract extended register
1475 let AddedComplexity = 1, hasSideEffects = 0 in {
1476 def Wrx : BaseAddSubEReg<isSub, 0, GPR32sp, GPR32sp,
1477 arith_extended_reg32<i32>, mnemonic, OpNode> {
1480 def Xrx : BaseAddSubEReg<isSub, 0, GPR64sp, GPR64sp,
1481 arith_extended_reg32to64<i64>, mnemonic, OpNode> {
1486 def Xrx64 : BaseAddSubEReg64<isSub, 0, GPR64sp, GPR64sp, GPR64,
1487 arith_extendlsl64, mnemonic> {
1488 // UXTX and SXTX only.
1489 let Inst{14-13} = 0b11;
1493 // Register/register aliases with no shift when SP is not used.
1494 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1495 GPR32, GPR32, GPR32, 0>;
1496 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1497 GPR64, GPR64, GPR64, 0>;
1499 // Register/register aliases with no shift when either the destination or
1500 // first source register is SP. This relies on the shifted register aliases
1501 // above matching first in the case when SP is not used.
1502 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1503 GPR32sp, GPR32sp, GPR32, 16>; // UXTW #0
1504 def : AddSubRegAlias<mnemonic,
1505 !cast<Instruction>(NAME#"Xrx64"),
1506 GPR64sp, GPR64sp, GPR64, 24>; // UXTX #0
1509 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode> {
1510 let isCompare = 1, Defs = [CPSR] in {
1511 // Add/Subtract immediate
1512 def Wri : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
1516 def Xri : BaseAddSubImm<isSub, 1, GPR64, GPR64sp, addsub_shifted_imm64,
1521 // Add/Subtract register
1522 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1523 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1525 // Add/Subtract shifted register
1526 def Wrs : BaseAddSubSReg<isSub, 1, GPR32, arith_shifted_reg32, mnemonic,
1530 def Xrs : BaseAddSubSReg<isSub, 1, GPR64, arith_shifted_reg64, mnemonic,
1535 // Add/Subtract extended register
1536 let AddedComplexity = 1 in {
1537 def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
1538 arith_extended_reg32<i32>, mnemonic, OpNode> {
1541 def Xrx : BaseAddSubEReg<isSub, 1, GPR64, GPR64sp,
1542 arith_extended_reg32<i64>, mnemonic, OpNode> {
1547 def Xrx64 : BaseAddSubEReg64<isSub, 1, GPR64, GPR64sp, GPR64,
1548 arith_extendlsl64, mnemonic> {
1549 // UXTX and SXTX only.
1550 let Inst{14-13} = 0b11;
1555 // Register/register aliases with no shift when SP is not used.
1556 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1557 GPR32, GPR32, GPR32, 0>;
1558 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1559 GPR64, GPR64, GPR64, 0>;
1561 // Register/register aliases with no shift when the first source register
1562 // is SP. This relies on the shifted register aliases above matching first
1563 // in the case when SP is not used.
1564 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1565 GPR32, GPR32sp, GPR32, 16>; // UXTW #0
1566 def : AddSubRegAlias<mnemonic,
1567 !cast<Instruction>(NAME#"Xrx64"),
1568 GPR64, GPR64sp, GPR64, 24>; // UXTX #0
1574 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
1575 SDTCisSameAs<0, 3>]>;
1576 def ARM64Extr : SDNode<"ARM64ISD::EXTR", SDTA64EXTR>;
1578 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
1580 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1581 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
1582 Sched<[WriteExtr, ReadExtrHi]> {
1588 let Inst{30-23} = 0b00100111;
1590 let Inst{20-16} = Rm;
1591 let Inst{15-10} = imm;
1596 multiclass ExtractImm<string asm> {
1597 def Wrri : BaseExtractImm<GPR32, imm0_31, asm,
1599 (ARM64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
1603 def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
1605 (ARM64Extr GPR64:$Rn, GPR64:$Rm, imm0_63:$imm))]> {
1616 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1617 class BaseBitfieldImm<bits<2> opc,
1618 RegisterClass regtype, Operand imm_type, string asm>
1619 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1620 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1627 let Inst{30-29} = opc;
1628 let Inst{28-23} = 0b100110;
1629 let Inst{21-16} = immr;
1630 let Inst{15-10} = imms;
1635 multiclass BitfieldImm<bits<2> opc, string asm> {
1636 def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
1640 def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
1646 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1647 class BaseBitfieldImmWith2RegArgs<bits<2> opc,
1648 RegisterClass regtype, Operand imm_type, string asm>
1649 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
1651 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
1658 let Inst{30-29} = opc;
1659 let Inst{28-23} = 0b100110;
1660 let Inst{21-16} = immr;
1661 let Inst{15-10} = imms;
1666 multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
1667 def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
1671 def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
1681 // Logical (immediate)
1682 class BaseLogicalImm<bits<2> opc, RegisterClass dregtype,
1683 RegisterClass sregtype, Operand imm_type, string asm,
1685 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
1686 asm, "\t$Rd, $Rn, $imm", "", pattern>,
1691 let Inst{30-29} = opc;
1692 let Inst{28-23} = 0b100100;
1693 let Inst{22} = imm{12};
1694 let Inst{21-16} = imm{11-6};
1695 let Inst{15-10} = imm{5-0};
1699 let DecoderMethod = "DecodeLogicalImmInstruction";
1702 // Logical (shifted register)
1703 class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
1704 logical_shifted_reg shifted_regtype, string asm,
1706 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1707 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1708 Sched<[WriteISReg]> {
1709 // The operands are in order to match the 'addr' MI operands, so we
1710 // don't need an encoder method and by-name matching. Just use the default
1711 // in-order handling. Since we're using by-order, make sure the names
1717 let Inst{30-29} = opc;
1718 let Inst{28-24} = 0b01010;
1719 let Inst{23-22} = shift{7-6};
1721 let Inst{20-16} = src2;
1722 let Inst{15-10} = shift{5-0};
1723 let Inst{9-5} = src1;
1724 let Inst{4-0} = dst;
1726 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1729 // Aliases for register+register logical instructions.
1730 class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
1731 : InstAlias<asm#" $dst, $src1, $src2",
1732 (inst regtype:$dst, regtype:$src1, regtype:$src2, 0)>;
1734 let AddedComplexity = 6 in
1735 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode> {
1736 def Wri : BaseLogicalImm<opc, GPR32sp, GPR32, logical_imm32, mnemonic,
1737 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
1738 logical_imm32:$imm))]> {
1740 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1742 def Xri : BaseLogicalImm<opc, GPR64sp, GPR64, logical_imm64, mnemonic,
1743 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
1744 logical_imm64:$imm))]> {
1749 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode> {
1750 let isCompare = 1, Defs = [CPSR] in {
1751 def Wri : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
1752 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
1754 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1756 def Xri : BaseLogicalImm<opc, GPR64, GPR64, logical_imm64, mnemonic,
1757 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
1760 } // end Defs = [CPSR]
1763 class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
1764 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1765 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1768 // Split from LogicalImm as not all instructions have both.
1769 multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
1770 SDPatternOperator OpNode> {
1771 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
1772 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
1774 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
1775 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
1776 logical_shifted_reg32:$Rm))]> {
1779 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
1780 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
1781 logical_shifted_reg64:$Rm))]> {
1785 def : LogicalRegAlias<mnemonic,
1786 !cast<Instruction>(NAME#"Wrs"), GPR32>;
1787 def : LogicalRegAlias<mnemonic,
1788 !cast<Instruction>(NAME#"Xrs"), GPR64>;
1791 // Split from LogicalReg to allow setting CPSR Defs
1792 multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic> {
1793 let Defs = [CPSR], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
1794 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic, []>{
1797 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic, []>{
1802 def : LogicalRegAlias<mnemonic,
1803 !cast<Instruction>(NAME#"Wrs"), GPR32>;
1804 def : LogicalRegAlias<mnemonic,
1805 !cast<Instruction>(NAME#"Xrs"), GPR64>;
1809 // Conditionally set flags
1813 // 4-bit immediate. Pretty-printed as <cc>
1814 def ccode : Operand<i32> {
1815 let PrintMethod = "printCondCode";
1818 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1819 class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
1820 : I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
1821 asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
1832 let Inst{29-21} = 0b111010010;
1833 let Inst{20-16} = imm;
1834 let Inst{15-12} = cond;
1835 let Inst{11-10} = 0b10;
1838 let Inst{3-0} = nzcv;
1841 multiclass CondSetFlagsImm<bit op, string asm> {
1842 def Wi : BaseCondSetFlagsImm<op, GPR32, asm> {
1845 def Xi : BaseCondSetFlagsImm<op, GPR64, asm> {
1850 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1851 class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
1852 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
1853 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
1864 let Inst{29-21} = 0b111010010;
1865 let Inst{20-16} = Rm;
1866 let Inst{15-12} = cond;
1867 let Inst{11-10} = 0b00;
1870 let Inst{3-0} = nzcv;
1873 multiclass CondSetFlagsReg<bit op, string asm> {
1874 def Wr : BaseCondSetFlagsReg<op, GPR32, asm> {
1877 def Xr : BaseCondSetFlagsReg<op, GPR64, asm> {
1883 // Conditional select
1886 class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
1887 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
1888 asm, "\t$Rd, $Rn, $Rm, $cond", "",
1890 (ARM64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), CPSR))]>,
1900 let Inst{29-21} = 0b011010100;
1901 let Inst{20-16} = Rm;
1902 let Inst{15-12} = cond;
1903 let Inst{11-10} = op2;
1908 multiclass CondSelect<bit op, bits<2> op2, string asm> {
1909 def Wr : BaseCondSelect<op, op2, GPR32, asm> {
1912 def Xr : BaseCondSelect<op, op2, GPR64, asm> {
1917 class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
1919 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
1920 asm, "\t$Rd, $Rn, $Rm, $cond", "",
1922 (ARM64csel regtype:$Rn, (frag regtype:$Rm),
1923 (i32 imm:$cond), CPSR))]>,
1933 let Inst{29-21} = 0b011010100;
1934 let Inst{20-16} = Rm;
1935 let Inst{15-12} = cond;
1936 let Inst{11-10} = op2;
1941 multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {
1942 def Wr : BaseCondSelectOp<op, op2, GPR32, asm, frag> {
1945 def Xr : BaseCondSelectOp<op, op2, GPR64, asm, frag> {
1951 // Special Mask Value
1953 def maski8_or_more : Operand<i32>,
1954 ImmLeaf<i32, [{ return (Imm & 0xff) == 0xff; }]> {
1956 def maski16_or_more : Operand<i32>,
1957 ImmLeaf<i32, [{ return (Imm & 0xffff) == 0xffff; }]> {
1965 // (unsigned immediate)
1966 // Indexed for 8-bit registers. offset is in range [0,4095].
1967 def MemoryIndexed8Operand : AsmOperandClass {
1968 let Name = "MemoryIndexed8";
1969 let DiagnosticType = "InvalidMemoryIndexed8";
1971 def am_indexed8 : Operand<i64>,
1972 ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []> {
1973 let PrintMethod = "printAMIndexed8";
1975 = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale1>";
1976 let ParserMatchClass = MemoryIndexed8Operand;
1977 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1980 // Indexed for 16-bit registers. offset is multiple of 2 in range [0,8190],
1981 // stored as immval/2 (the 12-bit literal that encodes directly into the insn).
1982 def MemoryIndexed16Operand : AsmOperandClass {
1983 let Name = "MemoryIndexed16";
1984 let DiagnosticType = "InvalidMemoryIndexed16";
1986 def am_indexed16 : Operand<i64>,
1987 ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []> {
1988 let PrintMethod = "printAMIndexed16";
1990 = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale2>";
1991 let ParserMatchClass = MemoryIndexed16Operand;
1992 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1995 // Indexed for 32-bit registers. offset is multiple of 4 in range [0,16380],
1996 // stored as immval/4 (the 12-bit literal that encodes directly into the insn).
1997 def MemoryIndexed32Operand : AsmOperandClass {
1998 let Name = "MemoryIndexed32";
1999 let DiagnosticType = "InvalidMemoryIndexed32";
2001 def am_indexed32 : Operand<i64>,
2002 ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []> {
2003 let PrintMethod = "printAMIndexed32";
2005 = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale4>";
2006 let ParserMatchClass = MemoryIndexed32Operand;
2007 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
2010 // Indexed for 64-bit registers. offset is multiple of 8 in range [0,32760],
2011 // stored as immval/8 (the 12-bit literal that encodes directly into the insn).
2012 def MemoryIndexed64Operand : AsmOperandClass {
2013 let Name = "MemoryIndexed64";
2014 let DiagnosticType = "InvalidMemoryIndexed64";
2016 def am_indexed64 : Operand<i64>,
2017 ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []> {
2018 let PrintMethod = "printAMIndexed64";
2020 = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale8>";
2021 let ParserMatchClass = MemoryIndexed64Operand;
2022 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
2025 // Indexed for 128-bit registers. offset is multiple of 16 in range [0,65520],
2026 // stored as immval/16 (the 12-bit literal that encodes directly into the insn).
2027 def MemoryIndexed128Operand : AsmOperandClass {
2028 let Name = "MemoryIndexed128";
2029 let DiagnosticType = "InvalidMemoryIndexed128";
2031 def am_indexed128 : Operand<i64>,
2032 ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []> {
2033 let PrintMethod = "printAMIndexed128";
2035 = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale16>";
2036 let ParserMatchClass = MemoryIndexed128Operand;
2037 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
2041 def MemoryNoIndexOperand : AsmOperandClass { let Name = "MemoryNoIndex"; }
2042 def am_noindex : Operand<i64>,
2043 ComplexPattern<i64, 1, "SelectAddrModeNoIndex", []> {
2044 let PrintMethod = "printAMNoIndex";
2045 let ParserMatchClass = MemoryNoIndexOperand;
2046 let MIOperandInfo = (ops GPR64sp:$base);
2049 class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2050 string asm, list<dag> pattern>
2051 : I<oops, iops, asm, "\t$Rt, $addr", "", pattern> {
2055 bits<5> base = addr{4-0};
2056 bits<12> offset = addr{16-5};
2058 let Inst{31-30} = sz;
2059 let Inst{29-27} = 0b111;
2061 let Inst{25-24} = 0b01;
2062 let Inst{23-22} = opc;
2063 let Inst{21-10} = offset;
2064 let Inst{9-5} = base;
2065 let Inst{4-0} = dst;
2067 let DecoderMethod = "DecodeUnsignedLdStInstruction";
2070 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2071 class LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2072 Operand indextype, string asm, list<dag> pattern>
2073 : BaseLoadStoreUI<sz, V, opc,
2074 (outs regtype:$Rt), (ins indextype:$addr), asm, pattern>,
2077 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2078 class StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2079 Operand indextype, string asm, list<dag> pattern>
2080 : BaseLoadStoreUI<sz, V, opc,
2081 (outs), (ins regtype:$Rt, indextype:$addr), asm, pattern>,
2084 def PrefetchOperand : AsmOperandClass {
2085 let Name = "Prefetch";
2086 let ParserMethod = "tryParsePrefetch";
2088 def prfop : Operand<i32> {
2089 let PrintMethod = "printPrefetchOp";
2090 let ParserMatchClass = PrefetchOperand;
2093 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2094 class PrefetchUI<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2095 : BaseLoadStoreUI<sz, V, opc,
2096 (outs), (ins prfop:$Rt, am_indexed64:$addr), asm, pat>,
2103 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2104 class LoadLiteral<bits<2> opc, bit V, RegisterClass regtype, string asm>
2105 : I<(outs regtype:$Rt), (ins am_brcond:$label),
2106 asm, "\t$Rt, $label", "", []>,
2110 let Inst{31-30} = opc;
2111 let Inst{29-27} = 0b011;
2113 let Inst{25-24} = 0b00;
2114 let Inst{23-5} = label;
2118 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2119 class PrefetchLiteral<bits<2> opc, bit V, string asm, list<dag> pat>
2120 : I<(outs), (ins prfop:$Rt, am_brcond:$label),
2121 asm, "\t$Rt, $label", "", pat>,
2125 let Inst{31-30} = opc;
2126 let Inst{29-27} = 0b011;
2128 let Inst{25-24} = 0b00;
2129 let Inst{23-5} = label;
2134 // Load/store register offset
2137 class MemROAsmOperand<int sz> : AsmOperandClass {
2138 let Name = "MemoryRegisterOffset"#sz;
2141 def MemROAsmOperand8 : MemROAsmOperand<8>;
2142 def MemROAsmOperand16 : MemROAsmOperand<16>;
2143 def MemROAsmOperand32 : MemROAsmOperand<32>;
2144 def MemROAsmOperand64 : MemROAsmOperand<64>;
2145 def MemROAsmOperand128 : MemROAsmOperand<128>;
2147 class ro_indexed<int sz> : Operand<i64> { // ComplexPattern<...>
2148 let PrintMethod = "printMemoryRegOffset"#sz;
2149 let MIOperandInfo = (ops GPR64sp:$base, GPR64:$offset, i32imm:$extend);
2152 def ro_indexed8 : ro_indexed<8>, ComplexPattern<i64, 3, "SelectAddrModeRO8", []> {
2153 let ParserMatchClass = MemROAsmOperand8;
2156 def ro_indexed16 : ro_indexed<16>, ComplexPattern<i64, 3, "SelectAddrModeRO16", []> {
2157 let ParserMatchClass = MemROAsmOperand16;
2160 def ro_indexed32 : ro_indexed<32>, ComplexPattern<i64, 3, "SelectAddrModeRO32", []> {
2161 let ParserMatchClass = MemROAsmOperand32;
2164 def ro_indexed64 : ro_indexed<64>, ComplexPattern<i64, 3, "SelectAddrModeRO64", []> {
2165 let ParserMatchClass = MemROAsmOperand64;
2168 def ro_indexed128 : ro_indexed<128>, ComplexPattern<i64, 3, "SelectAddrModeRO128", []> {
2169 let ParserMatchClass = MemROAsmOperand128;
2172 class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2173 string asm, dag ins, dag outs, list<dag> pat>
2174 : I<ins, outs, asm, "\t$Rt, $addr", "", pat> {
2175 // The operands are in order to match the 'addr' MI operands, so we
2176 // don't need an encoder method and by-name matching. Just use the default
2177 // in-order handling. Since we're using by-order, make sure the names
2183 let Inst{31-30} = sz;
2184 let Inst{29-27} = 0b111;
2186 let Inst{25-24} = 0b00;
2187 let Inst{23-22} = opc;
2189 let Inst{20-16} = offset;
2190 let Inst{15-13} = extend{3-1};
2192 let Inst{12} = extend{0};
2193 let Inst{11-10} = 0b10;
2194 let Inst{9-5} = base;
2195 let Inst{4-0} = dst;
2197 let DecoderMethod = "DecodeRegOffsetLdStInstruction";
2200 class Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2201 string asm, list<dag> pat>
2202 : LoadStore8RO<sz, V, opc, regtype, asm,
2203 (outs regtype:$Rt), (ins ro_indexed8:$addr), pat>,
2204 Sched<[WriteLDIdx, ReadAdrBase]>;
2206 class Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2207 string asm, list<dag> pat>
2208 : LoadStore8RO<sz, V, opc, regtype, asm,
2209 (outs), (ins regtype:$Rt, ro_indexed8:$addr), pat>,
2210 Sched<[WriteSTIdx, ReadAdrBase]>;
2212 class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2213 string asm, dag ins, dag outs, list<dag> pat>
2214 : I<ins, outs, asm, "\t$Rt, $addr", "", pat> {
2215 // The operands are in order to match the 'addr' MI operands, so we
2216 // don't need an encoder method and by-name matching. Just use the default
2217 // in-order handling. Since we're using by-order, make sure the names
2223 let Inst{31-30} = sz;
2224 let Inst{29-27} = 0b111;
2226 let Inst{25-24} = 0b00;
2227 let Inst{23-22} = opc;
2229 let Inst{20-16} = offset;
2230 let Inst{15-13} = extend{3-1};
2232 let Inst{12} = extend{0};
2233 let Inst{11-10} = 0b10;
2234 let Inst{9-5} = base;
2235 let Inst{4-0} = dst;
2237 let DecoderMethod = "DecodeRegOffsetLdStInstruction";
2240 class Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2241 string asm, list<dag> pat>
2242 : LoadStore16RO<sz, V, opc, regtype, asm,
2243 (outs regtype:$Rt), (ins ro_indexed16:$addr), pat>,
2244 Sched<[WriteLDIdx, ReadAdrBase]>;
2246 class Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2247 string asm, list<dag> pat>
2248 : LoadStore16RO<sz, V, opc, regtype, asm,
2249 (outs), (ins regtype:$Rt, ro_indexed16:$addr), pat>,
2250 Sched<[WriteSTIdx, ReadAdrBase]>;
2252 class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2253 string asm, dag ins, dag outs, list<dag> pat>
2254 : I<ins, outs, asm, "\t$Rt, $addr", "", pat> {
2255 // The operands are in order to match the 'addr' MI operands, so we
2256 // don't need an encoder method and by-name matching. Just use the default
2257 // in-order handling. Since we're using by-order, make sure the names
2263 let Inst{31-30} = sz;
2264 let Inst{29-27} = 0b111;
2266 let Inst{25-24} = 0b00;
2267 let Inst{23-22} = opc;
2269 let Inst{20-16} = offset;
2270 let Inst{15-13} = extend{3-1};
2272 let Inst{12} = extend{0};
2273 let Inst{11-10} = 0b10;
2274 let Inst{9-5} = base;
2275 let Inst{4-0} = dst;
2277 let DecoderMethod = "DecodeRegOffsetLdStInstruction";
2280 class Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2281 string asm, list<dag> pat>
2282 : LoadStore32RO<sz, V, opc, regtype, asm,
2283 (outs regtype:$Rt), (ins ro_indexed32:$addr), pat>,
2284 Sched<[WriteLDIdx, ReadAdrBase]>;
2286 class Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2287 string asm, list<dag> pat>
2288 : LoadStore32RO<sz, V, opc, regtype, asm,
2289 (outs), (ins regtype:$Rt, ro_indexed32:$addr), pat>,
2290 Sched<[WriteSTIdx, ReadAdrBase]>;
2292 class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2293 string asm, dag ins, dag outs, list<dag> pat>
2294 : I<ins, outs, asm, "\t$Rt, $addr", "", pat> {
2295 // The operands are in order to match the 'addr' MI operands, so we
2296 // don't need an encoder method and by-name matching. Just use the default
2297 // in-order handling. Since we're using by-order, make sure the names
2303 let Inst{31-30} = sz;
2304 let Inst{29-27} = 0b111;
2306 let Inst{25-24} = 0b00;
2307 let Inst{23-22} = opc;
2309 let Inst{20-16} = offset;
2310 let Inst{15-13} = extend{3-1};
2312 let Inst{12} = extend{0};
2313 let Inst{11-10} = 0b10;
2314 let Inst{9-5} = base;
2315 let Inst{4-0} = dst;
2317 let DecoderMethod = "DecodeRegOffsetLdStInstruction";
2320 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2321 class Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2322 string asm, list<dag> pat>
2323 : LoadStore64RO<sz, V, opc, regtype, asm,
2324 (outs regtype:$Rt), (ins ro_indexed64:$addr), pat>,
2325 Sched<[WriteLDIdx, ReadAdrBase]>;
2327 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2328 class Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2329 string asm, list<dag> pat>
2330 : LoadStore64RO<sz, V, opc, regtype, asm,
2331 (outs), (ins regtype:$Rt, ro_indexed64:$addr), pat>,
2332 Sched<[WriteSTIdx, ReadAdrBase]>;
2335 class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2336 string asm, dag ins, dag outs, list<dag> pat>
2337 : I<ins, outs, asm, "\t$Rt, $addr", "", pat> {
2338 // The operands are in order to match the 'addr' MI operands, so we
2339 // don't need an encoder method and by-name matching. Just use the default
2340 // in-order handling. Since we're using by-order, make sure the names
2346 let Inst{31-30} = sz;
2347 let Inst{29-27} = 0b111;
2349 let Inst{25-24} = 0b00;
2350 let Inst{23-22} = opc;
2352 let Inst{20-16} = offset;
2353 let Inst{15-13} = extend{3-1};
2355 let Inst{12} = extend{0};
2356 let Inst{11-10} = 0b10;
2357 let Inst{9-5} = base;
2358 let Inst{4-0} = dst;
2360 let DecoderMethod = "DecodeRegOffsetLdStInstruction";
2363 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2364 class Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2365 string asm, list<dag> pat>
2366 : LoadStore128RO<sz, V, opc, regtype, asm,
2367 (outs regtype:$Rt), (ins ro_indexed128:$addr), pat>,
2368 Sched<[WriteLDIdx, ReadAdrBase]>;
2370 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2371 class Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2372 string asm, list<dag> pat>
2373 : LoadStore128RO<sz, V, opc, regtype, asm,
2374 (outs), (ins regtype:$Rt, ro_indexed128:$addr), pat>,
2375 Sched<[WriteSTIdx, ReadAdrBase]>;
2377 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2378 class PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2379 : I<(outs), (ins prfop:$Rt, ro_indexed64:$addr), asm,
2380 "\t$Rt, $addr", "", pat>,
2382 // The operands are in order to match the 'addr' MI operands, so we
2383 // don't need an encoder method and by-name matching. Just use the default
2384 // in-order handling. Since we're using by-order, make sure the names
2390 let Inst{31-30} = sz;
2391 let Inst{29-27} = 0b111;
2393 let Inst{25-24} = 0b00;
2394 let Inst{23-22} = opc;
2396 let Inst{20-16} = offset;
2397 let Inst{15-13} = extend{3-1};
2399 let Inst{12} = extend{0};
2400 let Inst{11-10} = 0b10;
2401 let Inst{9-5} = base;
2402 let Inst{4-0} = dst;
2404 let DecoderMethod = "DecodeRegOffsetLdStInstruction";
2408 // Load/store unscaled immediate
2411 def MemoryUnscaledOperand : AsmOperandClass {
2412 let Name = "MemoryUnscaled";
2413 let DiagnosticType = "InvalidMemoryIndexedSImm9";
2415 class am_unscaled_operand : Operand<i64> {
2416 let PrintMethod = "printAMUnscaled";
2417 let ParserMatchClass = MemoryUnscaledOperand;
2418 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
2420 def am_unscaled : am_unscaled_operand;
2421 def am_unscaled8 : am_unscaled_operand,
2422 ComplexPattern<i64, 2, "SelectAddrModeUnscaled8", []>;
2423 def am_unscaled16 : am_unscaled_operand,
2424 ComplexPattern<i64, 2, "SelectAddrModeUnscaled16", []>;
2425 def am_unscaled32 : am_unscaled_operand,
2426 ComplexPattern<i64, 2, "SelectAddrModeUnscaled32", []>;
2427 def am_unscaled64 : am_unscaled_operand,
2428 ComplexPattern<i64, 2, "SelectAddrModeUnscaled64", []>;
2429 def am_unscaled128 : am_unscaled_operand,
2430 ComplexPattern<i64, 2, "SelectAddrModeUnscaled128", []>;
2432 class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2433 string asm, list<dag> pattern>
2434 : I<oops, iops, asm, "\t$Rt, $addr", "", pattern> {
2435 // The operands are in order to match the 'addr' MI operands, so we
2436 // don't need an encoder method and by-name matching. Just use the default
2437 // in-order handling. Since we're using by-order, make sure the names
2442 let Inst{31-30} = sz;
2443 let Inst{29-27} = 0b111;
2445 let Inst{25-24} = 0b00;
2446 let Inst{23-22} = opc;
2448 let Inst{20-12} = offset;
2449 let Inst{11-10} = 0b00;
2450 let Inst{9-5} = base;
2451 let Inst{4-0} = dst;
2453 let DecoderMethod = "DecodeSignedLdStInstruction";
2456 let AddedComplexity = 1 in // try this before LoadUI
2457 class LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2458 Operand amtype, string asm, list<dag> pattern>
2459 : BaseLoadStoreUnscale<sz, V, opc, (outs regtype:$Rt),
2460 (ins amtype:$addr), asm, pattern>,
2463 let AddedComplexity = 1 in // try this before StoreUI
2464 class StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2465 Operand amtype, string asm, list<dag> pattern>
2466 : BaseLoadStoreUnscale<sz, V, opc, (outs),
2467 (ins regtype:$Rt, amtype:$addr), asm, pattern>,
2470 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2471 class PrefetchUnscaled<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2472 : BaseLoadStoreUnscale<sz, V, opc, (outs),
2473 (ins prfop:$Rt, am_unscaled:$addr), asm, pat>,
2477 // Load/store unscaled immediate, unprivileged
2480 class BaseLoadStoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2481 dag oops, dag iops, string asm>
2482 : I<oops, iops, asm, "\t$Rt, $addr", "", []> {
2483 // The operands are in order to match the 'addr' MI operands, so we
2484 // don't need an encoder method and by-name matching. Just use the default
2485 // in-order handling. Since we're using by-order, make sure the names
2490 let Inst{31-30} = sz;
2491 let Inst{29-27} = 0b111;
2493 let Inst{25-24} = 0b00;
2494 let Inst{23-22} = opc;
2496 let Inst{20-12} = offset;
2497 let Inst{11-10} = 0b10;
2498 let Inst{9-5} = base;
2499 let Inst{4-0} = dst;
2501 let DecoderMethod = "DecodeSignedLdStInstruction";
2504 let mayStore = 0, mayLoad = 1, hasSideEffects = 0 in {
2505 class LoadUnprivileged<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2507 : BaseLoadStoreUnprivileged<sz, V, opc,
2508 (outs regtype:$Rt), (ins am_unscaled:$addr), asm>,
2512 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
2513 class StoreUnprivileged<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2515 : BaseLoadStoreUnprivileged<sz, V, opc,
2516 (outs), (ins regtype:$Rt, am_unscaled:$addr), asm>,
2521 // Load/store pre-indexed
2524 class BaseLoadStorePreIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2525 string asm, string cstr>
2526 : I<oops, iops, asm, "\t$Rt, $addr!", cstr, []> {
2527 // The operands are in order to match the 'addr' MI operands, so we
2528 // don't need an encoder method and by-name matching. Just use the default
2529 // in-order handling.
2533 let Inst{31-30} = sz;
2534 let Inst{29-27} = 0b111;
2536 let Inst{25-24} = 0;
2537 let Inst{23-22} = opc;
2539 let Inst{20-12} = offset;
2540 let Inst{11-10} = 0b11;
2541 let Inst{9-5} = base;
2542 let Inst{4-0} = dst;
2544 let DecoderMethod = "DecodeSignedLdStInstruction";
2547 let hasSideEffects = 0 in {
2548 let mayStore = 0, mayLoad = 1 in
2549 // FIXME: Modeling the write-back of these instructions for isel is tricky.
2550 // we need the complex addressing mode for the memory reference, but
2551 // we also need the write-back specified as a tied operand to the
2552 // base register. That combination does not play nicely with
2553 // the asm matcher and friends.
2554 class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2556 : BaseLoadStorePreIdx<sz, V, opc,
2557 (outs regtype:$Rt/*, GPR64sp:$wback*/),
2558 (ins am_unscaled:$addr), asm, ""/*"$addr.base = $wback"*/>,
2559 Sched<[WriteLD, WriteAdr]>;
2561 let mayStore = 1, mayLoad = 0 in
2562 class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2564 : BaseLoadStorePreIdx<sz, V, opc,
2565 (outs/* GPR64sp:$wback*/),
2566 (ins regtype:$Rt, am_unscaled:$addr),
2567 asm, ""/*"$addr.base = $wback"*/>,
2568 Sched<[WriteAdr, WriteST]>;
2569 } // hasSideEffects = 0
2571 // ISel pseudo-instructions which have the tied operands. When the MC lowering
2572 // logic finally gets smart enough to strip off tied operands that are just
2573 // for isel convenience, we can get rid of these pseudos and just reference
2574 // the real instructions directly.
2576 // Ironically, also because of the writeback operands, we can't put the
2577 // matcher pattern directly on the instruction, but need to define it
2580 // Loads aren't matched with patterns here at all, but rather in C++
2582 let mayStore = 0, mayLoad = 1, hasSideEffects = 0 in {
2583 class LoadPreIdxPseudo<RegisterClass regtype>
2584 : Pseudo<(outs regtype:$Rt, GPR64sp:$wback),
2585 (ins am_noindex:$addr, simm9:$offset), [],
2586 "$addr.base = $wback,@earlyclobber $wback">,
2587 Sched<[WriteLD, WriteAdr]>;
2588 class LoadPostIdxPseudo<RegisterClass regtype>
2589 : Pseudo<(outs regtype:$Rt, GPR64sp:$wback),
2590 (ins am_noindex:$addr, simm9:$offset), [],
2591 "$addr.base = $wback,@earlyclobber $wback">,
2592 Sched<[WriteLD, WriteI]>;
2594 multiclass StorePreIdxPseudo<RegisterClass regtype, ValueType Ty,
2595 SDPatternOperator OpNode> {
2596 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
2597 def _isel: Pseudo<(outs GPR64sp:$wback),
2598 (ins regtype:$Rt, am_noindex:$addr, simm9:$offset), [],
2599 "$addr.base = $wback,@earlyclobber $wback">,
2600 Sched<[WriteAdr, WriteST]>;
2602 def : Pat<(OpNode (Ty regtype:$Rt), am_noindex:$addr, simm9:$offset),
2603 (!cast<Instruction>(NAME#_isel) regtype:$Rt, am_noindex:$addr,
2608 // Load/store post-indexed
2611 // (pre-index) load/stores.
2612 class BaseLoadStorePostIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2613 string asm, string cstr>
2614 : I<oops, iops, asm, "\t$Rt, $addr, $idx", cstr, []> {
2615 // The operands are in order to match the 'addr' MI operands, so we
2616 // don't need an encoder method and by-name matching. Just use the default
2617 // in-order handling.
2621 let Inst{31-30} = sz;
2622 let Inst{29-27} = 0b111;
2624 let Inst{25-24} = 0b00;
2625 let Inst{23-22} = opc;
2627 let Inst{20-12} = offset;
2628 let Inst{11-10} = 0b01;
2629 let Inst{9-5} = base;
2630 let Inst{4-0} = dst;
2632 let DecoderMethod = "DecodeSignedLdStInstruction";
2635 let hasSideEffects = 0 in {
2636 let mayStore = 0, mayLoad = 1 in
2637 // FIXME: Modeling the write-back of these instructions for isel is tricky.
2638 // we need the complex addressing mode for the memory reference, but
2639 // we also need the write-back specified as a tied operand to the
2640 // base register. That combination does not play nicely with
2641 // the asm matcher and friends.
2642 class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2644 : BaseLoadStorePostIdx<sz, V, opc,
2645 (outs regtype:$Rt/*, GPR64sp:$wback*/),
2646 (ins am_noindex:$addr, simm9:$idx),
2647 asm, ""/*"$addr.base = $wback"*/>,
2648 Sched<[WriteLD, WriteI]>;
2650 let mayStore = 1, mayLoad = 0 in
2651 class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2653 : BaseLoadStorePostIdx<sz, V, opc,
2654 (outs/* GPR64sp:$wback*/),
2655 (ins regtype:$Rt, am_noindex:$addr, simm9:$idx),
2656 asm, ""/*"$addr.base = $wback"*/>,
2657 Sched<[WriteAdr, WriteST, ReadAdrBase]>;
2658 } // hasSideEffects = 0
2660 // ISel pseudo-instructions which have the tied operands. When the MC lowering
2661 // logic finally gets smart enough to strip off tied operands that are just
2662 // for isel convenience, we can get rid of these pseudos and just reference
2663 // the real instructions directly.
2665 // Ironically, also because of the writeback operands, we can't put the
2666 // matcher pattern directly on the instruction, but need to define it
2668 multiclass StorePostIdxPseudo<RegisterClass regtype, ValueType Ty,
2669 SDPatternOperator OpNode, Instruction Insn> {
2670 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
2671 def _isel: Pseudo<(outs GPR64sp:$wback),
2672 (ins regtype:$Rt, am_noindex:$addr, simm9:$idx), [],
2673 "$addr.base = $wback,@earlyclobber $wback">,
2674 PseudoInstExpansion<(Insn regtype:$Rt, am_noindex:$addr, simm9:$idx)>,
2675 Sched<[WriteAdr, WriteST, ReadAdrBase]>;
2677 def : Pat<(OpNode (Ty regtype:$Rt), am_noindex:$addr, simm9:$idx),
2678 (!cast<Instruction>(NAME#_isel) regtype:$Rt, am_noindex:$addr,
2686 // (indexed, offset)
2688 class BaseLoadStorePairOffset<bits<2> opc, bit V, bit L, dag oops, dag iops,
2690 : I<oops, iops, asm, "\t$Rt, $Rt2, $addr", "", []> {
2691 // The operands are in order to match the 'addr' MI operands, so we
2692 // don't need an encoder method and by-name matching. Just use the default
2693 // in-order handling. Since we're using by-order, make sure the names
2699 let Inst{31-30} = opc;
2700 let Inst{29-27} = 0b101;
2702 let Inst{25-23} = 0b010;
2704 let Inst{21-15} = offset;
2705 let Inst{14-10} = dst2;
2706 let Inst{9-5} = base;
2707 let Inst{4-0} = dst;
2709 let DecoderMethod = "DecodePairLdStInstruction";
2712 let hasSideEffects = 0 in {
2713 let mayStore = 0, mayLoad = 1 in
2714 class LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype,
2715 Operand indextype, string asm>
2716 : BaseLoadStorePairOffset<opc, V, 1,
2717 (outs regtype:$Rt, regtype:$Rt2),
2718 (ins indextype:$addr), asm>,
2719 Sched<[WriteLD, WriteLDHi]>;
2721 let mayLoad = 0, mayStore = 1 in
2722 class StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
2723 Operand indextype, string asm>
2724 : BaseLoadStorePairOffset<opc, V, 0, (outs),
2725 (ins regtype:$Rt, regtype:$Rt2, indextype:$addr),
2728 } // hasSideEffects = 0
2732 def MemoryIndexed32SImm7 : AsmOperandClass {
2733 let Name = "MemoryIndexed32SImm7";
2734 let DiagnosticType = "InvalidMemoryIndexed32SImm7";
2736 def am_indexed32simm7 : Operand<i32> { // ComplexPattern<...>
2737 let PrintMethod = "printAMIndexed32";
2738 let ParserMatchClass = MemoryIndexed32SImm7;
2739 let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
2742 def MemoryIndexed64SImm7 : AsmOperandClass {
2743 let Name = "MemoryIndexed64SImm7";
2744 let DiagnosticType = "InvalidMemoryIndexed64SImm7";
2746 def am_indexed64simm7 : Operand<i32> { // ComplexPattern<...>
2747 let PrintMethod = "printAMIndexed64";
2748 let ParserMatchClass = MemoryIndexed64SImm7;
2749 let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
2752 def MemoryIndexed128SImm7 : AsmOperandClass {
2753 let Name = "MemoryIndexed128SImm7";
2754 let DiagnosticType = "InvalidMemoryIndexed128SImm7";
2756 def am_indexed128simm7 : Operand<i32> { // ComplexPattern<...>
2757 let PrintMethod = "printAMIndexed128";
2758 let ParserMatchClass = MemoryIndexed128SImm7;
2759 let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
2762 class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
2764 : I<oops, iops, asm, "\t$Rt, $Rt2, $addr!", "", []> {
2765 // The operands are in order to match the 'addr' MI operands, so we
2766 // don't need an encoder method and by-name matching. Just use the default
2767 // in-order handling. Since we're using by-order, make sure the names
2773 let Inst{31-30} = opc;
2774 let Inst{29-27} = 0b101;
2776 let Inst{25-23} = 0b011;
2778 let Inst{21-15} = offset;
2779 let Inst{14-10} = dst2;
2780 let Inst{9-5} = base;
2781 let Inst{4-0} = dst;
2783 let DecoderMethod = "DecodePairLdStInstruction";
2786 let hasSideEffects = 0 in {
2787 let mayStore = 0, mayLoad = 1 in
2788 class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
2789 Operand addrmode, string asm>
2790 : BaseLoadStorePairPreIdx<opc, V, 1,
2791 (outs regtype:$Rt, regtype:$Rt2),
2792 (ins addrmode:$addr), asm>,
2793 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
2795 let mayStore = 1, mayLoad = 0 in
2796 class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
2797 Operand addrmode, string asm>
2798 : BaseLoadStorePairPreIdx<opc, V, 0, (outs),
2799 (ins regtype:$Rt, regtype:$Rt2, addrmode:$addr),
2801 Sched<[WriteAdr, WriteSTP]>;
2802 } // hasSideEffects = 0
2806 class BaseLoadStorePairPostIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
2808 : I<oops, iops, asm, "\t$Rt, $Rt2, $addr, $idx", "", []> {
2809 // The operands are in order to match the 'addr' MI operands, so we
2810 // don't need an encoder method and by-name matching. Just use the default
2811 // in-order handling. Since we're using by-order, make sure the names
2817 let Inst{31-30} = opc;
2818 let Inst{29-27} = 0b101;
2820 let Inst{25-23} = 0b001;
2822 let Inst{21-15} = offset;
2823 let Inst{14-10} = dst2;
2824 let Inst{9-5} = base;
2825 let Inst{4-0} = dst;
2827 let DecoderMethod = "DecodePairLdStInstruction";
2830 let hasSideEffects = 0 in {
2831 let mayStore = 0, mayLoad = 1 in
2832 class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
2833 Operand idxtype, string asm>
2834 : BaseLoadStorePairPostIdx<opc, V, 1,
2835 (outs regtype:$Rt, regtype:$Rt2),
2836 (ins am_noindex:$addr, idxtype:$idx), asm>,
2837 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
2839 let mayStore = 1, mayLoad = 0 in
2840 class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
2841 Operand idxtype, string asm>
2842 : BaseLoadStorePairPostIdx<opc, V, 0, (outs),
2843 (ins regtype:$Rt, regtype:$Rt2,
2844 am_noindex:$addr, idxtype:$idx),
2846 Sched<[WriteAdr, WriteSTP]>;
2847 } // hasSideEffects = 0
2851 class BaseLoadStorePairNoAlloc<bits<2> opc, bit V, bit L, dag oops, dag iops,
2853 : I<oops, iops, asm, "\t$Rt, $Rt2, $addr", "", []> {
2854 // The operands are in order to match the 'addr' MI operands, so we
2855 // don't need an encoder method and by-name matching. Just use the default
2856 // in-order handling. Since we're using by-order, make sure the names
2862 let Inst{31-30} = opc;
2863 let Inst{29-27} = 0b101;
2865 let Inst{25-23} = 0b000;
2867 let Inst{21-15} = offset;
2868 let Inst{14-10} = dst2;
2869 let Inst{9-5} = base;
2870 let Inst{4-0} = dst;
2872 let DecoderMethod = "DecodePairLdStInstruction";
2875 let hasSideEffects = 0 in {
2876 let mayStore = 0, mayLoad = 1 in
2877 class LoadPairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
2878 Operand indextype, string asm>
2879 : BaseLoadStorePairNoAlloc<opc, V, 1,
2880 (outs regtype:$Rt, regtype:$Rt2),
2881 (ins indextype:$addr), asm>,
2882 Sched<[WriteLD, WriteLDHi]>;
2884 let mayStore = 1, mayLoad = 0 in
2885 class StorePairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
2886 Operand indextype, string asm>
2887 : BaseLoadStorePairNoAlloc<opc, V, 0, (outs),
2888 (ins regtype:$Rt, regtype:$Rt2, indextype:$addr),
2891 } // hasSideEffects = 0
2894 // Load/store exclusive
2897 // True exclusive operations write to and/or read from the system's exclusive
2898 // monitors, which as far as a compiler is concerned can be modelled as a
2899 // random shared memory address. Hence LoadExclusive mayStore.
2900 let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
2901 class BaseLoadStoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
2902 dag oops, dag iops, string asm, string operands>
2903 : I<oops, iops, asm, operands, "", []> {
2904 let Inst{31-30} = sz;
2905 let Inst{29-24} = 0b001000;
2911 let DecoderMethod = "DecodeExclusiveLdStInstruction";
2914 // Neither Rs nor Rt2 operands.
2915 class LoadStoreExclusiveSimple<bits<2> sz, bit o2, bit L, bit o1, bit o0,
2916 dag oops, dag iops, string asm, string operands>
2917 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
2920 let Inst{20-16} = 0b11111;
2921 let Inst{14-10} = 0b11111;
2922 let Inst{9-5} = base;
2923 let Inst{4-0} = reg;
2926 // Simple load acquires don't set the exclusive monitor
2927 let mayLoad = 1, mayStore = 0 in
2928 class LoadAcquire<bits<2> sz, bit o2, bit L, bit o1, bit o0,
2929 RegisterClass regtype, string asm>
2930 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
2931 (ins am_noindex:$addr), asm, "\t$Rt, $addr">,
2934 class LoadExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
2935 RegisterClass regtype, string asm>
2936 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
2937 (ins am_noindex:$addr), asm, "\t$Rt, $addr">,
2940 class LoadExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
2941 RegisterClass regtype, string asm>
2942 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
2943 (outs regtype:$Rt, regtype:$Rt2),
2944 (ins am_noindex:$addr), asm,
2945 "\t$Rt, $Rt2, $addr">,
2946 Sched<[WriteLD, WriteLDHi]> {
2950 let Inst{20-16} = 0b11111;
2951 let Inst{14-10} = dst2;
2952 let Inst{9-5} = base;
2953 let Inst{4-0} = dst1;
2956 // Simple store release operations do not check the exclusive monitor.
2957 let mayLoad = 0, mayStore = 1 in
2958 class StoreRelease<bits<2> sz, bit o2, bit L, bit o1, bit o0,
2959 RegisterClass regtype, string asm>
2960 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs),
2961 (ins regtype:$Rt, am_noindex:$addr),
2962 asm, "\t$Rt, $addr">,
2965 let mayLoad = 1, mayStore = 1 in
2966 class StoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
2967 RegisterClass regtype, string asm>
2968 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, (outs GPR32:$Ws),
2969 (ins regtype:$Rt, am_noindex:$addr),
2970 asm, "\t$Ws, $Rt, $addr">,
2975 let Inst{20-16} = status;
2976 let Inst{14-10} = 0b11111;
2977 let Inst{9-5} = base;
2978 let Inst{4-0} = reg;
2980 let Constraints = "@earlyclobber $Ws";
2983 class StoreExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
2984 RegisterClass regtype, string asm>
2985 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
2987 (ins regtype:$Rt, regtype:$Rt2, am_noindex:$addr),
2988 asm, "\t$Ws, $Rt, $Rt2, $addr">,
2994 let Inst{20-16} = status;
2995 let Inst{14-10} = dst2;
2996 let Inst{9-5} = base;
2997 let Inst{4-0} = dst1;
2999 let Constraints = "@earlyclobber $Ws";
3003 // Exception generation
3006 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
3007 class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
3008 : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>,
3011 let Inst{31-24} = 0b11010100;
3012 let Inst{23-21} = op1;
3013 let Inst{20-5} = imm;
3014 let Inst{4-2} = 0b000;
3019 // Floating point to integer conversion
3022 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
3023 RegisterClass srcType, RegisterClass dstType,
3024 string asm, list<dag> pattern>
3025 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3026 asm, "\t$Rd, $Rn", "", pattern>,
3027 Sched<[WriteFCvt]> {
3031 let Inst{28-24} = 0b11110;
3032 let Inst{23-22} = type;
3034 let Inst{20-19} = rmode;
3035 let Inst{18-16} = opcode;
3036 let Inst{15-10} = 0;
3041 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3042 class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
3043 RegisterClass srcType, RegisterClass dstType,
3044 Operand immType, string asm>
3045 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3046 asm, "\t$Rd, $Rn, $scale", "", []>,
3047 Sched<[WriteFCvt]> {
3052 let Inst{28-24} = 0b11110;
3053 let Inst{23-22} = type;
3055 let Inst{20-19} = rmode;
3056 let Inst{18-16} = opcode;
3057 let Inst{15-10} = scale;
3062 multiclass FPToInteger<bits<2> rmode, bits<3> opcode, string asm, SDPatternOperator OpN> {
3063 // Unscaled single-precision to 32-bit
3064 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
3065 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3066 let Inst{31} = 0; // 32-bit GPR flag
3069 // Unscaled single-precision to 64-bit
3070 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
3071 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3072 let Inst{31} = 1; // 64-bit GPR flag
3075 // Unscaled double-precision to 32-bit
3076 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3077 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3078 let Inst{31} = 0; // 32-bit GPR flag
3081 // Unscaled double-precision to 64-bit
3082 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3083 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3084 let Inst{31} = 1; // 64-bit GPR flag
3087 // Scaled single-precision to 32-bit
3088 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
3089 fixedpoint32, asm> {
3090 let Inst{31} = 0; // 32-bit GPR flag
3093 // Scaled single-precision to 64-bit
3094 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
3095 fixedpoint64, asm> {
3096 let Inst{31} = 1; // 64-bit GPR flag
3099 // Scaled double-precision to 32-bit
3100 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3101 fixedpoint32, asm> {
3102 let Inst{31} = 0; // 32-bit GPR flag
3105 // Scaled double-precision to 64-bit
3106 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3107 fixedpoint64, asm> {
3108 let Inst{31} = 1; // 64-bit GPR flag
3113 // Integer to floating point conversion
3116 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
3117 class BaseIntegerToFP<bit isUnsigned,
3118 RegisterClass srcType, RegisterClass dstType,
3119 Operand immType, string asm>
3120 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3121 asm, "\t$Rd, $Rn, $scale", "", []>,
3122 Sched<[WriteFCvt]> {
3126 let Inst{30-23} = 0b00111100;
3127 let Inst{21-17} = 0b00001;
3128 let Inst{16} = isUnsigned;
3129 let Inst{15-10} = scale;
3134 class BaseIntegerToFPUnscaled<bit isUnsigned,
3135 RegisterClass srcType, RegisterClass dstType,
3136 ValueType dvt, string asm, SDNode node>
3137 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3138 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
3139 Sched<[WriteFCvt]> {
3143 let Inst{30-23} = 0b00111100;
3144 let Inst{21-17} = 0b10001;
3145 let Inst{16} = isUnsigned;
3146 let Inst{15-10} = 0b000000;
3151 multiclass IntegerToFP<bit isUnsigned, string asm, SDNode node> {
3153 def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
3154 let Inst{31} = 0; // 32-bit GPR flag
3155 let Inst{22} = 0; // 32-bit FPR flag
3158 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
3159 let Inst{31} = 0; // 32-bit GPR flag
3160 let Inst{22} = 1; // 64-bit FPR flag
3163 def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
3164 let Inst{31} = 1; // 64-bit GPR flag
3165 let Inst{22} = 0; // 32-bit FPR flag
3168 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
3169 let Inst{31} = 1; // 64-bit GPR flag
3170 let Inst{22} = 1; // 64-bit FPR flag
3174 def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint32, asm> {
3175 let Inst{31} = 0; // 32-bit GPR flag
3176 let Inst{22} = 0; // 32-bit FPR flag
3179 def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint32, asm> {
3180 let Inst{31} = 0; // 32-bit GPR flag
3181 let Inst{22} = 1; // 64-bit FPR flag
3184 def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint64, asm> {
3185 let Inst{31} = 1; // 64-bit GPR flag
3186 let Inst{22} = 0; // 32-bit FPR flag
3189 def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint64, asm> {
3190 let Inst{31} = 1; // 64-bit GPR flag
3191 let Inst{22} = 1; // 64-bit FPR flag
3196 // Unscaled integer <-> floating point conversion (i.e. FMOV)
3199 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3200 class BaseUnscaledConversion<bits<2> rmode, bits<3> opcode,
3201 RegisterClass srcType, RegisterClass dstType,
3203 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
3204 // We use COPY_TO_REGCLASS for these bitconvert operations.
3205 // copyPhysReg() expands the resultant COPY instructions after
3206 // regalloc is done. This gives greater freedom for the allocator
3207 // and related passes (coalescing, copy propagation, et. al.) to
3208 // be more effective.
3209 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
3210 Sched<[WriteFCopy]> {
3213 let Inst{30-23} = 0b00111100;
3215 let Inst{20-19} = rmode;
3216 let Inst{18-16} = opcode;
3217 let Inst{15-10} = 0b000000;
3222 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3223 class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
3224 RegisterClass srcType, RegisterOperand dstType, string asm>
3225 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd[1], $Rn", "", []>,
3226 Sched<[WriteFCopy]> {
3229 let Inst{30-23} = 0b00111101;
3231 let Inst{20-19} = rmode;
3232 let Inst{18-16} = opcode;
3233 let Inst{15-10} = 0b000000;
3238 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3239 class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode,
3240 RegisterOperand srcType, RegisterClass dstType, string asm>
3241 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn[1]", "", []>,
3242 Sched<[WriteFCopy]> {
3245 let Inst{30-23} = 0b00111101;
3247 let Inst{20-19} = rmode;
3248 let Inst{18-16} = opcode;
3249 let Inst{15-10} = 0b000000;
3256 multiclass UnscaledConversion<string asm> {
3257 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
3258 let Inst{31} = 0; // 32-bit GPR flag
3259 let Inst{22} = 0; // 32-bit FPR flag
3262 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
3263 let Inst{31} = 1; // 64-bit GPR flag
3264 let Inst{22} = 1; // 64-bit FPR flag
3267 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
3268 let Inst{31} = 0; // 32-bit GPR flag
3269 let Inst{22} = 0; // 32-bit FPR flag
3272 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
3273 let Inst{31} = 1; // 64-bit GPR flag
3274 let Inst{22} = 1; // 64-bit FPR flag
3277 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
3283 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
3289 def : InstAlias<asm#"$Vd.d[1], $Rn",
3290 (!cast<Instruction>(NAME#XDHighr) V128:$Vd, GPR64:$Rn), 0>;
3291 def : InstAlias<asm#"$Rd, $Vn.d[1]",
3292 (!cast<Instruction>(NAME#DXHighr) GPR64:$Rd, V128:$Vn), 0>;
3296 // Floating point conversion
3299 class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
3300 RegisterClass srcType, string asm, list<dag> pattern>
3301 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
3302 Sched<[WriteFCvt]> {
3305 let Inst{31-24} = 0b00011110;
3306 let Inst{23-22} = type;
3307 let Inst{21-17} = 0b10001;
3308 let Inst{16-15} = opcode;
3309 let Inst{14-10} = 0b10000;
3314 multiclass FPConversion<string asm> {
3315 // Double-precision to Half-precision
3316 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3317 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm, []>;
3319 // Double-precision to Single-precision
3320 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
3321 [(set FPR32:$Rd, (fround FPR64:$Rn))]>;
3323 // Half-precision to Double-precision
3324 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3325 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm, []>;
3327 // Half-precision to Single-precision
3328 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3329 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm, []>;
3331 // Single-precision to Double-precision
3332 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
3333 [(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
3335 // Single-precision to Half-precision
3336 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3337 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm, []>;
3341 // Single operand floating point data processing
3344 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3345 class BaseSingleOperandFPData<bits<4> opcode, RegisterClass regtype,
3346 ValueType vt, string asm, SDPatternOperator node>
3347 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
3348 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
3352 let Inst{31-23} = 0b000111100;
3353 let Inst{21-19} = 0b100;
3354 let Inst{18-15} = opcode;
3355 let Inst{14-10} = 0b10000;
3360 multiclass SingleOperandFPData<bits<4> opcode, string asm,
3361 SDPatternOperator node = null_frag> {
3362 def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
3363 let Inst{22} = 0; // 32-bit size flag
3366 def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
3367 let Inst{22} = 1; // 64-bit size flag
3372 // Two operand floating point data processing
3375 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3376 class BaseTwoOperandFPData<bits<4> opcode, RegisterClass regtype,
3377 string asm, list<dag> pat>
3378 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
3379 asm, "\t$Rd, $Rn, $Rm", "", pat>,
3384 let Inst{31-23} = 0b000111100;
3386 let Inst{20-16} = Rm;
3387 let Inst{15-12} = opcode;
3388 let Inst{11-10} = 0b10;
3393 multiclass TwoOperandFPData<bits<4> opcode, string asm,
3394 SDPatternOperator node = null_frag> {
3395 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3396 [(set (f32 FPR32:$Rd),
3397 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]> {
3398 let Inst{22} = 0; // 32-bit size flag
3401 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3402 [(set (f64 FPR64:$Rd),
3403 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]> {
3404 let Inst{22} = 1; // 64-bit size flag
3408 multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm, SDNode node> {
3409 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3410 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
3411 let Inst{22} = 0; // 32-bit size flag
3414 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3415 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
3416 let Inst{22} = 1; // 64-bit size flag
3422 // Three operand floating point data processing
3425 class BaseThreeOperandFPData<bit isNegated, bit isSub,
3426 RegisterClass regtype, string asm, list<dag> pat>
3427 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
3428 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
3429 Sched<[WriteFMul]> {
3434 let Inst{31-23} = 0b000111110;
3435 let Inst{21} = isNegated;
3436 let Inst{20-16} = Rm;
3437 let Inst{15} = isSub;
3438 let Inst{14-10} = Ra;
3443 multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
3444 SDPatternOperator node> {
3445 def Srrr : BaseThreeOperandFPData<isNegated, isSub, FPR32, asm,
3447 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm), (f32 FPR32:$Ra)))]> {
3448 let Inst{22} = 0; // 32-bit size flag
3451 def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
3453 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
3454 let Inst{22} = 1; // 64-bit size flag
3459 // Floating point data comparisons
3462 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3463 class BaseOneOperandFPComparison<bit signalAllNans,
3464 RegisterClass regtype, string asm,
3466 : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
3467 Sched<[WriteFCmp]> {
3469 let Inst{31-23} = 0b000111100;
3472 let Inst{20-16} = 0b00000;
3473 let Inst{15-10} = 0b001000;
3475 let Inst{4} = signalAllNans;
3476 let Inst{3-0} = 0b1000;
3479 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3480 class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
3481 string asm, list<dag> pat>
3482 : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
3483 Sched<[WriteFCmp]> {
3486 let Inst{31-23} = 0b000111100;
3488 let Inst{20-16} = Rm;
3489 let Inst{15-10} = 0b001000;
3491 let Inst{4} = signalAllNans;
3492 let Inst{3-0} = 0b0000;
3495 multiclass FPComparison<bit signalAllNans, string asm,
3496 SDPatternOperator OpNode = null_frag> {
3497 let Defs = [CPSR] in {
3498 def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
3499 [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit CPSR)]> {
3503 def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
3504 [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit CPSR)]> {
3508 def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
3509 [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit CPSR)]> {
3513 def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
3514 [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit CPSR)]> {
3521 // Floating point conditional comparisons
3524 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3525 class BaseFPCondComparison<bit signalAllNans,
3526 RegisterClass regtype, string asm>
3527 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
3528 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
3529 Sched<[WriteFCmp]> {
3535 let Inst{31-23} = 0b000111100;
3537 let Inst{20-16} = Rm;
3538 let Inst{15-12} = cond;
3539 let Inst{11-10} = 0b01;
3541 let Inst{4} = signalAllNans;
3542 let Inst{3-0} = nzcv;
3545 multiclass FPCondComparison<bit signalAllNans, string asm> {
3546 let Defs = [CPSR], Uses = [CPSR] in {
3547 def Srr : BaseFPCondComparison<signalAllNans, FPR32, asm> {
3551 def Drr : BaseFPCondComparison<signalAllNans, FPR64, asm> {
3554 } // Defs = [CPSR], Uses = [CPSR]
3558 // Floating point conditional select
3561 class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
3562 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
3563 asm, "\t$Rd, $Rn, $Rm, $cond", "",
3565 (ARM64csel (vt regtype:$Rn), regtype:$Rm,
3566 (i32 imm:$cond), CPSR))]>,
3573 let Inst{31-23} = 0b000111100;
3575 let Inst{20-16} = Rm;
3576 let Inst{15-12} = cond;
3577 let Inst{11-10} = 0b11;
3582 multiclass FPCondSelect<string asm> {
3583 let Uses = [CPSR] in {
3584 def Srrr : BaseFPCondSelect<FPR32, f32, asm> {
3588 def Drrr : BaseFPCondSelect<FPR64, f64, asm> {
3595 // Floating move immediate
3598 class BaseFPMoveImmediate<RegisterClass regtype, Operand fpimmtype, string asm>
3599 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
3600 [(set regtype:$Rd, fpimmtype:$imm)]>,
3601 Sched<[WriteFImm]> {
3604 let Inst{31-23} = 0b000111100;
3606 let Inst{20-13} = imm;
3607 let Inst{12-5} = 0b10000000;
3611 multiclass FPMoveImmediate<string asm> {
3612 def Si : BaseFPMoveImmediate<FPR32, fpimm32, asm> {
3616 def Di : BaseFPMoveImmediate<FPR64, fpimm64, asm> {
3621 //----------------------------------------------------------------------------
3623 //----------------------------------------------------------------------------
3625 def VectorIndexBOperand : AsmOperandClass { let Name = "VectorIndexB"; }
3626 def VectorIndexHOperand : AsmOperandClass { let Name = "VectorIndexH"; }
3627 def VectorIndexSOperand : AsmOperandClass { let Name = "VectorIndexS"; }
3628 def VectorIndexDOperand : AsmOperandClass { let Name = "VectorIndexD"; }
3629 def VectorIndexB : Operand<i64>, ImmLeaf<i64, [{
3630 return ((uint64_t)Imm) < 16;
3632 let ParserMatchClass = VectorIndexBOperand;
3633 let PrintMethod = "printVectorIndex";
3634 let MIOperandInfo = (ops i64imm);
3636 def VectorIndexH : Operand<i64>, ImmLeaf<i64, [{
3637 return ((uint64_t)Imm) < 8;
3639 let ParserMatchClass = VectorIndexHOperand;
3640 let PrintMethod = "printVectorIndex";
3641 let MIOperandInfo = (ops i64imm);
3643 def VectorIndexS : Operand<i64>, ImmLeaf<i64, [{
3644 return ((uint64_t)Imm) < 4;
3646 let ParserMatchClass = VectorIndexSOperand;
3647 let PrintMethod = "printVectorIndex";
3648 let MIOperandInfo = (ops i64imm);
3650 def VectorIndexD : Operand<i64>, ImmLeaf<i64, [{
3651 return ((uint64_t)Imm) < 2;
3653 let ParserMatchClass = VectorIndexDOperand;
3654 let PrintMethod = "printVectorIndex";
3655 let MIOperandInfo = (ops i64imm);
3658 //----------------------------------------------------------------------------
3659 // AdvSIMD three register vector instructions
3660 //----------------------------------------------------------------------------
3662 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3663 class BaseSIMDThreeSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
3664 RegisterOperand regtype, string asm, string kind,
3666 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
3667 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
3668 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
3676 let Inst{28-24} = 0b01110;
3677 let Inst{23-22} = size;
3679 let Inst{20-16} = Rm;
3680 let Inst{15-11} = opcode;
3686 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3687 class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
3688 RegisterOperand regtype, string asm, string kind,
3690 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
3691 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
3692 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
3700 let Inst{28-24} = 0b01110;
3701 let Inst{23-22} = size;
3703 let Inst{20-16} = Rm;
3704 let Inst{15-11} = opcode;
3710 // All operand sizes distinguished in the encoding.
3711 multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
3712 SDPatternOperator OpNode> {
3713 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
3715 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
3716 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
3718 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
3719 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
3721 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
3722 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
3724 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
3725 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
3727 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
3728 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
3730 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
3731 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b11, opc, V128,
3733 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
3736 // As above, but D sized elements unsupported.
3737 multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm,
3738 SDPatternOperator OpNode> {
3739 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
3741 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
3742 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
3744 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
3745 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
3747 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
3748 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
3750 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
3751 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
3753 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
3754 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
3756 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
3759 multiclass SIMDThreeSameVectorBHSTied<bit U, bits<5> opc, string asm,
3760 SDPatternOperator OpNode> {
3761 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b00, opc, V64,
3763 [(set (v8i8 V64:$dst),
3764 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
3765 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b00, opc, V128,
3767 [(set (v16i8 V128:$dst),
3768 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
3769 def v4i16 : BaseSIMDThreeSameVectorTied<0, U, 0b01, opc, V64,
3771 [(set (v4i16 V64:$dst),
3772 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
3773 def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b01, opc, V128,
3775 [(set (v8i16 V128:$dst),
3776 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
3777 def v2i32 : BaseSIMDThreeSameVectorTied<0, U, 0b10, opc, V64,
3779 [(set (v2i32 V64:$dst),
3780 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
3781 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b10, opc, V128,
3783 [(set (v4i32 V128:$dst),
3784 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
3787 // As above, but only B sized elements supported.
3788 multiclass SIMDThreeSameVectorB<bit U, bits<5> opc, string asm,
3789 SDPatternOperator OpNode> {
3790 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
3792 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
3793 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
3795 [(set (v16i8 V128:$Rd),
3796 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
3799 // As above, but only S and D sized floating point elements supported.
3800 multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<5> opc,
3801 string asm, SDPatternOperator OpNode> {
3802 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
3804 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
3805 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
3807 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
3808 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
3810 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
3813 multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<5> opc,
3815 SDPatternOperator OpNode> {
3816 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
3818 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
3819 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
3821 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
3822 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
3824 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
3827 multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<5> opc,
3828 string asm, SDPatternOperator OpNode> {
3829 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0}, opc, V64,
3831 [(set (v2f32 V64:$dst),
3832 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
3833 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0}, opc, V128,
3835 [(set (v4f32 V128:$dst),
3836 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
3837 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,1}, opc, V128,
3839 [(set (v2f64 V128:$dst),
3840 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
3843 // As above, but D and B sized elements unsupported.
3844 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
3845 SDPatternOperator OpNode> {
3846 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
3848 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
3849 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
3851 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
3852 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
3854 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
3855 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
3857 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
3860 // Logical three vector ops share opcode bits, and only use B sized elements.
3861 multiclass SIMDLogicalThreeVector<bit U, bits<2> size, string asm,
3862 SDPatternOperator OpNode = null_frag> {
3863 def v8i8 : BaseSIMDThreeSameVector<0, U, size, 0b00011, V64,
3865 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
3866 def v16i8 : BaseSIMDThreeSameVector<1, U, size, 0b00011, V128,
3868 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
3870 def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)),
3871 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
3872 def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
3873 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
3874 def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)),
3875 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
3877 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
3878 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
3879 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
3880 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
3881 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
3882 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
3885 multiclass SIMDLogicalThreeVectorTied<bit U, bits<2> size,
3886 string asm, SDPatternOperator OpNode> {
3887 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, size, 0b00011, V64,
3889 [(set (v8i8 V64:$dst),
3890 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
3891 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, size, 0b00011, V128,
3893 [(set (v16i8 V128:$dst),
3894 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
3895 (v16i8 V128:$Rm)))]>;
3897 def : Pat<(v4i16 (OpNode (v4i16 V64:$LHS), (v4i16 V64:$MHS),
3899 (!cast<Instruction>(NAME#"v8i8")
3900 V64:$LHS, V64:$MHS, V64:$RHS)>;
3901 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
3903 (!cast<Instruction>(NAME#"v8i8")
3904 V64:$LHS, V64:$MHS, V64:$RHS)>;
3905 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
3907 (!cast<Instruction>(NAME#"v8i8")
3908 V64:$LHS, V64:$MHS, V64:$RHS)>;
3910 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
3911 (v8i16 V128:$RHS))),
3912 (!cast<Instruction>(NAME#"v16i8")
3913 V128:$LHS, V128:$MHS, V128:$RHS)>;
3914 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
3915 (v4i32 V128:$RHS))),
3916 (!cast<Instruction>(NAME#"v16i8")
3917 V128:$LHS, V128:$MHS, V128:$RHS)>;
3918 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
3919 (v2i64 V128:$RHS))),
3920 (!cast<Instruction>(NAME#"v16i8")
3921 V128:$LHS, V128:$MHS, V128:$RHS)>;
3925 //----------------------------------------------------------------------------
3926 // AdvSIMD two register vector instructions.
3927 //----------------------------------------------------------------------------
3929 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3930 class BaseSIMDTwoSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
3931 RegisterOperand regtype, string asm, string dstkind,
3932 string srckind, list<dag> pattern>
3933 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
3934 "{\t$Rd" # dstkind # ", $Rn" # srckind #
3935 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
3942 let Inst{28-24} = 0b01110;
3943 let Inst{23-22} = size;
3944 let Inst{21-17} = 0b10000;
3945 let Inst{16-12} = opcode;
3946 let Inst{11-10} = 0b10;
3951 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3952 class BaseSIMDTwoSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
3953 RegisterOperand regtype, string asm, string dstkind,
3954 string srckind, list<dag> pattern>
3955 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
3956 "{\t$Rd" # dstkind # ", $Rn" # srckind #
3957 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
3964 let Inst{28-24} = 0b01110;
3965 let Inst{23-22} = size;
3966 let Inst{21-17} = 0b10000;
3967 let Inst{16-12} = opcode;
3968 let Inst{11-10} = 0b10;
3973 // Supports B, H, and S element sizes.
3974 multiclass SIMDTwoVectorBHS<bit U, bits<5> opc, string asm,
3975 SDPatternOperator OpNode> {
3976 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
3978 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
3979 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
3980 asm, ".16b", ".16b",
3981 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
3982 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
3984 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
3985 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
3987 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
3988 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
3990 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
3991 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
3993 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
3996 class BaseSIMDVectorLShiftLongBySize<bit Q, bits<2> size,
3997 RegisterOperand regtype, string asm, string dstkind,
3998 string srckind, string amount>
3999 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4000 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
4001 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
4007 let Inst{29-24} = 0b101110;
4008 let Inst{23-22} = size;
4009 let Inst{21-10} = 0b100001001110;
4014 multiclass SIMDVectorLShiftLongBySizeBHS {
4015 let neverHasSideEffects = 1 in {
4016 def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64,
4017 "shll", ".8h", ".8b", "8">;
4018 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
4019 "shll2", ".8h", ".16b", "8">;
4020 def v4i16 : BaseSIMDVectorLShiftLongBySize<0, 0b01, V64,
4021 "shll", ".4s", ".4h", "16">;
4022 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
4023 "shll2", ".4s", ".8h", "16">;
4024 def v2i32 : BaseSIMDVectorLShiftLongBySize<0, 0b10, V64,
4025 "shll", ".2d", ".2s", "32">;
4026 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
4027 "shll2", ".2d", ".4s", "32">;
4031 // Supports all element sizes.
4032 multiclass SIMDLongTwoVector<bit U, bits<5> opc, string asm,
4033 SDPatternOperator OpNode> {
4034 def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4036 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4037 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4039 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4040 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4042 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4043 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4045 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4046 def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4048 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4049 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4051 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4054 multiclass SIMDLongTwoVectorTied<bit U, bits<5> opc, string asm,
4055 SDPatternOperator OpNode> {
4056 def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4058 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
4060 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4062 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
4063 (v16i8 V128:$Rn)))]>;
4064 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4066 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
4067 (v4i16 V64:$Rn)))]>;
4068 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4070 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
4071 (v8i16 V128:$Rn)))]>;
4072 def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4074 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
4075 (v2i32 V64:$Rn)))]>;
4076 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4078 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
4079 (v4i32 V128:$Rn)))]>;
4082 // Supports all element sizes, except 1xD.
4083 multiclass SIMDTwoVectorBHSDTied<bit U, bits<5> opc, string asm,
4084 SDPatternOperator OpNode> {
4085 def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4087 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
4088 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4089 asm, ".16b", ".16b",
4090 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4091 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4093 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
4094 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4096 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4097 def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4099 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
4100 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4102 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4103 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, V128,
4105 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4108 multiclass SIMDTwoVectorBHSD<bit U, bits<5> opc, string asm,
4109 SDPatternOperator OpNode = null_frag> {
4110 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4112 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4113 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4114 asm, ".16b", ".16b",
4115 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4116 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4118 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4119 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4121 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4122 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4124 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4125 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4127 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4128 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, V128,
4130 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4134 // Supports only B element sizes.
4135 multiclass SIMDTwoVectorB<bit U, bits<2> size, bits<5> opc, string asm,
4136 SDPatternOperator OpNode> {
4137 def v8i8 : BaseSIMDTwoSameVector<0, U, size, opc, V64,
4139 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4140 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, V128,
4141 asm, ".16b", ".16b",
4142 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4146 // Supports only B and H element sizes.
4147 multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
4148 SDPatternOperator OpNode> {
4149 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4151 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
4152 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4153 asm, ".16b", ".16b",
4154 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4155 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4157 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
4158 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4160 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4163 // Supports only S and D element sizes, uses high bit of the size field
4164 // as an extra opcode bit.
4165 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
4166 SDPatternOperator OpNode> {
4167 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4169 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4170 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4172 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4173 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4175 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4178 // Supports only S element size.
4179 multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
4180 SDPatternOperator OpNode> {
4181 def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4183 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4184 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4186 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4190 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
4191 SDPatternOperator OpNode> {
4192 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4194 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4195 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4197 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4198 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4200 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4203 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
4204 SDPatternOperator OpNode> {
4205 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4207 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4208 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4210 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4211 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4213 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4217 class BaseSIMDMixedTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4218 RegisterOperand inreg, RegisterOperand outreg,
4219 string asm, string outkind, string inkind,
4221 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
4222 "{\t$Rd" # outkind # ", $Rn" # inkind #
4223 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
4230 let Inst{28-24} = 0b01110;
4231 let Inst{23-22} = size;
4232 let Inst{21-17} = 0b10000;
4233 let Inst{16-12} = opcode;
4234 let Inst{11-10} = 0b10;
4239 class BaseSIMDMixedTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4240 RegisterOperand inreg, RegisterOperand outreg,
4241 string asm, string outkind, string inkind,
4243 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
4244 "{\t$Rd" # outkind # ", $Rn" # inkind #
4245 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4252 let Inst{28-24} = 0b01110;
4253 let Inst{23-22} = size;
4254 let Inst{21-17} = 0b10000;
4255 let Inst{16-12} = opcode;
4256 let Inst{11-10} = 0b10;
4261 multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
4262 SDPatternOperator OpNode> {
4263 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4265 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4266 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
4267 asm#"2", ".16b", ".8h", []>;
4268 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
4270 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4271 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
4272 asm#"2", ".8h", ".4s", []>;
4273 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
4275 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4276 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
4277 asm#"2", ".4s", ".2d", []>;
4279 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4280 (!cast<Instruction>(NAME # "v16i8")
4281 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4282 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4283 (!cast<Instruction>(NAME # "v8i16")
4284 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4285 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4286 (!cast<Instruction>(NAME # "v4i32")
4287 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4290 class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4291 RegisterOperand regtype, string asm, string kind,
4292 ValueType dty, ValueType sty, SDNode OpNode>
4293 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4294 "{\t$Rd" # kind # ", $Rn" # kind # ", #0" #
4295 "|" # kind # "\t$Rd, $Rn, #0}", "",
4296 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
4303 let Inst{28-24} = 0b01110;
4304 let Inst{23-22} = size;
4305 let Inst{21-17} = 0b10000;
4306 let Inst{16-12} = opcode;
4307 let Inst{11-10} = 0b10;
4312 // Comparisons support all element sizes, except 1xD.
4313 multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
4315 def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, opc, V64,
4317 v8i8, v8i8, OpNode>;
4318 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, opc, V128,
4320 v16i8, v16i8, OpNode>;
4321 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, opc, V64,
4323 v4i16, v4i16, OpNode>;
4324 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, opc, V128,
4326 v8i16, v8i16, OpNode>;
4327 def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, opc, V64,
4329 v2i32, v2i32, OpNode>;
4330 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, opc, V128,
4332 v4i32, v4i32, OpNode>;
4333 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, opc, V128,
4335 v2i64, v2i64, OpNode>;
4338 // FP Comparisons support only S and D element sizes.
4339 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
4340 string asm, SDNode OpNode> {
4341 def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, opc, V64,
4343 v2i32, v2f32, OpNode>;
4344 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, opc, V128,
4346 v4i32, v4f32, OpNode>;
4347 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, opc, V128,
4349 v2i64, v2f64, OpNode>;
4352 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4353 class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4354 RegisterOperand outtype, RegisterOperand intype,
4355 string asm, string VdTy, string VnTy,
4357 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
4358 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
4365 let Inst{28-24} = 0b01110;
4366 let Inst{23-22} = size;
4367 let Inst{21-17} = 0b10000;
4368 let Inst{16-12} = opcode;
4369 let Inst{11-10} = 0b10;
4374 class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4375 RegisterOperand outtype, RegisterOperand intype,
4376 string asm, string VdTy, string VnTy,
4378 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
4379 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
4386 let Inst{28-24} = 0b01110;
4387 let Inst{23-22} = size;
4388 let Inst{21-17} = 0b10000;
4389 let Inst{16-12} = opcode;
4390 let Inst{11-10} = 0b10;
4395 multiclass SIMDFPWidenTwoVector<bit U, bit S, bits<5> opc, string asm> {
4396 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64,
4397 asm, ".4s", ".4h", []>;
4398 def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128,
4399 asm#"2", ".4s", ".8h", []>;
4400 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64,
4401 asm, ".2d", ".2s", []>;
4402 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
4403 asm#"2", ".2d", ".4s", []>;
4406 multiclass SIMDFPNarrowTwoVector<bit U, bit S, bits<5> opc, string asm> {
4407 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128,
4408 asm, ".4h", ".4s", []>;
4409 def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128,
4410 asm#"2", ".8h", ".4s", []>;
4411 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4412 asm, ".2s", ".2d", []>;
4413 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4414 asm#"2", ".4s", ".2d", []>;
4417 multiclass SIMDFPInexactCvtTwoVector<bit U, bit S, bits<5> opc, string asm,
4419 def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4421 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4422 def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4423 asm#"2", ".4s", ".2d", []>;
4425 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
4426 (!cast<Instruction>(NAME # "v4f32")
4427 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4430 //----------------------------------------------------------------------------
4431 // AdvSIMD three register different-size vector instructions.
4432 //----------------------------------------------------------------------------
4434 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4435 class BaseSIMDDifferentThreeVector<bit U, bits<3> size, bits<4> opcode,
4436 RegisterOperand outtype, RegisterOperand intype1,
4437 RegisterOperand intype2, string asm,
4438 string outkind, string inkind1, string inkind2,
4440 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
4441 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4442 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
4448 let Inst{30} = size{0};
4450 let Inst{28-24} = 0b01110;
4451 let Inst{23-22} = size{2-1};
4453 let Inst{20-16} = Rm;
4454 let Inst{15-12} = opcode;
4455 let Inst{11-10} = 0b00;
4460 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4461 class BaseSIMDDifferentThreeVectorTied<bit U, bits<3> size, bits<4> opcode,
4462 RegisterOperand outtype, RegisterOperand intype1,
4463 RegisterOperand intype2, string asm,
4464 string outkind, string inkind1, string inkind2,
4466 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
4467 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4468 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4474 let Inst{30} = size{0};
4476 let Inst{28-24} = 0b01110;
4477 let Inst{23-22} = size{2-1};
4479 let Inst{20-16} = Rm;
4480 let Inst{15-12} = opcode;
4481 let Inst{11-10} = 0b00;
4486 // FIXME: TableGen doesn't know how to deal with expanded types that also
4487 // change the element count (in this case, placing the results in
4488 // the high elements of the result register rather than the low
4489 // elements). Until that's fixed, we can't code-gen those.
4490 multiclass SIMDNarrowThreeVectorBHS<bit U, bits<4> opc, string asm,
4492 def v8i16_v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4494 asm, ".8b", ".8h", ".8h",
4495 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4496 def v8i16_v16i8 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4498 asm#"2", ".16b", ".8h", ".8h",
4500 def v4i32_v4i16 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4502 asm, ".4h", ".4s", ".4s",
4503 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4504 def v4i32_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4506 asm#"2", ".8h", ".4s", ".4s",
4508 def v2i64_v2i32 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4510 asm, ".2s", ".2d", ".2d",
4511 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4512 def v2i64_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4514 asm#"2", ".4s", ".2d", ".2d",
4518 // Patterns for the '2' variants involve INSERT_SUBREG, which you can't put in
4519 // a version attached to an instruction.
4520 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
4522 (!cast<Instruction>(NAME # "v8i16_v16i8")
4523 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4524 V128:$Rn, V128:$Rm)>;
4525 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
4527 (!cast<Instruction>(NAME # "v4i32_v8i16")
4528 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4529 V128:$Rn, V128:$Rm)>;
4530 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
4532 (!cast<Instruction>(NAME # "v2i64_v4i32")
4533 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4534 V128:$Rn, V128:$Rm)>;
4537 multiclass SIMDDifferentThreeVectorBD<bit U, bits<4> opc, string asm,
4539 def v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4541 asm, ".8h", ".8b", ".8b",
4542 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4543 def v16i8 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4545 asm#"2", ".8h", ".16b", ".16b", []>;
4546 def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
4548 asm, ".1q", ".1d", ".1d", []>;
4549 def v2i64 : BaseSIMDDifferentThreeVector<U, 0b111, opc,
4551 asm#"2", ".1q", ".2d", ".2d", []>;
4553 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
4554 (v8i8 (extract_high_v16i8 V128:$Rm)))),
4555 (!cast<Instruction>(NAME#"v16i8") V128:$Rn, V128:$Rm)>;
4558 multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
4559 SDPatternOperator OpNode> {
4560 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4562 asm, ".4s", ".4h", ".4h",
4563 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4564 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4566 asm#"2", ".4s", ".8h", ".8h",
4567 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
4568 (extract_high_v8i16 V128:$Rm)))]>;
4569 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4571 asm, ".2d", ".2s", ".2s",
4572 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4573 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4575 asm#"2", ".2d", ".4s", ".4s",
4576 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
4577 (extract_high_v4i32 V128:$Rm)))]>;
4580 multiclass SIMDLongThreeVectorBHSabdl<bit U, bits<4> opc, string asm,
4581 SDPatternOperator OpNode = null_frag> {
4582 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4584 asm, ".8h", ".8b", ".8b",
4585 [(set (v8i16 V128:$Rd),
4586 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
4587 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4589 asm#"2", ".8h", ".16b", ".16b",
4590 [(set (v8i16 V128:$Rd),
4591 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
4592 (extract_high_v16i8 V128:$Rm)))))]>;
4593 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4595 asm, ".4s", ".4h", ".4h",
4596 [(set (v4i32 V128:$Rd),
4597 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>;
4598 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4600 asm#"2", ".4s", ".8h", ".8h",
4601 [(set (v4i32 V128:$Rd),
4602 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
4603 (extract_high_v8i16 V128:$Rm)))))]>;
4604 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4606 asm, ".2d", ".2s", ".2s",
4607 [(set (v2i64 V128:$Rd),
4608 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
4609 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4611 asm#"2", ".2d", ".4s", ".4s",
4612 [(set (v2i64 V128:$Rd),
4613 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
4614 (extract_high_v4i32 V128:$Rm)))))]>;
4617 multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
4619 SDPatternOperator OpNode> {
4620 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
4622 asm, ".8h", ".8b", ".8b",
4623 [(set (v8i16 V128:$dst),
4624 (add (v8i16 V128:$Rd),
4625 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
4626 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4628 asm#"2", ".8h", ".16b", ".16b",
4629 [(set (v8i16 V128:$dst),
4630 (add (v8i16 V128:$Rd),
4631 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
4632 (extract_high_v16i8 V128:$Rm))))))]>;
4633 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
4635 asm, ".4s", ".4h", ".4h",
4636 [(set (v4i32 V128:$dst),
4637 (add (v4i32 V128:$Rd),
4638 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
4639 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4641 asm#"2", ".4s", ".8h", ".8h",
4642 [(set (v4i32 V128:$dst),
4643 (add (v4i32 V128:$Rd),
4644 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
4645 (extract_high_v8i16 V128:$Rm))))))]>;
4646 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
4648 asm, ".2d", ".2s", ".2s",
4649 [(set (v2i64 V128:$dst),
4650 (add (v2i64 V128:$Rd),
4651 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
4652 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4654 asm#"2", ".2d", ".4s", ".4s",
4655 [(set (v2i64 V128:$dst),
4656 (add (v2i64 V128:$Rd),
4657 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
4658 (extract_high_v4i32 V128:$Rm))))))]>;
4661 multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
4662 SDPatternOperator OpNode = null_frag> {
4663 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4665 asm, ".8h", ".8b", ".8b",
4666 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4667 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4669 asm#"2", ".8h", ".16b", ".16b",
4670 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
4671 (extract_high_v16i8 V128:$Rm)))]>;
4672 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4674 asm, ".4s", ".4h", ".4h",
4675 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4676 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4678 asm#"2", ".4s", ".8h", ".8h",
4679 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
4680 (extract_high_v8i16 V128:$Rm)))]>;
4681 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4683 asm, ".2d", ".2s", ".2s",
4684 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4685 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4687 asm#"2", ".2d", ".4s", ".4s",
4688 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
4689 (extract_high_v4i32 V128:$Rm)))]>;
4692 multiclass SIMDLongThreeVectorTiedBHS<bit U, bits<4> opc,
4694 SDPatternOperator OpNode> {
4695 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
4697 asm, ".8h", ".8b", ".8b",
4698 [(set (v8i16 V128:$dst),
4699 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4700 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4702 asm#"2", ".8h", ".16b", ".16b",
4703 [(set (v8i16 V128:$dst),
4704 (OpNode (v8i16 V128:$Rd),
4705 (extract_high_v16i8 V128:$Rn),
4706 (extract_high_v16i8 V128:$Rm)))]>;
4707 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
4709 asm, ".4s", ".4h", ".4h",
4710 [(set (v4i32 V128:$dst),
4711 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4712 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4714 asm#"2", ".4s", ".8h", ".8h",
4715 [(set (v4i32 V128:$dst),
4716 (OpNode (v4i32 V128:$Rd),
4717 (extract_high_v8i16 V128:$Rn),
4718 (extract_high_v8i16 V128:$Rm)))]>;
4719 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
4721 asm, ".2d", ".2s", ".2s",
4722 [(set (v2i64 V128:$dst),
4723 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4724 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4726 asm#"2", ".2d", ".4s", ".4s",
4727 [(set (v2i64 V128:$dst),
4728 (OpNode (v2i64 V128:$Rd),
4729 (extract_high_v4i32 V128:$Rn),
4730 (extract_high_v4i32 V128:$Rm)))]>;
4733 multiclass SIMDLongThreeVectorSQDMLXTiedHS<bit U, bits<4> opc, string asm,
4734 SDPatternOperator Accum> {
4735 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
4737 asm, ".4s", ".4h", ".4h",
4738 [(set (v4i32 V128:$dst),
4739 (Accum (v4i32 V128:$Rd),
4740 (v4i32 (int_arm64_neon_sqdmull (v4i16 V64:$Rn),
4741 (v4i16 V64:$Rm)))))]>;
4742 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4744 asm#"2", ".4s", ".8h", ".8h",
4745 [(set (v4i32 V128:$dst),
4746 (Accum (v4i32 V128:$Rd),
4747 (v4i32 (int_arm64_neon_sqdmull (extract_high_v8i16 V128:$Rn),
4748 (extract_high_v8i16 V128:$Rm)))))]>;
4749 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
4751 asm, ".2d", ".2s", ".2s",
4752 [(set (v2i64 V128:$dst),
4753 (Accum (v2i64 V128:$Rd),
4754 (v2i64 (int_arm64_neon_sqdmull (v2i32 V64:$Rn),
4755 (v2i32 V64:$Rm)))))]>;
4756 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4758 asm#"2", ".2d", ".4s", ".4s",
4759 [(set (v2i64 V128:$dst),
4760 (Accum (v2i64 V128:$Rd),
4761 (v2i64 (int_arm64_neon_sqdmull (extract_high_v4i32 V128:$Rn),
4762 (extract_high_v4i32 V128:$Rm)))))]>;
4765 multiclass SIMDWideThreeVectorBHS<bit U, bits<4> opc, string asm,
4766 SDPatternOperator OpNode> {
4767 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4769 asm, ".8h", ".8h", ".8b",
4770 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
4771 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4773 asm#"2", ".8h", ".8h", ".16b",
4774 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
4775 (extract_high_v16i8 V128:$Rm)))]>;
4776 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4778 asm, ".4s", ".4s", ".4h",
4779 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
4780 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4782 asm#"2", ".4s", ".4s", ".8h",
4783 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
4784 (extract_high_v8i16 V128:$Rm)))]>;
4785 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4787 asm, ".2d", ".2d", ".2s",
4788 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
4789 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4791 asm#"2", ".2d", ".2d", ".4s",
4792 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
4793 (extract_high_v4i32 V128:$Rm)))]>;
4796 //----------------------------------------------------------------------------
4797 // AdvSIMD bitwise extract from vector
4798 //----------------------------------------------------------------------------
4800 class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
4801 string asm, string kind>
4802 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
4803 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
4804 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
4805 [(set (vty regtype:$Rd),
4806 (ARM64ext regtype:$Rn, regtype:$Rm, (i32 imm:$imm)))]>,
4813 let Inst{30} = size;
4814 let Inst{29-21} = 0b101110000;
4815 let Inst{20-16} = Rm;
4817 let Inst{14-11} = imm;
4824 multiclass SIMDBitwiseExtract<string asm> {
4825 def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b">;
4826 def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
4829 //----------------------------------------------------------------------------
4830 // AdvSIMD zip vector
4831 //----------------------------------------------------------------------------
4833 class BaseSIMDZipVector<bits<3> size, bits<3> opc, RegisterOperand regtype,
4834 string asm, string kind, SDNode OpNode, ValueType valty>
4835 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
4836 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
4837 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
4838 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
4844 let Inst{30} = size{0};
4845 let Inst{29-24} = 0b001110;
4846 let Inst{23-22} = size{2-1};
4848 let Inst{20-16} = Rm;
4850 let Inst{14-12} = opc;
4851 let Inst{11-10} = 0b10;
4856 multiclass SIMDZipVector<bits<3>opc, string asm,
4858 def v8i8 : BaseSIMDZipVector<0b000, opc, V64,
4859 asm, ".8b", OpNode, v8i8>;
4860 def v16i8 : BaseSIMDZipVector<0b001, opc, V128,
4861 asm, ".16b", OpNode, v16i8>;
4862 def v4i16 : BaseSIMDZipVector<0b010, opc, V64,
4863 asm, ".4h", OpNode, v4i16>;
4864 def v8i16 : BaseSIMDZipVector<0b011, opc, V128,
4865 asm, ".8h", OpNode, v8i16>;
4866 def v2i32 : BaseSIMDZipVector<0b100, opc, V64,
4867 asm, ".2s", OpNode, v2i32>;
4868 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
4869 asm, ".4s", OpNode, v4i32>;
4870 def v2i64 : BaseSIMDZipVector<0b111, opc, V128,
4871 asm, ".2d", OpNode, v2i64>;
4873 def : Pat<(v2f32 (OpNode V64:$Rn, V64:$Rm)),
4874 (!cast<Instruction>(NAME#"v2i32") V64:$Rn, V64:$Rm)>;
4875 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
4876 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
4877 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
4878 (!cast<Instruction>(NAME#"v2i64") V128:$Rn, V128:$Rm)>;
4881 //----------------------------------------------------------------------------
4882 // AdvSIMD three register scalar instructions
4883 //----------------------------------------------------------------------------
4885 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
4886 class BaseSIMDThreeScalar<bit U, bits<2> size, bits<5> opcode,
4887 RegisterClass regtype, string asm,
4889 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
4890 "\t$Rd, $Rn, $Rm", "", pattern>,
4895 let Inst{31-30} = 0b01;
4897 let Inst{28-24} = 0b11110;
4898 let Inst{23-22} = size;
4900 let Inst{20-16} = Rm;
4901 let Inst{15-11} = opcode;
4907 multiclass SIMDThreeScalarD<bit U, bits<5> opc, string asm,
4908 SDPatternOperator OpNode> {
4909 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
4910 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
4913 multiclass SIMDThreeScalarBHSD<bit U, bits<5> opc, string asm,
4914 SDPatternOperator OpNode> {
4915 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
4916 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
4917 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm, []>;
4918 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
4919 def v1i8 : BaseSIMDThreeScalar<U, 0b00, opc, FPR8 , asm, []>;
4921 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4922 (!cast<Instruction>(NAME#"v1i64") FPR64:$Rn, FPR64:$Rm)>;
4923 def : Pat<(i32 (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm))),
4924 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
4927 multiclass SIMDThreeScalarHS<bit U, bits<5> opc, string asm,
4928 SDPatternOperator OpNode> {
4929 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm,
4930 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
4931 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
4934 multiclass SIMDThreeScalarSD<bit U, bit S, bits<5> opc, string asm,
4935 SDPatternOperator OpNode = null_frag> {
4936 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
4937 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
4938 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
4939 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
4940 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
4943 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4944 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
4947 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<5> opc, string asm,
4948 SDPatternOperator OpNode = null_frag> {
4949 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
4950 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
4951 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
4952 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
4953 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
4956 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
4957 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
4960 class BaseSIMDThreeScalarMixed<bit U, bits<2> size, bits<5> opcode,
4961 dag oops, dag iops, string asm, string cstr, list<dag> pat>
4962 : I<oops, iops, asm,
4963 "\t$Rd, $Rn, $Rm", cstr, pat>,
4968 let Inst{31-30} = 0b01;
4970 let Inst{28-24} = 0b11110;
4971 let Inst{23-22} = size;
4973 let Inst{20-16} = Rm;
4974 let Inst{15-11} = opcode;
4980 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4981 multiclass SIMDThreeScalarMixedHS<bit U, bits<5> opc, string asm,
4982 SDPatternOperator OpNode = null_frag> {
4983 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
4985 (ins FPR16:$Rn, FPR16:$Rm), asm, "", []>;
4986 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
4988 (ins FPR32:$Rn, FPR32:$Rm), asm, "",
4989 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
4992 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4993 multiclass SIMDThreeScalarMixedTiedHS<bit U, bits<5> opc, string asm,
4994 SDPatternOperator OpNode = null_frag> {
4995 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
4997 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
4998 asm, "$Rd = $dst", []>;
4999 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5001 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
5003 [(set (i64 FPR64:$dst),
5004 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5007 //----------------------------------------------------------------------------
5008 // AdvSIMD two register scalar instructions
5009 //----------------------------------------------------------------------------
5011 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5012 class BaseSIMDTwoScalar<bit U, bits<2> size, bits<5> opcode,
5013 RegisterClass regtype, RegisterClass regtype2,
5014 string asm, list<dag> pat>
5015 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
5016 "\t$Rd, $Rn", "", pat>,
5020 let Inst{31-30} = 0b01;
5022 let Inst{28-24} = 0b11110;
5023 let Inst{23-22} = size;
5024 let Inst{21-17} = 0b10000;
5025 let Inst{16-12} = opcode;
5026 let Inst{11-10} = 0b10;
5031 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5032 class BaseSIMDTwoScalarTied<bit U, bits<2> size, bits<5> opcode,
5033 RegisterClass regtype, RegisterClass regtype2,
5034 string asm, list<dag> pat>
5035 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
5036 "\t$Rd, $Rn", "$Rd = $dst", pat>,
5040 let Inst{31-30} = 0b01;
5042 let Inst{28-24} = 0b11110;
5043 let Inst{23-22} = size;
5044 let Inst{21-17} = 0b10000;
5045 let Inst{16-12} = opcode;
5046 let Inst{11-10} = 0b10;
5052 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5053 class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<5> opcode,
5054 RegisterClass regtype, string asm>
5055 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5056 "\t$Rd, $Rn, #0", "", []>,
5060 let Inst{31-30} = 0b01;
5062 let Inst{28-24} = 0b11110;
5063 let Inst{23-22} = size;
5064 let Inst{21-17} = 0b10000;
5065 let Inst{16-12} = opcode;
5066 let Inst{11-10} = 0b10;
5071 class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
5072 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
5073 [(set (f32 FPR32:$Rd), (int_arm64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
5077 let Inst{31-17} = 0b011111100110000;
5078 let Inst{16-12} = opcode;
5079 let Inst{11-10} = 0b10;
5084 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
5085 SDPatternOperator OpNode> {
5086 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm>;
5088 def : Pat<(v1i64 (OpNode FPR64:$Rn)),
5089 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5092 multiclass SIMDCmpTwoScalarSD<bit U, bit S, bits<5> opc, string asm,
5093 SDPatternOperator OpNode> {
5094 def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm>;
5095 def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm>;
5097 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
5098 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5101 multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
5102 SDPatternOperator OpNode = null_frag> {
5103 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5104 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
5106 def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
5107 (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
5110 multiclass SIMDTwoScalarSD<bit U, bit S, bits<5> opc, string asm> {
5111 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,[]>;
5112 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,[]>;
5115 multiclass SIMDTwoScalarCVTSD<bit U, bit S, bits<5> opc, string asm,
5116 SDPatternOperator OpNode> {
5117 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,
5118 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
5119 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,
5120 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
5123 multiclass SIMDTwoScalarBHSD<bit U, bits<5> opc, string asm,
5124 SDPatternOperator OpNode = null_frag> {
5125 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5126 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5127 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5128 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR32, asm,
5129 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
5130 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR16, asm, []>;
5131 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5134 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))),
5135 (!cast<Instruction>(NAME # v1i64) FPR64:$Rn)>;
5138 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5139 multiclass SIMDTwoScalarBHSDTied<bit U, bits<5> opc, string asm,
5141 def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
5142 [(set (v1i64 FPR64:$dst),
5143 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn)))]>;
5144 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR32, asm, []>;
5145 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR16, asm, []>;
5146 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5151 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5152 multiclass SIMDTwoScalarMixedBHS<bit U, bits<5> opc, string asm,
5153 SDPatternOperator OpNode = null_frag> {
5154 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR64, asm,
5155 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5156 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR32, asm, []>;
5157 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR16, asm, []>;
5160 //----------------------------------------------------------------------------
5161 // AdvSIMD scalar pairwise instructions
5162 //----------------------------------------------------------------------------
5164 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5165 class BaseSIMDPairwiseScalar<bit U, bits<2> size, bits<5> opcode,
5166 RegisterOperand regtype, RegisterOperand vectype,
5167 string asm, string kind>
5168 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5169 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
5173 let Inst{31-30} = 0b01;
5175 let Inst{28-24} = 0b11110;
5176 let Inst{23-22} = size;
5177 let Inst{21-17} = 0b11000;
5178 let Inst{16-12} = opcode;
5179 let Inst{11-10} = 0b10;
5184 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
5185 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
5189 multiclass SIMDPairwiseScalarSD<bit U, bit S, bits<5> opc, string asm> {
5190 def v2i32p : BaseSIMDPairwiseScalar<U, {S,0}, opc, FPR32Op, V64,
5192 def v2i64p : BaseSIMDPairwiseScalar<U, {S,1}, opc, FPR64Op, V128,
5196 //----------------------------------------------------------------------------
5197 // AdvSIMD across lanes instructions
5198 //----------------------------------------------------------------------------
5200 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5201 class BaseSIMDAcrossLanes<bit Q, bit U, bits<2> size, bits<5> opcode,
5202 RegisterClass regtype, RegisterOperand vectype,
5203 string asm, string kind, list<dag> pattern>
5204 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5205 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
5212 let Inst{28-24} = 0b01110;
5213 let Inst{23-22} = size;
5214 let Inst{21-17} = 0b11000;
5215 let Inst{16-12} = opcode;
5216 let Inst{11-10} = 0b10;
5221 multiclass SIMDAcrossLanesBHS<bit U, bits<5> opcode,
5223 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
5225 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
5227 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64,
5229 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
5231 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128,
5235 multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
5236 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64,
5238 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
5240 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
5242 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
5244 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
5248 multiclass SIMDAcrossLanesS<bits<5> opcode, bit sz1, string asm,
5250 def v4i32v : BaseSIMDAcrossLanes<1, 1, {sz1, 0}, opcode, FPR32, V128,
5252 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
5255 //----------------------------------------------------------------------------
5256 // AdvSIMD INS/DUP instructions
5257 //----------------------------------------------------------------------------
5259 // FIXME: There has got to be a better way to factor these. ugh.
5261 class BaseSIMDInsDup<bit Q, bit op, dag outs, dag ins, string asm,
5262 string operands, string constraints, list<dag> pattern>
5263 : I<outs, ins, asm, operands, constraints, pattern>,
5270 let Inst{28-21} = 0b01110000;
5277 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
5278 RegisterOperand vecreg, RegisterClass regtype>
5279 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
5280 "{\t$Rd" # size # ", $Rn" #
5281 "|" # size # "\t$Rd, $Rn}", "",
5282 [(set (vectype vecreg:$Rd), (ARM64dup regtype:$Rn))]> {
5283 let Inst{20-16} = imm5;
5284 let Inst{14-11} = 0b0001;
5287 class SIMDDupFromElement<bit Q, string dstkind, string srckind,
5288 ValueType vectype, ValueType insreg,
5289 RegisterOperand vecreg, Operand idxtype,
5290 ValueType elttype, SDNode OpNode>
5291 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
5292 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
5293 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
5294 [(set (vectype vecreg:$Rd),
5295 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
5296 let Inst{14-11} = 0b0000;
5299 class SIMDDup64FromElement
5300 : SIMDDupFromElement<1, ".2d", ".d", v2i64, v2i64, V128,
5301 VectorIndexD, i64, ARM64duplane64> {
5304 let Inst{19-16} = 0b1000;
5307 class SIMDDup32FromElement<bit Q, string size, ValueType vectype,
5308 RegisterOperand vecreg>
5309 : SIMDDupFromElement<Q, size, ".s", vectype, v4i32, vecreg,
5310 VectorIndexS, i64, ARM64duplane32> {
5312 let Inst{20-19} = idx;
5313 let Inst{18-16} = 0b100;
5316 class SIMDDup16FromElement<bit Q, string size, ValueType vectype,
5317 RegisterOperand vecreg>
5318 : SIMDDupFromElement<Q, size, ".h", vectype, v8i16, vecreg,
5319 VectorIndexH, i64, ARM64duplane16> {
5321 let Inst{20-18} = idx;
5322 let Inst{17-16} = 0b10;
5325 class SIMDDup8FromElement<bit Q, string size, ValueType vectype,
5326 RegisterOperand vecreg>
5327 : SIMDDupFromElement<Q, size, ".b", vectype, v16i8, vecreg,
5328 VectorIndexB, i64, ARM64duplane8> {
5330 let Inst{20-17} = idx;
5334 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
5335 Operand idxtype, string asm, list<dag> pattern>
5336 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
5337 "{\t$Rd, $Rn" # size # "$idx" #
5338 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
5339 let Inst{14-11} = imm4;
5342 class SIMDSMov<bit Q, string size, RegisterClass regtype,
5344 : BaseSIMDMov<Q, size, 0b0101, regtype, idxtype, "smov", []>;
5345 class SIMDUMov<bit Q, string size, ValueType vectype, RegisterClass regtype,
5347 : BaseSIMDMov<Q, size, 0b0111, regtype, idxtype, "umov",
5348 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
5350 class SIMDMovAlias<string asm, string size, Instruction inst,
5351 RegisterClass regtype, Operand idxtype>
5352 : InstAlias<asm#"{\t$dst, $src"#size#"$idx" #
5353 "|" # size # "\t$dst, $src$idx}",
5354 (inst regtype:$dst, V128:$src, idxtype:$idx)>;
5357 def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> {
5359 let Inst{20-17} = idx;
5362 def vi8to64 : SIMDSMov<1, ".b", GPR64, VectorIndexB> {
5364 let Inst{20-17} = idx;
5367 def vi16to32 : SIMDSMov<0, ".h", GPR32, VectorIndexH> {
5369 let Inst{20-18} = idx;
5370 let Inst{17-16} = 0b10;
5372 def vi16to64 : SIMDSMov<1, ".h", GPR64, VectorIndexH> {
5374 let Inst{20-18} = idx;
5375 let Inst{17-16} = 0b10;
5377 def vi32to64 : SIMDSMov<1, ".s", GPR64, VectorIndexS> {
5379 let Inst{20-19} = idx;
5380 let Inst{18-16} = 0b100;
5385 def vi8 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndexB> {
5387 let Inst{20-17} = idx;
5390 def vi16 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndexH> {
5392 let Inst{20-18} = idx;
5393 let Inst{17-16} = 0b10;
5395 def vi32 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndexS> {
5397 let Inst{20-19} = idx;
5398 let Inst{18-16} = 0b100;
5400 def vi64 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndexD> {
5403 let Inst{19-16} = 0b1000;
5405 def : SIMDMovAlias<"mov", ".s",
5406 !cast<Instruction>(NAME#"vi32"),
5407 GPR32, VectorIndexS>;
5408 def : SIMDMovAlias<"mov", ".d",
5409 !cast<Instruction>(NAME#"vi64"),
5410 GPR64, VectorIndexD>;
5413 class SIMDInsFromMain<string size, ValueType vectype,
5414 RegisterClass regtype, Operand idxtype>
5415 : BaseSIMDInsDup<1, 0, (outs V128:$dst),
5416 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
5417 "{\t$Rd" # size # "$idx, $Rn" #
5418 "|" # size # "\t$Rd$idx, $Rn}",
5421 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
5422 let Inst{14-11} = 0b0011;
5425 class SIMDInsFromElement<string size, ValueType vectype,
5426 ValueType elttype, Operand idxtype>
5427 : BaseSIMDInsDup<1, 1, (outs V128:$dst),
5428 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
5429 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
5430 "|" # size # "\t$Rd$idx, $Rn$idx2}",
5435 (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
5438 class SIMDInsMainMovAlias<string size, Instruction inst,
5439 RegisterClass regtype, Operand idxtype>
5440 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" #
5441 "|" # size #"\t$dst$idx, $src}",
5442 (inst V128:$dst, idxtype:$idx, regtype:$src)>;
5443 class SIMDInsElementMovAlias<string size, Instruction inst,
5445 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
5446 # "|" # size #" $dst$idx, $src$idx2}",
5447 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
5450 multiclass SIMDIns {
5451 def vi8gpr : SIMDInsFromMain<".b", v16i8, GPR32, VectorIndexB> {
5453 let Inst{20-17} = idx;
5456 def vi16gpr : SIMDInsFromMain<".h", v8i16, GPR32, VectorIndexH> {
5458 let Inst{20-18} = idx;
5459 let Inst{17-16} = 0b10;
5461 def vi32gpr : SIMDInsFromMain<".s", v4i32, GPR32, VectorIndexS> {
5463 let Inst{20-19} = idx;
5464 let Inst{18-16} = 0b100;
5466 def vi64gpr : SIMDInsFromMain<".d", v2i64, GPR64, VectorIndexD> {
5469 let Inst{19-16} = 0b1000;
5472 def vi8lane : SIMDInsFromElement<".b", v16i8, i32, VectorIndexB> {
5475 let Inst{20-17} = idx;
5477 let Inst{14-11} = idx2;
5479 def vi16lane : SIMDInsFromElement<".h", v8i16, i32, VectorIndexH> {
5482 let Inst{20-18} = idx;
5483 let Inst{17-16} = 0b10;
5484 let Inst{14-12} = idx2;
5487 def vi32lane : SIMDInsFromElement<".s", v4i32, i32, VectorIndexS> {
5490 let Inst{20-19} = idx;
5491 let Inst{18-16} = 0b100;
5492 let Inst{14-13} = idx2;
5493 let Inst{12-11} = 0;
5495 def vi64lane : SIMDInsFromElement<".d", v2i64, i64, VectorIndexD> {
5499 let Inst{19-16} = 0b1000;
5500 let Inst{14} = idx2;
5501 let Inst{13-11} = 0;
5504 // For all forms of the INS instruction, the "mov" mnemonic is the
5505 // preferred alias. Why they didn't just call the instruction "mov" in
5506 // the first place is a very good question indeed...
5507 def : SIMDInsMainMovAlias<".b", !cast<Instruction>(NAME#"vi8gpr"),
5508 GPR32, VectorIndexB>;
5509 def : SIMDInsMainMovAlias<".h", !cast<Instruction>(NAME#"vi16gpr"),
5510 GPR32, VectorIndexH>;
5511 def : SIMDInsMainMovAlias<".s", !cast<Instruction>(NAME#"vi32gpr"),
5512 GPR32, VectorIndexS>;
5513 def : SIMDInsMainMovAlias<".d", !cast<Instruction>(NAME#"vi64gpr"),
5514 GPR64, VectorIndexD>;
5516 def : SIMDInsElementMovAlias<".b", !cast<Instruction>(NAME#"vi8lane"),
5518 def : SIMDInsElementMovAlias<".h", !cast<Instruction>(NAME#"vi16lane"),
5520 def : SIMDInsElementMovAlias<".s", !cast<Instruction>(NAME#"vi32lane"),
5522 def : SIMDInsElementMovAlias<".d", !cast<Instruction>(NAME#"vi64lane"),
5526 //----------------------------------------------------------------------------
5528 //----------------------------------------------------------------------------
5530 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5531 class BaseSIMDTableLookup<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5532 RegisterOperand listtype, string asm, string kind>
5533 : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm,
5534 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "", []>,
5541 let Inst{29-21} = 0b001110000;
5542 let Inst{20-16} = Vm;
5544 let Inst{14-13} = len;
5546 let Inst{11-10} = 0b00;
5551 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5552 class BaseSIMDTableLookupTied<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5553 RegisterOperand listtype, string asm, string kind>
5554 : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm,
5555 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
5562 let Inst{29-21} = 0b001110000;
5563 let Inst{20-16} = Vm;
5565 let Inst{14-13} = len;
5567 let Inst{11-10} = 0b00;
5572 class SIMDTableLookupAlias<string asm, Instruction inst,
5573 RegisterOperand vectype, RegisterOperand listtype>
5574 : InstAlias<!strconcat(asm, "\t$dst, $lst, $index"),
5575 (inst vectype:$dst, listtype:$lst, vectype:$index), 0>;
5577 multiclass SIMDTableLookup<bit op, string asm> {
5578 def v8i8One : BaseSIMDTableLookup<0, 0b00, op, V64, VecListOne16b,
5580 def v8i8Two : BaseSIMDTableLookup<0, 0b01, op, V64, VecListTwo16b,
5582 def v8i8Three : BaseSIMDTableLookup<0, 0b10, op, V64, VecListThree16b,
5584 def v8i8Four : BaseSIMDTableLookup<0, 0b11, op, V64, VecListFour16b,
5586 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
5588 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
5590 def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b,
5592 def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b,
5595 def : SIMDTableLookupAlias<asm # ".8b",
5596 !cast<Instruction>(NAME#"v8i8One"),
5597 V64, VecListOne128>;
5598 def : SIMDTableLookupAlias<asm # ".8b",
5599 !cast<Instruction>(NAME#"v8i8Two"),
5600 V64, VecListTwo128>;
5601 def : SIMDTableLookupAlias<asm # ".8b",
5602 !cast<Instruction>(NAME#"v8i8Three"),
5603 V64, VecListThree128>;
5604 def : SIMDTableLookupAlias<asm # ".8b",
5605 !cast<Instruction>(NAME#"v8i8Four"),
5606 V64, VecListFour128>;
5607 def : SIMDTableLookupAlias<asm # ".16b",
5608 !cast<Instruction>(NAME#"v16i8One"),
5609 V128, VecListOne128>;
5610 def : SIMDTableLookupAlias<asm # ".16b",
5611 !cast<Instruction>(NAME#"v16i8Two"),
5612 V128, VecListTwo128>;
5613 def : SIMDTableLookupAlias<asm # ".16b",
5614 !cast<Instruction>(NAME#"v16i8Three"),
5615 V128, VecListThree128>;
5616 def : SIMDTableLookupAlias<asm # ".16b",
5617 !cast<Instruction>(NAME#"v16i8Four"),
5618 V128, VecListFour128>;
5621 multiclass SIMDTableLookupTied<bit op, string asm> {
5622 def v8i8One : BaseSIMDTableLookupTied<0, 0b00, op, V64, VecListOne16b,
5624 def v8i8Two : BaseSIMDTableLookupTied<0, 0b01, op, V64, VecListTwo16b,
5626 def v8i8Three : BaseSIMDTableLookupTied<0, 0b10, op, V64, VecListThree16b,
5628 def v8i8Four : BaseSIMDTableLookupTied<0, 0b11, op, V64, VecListFour16b,
5630 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
5632 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
5634 def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b,
5636 def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b,
5639 def : SIMDTableLookupAlias<asm # ".8b",
5640 !cast<Instruction>(NAME#"v8i8One"),
5641 V64, VecListOne128>;
5642 def : SIMDTableLookupAlias<asm # ".8b",
5643 !cast<Instruction>(NAME#"v8i8Two"),
5644 V64, VecListTwo128>;
5645 def : SIMDTableLookupAlias<asm # ".8b",
5646 !cast<Instruction>(NAME#"v8i8Three"),
5647 V64, VecListThree128>;
5648 def : SIMDTableLookupAlias<asm # ".8b",
5649 !cast<Instruction>(NAME#"v8i8Four"),
5650 V64, VecListFour128>;
5651 def : SIMDTableLookupAlias<asm # ".16b",
5652 !cast<Instruction>(NAME#"v16i8One"),
5653 V128, VecListOne128>;
5654 def : SIMDTableLookupAlias<asm # ".16b",
5655 !cast<Instruction>(NAME#"v16i8Two"),
5656 V128, VecListTwo128>;
5657 def : SIMDTableLookupAlias<asm # ".16b",
5658 !cast<Instruction>(NAME#"v16i8Three"),
5659 V128, VecListThree128>;
5660 def : SIMDTableLookupAlias<asm # ".16b",
5661 !cast<Instruction>(NAME#"v16i8Four"),
5662 V128, VecListFour128>;
5666 //----------------------------------------------------------------------------
5667 // AdvSIMD scalar CPY
5668 //----------------------------------------------------------------------------
5669 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5670 class BaseSIMDScalarCPY<RegisterClass regtype, RegisterOperand vectype,
5671 string kind, Operand idxtype>
5672 : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), "mov",
5673 "{\t$dst, $src" # kind # "$idx" #
5674 "|\t$dst, $src$idx}", "", []>,
5678 let Inst{31-21} = 0b01011110000;
5679 let Inst{15-10} = 0b000001;
5680 let Inst{9-5} = src;
5681 let Inst{4-0} = dst;
5684 class SIMDScalarCPYAlias<string asm, string size, Instruction inst,
5685 RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
5686 : InstAlias<asm # "{\t$dst, $src" # size # "$index" #
5687 # "|\t$dst, $src$index}",
5688 (inst regtype:$dst, vectype:$src, idxtype:$index)>;
5691 multiclass SIMDScalarCPY<string asm> {
5692 def i8 : BaseSIMDScalarCPY<FPR8, V128, ".b", VectorIndexB> {
5694 let Inst{20-17} = idx;
5697 def i16 : BaseSIMDScalarCPY<FPR16, V128, ".h", VectorIndexH> {
5699 let Inst{20-18} = idx;
5700 let Inst{17-16} = 0b10;
5702 def i32 : BaseSIMDScalarCPY<FPR32, V128, ".s", VectorIndexS> {
5704 let Inst{20-19} = idx;
5705 let Inst{18-16} = 0b100;
5707 def i64 : BaseSIMDScalarCPY<FPR64, V128, ".d", VectorIndexD> {
5710 let Inst{19-16} = 0b1000;
5713 // 'DUP' mnemonic aliases.
5714 def : SIMDScalarCPYAlias<"dup", ".b",
5715 !cast<Instruction>(NAME#"i8"),
5716 FPR8, V128, VectorIndexB>;
5717 def : SIMDScalarCPYAlias<"dup", ".h",
5718 !cast<Instruction>(NAME#"i16"),
5719 FPR16, V128, VectorIndexH>;
5720 def : SIMDScalarCPYAlias<"dup", ".s",
5721 !cast<Instruction>(NAME#"i32"),
5722 FPR32, V128, VectorIndexS>;
5723 def : SIMDScalarCPYAlias<"dup", ".d",
5724 !cast<Instruction>(NAME#"i64"),
5725 FPR64, V128, VectorIndexD>;
5728 //----------------------------------------------------------------------------
5729 // AdvSIMD modified immediate instructions
5730 //----------------------------------------------------------------------------
5732 class BaseSIMDModifiedImm<bit Q, bit op, dag oops, dag iops,
5733 string asm, string op_string,
5734 string cstr, list<dag> pattern>
5735 : I<oops, iops, asm, op_string, cstr, pattern>,
5742 let Inst{28-19} = 0b0111100000;
5743 let Inst{18-16} = imm8{7-5};
5744 let Inst{11-10} = 0b01;
5745 let Inst{9-5} = imm8{4-0};
5749 class BaseSIMDModifiedImmVector<bit Q, bit op, RegisterOperand vectype,
5750 Operand immtype, dag opt_shift_iop,
5751 string opt_shift, string asm, string kind,
5753 : BaseSIMDModifiedImm<Q, op, (outs vectype:$Rd),
5754 !con((ins immtype:$imm8), opt_shift_iop), asm,
5755 "{\t$Rd" # kind # ", $imm8" # opt_shift #
5756 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
5758 let DecoderMethod = "DecodeModImmInstruction";
5761 class BaseSIMDModifiedImmVectorTied<bit Q, bit op, RegisterOperand vectype,
5762 Operand immtype, dag opt_shift_iop,
5763 string opt_shift, string asm, string kind,
5765 : BaseSIMDModifiedImm<Q, op, (outs vectype:$dst),
5766 !con((ins vectype:$Rd, immtype:$imm8), opt_shift_iop),
5767 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
5768 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
5769 "$Rd = $dst", pattern> {
5770 let DecoderMethod = "DecodeModImmTiedInstruction";
5773 class BaseSIMDModifiedImmVectorShift<bit Q, bit op, bits<2> b15_b12,
5774 RegisterOperand vectype, string asm,
5775 string kind, list<dag> pattern>
5776 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
5777 (ins logical_vec_shift:$shift),
5778 "$shift", asm, kind, pattern> {
5780 let Inst{15} = b15_b12{1};
5781 let Inst{14-13} = shift;
5782 let Inst{12} = b15_b12{0};
5785 class BaseSIMDModifiedImmVectorShiftTied<bit Q, bit op, bits<2> b15_b12,
5786 RegisterOperand vectype, string asm,
5787 string kind, list<dag> pattern>
5788 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
5789 (ins logical_vec_shift:$shift),
5790 "$shift", asm, kind, pattern> {
5792 let Inst{15} = b15_b12{1};
5793 let Inst{14-13} = shift;
5794 let Inst{12} = b15_b12{0};
5798 class BaseSIMDModifiedImmVectorShiftHalf<bit Q, bit op, bits<2> b15_b12,
5799 RegisterOperand vectype, string asm,
5800 string kind, list<dag> pattern>
5801 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
5802 (ins logical_vec_hw_shift:$shift),
5803 "$shift", asm, kind, pattern> {
5805 let Inst{15} = b15_b12{1};
5807 let Inst{13} = shift{0};
5808 let Inst{12} = b15_b12{0};
5811 class BaseSIMDModifiedImmVectorShiftHalfTied<bit Q, bit op, bits<2> b15_b12,
5812 RegisterOperand vectype, string asm,
5813 string kind, list<dag> pattern>
5814 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
5815 (ins logical_vec_hw_shift:$shift),
5816 "$shift", asm, kind, pattern> {
5818 let Inst{15} = b15_b12{1};
5820 let Inst{13} = shift{0};
5821 let Inst{12} = b15_b12{0};
5824 multiclass SIMDModifiedImmVectorShift<bit op, bits<2> hw_cmode, bits<2> w_cmode,
5826 def v4i16 : BaseSIMDModifiedImmVectorShiftHalf<0, op, hw_cmode, V64,
5828 def v8i16 : BaseSIMDModifiedImmVectorShiftHalf<1, op, hw_cmode, V128,
5831 def v2i32 : BaseSIMDModifiedImmVectorShift<0, op, w_cmode, V64,
5833 def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128,
5837 multiclass SIMDModifiedImmVectorShiftTied<bit op, bits<2> hw_cmode,
5838 bits<2> w_cmode, string asm,
5840 def v4i16 : BaseSIMDModifiedImmVectorShiftHalfTied<0, op, hw_cmode, V64,
5842 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
5844 (i32 imm:$shift)))]>;
5845 def v8i16 : BaseSIMDModifiedImmVectorShiftHalfTied<1, op, hw_cmode, V128,
5847 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
5849 (i32 imm:$shift)))]>;
5851 def v2i32 : BaseSIMDModifiedImmVectorShiftTied<0, op, w_cmode, V64,
5853 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
5855 (i32 imm:$shift)))]>;
5856 def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128,
5858 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
5860 (i32 imm:$shift)))]>;
5863 class SIMDModifiedImmMoveMSL<bit Q, bit op, bits<4> cmode,
5864 RegisterOperand vectype, string asm,
5865 string kind, list<dag> pattern>
5866 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
5867 (ins move_vec_shift:$shift),
5868 "$shift", asm, kind, pattern> {
5870 let Inst{15-13} = cmode{3-1};
5871 let Inst{12} = shift;
5874 class SIMDModifiedImmVectorNoShift<bit Q, bit op, bits<4> cmode,
5875 RegisterOperand vectype,
5876 Operand imm_type, string asm,
5877 string kind, list<dag> pattern>
5878 : BaseSIMDModifiedImmVector<Q, op, vectype, imm_type, (ins), "",
5879 asm, kind, pattern> {
5880 let Inst{15-12} = cmode;
5883 class SIMDModifiedImmScalarNoShift<bit Q, bit op, bits<4> cmode, string asm,
5885 : BaseSIMDModifiedImm<Q, op, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
5886 "\t$Rd, $imm8", "", pattern> {
5887 let Inst{15-12} = cmode;
5888 let DecoderMethod = "DecodeModImmInstruction";
5891 //----------------------------------------------------------------------------
5892 // AdvSIMD indexed element
5893 //----------------------------------------------------------------------------
5895 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5896 class BaseSIMDIndexed<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
5897 RegisterOperand dst_reg, RegisterOperand lhs_reg,
5898 RegisterOperand rhs_reg, Operand vec_idx, string asm,
5899 string apple_kind, string dst_kind, string lhs_kind,
5900 string rhs_kind, list<dag> pattern>
5901 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
5903 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
5904 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
5913 let Inst{28} = Scalar;
5914 let Inst{27-24} = 0b1111;
5915 let Inst{23-22} = size;
5916 // Bit 21 must be set by the derived class.
5917 let Inst{20-16} = Rm;
5918 let Inst{15-12} = opc;
5919 // Bit 11 must be set by the derived class.
5925 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5926 class BaseSIMDIndexedTied<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
5927 RegisterOperand dst_reg, RegisterOperand lhs_reg,
5928 RegisterOperand rhs_reg, Operand vec_idx, string asm,
5929 string apple_kind, string dst_kind, string lhs_kind,
5930 string rhs_kind, list<dag> pattern>
5931 : I<(outs dst_reg:$dst),
5932 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
5933 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
5934 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
5943 let Inst{28} = Scalar;
5944 let Inst{27-24} = 0b1111;
5945 let Inst{23-22} = size;
5946 // Bit 21 must be set by the derived class.
5947 let Inst{20-16} = Rm;
5948 let Inst{15-12} = opc;
5949 // Bit 11 must be set by the derived class.
5955 multiclass SIMDFPIndexedSD<bit U, bits<4> opc, string asm,
5956 SDPatternOperator OpNode> {
5957 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
5960 asm, ".2s", ".2s", ".2s", ".s",
5961 [(set (v2f32 V64:$Rd),
5962 (OpNode (v2f32 V64:$Rn),
5963 (v2f32 (ARM64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
5965 let Inst{11} = idx{1};
5966 let Inst{21} = idx{0};
5969 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
5972 asm, ".4s", ".4s", ".4s", ".s",
5973 [(set (v4f32 V128:$Rd),
5974 (OpNode (v4f32 V128:$Rn),
5975 (v4f32 (ARM64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
5977 let Inst{11} = idx{1};
5978 let Inst{21} = idx{0};
5981 def v2i64_indexed : BaseSIMDIndexed<1, U, 0, 0b11, opc,
5984 asm, ".2d", ".2d", ".2d", ".d",
5985 [(set (v2f64 V128:$Rd),
5986 (OpNode (v2f64 V128:$Rn),
5987 (v2f64 (ARM64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))))]> {
5989 let Inst{11} = idx{0};
5993 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
5994 FPR32Op, FPR32Op, V128, VectorIndexS,
5995 asm, ".s", "", "", ".s",
5996 [(set (f32 FPR32Op:$Rd),
5997 (OpNode (f32 FPR32Op:$Rn),
5998 (f32 (vector_extract (v4f32 V128:$Rm),
5999 VectorIndexS:$idx))))]> {
6001 let Inst{11} = idx{1};
6002 let Inst{21} = idx{0};
6005 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b11, opc,
6006 FPR64Op, FPR64Op, V128, VectorIndexD,
6007 asm, ".d", "", "", ".d",
6008 [(set (f64 FPR64Op:$Rd),
6009 (OpNode (f64 FPR64Op:$Rn),
6010 (f64 (vector_extract (v2f64 V128:$Rm),
6011 VectorIndexD:$idx))))]> {
6013 let Inst{11} = idx{0};
6018 multiclass SIMDFPIndexedSDTiedPatterns<string INST, SDPatternOperator OpNode> {
6019 // 2 variants for the .2s version: DUPLANE from 128-bit and DUP scalar.
6020 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6021 (ARM64duplane32 (v4f32 V128:$Rm),
6022 VectorIndexS:$idx))),
6023 (!cast<Instruction>(INST # v2i32_indexed)
6024 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6025 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6026 (ARM64dup (f32 FPR32Op:$Rm)))),
6027 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6028 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6031 // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar.
6032 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6033 (ARM64duplane32 (v4f32 V128:$Rm),
6034 VectorIndexS:$idx))),
6035 (!cast<Instruction>(INST # "v4i32_indexed")
6036 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6037 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6038 (ARM64dup (f32 FPR32Op:$Rm)))),
6039 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6040 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6042 // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar.
6043 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6044 (ARM64duplane64 (v2f64 V128:$Rm),
6045 VectorIndexD:$idx))),
6046 (!cast<Instruction>(INST # "v2i64_indexed")
6047 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6048 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6049 (ARM64dup (f64 FPR64Op:$Rm)))),
6050 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6051 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
6053 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
6054 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6055 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))),
6056 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6057 V128:$Rm, VectorIndexS:$idx)>;
6058 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6059 (vector_extract (v2f32 V64:$Rm), VectorIndexS:$idx))),
6060 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6061 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
6063 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
6064 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
6065 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
6066 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
6067 V128:$Rm, VectorIndexD:$idx)>;
6070 multiclass SIMDFPIndexedSDTied<bit U, bits<4> opc, string asm> {
6071 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64,
6073 asm, ".2s", ".2s", ".2s", ".s", []> {
6075 let Inst{11} = idx{1};
6076 let Inst{21} = idx{0};
6079 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6082 asm, ".4s", ".4s", ".4s", ".s", []> {
6084 let Inst{11} = idx{1};
6085 let Inst{21} = idx{0};
6088 def v2i64_indexed : BaseSIMDIndexedTied<1, U, 0, 0b11, opc,
6091 asm, ".2d", ".2d", ".2d", ".d", []> {
6093 let Inst{11} = idx{0};
6098 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6099 FPR32Op, FPR32Op, V128, VectorIndexS,
6100 asm, ".s", "", "", ".s", []> {
6102 let Inst{11} = idx{1};
6103 let Inst{21} = idx{0};
6106 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b11, opc,
6107 FPR64Op, FPR64Op, V128, VectorIndexD,
6108 asm, ".d", "", "", ".d", []> {
6110 let Inst{11} = idx{0};
6115 multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
6116 SDPatternOperator OpNode> {
6117 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64,
6118 V128_lo, VectorIndexH,
6119 asm, ".4h", ".4h", ".4h", ".h",
6120 [(set (v4i16 V64:$Rd),
6121 (OpNode (v4i16 V64:$Rn),
6122 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6124 let Inst{11} = idx{2};
6125 let Inst{21} = idx{1};
6126 let Inst{20} = idx{0};
6129 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6131 V128_lo, VectorIndexH,
6132 asm, ".8h", ".8h", ".8h", ".h",
6133 [(set (v8i16 V128:$Rd),
6134 (OpNode (v8i16 V128:$Rn),
6135 (v8i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6137 let Inst{11} = idx{2};
6138 let Inst{21} = idx{1};
6139 let Inst{20} = idx{0};
6142 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6145 asm, ".2s", ".2s", ".2s", ".s",
6146 [(set (v2i32 V64:$Rd),
6147 (OpNode (v2i32 V64:$Rn),
6148 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6150 let Inst{11} = idx{1};
6151 let Inst{21} = idx{0};
6154 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6157 asm, ".4s", ".4s", ".4s", ".s",
6158 [(set (v4i32 V128:$Rd),
6159 (OpNode (v4i32 V128:$Rn),
6160 (v4i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6162 let Inst{11} = idx{1};
6163 let Inst{21} = idx{0};
6166 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6167 FPR16Op, FPR16Op, V128_lo, VectorIndexH,
6168 asm, ".h", "", "", ".h", []> {
6170 let Inst{11} = idx{2};
6171 let Inst{21} = idx{1};
6172 let Inst{20} = idx{0};
6175 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6176 FPR32Op, FPR32Op, V128, VectorIndexS,
6177 asm, ".s", "", "", ".s",
6178 [(set (i32 FPR32Op:$Rd),
6179 (OpNode FPR32Op:$Rn,
6180 (i32 (vector_extract (v4i32 V128:$Rm),
6181 VectorIndexS:$idx))))]> {
6183 let Inst{11} = idx{1};
6184 let Inst{21} = idx{0};
6188 multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
6189 SDPatternOperator OpNode> {
6190 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6192 V128_lo, VectorIndexH,
6193 asm, ".4h", ".4h", ".4h", ".h",
6194 [(set (v4i16 V64:$Rd),
6195 (OpNode (v4i16 V64:$Rn),
6196 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6198 let Inst{11} = idx{2};
6199 let Inst{21} = idx{1};
6200 let Inst{20} = idx{0};
6203 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6205 V128_lo, VectorIndexH,
6206 asm, ".8h", ".8h", ".8h", ".h",
6207 [(set (v8i16 V128:$Rd),
6208 (OpNode (v8i16 V128:$Rn),
6209 (v8i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6211 let Inst{11} = idx{2};
6212 let Inst{21} = idx{1};
6213 let Inst{20} = idx{0};
6216 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6219 asm, ".2s", ".2s", ".2s", ".s",
6220 [(set (v2i32 V64:$Rd),
6221 (OpNode (v2i32 V64:$Rn),
6222 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6224 let Inst{11} = idx{1};
6225 let Inst{21} = idx{0};
6228 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6231 asm, ".4s", ".4s", ".4s", ".s",
6232 [(set (v4i32 V128:$Rd),
6233 (OpNode (v4i32 V128:$Rn),
6234 (v4i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6236 let Inst{11} = idx{1};
6237 let Inst{21} = idx{0};
6241 multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
6242 SDPatternOperator OpNode> {
6243 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64,
6244 V128_lo, VectorIndexH,
6245 asm, ".4h", ".4h", ".4h", ".h",
6246 [(set (v4i16 V64:$dst),
6247 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
6248 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6250 let Inst{11} = idx{2};
6251 let Inst{21} = idx{1};
6252 let Inst{20} = idx{0};
6255 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6257 V128_lo, VectorIndexH,
6258 asm, ".8h", ".8h", ".8h", ".h",
6259 [(set (v8i16 V128:$dst),
6260 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
6261 (v8i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6263 let Inst{11} = idx{2};
6264 let Inst{21} = idx{1};
6265 let Inst{20} = idx{0};
6268 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6271 asm, ".2s", ".2s", ".2s", ".s",
6272 [(set (v2i32 V64:$dst),
6273 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
6274 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6276 let Inst{11} = idx{1};
6277 let Inst{21} = idx{0};
6280 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6283 asm, ".4s", ".4s", ".4s", ".s",
6284 [(set (v4i32 V128:$dst),
6285 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
6286 (v4i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6288 let Inst{11} = idx{1};
6289 let Inst{21} = idx{0};
6293 multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
6294 SDPatternOperator OpNode> {
6295 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6297 V128_lo, VectorIndexH,
6298 asm, ".4s", ".4s", ".4h", ".h",
6299 [(set (v4i32 V128:$Rd),
6300 (OpNode (v4i16 V64:$Rn),
6301 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6303 let Inst{11} = idx{2};
6304 let Inst{21} = idx{1};
6305 let Inst{20} = idx{0};
6308 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6310 V128_lo, VectorIndexH,
6311 asm#"2", ".4s", ".4s", ".8h", ".h",
6312 [(set (v4i32 V128:$Rd),
6313 (OpNode (extract_high_v8i16 V128:$Rn),
6314 (extract_high_v8i16 (ARM64duplane16 (v8i16 V128_lo:$Rm),
6315 VectorIndexH:$idx))))]> {
6318 let Inst{11} = idx{2};
6319 let Inst{21} = idx{1};
6320 let Inst{20} = idx{0};
6323 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6326 asm, ".2d", ".2d", ".2s", ".s",
6327 [(set (v2i64 V128:$Rd),
6328 (OpNode (v2i32 V64:$Rn),
6329 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6331 let Inst{11} = idx{1};
6332 let Inst{21} = idx{0};
6335 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6338 asm#"2", ".2d", ".2d", ".4s", ".s",
6339 [(set (v2i64 V128:$Rd),
6340 (OpNode (extract_high_v4i32 V128:$Rn),
6341 (extract_high_v4i32 (ARM64duplane32 (v4i32 V128:$Rm),
6342 VectorIndexS:$idx))))]> {
6344 let Inst{11} = idx{1};
6345 let Inst{21} = idx{0};
6348 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6349 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6350 asm, ".h", "", "", ".h", []> {
6352 let Inst{11} = idx{2};
6353 let Inst{21} = idx{1};
6354 let Inst{20} = idx{0};
6357 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6358 FPR64Op, FPR32Op, V128, VectorIndexS,
6359 asm, ".s", "", "", ".s", []> {
6361 let Inst{11} = idx{1};
6362 let Inst{21} = idx{0};
6366 multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
6367 SDPatternOperator Accum> {
6368 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6370 V128_lo, VectorIndexH,
6371 asm, ".4s", ".4s", ".4h", ".h",
6372 [(set (v4i32 V128:$dst),
6373 (Accum (v4i32 V128:$Rd),
6374 (v4i32 (int_arm64_neon_sqdmull
6376 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm),
6377 VectorIndexH:$idx))))))]> {
6379 let Inst{11} = idx{2};
6380 let Inst{21} = idx{1};
6381 let Inst{20} = idx{0};
6384 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
6385 // intermediate EXTRACT_SUBREG would be untyped.
6386 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
6387 (i32 (vector_extract (v4i32
6388 (int_arm64_neon_sqdmull (v4i16 V64:$Rn),
6389 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm),
6390 VectorIndexH:$idx)))),
6393 (!cast<Instruction>(NAME # v4i16_indexed)
6394 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
6395 V128_lo:$Rm, VectorIndexH:$idx),
6398 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6400 V128_lo, VectorIndexH,
6401 asm#"2", ".4s", ".4s", ".8h", ".h",
6402 [(set (v4i32 V128:$dst),
6403 (Accum (v4i32 V128:$Rd),
6404 (v4i32 (int_arm64_neon_sqdmull
6405 (extract_high_v8i16 V128:$Rn),
6407 (ARM64duplane16 (v8i16 V128_lo:$Rm),
6408 VectorIndexH:$idx))))))]> {
6410 let Inst{11} = idx{2};
6411 let Inst{21} = idx{1};
6412 let Inst{20} = idx{0};
6415 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6418 asm, ".2d", ".2d", ".2s", ".s",
6419 [(set (v2i64 V128:$dst),
6420 (Accum (v2i64 V128:$Rd),
6421 (v2i64 (int_arm64_neon_sqdmull
6423 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm),
6424 VectorIndexS:$idx))))))]> {
6426 let Inst{11} = idx{1};
6427 let Inst{21} = idx{0};
6430 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6433 asm#"2", ".2d", ".2d", ".4s", ".s",
6434 [(set (v2i64 V128:$dst),
6435 (Accum (v2i64 V128:$Rd),
6436 (v2i64 (int_arm64_neon_sqdmull
6437 (extract_high_v4i32 V128:$Rn),
6439 (ARM64duplane32 (v4i32 V128:$Rm),
6440 VectorIndexS:$idx))))))]> {
6442 let Inst{11} = idx{1};
6443 let Inst{21} = idx{0};
6446 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
6447 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6448 asm, ".h", "", "", ".h", []> {
6450 let Inst{11} = idx{2};
6451 let Inst{21} = idx{1};
6452 let Inst{20} = idx{0};
6456 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6457 FPR64Op, FPR32Op, V128, VectorIndexS,
6458 asm, ".s", "", "", ".s",
6459 [(set (i64 FPR64Op:$dst),
6460 (Accum (i64 FPR64Op:$Rd),
6461 (i64 (int_arm64_neon_sqdmulls_scalar
6463 (i32 (vector_extract (v4i32 V128:$Rm),
6464 VectorIndexS:$idx))))))]> {
6467 let Inst{11} = idx{1};
6468 let Inst{21} = idx{0};
6472 multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
6473 SDPatternOperator OpNode> {
6474 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6475 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6477 V128_lo, VectorIndexH,
6478 asm, ".4s", ".4s", ".4h", ".h",
6479 [(set (v4i32 V128:$Rd),
6480 (OpNode (v4i16 V64:$Rn),
6481 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6483 let Inst{11} = idx{2};
6484 let Inst{21} = idx{1};
6485 let Inst{20} = idx{0};
6488 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6490 V128_lo, VectorIndexH,
6491 asm#"2", ".4s", ".4s", ".8h", ".h",
6492 [(set (v4i32 V128:$Rd),
6493 (OpNode (extract_high_v8i16 V128:$Rn),
6494 (extract_high_v8i16 (ARM64duplane16 (v8i16 V128_lo:$Rm),
6495 VectorIndexH:$idx))))]> {
6498 let Inst{11} = idx{2};
6499 let Inst{21} = idx{1};
6500 let Inst{20} = idx{0};
6503 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6506 asm, ".2d", ".2d", ".2s", ".s",
6507 [(set (v2i64 V128:$Rd),
6508 (OpNode (v2i32 V64:$Rn),
6509 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6511 let Inst{11} = idx{1};
6512 let Inst{21} = idx{0};
6515 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6518 asm#"2", ".2d", ".2d", ".4s", ".s",
6519 [(set (v2i64 V128:$Rd),
6520 (OpNode (extract_high_v4i32 V128:$Rn),
6521 (extract_high_v4i32 (ARM64duplane32 (v4i32 V128:$Rm),
6522 VectorIndexS:$idx))))]> {
6524 let Inst{11} = idx{1};
6525 let Inst{21} = idx{0};
6530 multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
6531 SDPatternOperator OpNode> {
6532 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6533 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6535 V128_lo, VectorIndexH,
6536 asm, ".4s", ".4s", ".4h", ".h",
6537 [(set (v4i32 V128:$dst),
6538 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
6539 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6541 let Inst{11} = idx{2};
6542 let Inst{21} = idx{1};
6543 let Inst{20} = idx{0};
6546 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6548 V128_lo, VectorIndexH,
6549 asm#"2", ".4s", ".4s", ".8h", ".h",
6550 [(set (v4i32 V128:$dst),
6551 (OpNode (v4i32 V128:$Rd),
6552 (extract_high_v8i16 V128:$Rn),
6553 (extract_high_v8i16 (ARM64duplane16 (v8i16 V128_lo:$Rm),
6554 VectorIndexH:$idx))))]> {
6556 let Inst{11} = idx{2};
6557 let Inst{21} = idx{1};
6558 let Inst{20} = idx{0};
6561 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6564 asm, ".2d", ".2d", ".2s", ".s",
6565 [(set (v2i64 V128:$dst),
6566 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
6567 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6569 let Inst{11} = idx{1};
6570 let Inst{21} = idx{0};
6573 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6576 asm#"2", ".2d", ".2d", ".4s", ".s",
6577 [(set (v2i64 V128:$dst),
6578 (OpNode (v2i64 V128:$Rd),
6579 (extract_high_v4i32 V128:$Rn),
6580 (extract_high_v4i32 (ARM64duplane32 (v4i32 V128:$Rm),
6581 VectorIndexS:$idx))))]> {
6583 let Inst{11} = idx{1};
6584 let Inst{21} = idx{0};
6589 //----------------------------------------------------------------------------
6590 // AdvSIMD scalar shift by immediate
6591 //----------------------------------------------------------------------------
6593 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6594 class BaseSIMDScalarShift<bit U, bits<5> opc, bits<7> fixed_imm,
6595 RegisterClass regtype1, RegisterClass regtype2,
6596 Operand immtype, string asm, list<dag> pattern>
6597 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
6598 asm, "\t$Rd, $Rn, $imm", "", pattern>,
6603 let Inst{31-30} = 0b01;
6605 let Inst{28-23} = 0b111110;
6606 let Inst{22-16} = fixed_imm;
6607 let Inst{15-11} = opc;
6613 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6614 class BaseSIMDScalarShiftTied<bit U, bits<5> opc, bits<7> fixed_imm,
6615 RegisterClass regtype1, RegisterClass regtype2,
6616 Operand immtype, string asm, list<dag> pattern>
6617 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
6618 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
6623 let Inst{31-30} = 0b01;
6625 let Inst{28-23} = 0b111110;
6626 let Inst{22-16} = fixed_imm;
6627 let Inst{15-11} = opc;
6634 multiclass SIMDScalarRShiftSD<bit U, bits<5> opc, string asm> {
6635 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
6636 FPR32, FPR32, vecshiftR32, asm, []> {
6637 let Inst{20-16} = imm{4-0};
6640 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
6641 FPR64, FPR64, vecshiftR64, asm, []> {
6642 let Inst{21-16} = imm{5-0};
6646 multiclass SIMDScalarRShiftD<bit U, bits<5> opc, string asm,
6647 SDPatternOperator OpNode> {
6648 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
6649 FPR64, FPR64, vecshiftR64, asm,
6650 [(set (v1i64 FPR64:$Rd),
6651 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
6652 let Inst{21-16} = imm{5-0};
6656 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6657 multiclass SIMDScalarRShiftDTied<bit U, bits<5> opc, string asm,
6658 SDPatternOperator OpNode = null_frag> {
6659 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
6660 FPR64, FPR64, vecshiftR64, asm,
6661 [(set (v1i64 FPR64:$dst),
6662 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
6663 (i32 vecshiftR64:$imm)))]> {
6664 let Inst{21-16} = imm{5-0};
6668 multiclass SIMDScalarLShiftD<bit U, bits<5> opc, string asm,
6669 SDPatternOperator OpNode> {
6670 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
6671 FPR64, FPR64, vecshiftL64, asm,
6672 [(set (v1i64 FPR64:$Rd),
6673 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
6674 let Inst{21-16} = imm{5-0};
6678 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6679 multiclass SIMDScalarLShiftDTied<bit U, bits<5> opc, string asm> {
6680 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
6681 FPR64, FPR64, vecshiftL64, asm, []> {
6682 let Inst{21-16} = imm{5-0};
6686 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6687 multiclass SIMDScalarRShiftBHS<bit U, bits<5> opc, string asm,
6688 SDPatternOperator OpNode = null_frag> {
6689 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
6690 FPR8, FPR16, vecshiftR8, asm, []> {
6691 let Inst{18-16} = imm{2-0};
6694 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
6695 FPR16, FPR32, vecshiftR16, asm, []> {
6696 let Inst{19-16} = imm{3-0};
6699 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
6700 FPR32, FPR64, vecshiftR32, asm,
6701 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
6702 let Inst{20-16} = imm{4-0};
6706 multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm,
6707 SDPatternOperator OpNode> {
6708 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
6709 FPR8, FPR8, vecshiftL8, asm, []> {
6710 let Inst{18-16} = imm{2-0};
6713 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
6714 FPR16, FPR16, vecshiftL16, asm, []> {
6715 let Inst{19-16} = imm{3-0};
6718 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
6719 FPR32, FPR32, vecshiftL32, asm,
6720 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
6721 let Inst{20-16} = imm{4-0};
6724 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
6725 FPR64, FPR64, vecshiftL64, asm,
6726 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn),
6727 (i32 vecshiftL64:$imm)))]> {
6728 let Inst{21-16} = imm{5-0};
6732 multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {
6733 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
6734 FPR8, FPR8, vecshiftR8, asm, []> {
6735 let Inst{18-16} = imm{2-0};
6738 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
6739 FPR16, FPR16, vecshiftR16, asm, []> {
6740 let Inst{19-16} = imm{3-0};
6743 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
6744 FPR32, FPR32, vecshiftR32, asm, []> {
6745 let Inst{20-16} = imm{4-0};
6748 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
6749 FPR64, FPR64, vecshiftR64, asm, []> {
6750 let Inst{21-16} = imm{5-0};
6754 //----------------------------------------------------------------------------
6755 // AdvSIMD vector x indexed element
6756 //----------------------------------------------------------------------------
6758 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6759 class BaseSIMDVectorShift<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
6760 RegisterOperand dst_reg, RegisterOperand src_reg,
6762 string asm, string dst_kind, string src_kind,
6764 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
6765 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
6766 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
6773 let Inst{28-23} = 0b011110;
6774 let Inst{22-16} = fixed_imm;
6775 let Inst{15-11} = opc;
6781 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6782 class BaseSIMDVectorShiftTied<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
6783 RegisterOperand vectype1, RegisterOperand vectype2,
6785 string asm, string dst_kind, string src_kind,
6787 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
6788 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
6789 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
6796 let Inst{28-23} = 0b011110;
6797 let Inst{22-16} = fixed_imm;
6798 let Inst{15-11} = opc;
6804 multiclass SIMDVectorRShiftSD<bit U, bits<5> opc, string asm,
6806 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
6807 V64, V64, vecshiftR32,
6809 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
6811 let Inst{20-16} = imm;
6814 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
6815 V128, V128, vecshiftR32,
6817 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
6819 let Inst{20-16} = imm;
6822 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
6823 V128, V128, vecshiftR64,
6825 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
6827 let Inst{21-16} = imm;
6831 multiclass SIMDVectorRShiftSDToFP<bit U, bits<5> opc, string asm,
6833 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
6834 V64, V64, vecshiftR32,
6836 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
6838 let Inst{20-16} = imm;
6841 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
6842 V128, V128, vecshiftR32,
6844 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
6846 let Inst{20-16} = imm;
6849 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
6850 V128, V128, vecshiftR64,
6852 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
6854 let Inst{21-16} = imm;
6858 multiclass SIMDVectorRShiftNarrowBHS<bit U, bits<5> opc, string asm,
6859 SDPatternOperator OpNode> {
6860 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
6861 V64, V128, vecshiftR16Narrow,
6863 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
6865 let Inst{18-16} = imm;
6868 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
6869 V128, V128, vecshiftR16Narrow,
6870 asm#"2", ".16b", ".8h", []> {
6872 let Inst{18-16} = imm;
6873 let hasSideEffects = 0;
6876 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
6877 V64, V128, vecshiftR32Narrow,
6879 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
6881 let Inst{19-16} = imm;
6884 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
6885 V128, V128, vecshiftR32Narrow,
6886 asm#"2", ".8h", ".4s", []> {
6888 let Inst{19-16} = imm;
6889 let hasSideEffects = 0;
6892 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
6893 V64, V128, vecshiftR64Narrow,
6895 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
6897 let Inst{20-16} = imm;
6900 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
6901 V128, V128, vecshiftR64Narrow,
6902 asm#"2", ".4s", ".2d", []> {
6904 let Inst{20-16} = imm;
6905 let hasSideEffects = 0;
6908 // TableGen doesn't like patters w/ INSERT_SUBREG on the instructions
6909 // themselves, so put them here instead.
6911 // Patterns involving what's effectively an insert high and a normal
6912 // intrinsic, represented by CONCAT_VECTORS.
6913 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
6914 vecshiftR16Narrow:$imm)),
6915 (!cast<Instruction>(NAME # "v16i8_shift")
6916 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
6917 V128:$Rn, vecshiftR16Narrow:$imm)>;
6918 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
6919 vecshiftR32Narrow:$imm)),
6920 (!cast<Instruction>(NAME # "v8i16_shift")
6921 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
6922 V128:$Rn, vecshiftR32Narrow:$imm)>;
6923 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
6924 vecshiftR64Narrow:$imm)),
6925 (!cast<Instruction>(NAME # "v4i32_shift")
6926 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
6927 V128:$Rn, vecshiftR64Narrow:$imm)>;
6930 multiclass SIMDVectorLShiftBHSD<bit U, bits<5> opc, string asm,
6931 SDPatternOperator OpNode> {
6932 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
6933 V64, V64, vecshiftL8,
6935 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
6936 (i32 vecshiftL8:$imm)))]> {
6938 let Inst{18-16} = imm;
6941 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
6942 V128, V128, vecshiftL8,
6943 asm, ".16b", ".16b",
6944 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
6945 (i32 vecshiftL8:$imm)))]> {
6947 let Inst{18-16} = imm;
6950 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
6951 V64, V64, vecshiftL16,
6953 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
6954 (i32 vecshiftL16:$imm)))]> {
6956 let Inst{19-16} = imm;
6959 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
6960 V128, V128, vecshiftL16,
6962 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
6963 (i32 vecshiftL16:$imm)))]> {
6965 let Inst{19-16} = imm;
6968 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
6969 V64, V64, vecshiftL32,
6971 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
6972 (i32 vecshiftL32:$imm)))]> {
6974 let Inst{20-16} = imm;
6977 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
6978 V128, V128, vecshiftL32,
6980 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
6981 (i32 vecshiftL32:$imm)))]> {
6983 let Inst{20-16} = imm;
6986 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
6987 V128, V128, vecshiftL64,
6989 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
6990 (i32 vecshiftL64:$imm)))]> {
6992 let Inst{21-16} = imm;
6996 multiclass SIMDVectorRShiftBHSD<bit U, bits<5> opc, string asm,
6997 SDPatternOperator OpNode> {
6998 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
6999 V64, V64, vecshiftR8,
7001 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7002 (i32 vecshiftR8:$imm)))]> {
7004 let Inst{18-16} = imm;
7007 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7008 V128, V128, vecshiftR8,
7009 asm, ".16b", ".16b",
7010 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7011 (i32 vecshiftR8:$imm)))]> {
7013 let Inst{18-16} = imm;
7016 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7017 V64, V64, vecshiftR16,
7019 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7020 (i32 vecshiftR16:$imm)))]> {
7022 let Inst{19-16} = imm;
7025 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7026 V128, V128, vecshiftR16,
7028 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7029 (i32 vecshiftR16:$imm)))]> {
7031 let Inst{19-16} = imm;
7034 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7035 V64, V64, vecshiftR32,
7037 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7038 (i32 vecshiftR32:$imm)))]> {
7040 let Inst{20-16} = imm;
7043 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7044 V128, V128, vecshiftR32,
7046 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7047 (i32 vecshiftR32:$imm)))]> {
7049 let Inst{20-16} = imm;
7052 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7053 V128, V128, vecshiftR64,
7055 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7056 (i32 vecshiftR64:$imm)))]> {
7058 let Inst{21-16} = imm;
7062 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
7063 multiclass SIMDVectorRShiftBHSDTied<bit U, bits<5> opc, string asm,
7064 SDPatternOperator OpNode = null_frag> {
7065 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7066 V64, V64, vecshiftR8, asm, ".8b", ".8b",
7067 [(set (v8i8 V64:$dst),
7068 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7069 (i32 vecshiftR8:$imm)))]> {
7071 let Inst{18-16} = imm;
7074 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7075 V128, V128, vecshiftR8, asm, ".16b", ".16b",
7076 [(set (v16i8 V128:$dst),
7077 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7078 (i32 vecshiftR8:$imm)))]> {
7080 let Inst{18-16} = imm;
7083 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7084 V64, V64, vecshiftR16, asm, ".4h", ".4h",
7085 [(set (v4i16 V64:$dst),
7086 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7087 (i32 vecshiftR16:$imm)))]> {
7089 let Inst{19-16} = imm;
7092 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7093 V128, V128, vecshiftR16, asm, ".8h", ".8h",
7094 [(set (v8i16 V128:$dst),
7095 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7096 (i32 vecshiftR16:$imm)))]> {
7098 let Inst{19-16} = imm;
7101 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7102 V64, V64, vecshiftR32, asm, ".2s", ".2s",
7103 [(set (v2i32 V64:$dst),
7104 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7105 (i32 vecshiftR32:$imm)))]> {
7107 let Inst{20-16} = imm;
7110 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7111 V128, V128, vecshiftR32, asm, ".4s", ".4s",
7112 [(set (v4i32 V128:$dst),
7113 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7114 (i32 vecshiftR32:$imm)))]> {
7116 let Inst{20-16} = imm;
7119 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7120 V128, V128, vecshiftR64,
7121 asm, ".2d", ".2d", [(set (v2i64 V128:$dst),
7122 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7123 (i32 vecshiftR64:$imm)))]> {
7125 let Inst{21-16} = imm;
7129 multiclass SIMDVectorLShiftBHSDTied<bit U, bits<5> opc, string asm,
7130 SDPatternOperator OpNode = null_frag> {
7131 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7132 V64, V64, vecshiftL8,
7134 [(set (v8i8 V64:$dst),
7135 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7136 (i32 vecshiftL8:$imm)))]> {
7138 let Inst{18-16} = imm;
7141 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7142 V128, V128, vecshiftL8,
7143 asm, ".16b", ".16b",
7144 [(set (v16i8 V128:$dst),
7145 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7146 (i32 vecshiftL8:$imm)))]> {
7148 let Inst{18-16} = imm;
7151 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7152 V64, V64, vecshiftL16,
7154 [(set (v4i16 V64:$dst),
7155 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7156 (i32 vecshiftL16:$imm)))]> {
7158 let Inst{19-16} = imm;
7161 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7162 V128, V128, vecshiftL16,
7164 [(set (v8i16 V128:$dst),
7165 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7166 (i32 vecshiftL16:$imm)))]> {
7168 let Inst{19-16} = imm;
7171 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7172 V64, V64, vecshiftL32,
7174 [(set (v2i32 V64:$dst),
7175 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7176 (i32 vecshiftL32:$imm)))]> {
7178 let Inst{20-16} = imm;
7181 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7182 V128, V128, vecshiftL32,
7184 [(set (v4i32 V128:$dst),
7185 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7186 (i32 vecshiftL32:$imm)))]> {
7188 let Inst{20-16} = imm;
7191 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7192 V128, V128, vecshiftL64,
7194 [(set (v2i64 V128:$dst),
7195 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7196 (i32 vecshiftL64:$imm)))]> {
7198 let Inst{21-16} = imm;
7202 multiclass SIMDVectorLShiftLongBHSD<bit U, bits<5> opc, string asm,
7203 SDPatternOperator OpNode> {
7204 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7205 V128, V64, vecshiftL8, asm, ".8h", ".8b",
7206 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
7208 let Inst{18-16} = imm;
7211 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7212 V128, V128, vecshiftL8,
7213 asm#"2", ".8h", ".16b",
7214 [(set (v8i16 V128:$Rd),
7215 (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> {
7217 let Inst{18-16} = imm;
7220 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7221 V128, V64, vecshiftL16, asm, ".4s", ".4h",
7222 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
7224 let Inst{19-16} = imm;
7227 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7228 V128, V128, vecshiftL16,
7229 asm#"2", ".4s", ".8h",
7230 [(set (v4i32 V128:$Rd),
7231 (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> {
7234 let Inst{19-16} = imm;
7237 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7238 V128, V64, vecshiftL32, asm, ".2d", ".2s",
7239 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
7241 let Inst{20-16} = imm;
7244 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7245 V128, V128, vecshiftL32,
7246 asm#"2", ".2d", ".4s",
7247 [(set (v2i64 V128:$Rd),
7248 (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> {
7250 let Inst{20-16} = imm;
7256 // Vector load/store
7258 // SIMD ldX/stX no-index memory references don't allow the optional
7259 // ", #0" constant and handle post-indexing explicitly, so we use
7260 // a more specialized parse method for them. Otherwise, it's the same as
7261 // the general am_noindex handling.
7262 def MemorySIMDNoIndexOperand : AsmOperandClass {
7263 let Name = "MemorySIMDNoIndex";
7264 let ParserMethod = "tryParseNoIndexMemory";
7266 def am_simdnoindex : Operand<i64>,
7267 ComplexPattern<i64, 1, "SelectAddrModeNoIndex", []> {
7268 let PrintMethod = "printAMNoIndex";
7269 let ParserMatchClass = MemorySIMDNoIndexOperand;
7270 let MIOperandInfo = (ops GPR64sp:$base);
7271 let DecoderMethod = "DecodeGPR64spRegisterClass";
7274 class BaseSIMDLdSt<bit Q, bit L, bits<4> opcode, bits<2> size,
7275 string asm, dag oops, dag iops, list<dag> pattern>
7276 : I<oops, iops, asm, "\t$Vt, $vaddr", "", pattern> {
7281 let Inst{29-23} = 0b0011000;
7283 let Inst{21-16} = 0b000000;
7284 let Inst{15-12} = opcode;
7285 let Inst{11-10} = size;
7286 let Inst{9-5} = vaddr;
7290 class BaseSIMDLdStPost<bit Q, bit L, bits<4> opcode, bits<2> size,
7291 string asm, dag oops, dag iops>
7292 : I<oops, iops, asm, "\t$Vt, $vaddr, $Xm", "", []> {
7298 let Inst{29-23} = 0b0011001;
7301 let Inst{20-16} = Xm;
7302 let Inst{15-12} = opcode;
7303 let Inst{11-10} = size;
7304 let Inst{9-5} = vaddr;
7306 let DecoderMethod = "DecodeSIMDLdStPost";
7309 // The immediate form of AdvSIMD post-indexed addressing is encoded with
7310 // register post-index addressing from the zero register.
7311 multiclass SIMDLdStAliases<string asm, string layout, string Count,
7312 int Offset, int Size> {
7313 // E.g. "ld1 { v0.8b, v1.8b }, [x1], #16"
7314 // "ld1\t$Vt, $vaddr, #16"
7315 // may get mapped to
7316 // (LD1Twov8b_POST VecListTwo8b:$Vt, am_simdnoindex:$vaddr, XZR)
7317 def : InstAlias<asm # "\t$Vt, $vaddr, #" # Offset,
7318 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7319 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
7320 am_simdnoindex:$vaddr, XZR), 1>;
7322 // E.g. "ld1.8b { v0, v1 }, [x1], #16"
7323 // "ld1.8b\t$Vt, $vaddr, #16"
7324 // may get mapped to
7325 // (LD1Twov8b_POST VecListTwo64:$Vt, am_simdnoindex:$vaddr, XZR)
7326 def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr, #" # Offset,
7327 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7328 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7329 am_simdnoindex:$vaddr, XZR), 0>;
7331 // E.g. "ld1.8b { v0, v1 }, [x1]"
7332 // "ld1\t$Vt, $vaddr"
7333 // may get mapped to
7334 // (LD1Twov8b VecListTwo64:$Vt, am_simdnoindex:$vaddr)
7335 def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr",
7336 (!cast<Instruction>(NAME # Count # "v" # layout)
7337 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7338 am_simdnoindex:$vaddr), 0>;
7340 // E.g. "ld1.8b { v0, v1 }, [x1], x2"
7341 // "ld1\t$Vt, $vaddr, $Xm"
7342 // may get mapped to
7343 // (LD1Twov8b_POST VecListTwo64:$Vt, am_simdnoindex:$vaddr, GPR64pi8:$Xm)
7344 def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr, $Xm",
7345 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7346 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7347 am_simdnoindex:$vaddr,
7348 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
7351 multiclass BaseSIMDLdN<string Count, string asm, string veclist, int Offset128,
7352 int Offset64, bits<4> opcode> {
7353 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7354 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
7355 (outs !cast<RegisterOperand>(veclist # "16b"):$Vt),
7356 (ins am_simdnoindex:$vaddr), []>;
7357 def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm,
7358 (outs !cast<RegisterOperand>(veclist # "8h"):$Vt),
7359 (ins am_simdnoindex:$vaddr), []>;
7360 def v4s : BaseSIMDLdSt<1, 1, opcode, 0b10, asm,
7361 (outs !cast<RegisterOperand>(veclist # "4s"):$Vt),
7362 (ins am_simdnoindex:$vaddr), []>;
7363 def v2d : BaseSIMDLdSt<1, 1, opcode, 0b11, asm,
7364 (outs !cast<RegisterOperand>(veclist # "2d"):$Vt),
7365 (ins am_simdnoindex:$vaddr), []>;
7366 def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm,
7367 (outs !cast<RegisterOperand>(veclist # "8b"):$Vt),
7368 (ins am_simdnoindex:$vaddr), []>;
7369 def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm,
7370 (outs !cast<RegisterOperand>(veclist # "4h"):$Vt),
7371 (ins am_simdnoindex:$vaddr), []>;
7372 def v2s : BaseSIMDLdSt<0, 1, opcode, 0b10, asm,
7373 (outs !cast<RegisterOperand>(veclist # "2s"):$Vt),
7374 (ins am_simdnoindex:$vaddr), []>;
7377 def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
7378 (outs !cast<RegisterOperand>(veclist # "16b"):$Vt),
7379 (ins am_simdnoindex:$vaddr,
7380 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7381 def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
7382 (outs !cast<RegisterOperand>(veclist # "8h"):$Vt),
7383 (ins am_simdnoindex:$vaddr,
7384 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7385 def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm,
7386 (outs !cast<RegisterOperand>(veclist # "4s"):$Vt),
7387 (ins am_simdnoindex:$vaddr,
7388 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7389 def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm,
7390 (outs !cast<RegisterOperand>(veclist # "2d"):$Vt),
7391 (ins am_simdnoindex:$vaddr,
7392 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7393 def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
7394 (outs !cast<RegisterOperand>(veclist # "8b"):$Vt),
7395 (ins am_simdnoindex:$vaddr,
7396 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7397 def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
7398 (outs !cast<RegisterOperand>(veclist # "4h"):$Vt),
7399 (ins am_simdnoindex:$vaddr,
7400 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7401 def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm,
7402 (outs !cast<RegisterOperand>(veclist # "2s"):$Vt),
7403 (ins am_simdnoindex:$vaddr,
7404 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7407 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7408 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7409 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7410 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7411 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7412 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7413 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7416 // Only ld1/st1 has a v1d version.
7417 multiclass BaseSIMDStN<string Count, string asm, string veclist, int Offset128,
7418 int Offset64, bits<4> opcode> {
7419 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in {
7420 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
7421 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7422 am_simdnoindex:$vaddr), []>;
7423 def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs),
7424 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7425 am_simdnoindex:$vaddr), []>;
7426 def v4s : BaseSIMDLdSt<1, 0, opcode, 0b10, asm, (outs),
7427 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7428 am_simdnoindex:$vaddr), []>;
7429 def v2d : BaseSIMDLdSt<1, 0, opcode, 0b11, asm, (outs),
7430 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7431 am_simdnoindex:$vaddr), []>;
7432 def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs),
7433 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7434 am_simdnoindex:$vaddr), []>;
7435 def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs),
7436 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7437 am_simdnoindex:$vaddr), []>;
7438 def v2s : BaseSIMDLdSt<0, 0, opcode, 0b10, asm, (outs),
7439 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7440 am_simdnoindex:$vaddr), []>;
7442 def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm, (outs),
7443 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7444 am_simdnoindex:$vaddr,
7445 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7446 def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm, (outs),
7447 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7448 am_simdnoindex:$vaddr,
7449 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7450 def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm, (outs),
7451 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7452 am_simdnoindex:$vaddr,
7453 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7454 def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm, (outs),
7455 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7456 am_simdnoindex:$vaddr,
7457 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7458 def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm, (outs),
7459 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7460 am_simdnoindex:$vaddr,
7461 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7462 def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm, (outs),
7463 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7464 am_simdnoindex:$vaddr,
7465 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7466 def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm, (outs),
7467 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7468 am_simdnoindex:$vaddr,
7469 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7472 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7473 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7474 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7475 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7476 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7477 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7478 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7481 multiclass BaseSIMDLd1<string Count, string asm, string veclist,
7482 int Offset128, int Offset64, bits<4> opcode>
7483 : BaseSIMDLdN<Count, asm, veclist, Offset128, Offset64, opcode> {
7485 // LD1 instructions have extra "1d" variants.
7486 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7487 def v1d : BaseSIMDLdSt<0, 1, opcode, 0b11, asm,
7488 (outs !cast<RegisterOperand>(veclist # "1d"):$Vt),
7489 (ins am_simdnoindex:$vaddr), []>;
7491 def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm,
7492 (outs !cast<RegisterOperand>(veclist # "1d"):$Vt),
7493 (ins am_simdnoindex:$vaddr,
7494 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7497 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7500 multiclass BaseSIMDSt1<string Count, string asm, string veclist,
7501 int Offset128, int Offset64, bits<4> opcode>
7502 : BaseSIMDStN<Count, asm, veclist, Offset128, Offset64, opcode> {
7504 // ST1 instructions have extra "1d" variants.
7505 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
7506 def v1d : BaseSIMDLdSt<0, 0, opcode, 0b11, asm, (outs),
7507 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7508 am_simdnoindex:$vaddr), []>;
7510 def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm, (outs),
7511 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7512 am_simdnoindex:$vaddr,
7513 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7516 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7519 multiclass SIMDLd1Multiple<string asm> {
7520 defm One : BaseSIMDLd1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7521 defm Two : BaseSIMDLd1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7522 defm Three : BaseSIMDLd1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7523 defm Four : BaseSIMDLd1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7526 multiclass SIMDSt1Multiple<string asm> {
7527 defm One : BaseSIMDSt1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7528 defm Two : BaseSIMDSt1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7529 defm Three : BaseSIMDSt1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7530 defm Four : BaseSIMDSt1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7533 multiclass SIMDLd2Multiple<string asm> {
7534 defm Two : BaseSIMDLdN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7537 multiclass SIMDSt2Multiple<string asm> {
7538 defm Two : BaseSIMDStN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7541 multiclass SIMDLd3Multiple<string asm> {
7542 defm Three : BaseSIMDLdN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
7545 multiclass SIMDSt3Multiple<string asm> {
7546 defm Three : BaseSIMDStN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
7549 multiclass SIMDLd4Multiple<string asm> {
7550 defm Four : BaseSIMDLdN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
7553 multiclass SIMDSt4Multiple<string asm> {
7554 defm Four : BaseSIMDStN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
7558 // AdvSIMD Load/store single-element
7561 class BaseSIMDLdStSingle<bit L, bit R, bits<3> opcode,
7562 string asm, string operands, dag oops, dag iops,
7564 : I<oops, iops, asm, operands, "", pattern> {
7568 let Inst{29-24} = 0b001101;
7571 let Inst{15-13} = opcode;
7572 let Inst{9-5} = vaddr;
7574 let DecoderMethod = "DecodeSIMDLdStSingle";
7577 class BaseSIMDLdStSingleTied<bit L, bit R, bits<3> opcode,
7578 string asm, string operands, dag oops, dag iops,
7580 : I<oops, iops, asm, operands, "$Vt = $dst", pattern> {
7584 let Inst{29-24} = 0b001101;
7587 let Inst{15-13} = opcode;
7588 let Inst{9-5} = vaddr;
7590 let DecoderMethod = "DecodeSIMDLdStSingleTied";
7594 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7595 class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
7597 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, $vaddr",
7598 (outs listtype:$Vt), (ins am_simdnoindex:$vaddr), []> {
7601 let Inst{20-16} = 0b00000;
7603 let Inst{11-10} = size;
7605 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7606 class BaseSIMDLdRPost<bit Q, bit R, bits<3> opcode, bit S, bits<2> size,
7607 string asm, Operand listtype, Operand GPR64pi>
7608 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, $vaddr, $Xm",
7609 (outs listtype:$Vt),
7610 (ins am_simdnoindex:$vaddr, GPR64pi:$Xm), []> {
7614 let Inst{20-16} = Xm;
7616 let Inst{11-10} = size;
7619 multiclass SIMDLdrAliases<string asm, string layout, string Count,
7620 int Offset, int Size> {
7621 // E.g. "ld1r { v0.8b }, [x1], #1"
7622 // "ld1r.8b\t$Vt, $vaddr, #1"
7623 // may get mapped to
7624 // (LD1Rv8b_POST VecListOne8b:$Vt, am_simdnoindex:$vaddr, XZR)
7625 def : InstAlias<asm # "\t$Vt, $vaddr, #" # Offset,
7626 (!cast<Instruction>(NAME # "v" # layout # "_POST")
7627 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
7628 am_simdnoindex:$vaddr, XZR), 1>;
7630 // E.g. "ld1r.8b { v0 }, [x1], #1"
7631 // "ld1r.8b\t$Vt, $vaddr, #1"
7632 // may get mapped to
7633 // (LD1Rv8b_POST VecListOne64:$Vt, am_simdnoindex:$vaddr, XZR)
7634 def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr, #" # Offset,
7635 (!cast<Instruction>(NAME # "v" # layout # "_POST")
7636 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7637 am_simdnoindex:$vaddr, XZR), 0>;
7639 // E.g. "ld1r.8b { v0 }, [x1]"
7640 // "ld1r.8b\t$Vt, $vaddr"
7641 // may get mapped to
7642 // (LD1Rv8b VecListOne64:$Vt, am_simdnoindex:$vaddr)
7643 def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr",
7644 (!cast<Instruction>(NAME # "v" # layout)
7645 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7646 am_simdnoindex:$vaddr), 0>;
7648 // E.g. "ld1r.8b { v0 }, [x1], x2"
7649 // "ld1r.8b\t$Vt, $vaddr, $Xm"
7650 // may get mapped to
7651 // (LD1Rv8b_POST VecListOne64:$Vt, am_simdnoindex:$vaddr, GPR64pi1:$Xm)
7652 def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr, $Xm",
7653 (!cast<Instruction>(NAME # "v" # layout # "_POST")
7654 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7655 am_simdnoindex:$vaddr,
7656 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
7659 multiclass SIMDLdR<bit R, bits<3> opcode, bit S, string asm, string Count,
7660 int Offset1, int Offset2, int Offset4, int Offset8> {
7661 def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
7662 !cast<Operand>("VecList" # Count # "8b")>;
7663 def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
7664 !cast<Operand>("VecList" # Count #"16b")>;
7665 def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
7666 !cast<Operand>("VecList" # Count #"4h")>;
7667 def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
7668 !cast<Operand>("VecList" # Count #"8h")>;
7669 def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm,
7670 !cast<Operand>("VecList" # Count #"2s")>;
7671 def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm,
7672 !cast<Operand>("VecList" # Count #"4s")>;
7673 def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm,
7674 !cast<Operand>("VecList" # Count #"1d")>;
7675 def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm,
7676 !cast<Operand>("VecList" # Count #"2d")>;
7678 def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
7679 !cast<Operand>("VecList" # Count # "8b"),
7680 !cast<Operand>("GPR64pi" # Offset1)>;
7681 def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
7682 !cast<Operand>("VecList" # Count # "16b"),
7683 !cast<Operand>("GPR64pi" # Offset1)>;
7684 def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
7685 !cast<Operand>("VecList" # Count # "4h"),
7686 !cast<Operand>("GPR64pi" # Offset2)>;
7687 def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
7688 !cast<Operand>("VecList" # Count # "8h"),
7689 !cast<Operand>("GPR64pi" # Offset2)>;
7690 def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm,
7691 !cast<Operand>("VecList" # Count # "2s"),
7692 !cast<Operand>("GPR64pi" # Offset4)>;
7693 def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm,
7694 !cast<Operand>("VecList" # Count # "4s"),
7695 !cast<Operand>("GPR64pi" # Offset4)>;
7696 def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm,
7697 !cast<Operand>("VecList" # Count # "1d"),
7698 !cast<Operand>("GPR64pi" # Offset8)>;
7699 def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm,
7700 !cast<Operand>("VecList" # Count # "2d"),
7701 !cast<Operand>("GPR64pi" # Offset8)>;
7703 defm : SIMDLdrAliases<asm, "8b", Count, Offset1, 64>;
7704 defm : SIMDLdrAliases<asm, "16b", Count, Offset1, 128>;
7705 defm : SIMDLdrAliases<asm, "4h", Count, Offset2, 64>;
7706 defm : SIMDLdrAliases<asm, "8h", Count, Offset2, 128>;
7707 defm : SIMDLdrAliases<asm, "2s", Count, Offset4, 64>;
7708 defm : SIMDLdrAliases<asm, "4s", Count, Offset4, 128>;
7709 defm : SIMDLdrAliases<asm, "1d", Count, Offset8, 64>;
7710 defm : SIMDLdrAliases<asm, "2d", Count, Offset8, 128>;
7713 class SIMDLdStSingleB<bit L, bit R, bits<3> opcode, string asm,
7714 dag oops, dag iops, list<dag> pattern>
7715 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
7717 // idx encoded in Q:S:size fields.
7719 let Inst{30} = idx{3};
7721 let Inst{20-16} = 0b00000;
7722 let Inst{12} = idx{2};
7723 let Inst{11-10} = idx{1-0};
7725 class SIMDLdStSingleBTied<bit L, bit R, bits<3> opcode, string asm,
7726 dag oops, dag iops, list<dag> pattern>
7727 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
7729 // idx encoded in Q:S:size fields.
7731 let Inst{30} = idx{3};
7733 let Inst{20-16} = 0b00000;
7734 let Inst{12} = idx{2};
7735 let Inst{11-10} = idx{1-0};
7737 class SIMDLdStSingleBPost<bit L, bit R, bits<3> opcode, string asm,
7739 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
7741 // idx encoded in Q:S:size fields.
7744 let Inst{30} = idx{3};
7746 let Inst{20-16} = Xm;
7747 let Inst{12} = idx{2};
7748 let Inst{11-10} = idx{1-0};
7750 class SIMDLdStSingleBTiedPost<bit L, bit R, bits<3> opcode, string asm,
7752 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
7754 // idx encoded in Q:S:size fields.
7757 let Inst{30} = idx{3};
7759 let Inst{20-16} = Xm;
7760 let Inst{12} = idx{2};
7761 let Inst{11-10} = idx{1-0};
7764 class SIMDLdStSingleH<bit L, bit R, bits<3> opcode, bit size, string asm,
7765 dag oops, dag iops, list<dag> pattern>
7766 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
7768 // idx encoded in Q:S:size<1> fields.
7770 let Inst{30} = idx{2};
7772 let Inst{20-16} = 0b00000;
7773 let Inst{12} = idx{1};
7774 let Inst{11} = idx{0};
7775 let Inst{10} = size;
7777 class SIMDLdStSingleHTied<bit L, bit R, bits<3> opcode, bit size, string asm,
7778 dag oops, dag iops, list<dag> pattern>
7779 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
7781 // idx encoded in Q:S:size<1> fields.
7783 let Inst{30} = idx{2};
7785 let Inst{20-16} = 0b00000;
7786 let Inst{12} = idx{1};
7787 let Inst{11} = idx{0};
7788 let Inst{10} = size;
7791 class SIMDLdStSingleHPost<bit L, bit R, bits<3> opcode, bit size, string asm,
7793 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
7795 // idx encoded in Q:S:size<1> fields.
7798 let Inst{30} = idx{2};
7800 let Inst{20-16} = Xm;
7801 let Inst{12} = idx{1};
7802 let Inst{11} = idx{0};
7803 let Inst{10} = size;
7805 class SIMDLdStSingleHTiedPost<bit L, bit R, bits<3> opcode, bit size, string asm,
7807 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
7809 // idx encoded in Q:S:size<1> fields.
7812 let Inst{30} = idx{2};
7814 let Inst{20-16} = Xm;
7815 let Inst{12} = idx{1};
7816 let Inst{11} = idx{0};
7817 let Inst{10} = size;
7819 class SIMDLdStSingleS<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
7820 dag oops, dag iops, list<dag> pattern>
7821 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
7823 // idx encoded in Q:S fields.
7825 let Inst{30} = idx{1};
7827 let Inst{20-16} = 0b00000;
7828 let Inst{12} = idx{0};
7829 let Inst{11-10} = size;
7831 class SIMDLdStSingleSTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
7832 dag oops, dag iops, list<dag> pattern>
7833 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
7835 // idx encoded in Q:S fields.
7837 let Inst{30} = idx{1};
7839 let Inst{20-16} = 0b00000;
7840 let Inst{12} = idx{0};
7841 let Inst{11-10} = size;
7843 class SIMDLdStSingleSPost<bit L, bit R, bits<3> opcode, bits<2> size,
7844 string asm, dag oops, dag iops>
7845 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
7847 // idx encoded in Q:S fields.
7850 let Inst{30} = idx{1};
7852 let Inst{20-16} = Xm;
7853 let Inst{12} = idx{0};
7854 let Inst{11-10} = size;
7856 class SIMDLdStSingleSTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
7857 string asm, dag oops, dag iops>
7858 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
7860 // idx encoded in Q:S fields.
7863 let Inst{30} = idx{1};
7865 let Inst{20-16} = Xm;
7866 let Inst{12} = idx{0};
7867 let Inst{11-10} = size;
7869 class SIMDLdStSingleD<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
7870 dag oops, dag iops, list<dag> pattern>
7871 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
7873 // idx encoded in Q field.
7877 let Inst{20-16} = 0b00000;
7879 let Inst{11-10} = size;
7881 class SIMDLdStSingleDTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
7882 dag oops, dag iops, list<dag> pattern>
7883 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", oops, iops,
7885 // idx encoded in Q field.
7889 let Inst{20-16} = 0b00000;
7891 let Inst{11-10} = size;
7893 class SIMDLdStSingleDPost<bit L, bit R, bits<3> opcode, bits<2> size,
7894 string asm, dag oops, dag iops>
7895 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
7897 // idx encoded in Q field.
7902 let Inst{20-16} = Xm;
7904 let Inst{11-10} = size;
7906 class SIMDLdStSingleDTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
7907 string asm, dag oops, dag iops>
7908 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
7910 // idx encoded in Q field.
7915 let Inst{20-16} = Xm;
7917 let Inst{11-10} = size;
7920 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7921 multiclass SIMDLdSingleBTied<bit R, bits<3> opcode, string asm,
7922 RegisterOperand listtype,
7923 RegisterOperand GPR64pi> {
7924 def i8 : SIMDLdStSingleBTied<1, R, opcode, asm,
7925 (outs listtype:$dst),
7926 (ins listtype:$Vt, VectorIndexB:$idx,
7927 am_simdnoindex:$vaddr), []>;
7929 def i8_POST : SIMDLdStSingleBTiedPost<1, R, opcode, asm,
7930 (outs listtype:$dst),
7931 (ins listtype:$Vt, VectorIndexB:$idx,
7932 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
7934 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7935 multiclass SIMDLdSingleHTied<bit R, bits<3> opcode, bit size, string asm,
7936 RegisterOperand listtype,
7937 RegisterOperand GPR64pi> {
7938 def i16 : SIMDLdStSingleHTied<1, R, opcode, size, asm,
7939 (outs listtype:$dst),
7940 (ins listtype:$Vt, VectorIndexH:$idx,
7941 am_simdnoindex:$vaddr), []>;
7943 def i16_POST : SIMDLdStSingleHTiedPost<1, R, opcode, size, asm,
7944 (outs listtype:$dst),
7945 (ins listtype:$Vt, VectorIndexH:$idx,
7946 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
7948 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7949 multiclass SIMDLdSingleSTied<bit R, bits<3> opcode, bits<2> size,string asm,
7950 RegisterOperand listtype,
7951 RegisterOperand GPR64pi> {
7952 def i32 : SIMDLdStSingleSTied<1, R, opcode, size, asm,
7953 (outs listtype:$dst),
7954 (ins listtype:$Vt, VectorIndexS:$idx,
7955 am_simdnoindex:$vaddr), []>;
7957 def i32_POST : SIMDLdStSingleSTiedPost<1, R, opcode, size, asm,
7958 (outs listtype:$dst),
7959 (ins listtype:$Vt, VectorIndexS:$idx,
7960 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
7962 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7963 multiclass SIMDLdSingleDTied<bit R, bits<3> opcode, bits<2> size, string asm,
7964 RegisterOperand listtype,
7965 RegisterOperand GPR64pi> {
7966 def i64 : SIMDLdStSingleDTied<1, R, opcode, size, asm,
7967 (outs listtype:$dst),
7968 (ins listtype:$Vt, VectorIndexD:$idx,
7969 am_simdnoindex:$vaddr), []>;
7971 def i64_POST : SIMDLdStSingleDTiedPost<1, R, opcode, size, asm,
7972 (outs listtype:$dst),
7973 (ins listtype:$Vt, VectorIndexD:$idx,
7974 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
7976 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
7977 multiclass SIMDStSingleB<bit R, bits<3> opcode, string asm,
7978 RegisterOperand listtype, list<dag> pattern,
7979 RegisterOperand GPR64pi> {
7980 def i8 : SIMDLdStSingleB<0, R, opcode, asm,
7981 (outs), (ins listtype:$Vt, VectorIndexB:$idx,
7982 am_simdnoindex:$vaddr),
7985 def i8_POST : SIMDLdStSingleBPost<0, R, opcode, asm,
7986 (outs), (ins listtype:$Vt, VectorIndexB:$idx,
7987 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
7989 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
7990 multiclass SIMDStSingleH<bit R, bits<3> opcode, bit size, string asm,
7991 RegisterOperand listtype, list<dag> pattern,
7992 RegisterOperand GPR64pi> {
7993 def i16 : SIMDLdStSingleH<0, R, opcode, size, asm,
7994 (outs), (ins listtype:$Vt, VectorIndexH:$idx,
7995 am_simdnoindex:$vaddr),
7998 def i16_POST : SIMDLdStSingleHPost<0, R, opcode, size, asm,
7999 (outs), (ins listtype:$Vt, VectorIndexH:$idx,
8000 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
8002 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8003 multiclass SIMDStSingleS<bit R, bits<3> opcode, bits<2> size,string asm,
8004 RegisterOperand listtype, list<dag> pattern,
8005 RegisterOperand GPR64pi> {
8006 def i32 : SIMDLdStSingleS<0, R, opcode, size, asm,
8007 (outs), (ins listtype:$Vt, VectorIndexS:$idx,
8008 am_simdnoindex:$vaddr),
8011 def i32_POST : SIMDLdStSingleSPost<0, R, opcode, size, asm,
8012 (outs), (ins listtype:$Vt, VectorIndexS:$idx,
8013 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
8015 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8016 multiclass SIMDStSingleD<bit R, bits<3> opcode, bits<2> size, string asm,
8017 RegisterOperand listtype, list<dag> pattern,
8018 RegisterOperand GPR64pi> {
8019 def i64 : SIMDLdStSingleD<0, R, opcode, size, asm,
8020 (outs), (ins listtype:$Vt, VectorIndexD:$idx,
8021 am_simdnoindex:$vaddr), pattern>;
8023 def i64_POST : SIMDLdStSingleDPost<0, R, opcode, size, asm,
8024 (outs), (ins listtype:$Vt, VectorIndexD:$idx,
8025 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
8028 multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
8029 string Count, int Offset, Operand idxtype> {
8030 // E.g. "ld1 { v0.8b }[0], [x1], #1"
8031 // "ld1\t$Vt, $vaddr, #1"
8032 // may get mapped to
8033 // (LD1Rv8b_POST VecListOne8b:$Vt, am_simdnoindex:$vaddr, XZR)
8034 def : InstAlias<asm # "\t$Vt$idx, $vaddr, #" # Offset,
8035 (!cast<Instruction>(NAME # Type # "_POST")
8036 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8037 idxtype:$idx, am_simdnoindex:$vaddr, XZR), 1>;
8039 // E.g. "ld1.8b { v0 }[0], [x1], #1"
8040 // "ld1.8b\t$Vt, $vaddr, #1"
8041 // may get mapped to
8042 // (LD1Rv8b_POST VecListOne64:$Vt, am_simdnoindex:$vaddr, XZR)
8043 def : InstAlias<asm # "." # layout # "\t$Vt$idx, $vaddr, #" # Offset,
8044 (!cast<Instruction>(NAME # Type # "_POST")
8045 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8046 idxtype:$idx, am_simdnoindex:$vaddr, XZR), 0>;
8048 // E.g. "ld1.8b { v0 }[0], [x1]"
8049 // "ld1.8b\t$Vt, $vaddr"
8050 // may get mapped to
8051 // (LD1Rv8b VecListOne64:$Vt, am_simdnoindex:$vaddr)
8052 def : InstAlias<asm # "." # layout # "\t$Vt$idx, $vaddr",
8053 (!cast<Instruction>(NAME # Type)
8054 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8055 idxtype:$idx, am_simdnoindex:$vaddr), 0>;
8057 // E.g. "ld1.8b { v0 }[0], [x1], x2"
8058 // "ld1.8b\t$Vt, $vaddr, $Xm"
8059 // may get mapped to
8060 // (LD1Rv8b_POST VecListOne64:$Vt, am_simdnoindex:$vaddr, GPR64pi1:$Xm)
8061 def : InstAlias<asm # "." # layout # "\t$Vt$idx, $vaddr, $Xm",
8062 (!cast<Instruction>(NAME # Type # "_POST")
8063 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8064 idxtype:$idx, am_simdnoindex:$vaddr,
8065 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8068 multiclass SIMDLdSt1SingleAliases<string asm> {
8069 defm : SIMDLdStSingleAliases<asm, "b", "i8", "One", 1, VectorIndexB>;
8070 defm : SIMDLdStSingleAliases<asm, "h", "i16", "One", 2, VectorIndexH>;
8071 defm : SIMDLdStSingleAliases<asm, "s", "i32", "One", 4, VectorIndexS>;
8072 defm : SIMDLdStSingleAliases<asm, "d", "i64", "One", 8, VectorIndexD>;
8075 multiclass SIMDLdSt2SingleAliases<string asm> {
8076 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Two", 2, VectorIndexB>;
8077 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Two", 4, VectorIndexH>;
8078 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Two", 8, VectorIndexS>;
8079 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Two", 16, VectorIndexD>;
8082 multiclass SIMDLdSt3SingleAliases<string asm> {
8083 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Three", 3, VectorIndexB>;
8084 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Three", 6, VectorIndexH>;
8085 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Three", 12, VectorIndexS>;
8086 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Three", 24, VectorIndexD>;
8089 multiclass SIMDLdSt4SingleAliases<string asm> {
8090 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Four", 4, VectorIndexB>;
8091 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Four", 8, VectorIndexH>;
8092 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Four", 16, VectorIndexS>;
8093 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Four", 32, VectorIndexD>;
8096 //----------------------------------------------------------------------------
8097 // Crypto extensions
8098 //----------------------------------------------------------------------------
8100 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8101 class AESBase<bits<4> opc, string asm, dag outs, dag ins, string cstr,
8103 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
8107 let Inst{31-16} = 0b0100111000101000;
8108 let Inst{15-12} = opc;
8109 let Inst{11-10} = 0b10;
8114 class AESInst<bits<4> opc, string asm, Intrinsic OpNode>
8115 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
8116 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
8118 class AESTiedInst<bits<4> opc, string asm, Intrinsic OpNode>
8119 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
8121 [(set (v16i8 V128:$dst),
8122 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
8124 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8125 class SHA3OpTiedInst<bits<3> opc, string asm, string dst_lhs_kind,
8126 dag oops, dag iops, list<dag> pat>
8127 : I<oops, iops, asm,
8128 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
8129 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
8134 let Inst{31-21} = 0b01011110000;
8135 let Inst{20-16} = Rm;
8137 let Inst{14-12} = opc;
8138 let Inst{11-10} = 0b00;
8143 class SHATiedInstQSV<bits<3> opc, string asm, Intrinsic OpNode>
8144 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8145 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
8146 [(set (v4i32 FPR128:$dst),
8147 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
8148 (v4i32 V128:$Rm)))]>;
8150 class SHATiedInstVVV<bits<3> opc, string asm, Intrinsic OpNode>
8151 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
8152 (ins V128:$Rd, V128:$Rn, V128:$Rm),
8153 [(set (v4i32 V128:$dst),
8154 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8155 (v4i32 V128:$Rm)))]>;
8157 class SHATiedInstQQV<bits<3> opc, string asm, Intrinsic OpNode>
8158 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8159 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
8160 [(set (v4i32 FPR128:$dst),
8161 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
8162 (v4i32 V128:$Rm)))]>;
8164 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8165 class SHA2OpInst<bits<4> opc, string asm, string kind,
8166 string cstr, dag oops, dag iops,
8168 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
8169 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
8173 let Inst{31-16} = 0b0101111000101000;
8174 let Inst{15-12} = opc;
8175 let Inst{11-10} = 0b10;
8180 class SHATiedInstVV<bits<4> opc, string asm, Intrinsic OpNode>
8181 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
8182 (ins V128:$Rd, V128:$Rn),
8183 [(set (v4i32 V128:$dst),
8184 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
8186 class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode>
8187 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
8188 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
8190 // Allow the size specifier tokens to be upper case, not just lower.
8191 def : TokenAlias<".8B", ".8b">;
8192 def : TokenAlias<".4H", ".4h">;
8193 def : TokenAlias<".2S", ".2s">;
8194 def : TokenAlias<".1D", ".1d">;
8195 def : TokenAlias<".16B", ".16b">;
8196 def : TokenAlias<".8H", ".8h">;
8197 def : TokenAlias<".4S", ".4s">;
8198 def : TokenAlias<".2D", ".2d">;
8199 def : TokenAlias<".B", ".b">;
8200 def : TokenAlias<".H", ".h">;
8201 def : TokenAlias<".S", ".s">;
8202 def : TokenAlias<".D", ".d">;