1 //===- ARM64InstrFormats.td - ARM64 Instruction Formats ------*- tblgen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Describe ARM64 instructions format here
14 // Format specifies the encoding used by the instruction. This is part of the
15 // ad-hoc solution used to emit machine instruction encodings by our machine
17 class Format<bits<2> val> {
21 def PseudoFrm : Format<0>;
22 def NormalFrm : Format<1>; // Do we need any others?
24 // ARM64 Instruction Format
25 class ARM64Inst<Format f, string cstr> : Instruction {
26 field bits<32> Inst; // Instruction encoding.
27 // Mask of bits that cause an encoding to be UNPREDICTABLE.
28 // If a bit is set, then if the corresponding bit in the
29 // target encoding differs from its value in the "Inst" field,
30 // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
31 field bits<32> Unpredictable = 0;
32 // SoftFail is the generic name for this field, but we alias it so
33 // as to make it more obvious what it means in ARM-land.
34 field bits<32> SoftFail = Unpredictable;
35 let Namespace = "ARM64";
37 bits<2> Form = F.Value;
39 let Constraints = cstr;
42 // Pseudo instructions (don't have encoding information)
43 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
44 : ARM64Inst<PseudoFrm, cstr> {
45 dag OutOperandList = oops;
46 dag InOperandList = iops;
47 let Pattern = pattern;
48 let isCodeGenOnly = 1;
51 // Real instructions (have encoding information)
52 class EncodedI<string cstr, list<dag> pattern> : ARM64Inst<NormalFrm, cstr> {
53 let Pattern = pattern;
57 // Normal instructions
58 class I<dag oops, dag iops, string asm, string operands, string cstr,
60 : EncodedI<cstr, pattern> {
61 dag OutOperandList = oops;
62 dag InOperandList = iops;
63 let AsmString = !strconcat(asm, operands);
66 class TriOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$MHS, node:$RHS), res>;
67 class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
68 class UnOpFrag<dag res> : PatFrag<(ops node:$LHS), res>;
70 // Helper fragment for an extract of the high portion of a 128-bit vector.
71 def extract_high_v16i8 :
72 UnOpFrag<(extract_subvector (v16i8 node:$LHS), (i64 8))>;
73 def extract_high_v8i16 :
74 UnOpFrag<(extract_subvector (v8i16 node:$LHS), (i64 4))>;
75 def extract_high_v4i32 :
76 UnOpFrag<(extract_subvector (v4i32 node:$LHS), (i64 2))>;
77 def extract_high_v2i64 :
78 UnOpFrag<(extract_subvector (v2i64 node:$LHS), (i64 1))>;
80 //===----------------------------------------------------------------------===//
81 // Asm Operand Classes.
84 // Shifter operand for arithmetic shifted encodings.
85 def ShifterOperand : AsmOperandClass {
89 // Shifter operand for mov immediate encodings.
90 def MovImm32ShifterOperand : AsmOperandClass {
91 let SuperClasses = [ShifterOperand];
92 let Name = "MovImm32Shifter";
93 let RenderMethod = "addShifterOperands";
95 def MovImm64ShifterOperand : AsmOperandClass {
96 let SuperClasses = [ShifterOperand];
97 let Name = "MovImm64Shifter";
98 let RenderMethod = "addShifterOperands";
101 // Shifter operand for arithmetic register shifted encodings.
102 class ArithmeticShifterOperand<int width> : AsmOperandClass {
103 let SuperClasses = [ShifterOperand];
104 let Name = "ArithmeticShifter" # width;
105 let PredicateMethod = "isArithmeticShifter<" # width # ">";
106 let RenderMethod = "addShifterOperands";
107 let DiagnosticType = "AddSubRegShift" # width;
110 def ArithmeticShifterOperand32 : ArithmeticShifterOperand<32>;
111 def ArithmeticShifterOperand64 : ArithmeticShifterOperand<64>;
113 // Shifter operand for logical register shifted encodings.
114 class LogicalShifterOperand<int width> : AsmOperandClass {
115 let SuperClasses = [ShifterOperand];
116 let Name = "LogicalShifter" # width;
117 let PredicateMethod = "isLogicalShifter<" # width # ">";
118 let RenderMethod = "addShifterOperands";
119 let DiagnosticType = "AddSubRegShift" # width;
122 def LogicalShifterOperand32 : LogicalShifterOperand<32>;
123 def LogicalShifterOperand64 : LogicalShifterOperand<64>;
125 // Shifter operand for logical vector 128/64-bit shifted encodings.
126 def LogicalVecShifterOperand : AsmOperandClass {
127 let SuperClasses = [ShifterOperand];
128 let Name = "LogicalVecShifter";
129 let RenderMethod = "addShifterOperands";
131 def LogicalVecHalfWordShifterOperand : AsmOperandClass {
132 let SuperClasses = [LogicalVecShifterOperand];
133 let Name = "LogicalVecHalfWordShifter";
134 let RenderMethod = "addShifterOperands";
137 // The "MSL" shifter on the vector MOVI instruction.
138 def MoveVecShifterOperand : AsmOperandClass {
139 let SuperClasses = [ShifterOperand];
140 let Name = "MoveVecShifter";
141 let RenderMethod = "addShifterOperands";
144 // Extend operand for arithmetic encodings.
145 def ExtendOperand : AsmOperandClass {
147 let DiagnosticType = "AddSubRegExtendLarge";
149 def ExtendOperand64 : AsmOperandClass {
150 let SuperClasses = [ExtendOperand];
151 let Name = "Extend64";
152 let DiagnosticType = "AddSubRegExtendSmall";
154 // 'extend' that's a lsl of a 64-bit register.
155 def ExtendOperandLSL64 : AsmOperandClass {
156 let SuperClasses = [ExtendOperand];
157 let Name = "ExtendLSL64";
158 let RenderMethod = "addExtend64Operands";
159 let DiagnosticType = "AddSubRegExtendLarge";
162 // 8-bit floating-point immediate encodings.
163 def FPImmOperand : AsmOperandClass {
165 let ParserMethod = "tryParseFPImm";
168 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
169 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
170 // are encoded as the eight bit value 'abcdefgh'.
171 def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }
174 //===----------------------------------------------------------------------===//
175 // Operand Definitions.
178 // ADR[P] instruction labels.
179 def AdrpOperand : AsmOperandClass {
180 let Name = "AdrpLabel";
181 let ParserMethod = "tryParseAdrpLabel";
182 let DiagnosticType = "InvalidLabel";
184 def adrplabel : Operand<i64> {
185 let EncoderMethod = "getAdrLabelOpValue";
186 let PrintMethod = "printAdrpLabel";
187 let ParserMatchClass = AdrpOperand;
190 def AdrOperand : AsmOperandClass {
191 let Name = "AdrLabel";
192 let ParserMethod = "tryParseAdrLabel";
193 let DiagnosticType = "InvalidLabel";
195 def adrlabel : Operand<i64> {
196 let EncoderMethod = "getAdrLabelOpValue";
197 let ParserMatchClass = AdrOperand;
200 // simm9 predicate - True if the immediate is in the range [-256, 255].
201 def SImm9Operand : AsmOperandClass {
203 let DiagnosticType = "InvalidMemoryIndexedSImm9";
205 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
206 let ParserMatchClass = SImm9Operand;
209 // simm7s4 predicate - True if the immediate is a multiple of 4 in the range
211 def SImm7s4Operand : AsmOperandClass {
212 let Name = "SImm7s4";
213 let DiagnosticType = "InvalidMemoryIndexed32SImm7";
215 def simm7s4 : Operand<i32> {
216 let ParserMatchClass = SImm7s4Operand;
217 let PrintMethod = "printImmScale<4>";
220 // simm7s8 predicate - True if the immediate is a multiple of 8 in the range
222 def SImm7s8Operand : AsmOperandClass {
223 let Name = "SImm7s8";
224 let DiagnosticType = "InvalidMemoryIndexed64SImm7";
226 def simm7s8 : Operand<i32> {
227 let ParserMatchClass = SImm7s8Operand;
228 let PrintMethod = "printImmScale<8>";
231 // simm7s16 predicate - True if the immediate is a multiple of 16 in the range
233 def SImm7s16Operand : AsmOperandClass {
234 let Name = "SImm7s16";
235 let DiagnosticType = "InvalidMemoryIndexed64SImm7";
237 def simm7s16 : Operand<i32> {
238 let ParserMatchClass = SImm7s16Operand;
239 let PrintMethod = "printImmScale<16>";
242 // imm0_65535 predicate - True if the immediate is in the range [0,65535].
243 def Imm0_65535Operand : AsmOperandClass { let Name = "Imm0_65535"; }
244 def imm0_65535 : Operand<i32>, ImmLeaf<i32, [{
245 return ((uint32_t)Imm) < 65536;
247 let ParserMatchClass = Imm0_65535Operand;
248 let PrintMethod = "printHexImm";
251 class AsmImmRange<int Low, int High> : AsmOperandClass {
252 let Name = "Imm" # Low # "_" # High;
253 let DiagnosticType = "InvalidImm" # Low # "_" # High;
256 def Imm1_8Operand : AsmImmRange<1, 8>;
257 def Imm1_16Operand : AsmImmRange<1, 16>;
258 def Imm1_32Operand : AsmImmRange<1, 32>;
259 def Imm1_64Operand : AsmImmRange<1, 64>;
261 def MovZSymbolG3AsmOperand : AsmOperandClass {
262 let Name = "MovZSymbolG3";
263 let RenderMethod = "addImmOperands";
266 def movz_symbol_g3 : Operand<i32> {
267 let ParserMatchClass = MovZSymbolG3AsmOperand;
270 def MovZSymbolG2AsmOperand : AsmOperandClass {
271 let Name = "MovZSymbolG2";
272 let RenderMethod = "addImmOperands";
275 def movz_symbol_g2 : Operand<i32> {
276 let ParserMatchClass = MovZSymbolG2AsmOperand;
279 def MovZSymbolG1AsmOperand : AsmOperandClass {
280 let Name = "MovZSymbolG1";
281 let RenderMethod = "addImmOperands";
284 def movz_symbol_g1 : Operand<i32> {
285 let ParserMatchClass = MovZSymbolG1AsmOperand;
288 def MovZSymbolG0AsmOperand : AsmOperandClass {
289 let Name = "MovZSymbolG0";
290 let RenderMethod = "addImmOperands";
293 def movz_symbol_g0 : Operand<i32> {
294 let ParserMatchClass = MovZSymbolG0AsmOperand;
297 def MovKSymbolG3AsmOperand : AsmOperandClass {
298 let Name = "MovKSymbolG3";
299 let RenderMethod = "addImmOperands";
302 def movk_symbol_g3 : Operand<i32> {
303 let ParserMatchClass = MovKSymbolG3AsmOperand;
306 def MovKSymbolG2AsmOperand : AsmOperandClass {
307 let Name = "MovKSymbolG2";
308 let RenderMethod = "addImmOperands";
311 def movk_symbol_g2 : Operand<i32> {
312 let ParserMatchClass = MovKSymbolG2AsmOperand;
315 def MovKSymbolG1AsmOperand : AsmOperandClass {
316 let Name = "MovKSymbolG1";
317 let RenderMethod = "addImmOperands";
320 def movk_symbol_g1 : Operand<i32> {
321 let ParserMatchClass = MovKSymbolG1AsmOperand;
324 def MovKSymbolG0AsmOperand : AsmOperandClass {
325 let Name = "MovKSymbolG0";
326 let RenderMethod = "addImmOperands";
329 def movk_symbol_g0 : Operand<i32> {
330 let ParserMatchClass = MovKSymbolG0AsmOperand;
333 class fixedpoint_i32<ValueType FloatVT>
335 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm, ld]> {
336 let EncoderMethod = "getFixedPointScaleOpValue";
337 let DecoderMethod = "DecodeFixedPointScaleImm32";
338 let ParserMatchClass = Imm1_32Operand;
341 class fixedpoint_i64<ValueType FloatVT>
343 ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm, ld]> {
344 let EncoderMethod = "getFixedPointScaleOpValue";
345 let DecoderMethod = "DecodeFixedPointScaleImm64";
346 let ParserMatchClass = Imm1_64Operand;
349 def fixedpoint_f32_i32 : fixedpoint_i32<f32>;
350 def fixedpoint_f64_i32 : fixedpoint_i32<f64>;
352 def fixedpoint_f32_i64 : fixedpoint_i64<f32>;
353 def fixedpoint_f64_i64 : fixedpoint_i64<f64>;
355 def vecshiftR8 : Operand<i32>, ImmLeaf<i32, [{
356 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
358 let EncoderMethod = "getVecShiftR8OpValue";
359 let DecoderMethod = "DecodeVecShiftR8Imm";
360 let ParserMatchClass = Imm1_8Operand;
362 def vecshiftR16 : Operand<i32>, ImmLeaf<i32, [{
363 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
365 let EncoderMethod = "getVecShiftR16OpValue";
366 let DecoderMethod = "DecodeVecShiftR16Imm";
367 let ParserMatchClass = Imm1_16Operand;
369 def vecshiftR16Narrow : Operand<i32>, ImmLeaf<i32, [{
370 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
372 let EncoderMethod = "getVecShiftR16OpValue";
373 let DecoderMethod = "DecodeVecShiftR16ImmNarrow";
374 let ParserMatchClass = Imm1_8Operand;
376 def vecshiftR32 : Operand<i32>, ImmLeaf<i32, [{
377 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
379 let EncoderMethod = "getVecShiftR32OpValue";
380 let DecoderMethod = "DecodeVecShiftR32Imm";
381 let ParserMatchClass = Imm1_32Operand;
383 def vecshiftR32Narrow : Operand<i32>, ImmLeaf<i32, [{
384 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
386 let EncoderMethod = "getVecShiftR32OpValue";
387 let DecoderMethod = "DecodeVecShiftR32ImmNarrow";
388 let ParserMatchClass = Imm1_16Operand;
390 def vecshiftR64 : Operand<i32>, ImmLeaf<i32, [{
391 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
393 let EncoderMethod = "getVecShiftR64OpValue";
394 let DecoderMethod = "DecodeVecShiftR64Imm";
395 let ParserMatchClass = Imm1_64Operand;
397 def vecshiftR64Narrow : Operand<i32>, ImmLeaf<i32, [{
398 return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
400 let EncoderMethod = "getVecShiftR64OpValue";
401 let DecoderMethod = "DecodeVecShiftR64ImmNarrow";
402 let ParserMatchClass = Imm1_32Operand;
405 def Imm0_7Operand : AsmImmRange<0, 7>;
406 def Imm0_15Operand : AsmImmRange<0, 15>;
407 def Imm0_31Operand : AsmImmRange<0, 31>;
408 def Imm0_63Operand : AsmImmRange<0, 63>;
410 def vecshiftL8 : Operand<i32>, ImmLeaf<i32, [{
411 return (((uint32_t)Imm) < 8);
413 let EncoderMethod = "getVecShiftL8OpValue";
414 let DecoderMethod = "DecodeVecShiftL8Imm";
415 let ParserMatchClass = Imm0_7Operand;
417 def vecshiftL16 : Operand<i32>, ImmLeaf<i32, [{
418 return (((uint32_t)Imm) < 16);
420 let EncoderMethod = "getVecShiftL16OpValue";
421 let DecoderMethod = "DecodeVecShiftL16Imm";
422 let ParserMatchClass = Imm0_15Operand;
424 def vecshiftL32 : Operand<i32>, ImmLeaf<i32, [{
425 return (((uint32_t)Imm) < 32);
427 let EncoderMethod = "getVecShiftL32OpValue";
428 let DecoderMethod = "DecodeVecShiftL32Imm";
429 let ParserMatchClass = Imm0_31Operand;
431 def vecshiftL64 : Operand<i32>, ImmLeaf<i32, [{
432 return (((uint32_t)Imm) < 64);
434 let EncoderMethod = "getVecShiftL64OpValue";
435 let DecoderMethod = "DecodeVecShiftL64Imm";
436 let ParserMatchClass = Imm0_63Operand;
440 // Crazy immediate formats used by 32-bit and 64-bit logical immediate
441 // instructions for splatting repeating bit patterns across the immediate.
442 def logical_imm32_XFORM : SDNodeXForm<imm, [{
443 uint64_t enc = ARM64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
444 return CurDAG->getTargetConstant(enc, MVT::i32);
446 def logical_imm64_XFORM : SDNodeXForm<imm, [{
447 uint64_t enc = ARM64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
448 return CurDAG->getTargetConstant(enc, MVT::i32);
451 def LogicalImm32Operand : AsmOperandClass {
452 let Name = "LogicalImm32";
453 let DiagnosticType = "LogicalSecondSource";
455 def LogicalImm64Operand : AsmOperandClass {
456 let Name = "LogicalImm64";
457 let DiagnosticType = "LogicalSecondSource";
459 def logical_imm32 : Operand<i32>, PatLeaf<(imm), [{
460 return ARM64_AM::isLogicalImmediate(N->getZExtValue(), 32);
461 }], logical_imm32_XFORM> {
462 let PrintMethod = "printLogicalImm32";
463 let ParserMatchClass = LogicalImm32Operand;
465 def logical_imm64 : Operand<i64>, PatLeaf<(imm), [{
466 return ARM64_AM::isLogicalImmediate(N->getZExtValue(), 64);
467 }], logical_imm64_XFORM> {
468 let PrintMethod = "printLogicalImm64";
469 let ParserMatchClass = LogicalImm64Operand;
472 // imm0_255 predicate - True if the immediate is in the range [0,255].
473 def Imm0_255Operand : AsmOperandClass { let Name = "Imm0_255"; }
474 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
475 return ((uint32_t)Imm) < 256;
477 let ParserMatchClass = Imm0_255Operand;
478 let PrintMethod = "printHexImm";
481 // imm0_127 predicate - True if the immediate is in the range [0,127]
482 def Imm0_127Operand : AsmOperandClass { let Name = "Imm0_127"; }
483 def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
484 return ((uint32_t)Imm) < 128;
486 let ParserMatchClass = Imm0_127Operand;
487 let PrintMethod = "printHexImm";
490 // NOTE: These imm0_N operands have to be of type i64 because i64 is the size
491 // for all shift-amounts.
493 // imm0_63 predicate - True if the immediate is in the range [0,63]
494 def imm0_63 : Operand<i64>, ImmLeaf<i64, [{
495 return ((uint64_t)Imm) < 64;
497 let ParserMatchClass = Imm0_63Operand;
500 // imm0_31 predicate - True if the immediate is in the range [0,31]
501 def imm0_31 : Operand<i64>, ImmLeaf<i64, [{
502 return ((uint64_t)Imm) < 32;
504 let ParserMatchClass = Imm0_31Operand;
507 // imm0_15 predicate - True if the immediate is in the range [0,15]
508 def imm0_15 : Operand<i64>, ImmLeaf<i64, [{
509 return ((uint64_t)Imm) < 16;
511 let ParserMatchClass = Imm0_15Operand;
514 // imm0_7 predicate - True if the immediate is in the range [0,7]
515 def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
516 return ((uint64_t)Imm) < 8;
518 let ParserMatchClass = Imm0_7Operand;
521 // An arithmetic shifter operand:
522 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
524 class arith_shift<ValueType Ty, int width> : Operand<Ty> {
525 let PrintMethod = "printShifter";
526 let ParserMatchClass = !cast<AsmOperandClass>(
527 "ArithmeticShifterOperand" # width);
530 def arith_shift32 : arith_shift<i32, 32>;
531 def arith_shift64 : arith_shift<i64, 64>;
533 class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
535 ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
536 let PrintMethod = "printShiftedRegister";
537 let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
540 def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
541 def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;
543 // An arithmetic shifter operand:
544 // {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr, 11 = ror
546 class logical_shift<int width> : Operand<i32> {
547 let PrintMethod = "printShifter";
548 let ParserMatchClass = !cast<AsmOperandClass>(
549 "LogicalShifterOperand" # width);
552 def logical_shift32 : logical_shift<32>;
553 def logical_shift64 : logical_shift<64>;
555 class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
557 ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
558 let PrintMethod = "printShiftedRegister";
559 let MIOperandInfo = (ops regclass, shiftop);
562 def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
563 def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;
565 // A logical vector shifter operand:
566 // {7-6} - shift type: 00 = lsl
567 // {5-0} - imm6: #0, #8, #16, or #24
568 def logical_vec_shift : Operand<i32> {
569 let PrintMethod = "printShifter";
570 let EncoderMethod = "getVecShifterOpValue";
571 let ParserMatchClass = LogicalVecShifterOperand;
574 // A logical vector half-word shifter operand:
575 // {7-6} - shift type: 00 = lsl
576 // {5-0} - imm6: #0 or #8
577 def logical_vec_hw_shift : Operand<i32> {
578 let PrintMethod = "printShifter";
579 let EncoderMethod = "getVecShifterOpValue";
580 let ParserMatchClass = LogicalVecHalfWordShifterOperand;
583 // A vector move shifter operand:
584 // {0} - imm1: #8 or #16
585 def move_vec_shift : Operand<i32> {
586 let PrintMethod = "printShifter";
587 let EncoderMethod = "getMoveVecShifterOpValue";
588 let ParserMatchClass = MoveVecShifterOperand;
591 def AddSubImmOperand : AsmOperandClass {
592 let Name = "AddSubImm";
593 let ParserMethod = "tryParseAddSubImm";
594 let DiagnosticType = "AddSubSecondSource";
596 // An ADD/SUB immediate shifter operand:
598 // {7-6} - shift type: 00 = lsl
599 // {5-0} - imm6: #0 or #12
600 class addsub_shifted_imm<ValueType Ty>
601 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectArithImmed", [imm]> {
602 let PrintMethod = "printAddSubImm";
603 let EncoderMethod = "getAddSubImmOpValue";
604 let ParserMatchClass = AddSubImmOperand;
605 let MIOperandInfo = (ops i32imm, i32imm);
608 def addsub_shifted_imm32 : addsub_shifted_imm<i32>;
609 def addsub_shifted_imm64 : addsub_shifted_imm<i64>;
611 class neg_addsub_shifted_imm<ValueType Ty>
612 : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
613 let PrintMethod = "printAddSubImm";
614 let EncoderMethod = "getAddSubImmOpValue";
615 let ParserMatchClass = AddSubImmOperand;
616 let MIOperandInfo = (ops i32imm, i32imm);
619 def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm<i32>;
620 def neg_addsub_shifted_imm64 : neg_addsub_shifted_imm<i64>;
622 // An extend operand:
623 // {5-3} - extend type
625 def arith_extend : Operand<i32> {
626 let PrintMethod = "printExtend";
627 let ParserMatchClass = ExtendOperand;
629 def arith_extend64 : Operand<i32> {
630 let PrintMethod = "printExtend";
631 let ParserMatchClass = ExtendOperand64;
634 // 'extend' that's a lsl of a 64-bit register.
635 def arith_extendlsl64 : Operand<i32> {
636 let PrintMethod = "printExtend";
637 let ParserMatchClass = ExtendOperandLSL64;
640 class arith_extended_reg32<ValueType Ty> : Operand<Ty>,
641 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
642 let PrintMethod = "printExtendedRegister";
643 let MIOperandInfo = (ops GPR32, arith_extend);
646 class arith_extended_reg32to64<ValueType Ty> : Operand<Ty>,
647 ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
648 let PrintMethod = "printExtendedRegister";
649 let MIOperandInfo = (ops GPR32, arith_extend64);
652 // Floating-point immediate.
653 def fpimm32 : Operand<f32>,
654 PatLeaf<(f32 fpimm), [{
655 return ARM64_AM::getFP32Imm(N->getValueAPF()) != -1;
656 }], SDNodeXForm<fpimm, [{
657 APFloat InVal = N->getValueAPF();
658 uint32_t enc = ARM64_AM::getFP32Imm(InVal);
659 return CurDAG->getTargetConstant(enc, MVT::i32);
661 let ParserMatchClass = FPImmOperand;
662 let PrintMethod = "printFPImmOperand";
664 def fpimm64 : Operand<f64>,
665 PatLeaf<(f64 fpimm), [{
666 return ARM64_AM::getFP64Imm(N->getValueAPF()) != -1;
667 }], SDNodeXForm<fpimm, [{
668 APFloat InVal = N->getValueAPF();
669 uint32_t enc = ARM64_AM::getFP64Imm(InVal);
670 return CurDAG->getTargetConstant(enc, MVT::i32);
672 let ParserMatchClass = FPImmOperand;
673 let PrintMethod = "printFPImmOperand";
676 def fpimm8 : Operand<i32> {
677 let ParserMatchClass = FPImmOperand;
678 let PrintMethod = "printFPImmOperand";
681 def fpimm0 : PatLeaf<(fpimm), [{
682 return N->isExactlyValue(+0.0);
685 // 8-bit immediate for AdvSIMD where 64-bit values of the form:
686 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
687 // are encoded as the eight bit value 'abcdefgh'.
688 def simdimmtype10 : Operand<i32>,
689 PatLeaf<(f64 fpimm), [{
690 return ARM64_AM::isAdvSIMDModImmType10(N->getValueAPF()
693 }], SDNodeXForm<fpimm, [{
694 APFloat InVal = N->getValueAPF();
695 uint32_t enc = ARM64_AM::encodeAdvSIMDModImmType10(N->getValueAPF()
698 return CurDAG->getTargetConstant(enc, MVT::i32);
700 let ParserMatchClass = SIMDImmType10Operand;
701 let PrintMethod = "printSIMDType10Operand";
709 // Base encoding for system instruction operands.
710 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
711 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands>
712 : I<oops, iops, asm, operands, "", []> {
713 let Inst{31-22} = 0b1101010100;
717 // System instructions which do not have an Rt register.
718 class SimpleSystemI<bit L, dag iops, string asm, string operands>
719 : BaseSystemI<L, (outs), iops, asm, operands> {
720 let Inst{4-0} = 0b11111;
723 // System instructions which have an Rt register.
724 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
725 : BaseSystemI<L, oops, iops, asm, operands>,
731 // Hint instructions that take both a CRm and a 3-bit immediate.
732 class HintI<string mnemonic>
733 : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#" $imm", "">,
736 let Inst{20-12} = 0b000110010;
737 let Inst{11-5} = imm;
740 // System instructions taking a single literal operand which encodes into
741 // CRm. op2 differentiates the opcodes.
742 def BarrierAsmOperand : AsmOperandClass {
743 let Name = "Barrier";
744 let ParserMethod = "tryParseBarrierOperand";
746 def barrier_op : Operand<i32> {
747 let PrintMethod = "printBarrierOption";
748 let ParserMatchClass = BarrierAsmOperand;
750 class CRmSystemI<Operand crmtype, bits<3> opc, string asm>
751 : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm">,
752 Sched<[WriteBarrier]> {
754 let Inst{20-12} = 0b000110011;
755 let Inst{11-8} = CRm;
759 // MRS/MSR system instructions. These have different operand classes because
760 // a different subset of registers can be accessed through each instruction.
761 def MRSSystemRegisterOperand : AsmOperandClass {
762 let Name = "MRSSystemRegister";
763 let ParserMethod = "tryParseSysReg";
764 let DiagnosticType = "MRS";
766 // concatenation of 1, op0, op1, CRn, CRm, op2. 16-bit immediate.
767 def mrs_sysreg_op : Operand<i32> {
768 let ParserMatchClass = MRSSystemRegisterOperand;
769 let DecoderMethod = "DecodeMRSSystemRegister";
770 let PrintMethod = "printMRSSystemRegister";
773 def MSRSystemRegisterOperand : AsmOperandClass {
774 let Name = "MSRSystemRegister";
775 let ParserMethod = "tryParseSysReg";
776 let DiagnosticType = "MSR";
778 def msr_sysreg_op : Operand<i32> {
779 let ParserMatchClass = MSRSystemRegisterOperand;
780 let DecoderMethod = "DecodeMSRSystemRegister";
781 let PrintMethod = "printMSRSystemRegister";
784 class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
785 "mrs", "\t$Rt, $systemreg"> {
788 let Inst{19-5} = systemreg;
791 // FIXME: Some of these def NZCV, others don't. Best way to model that?
792 // Explicitly modeling each of the system register as a register class
793 // would do it, but feels like overkill at this point.
794 class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
795 "msr", "\t$systemreg, $Rt"> {
798 let Inst{19-5} = systemreg;
801 def SystemPStateFieldOperand : AsmOperandClass {
802 let Name = "SystemPStateField";
803 let ParserMethod = "tryParseSysReg";
805 def pstatefield_op : Operand<i32> {
806 let ParserMatchClass = SystemPStateFieldOperand;
807 let PrintMethod = "printSystemPStateField";
812 : SimpleSystemI<0, (ins pstatefield_op:$pstate_field, imm0_15:$imm),
813 "msr", "\t$pstate_field, $imm">,
817 let Inst{20-19} = 0b00;
818 let Inst{18-16} = pstatefield{5-3};
819 let Inst{15-12} = 0b0100;
820 let Inst{11-8} = imm;
821 let Inst{7-5} = pstatefield{2-0};
823 let DecoderMethod = "DecodeSystemPStateInstruction";
826 // SYS and SYSL generic system instructions.
827 def SysCRAsmOperand : AsmOperandClass {
829 let ParserMethod = "tryParseSysCROperand";
832 def sys_cr_op : Operand<i32> {
833 let PrintMethod = "printSysCROperand";
834 let ParserMatchClass = SysCRAsmOperand;
837 class SystemXtI<bit L, string asm>
838 : RtSystemI<L, (outs),
839 (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
840 asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> {
845 let Inst{20-19} = 0b01;
846 let Inst{18-16} = op1;
847 let Inst{15-12} = Cn;
852 class SystemLXtI<bit L, string asm>
853 : RtSystemI<L, (outs),
854 (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
855 asm, "\t$Rt, $op1, $Cn, $Cm, $op2"> {
860 let Inst{20-19} = 0b01;
861 let Inst{18-16} = op1;
862 let Inst{15-12} = Cn;
868 // Branch (register) instructions:
876 // otherwise UNDEFINED
877 class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
878 string operands, list<dag> pattern>
879 : I<oops, iops, asm, operands, "", pattern>, Sched<[WriteBrReg]> {
880 let Inst{31-25} = 0b1101011;
881 let Inst{24-21} = opc;
882 let Inst{20-16} = 0b11111;
883 let Inst{15-10} = 0b000000;
884 let Inst{4-0} = 0b00000;
887 class BranchReg<bits<4> opc, string asm, list<dag> pattern>
888 : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
893 let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in
894 class SpecialReturn<bits<4> opc, string asm>
895 : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
896 let Inst{9-5} = 0b11111;
900 // Conditional branch instruction.
902 // Branch condition code.
903 // 4-bit immediate. Pretty-printed as .<cc>
904 def dotCcode : Operand<i32> {
905 let PrintMethod = "printDotCondCode";
908 // Conditional branch target. 19-bit immediate. The low two bits of the target
909 // offset are implied zero and so are not part of the immediate.
910 def PCRelLabel19Operand : AsmOperandClass {
911 let Name = "PCRelLabel19";
913 def am_brcond : Operand<OtherVT> {
914 let EncoderMethod = "getCondBranchTargetOpValue";
915 let DecoderMethod = "DecodePCRelLabel19";
916 let PrintMethod = "printAlignedLabel";
917 let ParserMatchClass = PCRelLabel19Operand;
920 class BranchCond : I<(outs), (ins dotCcode:$cond, am_brcond:$target),
921 "b", "$cond\t$target", "",
922 [(ARM64brcond bb:$target, imm:$cond, NZCV)]>,
925 let isTerminator = 1;
930 let Inst{31-24} = 0b01010100;
931 let Inst{23-5} = target;
933 let Inst{3-0} = cond;
937 // Compare-and-branch instructions.
939 class BaseCmpBranch<RegisterClass regtype, bit op, string asm, SDNode node>
940 : I<(outs), (ins regtype:$Rt, am_brcond:$target),
941 asm, "\t$Rt, $target", "",
942 [(node regtype:$Rt, bb:$target)]>,
945 let isTerminator = 1;
949 let Inst{30-25} = 0b011010;
951 let Inst{23-5} = target;
955 multiclass CmpBranch<bit op, string asm, SDNode node> {
956 def W : BaseCmpBranch<GPR32, op, asm, node> {
959 def X : BaseCmpBranch<GPR64, op, asm, node> {
965 // Test-bit-and-branch instructions.
967 // Test-and-branch target. 14-bit sign-extended immediate. The low two bits of
968 // the target offset are implied zero and so are not part of the immediate.
969 def BranchTarget14Operand : AsmOperandClass {
970 let Name = "BranchTarget14";
972 def am_tbrcond : Operand<OtherVT> {
973 let EncoderMethod = "getTestBranchTargetOpValue";
974 let PrintMethod = "printAlignedLabel";
975 let ParserMatchClass = BranchTarget14Operand;
978 class TestBranch<bit op, string asm, SDNode node>
979 : I<(outs), (ins GPR64:$Rt, imm0_63:$bit_off, am_tbrcond:$target),
980 asm, "\t$Rt, $bit_off, $target", "",
981 [(node GPR64:$Rt, imm0_63:$bit_off, bb:$target)]>,
984 let isTerminator = 1;
990 let Inst{31} = bit_off{5};
991 let Inst{30-25} = 0b011011;
993 let Inst{23-19} = bit_off{4-0};
994 let Inst{18-5} = target;
997 let DecoderMethod = "DecodeTestAndBranch";
1001 // Unconditional branch (immediate) instructions.
1003 def BranchTarget26Operand : AsmOperandClass {
1004 let Name = "BranchTarget26";
1006 def am_b_target : Operand<OtherVT> {
1007 let EncoderMethod = "getBranchTargetOpValue";
1008 let PrintMethod = "printAlignedLabel";
1009 let ParserMatchClass = BranchTarget26Operand;
1011 def am_bl_target : Operand<i64> {
1012 let EncoderMethod = "getBranchTargetOpValue";
1013 let PrintMethod = "printAlignedLabel";
1014 let ParserMatchClass = BranchTarget26Operand;
1017 class BImm<bit op, dag iops, string asm, list<dag> pattern>
1018 : I<(outs), iops, asm, "\t$addr", "", pattern>, Sched<[WriteBr]> {
1021 let Inst{30-26} = 0b00101;
1022 let Inst{25-0} = addr;
1024 let DecoderMethod = "DecodeUnconditionalBranch";
1027 class BranchImm<bit op, string asm, list<dag> pattern>
1028 : BImm<op, (ins am_b_target:$addr), asm, pattern>;
1029 class CallImm<bit op, string asm, list<dag> pattern>
1030 : BImm<op, (ins am_bl_target:$addr), asm, pattern>;
1033 // Basic one-operand data processing instructions.
1036 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1037 class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
1038 SDPatternOperator node>
1039 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
1040 [(set regtype:$Rd, (node regtype:$Rn))]>,
1045 let Inst{30-13} = 0b101101011000000000;
1046 let Inst{12-10} = opc;
1051 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1052 multiclass OneOperandData<bits<3> opc, string asm,
1053 SDPatternOperator node = null_frag> {
1054 def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
1058 def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
1063 class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
1064 : BaseOneOperandData<opc, GPR32, asm, node> {
1068 class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
1069 : BaseOneOperandData<opc, GPR64, asm, node> {
1074 // Basic two-operand data processing instructions.
1076 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1078 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1079 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1085 let Inst{30} = isSub;
1086 let Inst{28-21} = 0b11010000;
1087 let Inst{20-16} = Rm;
1088 let Inst{15-10} = 0;
1093 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
1095 : BaseBaseAddSubCarry<isSub, regtype, asm,
1096 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;
1098 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
1100 : BaseBaseAddSubCarry<isSub, regtype, asm,
1101 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
1106 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
1107 SDNode OpNode, SDNode OpNode_setflags> {
1108 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
1112 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
1118 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
1123 def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
1130 class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
1131 SDPatternOperator OpNode>
1132 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1133 asm, "\t$Rd, $Rn, $Rm", "",
1134 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]> {
1138 let Inst{30-21} = 0b0011010110;
1139 let Inst{20-16} = Rm;
1140 let Inst{15-14} = 0b00;
1141 let Inst{13-10} = opc;
1146 class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
1147 SDPatternOperator OpNode>
1148 : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
1149 let Inst{10} = isSigned;
1152 multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
1153 def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
1154 Sched<[WriteID32]> {
1157 def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
1158 Sched<[WriteID64]> {
1163 class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
1164 SDPatternOperator OpNode = null_frag>
1165 : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
1167 let Inst{11-10} = shift_type;
1170 multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
1171 def Wr : BaseShift<shift_type, GPR32, asm> {
1175 def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
1179 def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
1180 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
1181 (EXTRACT_SUBREG i64:$Rm, sub_32))>;
1183 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
1184 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1186 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
1187 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1189 def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
1190 (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;
1193 class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
1194 : InstAlias<asm#" $dst, $src1, $src2",
1195 (inst regtype:$dst, regtype:$src1, regtype:$src2)>;
1197 class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
1198 RegisterClass addtype, string asm,
1200 : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
1201 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
1206 let Inst{30-24} = 0b0011011;
1207 let Inst{23-21} = opc;
1208 let Inst{20-16} = Rm;
1209 let Inst{15} = isSub;
1210 let Inst{14-10} = Ra;
1215 multiclass MulAccum<bit isSub, string asm, SDNode AccNode> {
1216 def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm,
1217 [(set GPR32:$Rd, (AccNode GPR32:$Ra, (mul GPR32:$Rn, GPR32:$Rm)))]>,
1218 Sched<[WriteIM32]> {
1222 def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm,
1223 [(set GPR64:$Rd, (AccNode GPR64:$Ra, (mul GPR64:$Rn, GPR64:$Rm)))]>,
1224 Sched<[WriteIM64]> {
1229 class WideMulAccum<bit isSub, bits<3> opc, string asm,
1230 SDNode AccNode, SDNode ExtNode>
1231 : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
1232 [(set GPR64:$Rd, (AccNode GPR64:$Ra,
1233 (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
1234 Sched<[WriteIM32]> {
1238 class MulHi<bits<3> opc, string asm, SDNode OpNode>
1239 : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
1240 asm, "\t$Rd, $Rn, $Rm", "",
1241 [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
1242 Sched<[WriteIM64]> {
1246 let Inst{31-24} = 0b10011011;
1247 let Inst{23-21} = opc;
1248 let Inst{20-16} = Rm;
1253 // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
1254 // (i.e. all bits 1) but is ignored by the processor.
1255 let PostEncoderMethod = "fixMulHigh";
1258 class MulAccumWAlias<string asm, Instruction inst>
1259 : InstAlias<asm#" $dst, $src1, $src2",
1260 (inst GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR)>;
1261 class MulAccumXAlias<string asm, Instruction inst>
1262 : InstAlias<asm#" $dst, $src1, $src2",
1263 (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
1264 class WideMulAccumAlias<string asm, Instruction inst>
1265 : InstAlias<asm#" $dst, $src1, $src2",
1266 (inst GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR)>;
1268 class BaseCRC32<bit sf, bits<2> sz, bit C, RegisterClass StreamReg,
1269 SDPatternOperator OpNode, string asm>
1270 : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
1271 asm, "\t$Rd, $Rn, $Rm", "",
1272 [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
1273 Sched<[WriteISReg]> {
1279 let Inst{30-21} = 0b0011010110;
1280 let Inst{20-16} = Rm;
1281 let Inst{15-13} = 0b010;
1283 let Inst{11-10} = sz;
1286 let Predicates = [HasCRC];
1290 // Address generation.
1293 class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
1294 : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "",
1299 let Inst{31} = page;
1300 let Inst{30-29} = label{1-0};
1301 let Inst{28-24} = 0b10000;
1302 let Inst{23-5} = label{20-2};
1305 let DecoderMethod = "DecodeAdrInstruction";
1312 def movimm32_imm : Operand<i32> {
1313 let ParserMatchClass = Imm0_65535Operand;
1314 let EncoderMethod = "getMoveWideImmOpValue";
1315 let PrintMethod = "printHexImm";
1317 def movimm32_shift : Operand<i32> {
1318 let PrintMethod = "printShifter";
1319 let ParserMatchClass = MovImm32ShifterOperand;
1321 def movimm64_shift : Operand<i32> {
1322 let PrintMethod = "printShifter";
1323 let ParserMatchClass = MovImm64ShifterOperand;
1326 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1327 class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1329 : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
1330 asm, "\t$Rd, $imm$shift", "", []>,
1335 let Inst{30-29} = opc;
1336 let Inst{28-23} = 0b100101;
1337 let Inst{22-21} = shift{5-4};
1338 let Inst{20-5} = imm;
1341 let DecoderMethod = "DecodeMoveImmInstruction";
1344 multiclass MoveImmediate<bits<2> opc, string asm> {
1345 def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
1349 def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
1354 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1355 class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
1357 : I<(outs regtype:$Rd),
1358 (ins regtype:$src, movimm32_imm:$imm, shifter:$shift),
1359 asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
1364 let Inst{30-29} = opc;
1365 let Inst{28-23} = 0b100101;
1366 let Inst{22-21} = shift{5-4};
1367 let Inst{20-5} = imm;
1370 let DecoderMethod = "DecodeMoveImmInstruction";
1373 multiclass InsertImmediate<bits<2> opc, string asm> {
1374 def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
1378 def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
1387 class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
1388 RegisterClass srcRegtype, addsub_shifted_imm immtype,
1389 string asm, SDPatternOperator OpNode>
1390 : I<(outs dstRegtype:$Rd), (ins srcRegtype:$Rn, immtype:$imm),
1391 asm, "\t$Rd, $Rn, $imm", "",
1392 [(set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))]>,
1397 let Inst{30} = isSub;
1398 let Inst{29} = setFlags;
1399 let Inst{28-24} = 0b10001;
1400 let Inst{23-22} = imm{13-12}; // '00' => lsl #0, '01' => lsl #12
1401 let Inst{21-10} = imm{11-0};
1404 let DecoderMethod = "DecodeBaseAddSubImm";
1407 class BaseAddSubRegPseudo<RegisterClass regtype,
1408 SDPatternOperator OpNode>
1409 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1410 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1413 class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
1414 arith_shifted_reg shifted_regtype, string asm,
1415 SDPatternOperator OpNode>
1416 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1417 asm, "\t$Rd, $Rn, $Rm", "",
1418 [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
1419 Sched<[WriteISReg]> {
1420 // The operands are in order to match the 'addr' MI operands, so we
1421 // don't need an encoder method and by-name matching. Just use the default
1422 // in-order handling. Since we're using by-order, make sure the names
1428 let Inst{30} = isSub;
1429 let Inst{29} = setFlags;
1430 let Inst{28-24} = 0b01011;
1431 let Inst{23-22} = shift{7-6};
1433 let Inst{20-16} = src2;
1434 let Inst{15-10} = shift{5-0};
1435 let Inst{9-5} = src1;
1436 let Inst{4-0} = dst;
1438 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1441 class BaseAddSubEReg<bit isSub, bit setFlags, RegisterClass dstRegtype,
1442 RegisterClass src1Regtype, Operand src2Regtype,
1443 string asm, SDPatternOperator OpNode>
1444 : I<(outs dstRegtype:$R1),
1445 (ins src1Regtype:$R2, src2Regtype:$R3),
1446 asm, "\t$R1, $R2, $R3", "",
1447 [(set dstRegtype:$R1, (OpNode src1Regtype:$R2, src2Regtype:$R3))]>,
1448 Sched<[WriteIEReg]> {
1453 let Inst{30} = isSub;
1454 let Inst{29} = setFlags;
1455 let Inst{28-24} = 0b01011;
1456 let Inst{23-21} = 0b001;
1457 let Inst{20-16} = Rm;
1458 let Inst{15-13} = ext{5-3};
1459 let Inst{12-10} = ext{2-0};
1463 let DecoderMethod = "DecodeAddSubERegInstruction";
1466 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1467 class BaseAddSubEReg64<bit isSub, bit setFlags, RegisterClass dstRegtype,
1468 RegisterClass src1Regtype, RegisterClass src2Regtype,
1469 Operand ext_op, string asm>
1470 : I<(outs dstRegtype:$Rd),
1471 (ins src1Regtype:$Rn, src2Regtype:$Rm, ext_op:$ext),
1472 asm, "\t$Rd, $Rn, $Rm$ext", "", []>,
1473 Sched<[WriteIEReg]> {
1478 let Inst{30} = isSub;
1479 let Inst{29} = setFlags;
1480 let Inst{28-24} = 0b01011;
1481 let Inst{23-21} = 0b001;
1482 let Inst{20-16} = Rm;
1483 let Inst{15} = ext{5};
1484 let Inst{12-10} = ext{2-0};
1488 let DecoderMethod = "DecodeAddSubERegInstruction";
1491 // Aliases for register+register add/subtract.
1492 class AddSubRegAlias<string asm, Instruction inst, RegisterClass dstRegtype,
1493 RegisterClass src1Regtype, RegisterClass src2Regtype,
1495 : InstAlias<asm#" $dst, $src1, $src2",
1496 (inst dstRegtype:$dst, src1Regtype:$src1, src2Regtype:$src2,
1499 multiclass AddSub<bit isSub, string mnemonic,
1500 SDPatternOperator OpNode = null_frag> {
1501 let hasSideEffects = 0 in {
1502 // Add/Subtract immediate
1503 def Wri : BaseAddSubImm<isSub, 0, GPR32sp, GPR32sp, addsub_shifted_imm32,
1507 def Xri : BaseAddSubImm<isSub, 0, GPR64sp, GPR64sp, addsub_shifted_imm64,
1512 // Add/Subtract register - Only used for CodeGen
1513 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1514 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1516 // Add/Subtract shifted register
1517 def Wrs : BaseAddSubSReg<isSub, 0, GPR32, arith_shifted_reg32, mnemonic,
1521 def Xrs : BaseAddSubSReg<isSub, 0, GPR64, arith_shifted_reg64, mnemonic,
1527 // Add/Subtract extended register
1528 let AddedComplexity = 1, hasSideEffects = 0 in {
1529 def Wrx : BaseAddSubEReg<isSub, 0, GPR32sp, GPR32sp,
1530 arith_extended_reg32<i32>, mnemonic, OpNode> {
1533 def Xrx : BaseAddSubEReg<isSub, 0, GPR64sp, GPR64sp,
1534 arith_extended_reg32to64<i64>, mnemonic, OpNode> {
1539 def Xrx64 : BaseAddSubEReg64<isSub, 0, GPR64sp, GPR64sp, GPR64,
1540 arith_extendlsl64, mnemonic> {
1541 // UXTX and SXTX only.
1542 let Inst{14-13} = 0b11;
1546 // Register/register aliases with no shift when SP is not used.
1547 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1548 GPR32, GPR32, GPR32, 0>;
1549 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1550 GPR64, GPR64, GPR64, 0>;
1552 // Register/register aliases with no shift when either the destination or
1553 // first source register is SP. This relies on the shifted register aliases
1554 // above matching first in the case when SP is not used.
1555 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1556 GPR32sp, GPR32sp, GPR32, 16>; // UXTW #0
1557 def : AddSubRegAlias<mnemonic,
1558 !cast<Instruction>(NAME#"Xrx64"),
1559 GPR64sp, GPR64sp, GPR64, 24>; // UXTX #0
1562 multiclass AddSubS<bit isSub, string mnemonic, SDNode OpNode, string cmp> {
1563 let isCompare = 1, Defs = [NZCV] in {
1564 // Add/Subtract immediate
1565 def Wri : BaseAddSubImm<isSub, 1, GPR32, GPR32sp, addsub_shifted_imm32,
1569 def Xri : BaseAddSubImm<isSub, 1, GPR64, GPR64sp, addsub_shifted_imm64,
1574 // Add/Subtract register
1575 def Wrr : BaseAddSubRegPseudo<GPR32, OpNode>;
1576 def Xrr : BaseAddSubRegPseudo<GPR64, OpNode>;
1578 // Add/Subtract shifted register
1579 def Wrs : BaseAddSubSReg<isSub, 1, GPR32, arith_shifted_reg32, mnemonic,
1583 def Xrs : BaseAddSubSReg<isSub, 1, GPR64, arith_shifted_reg64, mnemonic,
1588 // Add/Subtract extended register
1589 let AddedComplexity = 1 in {
1590 def Wrx : BaseAddSubEReg<isSub, 1, GPR32, GPR32sp,
1591 arith_extended_reg32<i32>, mnemonic, OpNode> {
1594 def Xrx : BaseAddSubEReg<isSub, 1, GPR64, GPR64sp,
1595 arith_extended_reg32<i64>, mnemonic, OpNode> {
1600 def Xrx64 : BaseAddSubEReg64<isSub, 1, GPR64, GPR64sp, GPR64,
1601 arith_extendlsl64, mnemonic> {
1602 // UXTX and SXTX only.
1603 let Inst{14-13} = 0b11;
1609 def : InstAlias<cmp#" $src, $imm", (!cast<Instruction>(NAME#"Wri")
1610 WZR, GPR32sp:$src, addsub_shifted_imm32:$imm)>;
1611 def : InstAlias<cmp#" $src, $imm", (!cast<Instruction>(NAME#"Xri")
1612 XZR, GPR64sp:$src, addsub_shifted_imm64:$imm)>;
1613 def : InstAlias<cmp#" $src1, $src2, $sh", (!cast<Instruction>(NAME#"Wrx")
1614 WZR, GPR32sp:$src1, GPR32:$src2, arith_extend:$sh)>;
1615 def : InstAlias<cmp#" $src1, $src2, $sh", (!cast<Instruction>(NAME#"Xrx")
1616 XZR, GPR64sp:$src1, GPR32:$src2, arith_extend:$sh)>;
1617 def : InstAlias<cmp#" $src1, $src2, $sh", (!cast<Instruction>(NAME#"Xrx64")
1618 XZR, GPR64sp:$src1, GPR64:$src2, arith_extendlsl64:$sh)>;
1619 def : InstAlias<cmp#" $src1, $src2, $sh", (!cast<Instruction>(NAME#"Wrs")
1620 WZR, GPR32:$src1, GPR32:$src2, arith_shift32:$sh)>;
1621 def : InstAlias<cmp#" $src1, $src2, $sh", (!cast<Instruction>(NAME#"Xrs")
1622 XZR, GPR64:$src1, GPR64:$src2, arith_shift64:$sh)>;
1624 // Compare shorthands
1625 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Wrs")
1626 WZR, GPR32:$src1, GPR32:$src2, 0)>;
1627 def : InstAlias<cmp#" $src1, $src2", (!cast<Instruction>(NAME#"Xrs")
1628 XZR, GPR64:$src1, GPR64:$src2, 0)>;
1630 // Register/register aliases with no shift when SP is not used.
1631 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrs"),
1632 GPR32, GPR32, GPR32, 0>;
1633 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Xrs"),
1634 GPR64, GPR64, GPR64, 0>;
1636 // Register/register aliases with no shift when the first source register
1637 // is SP. This relies on the shifted register aliases above matching first
1638 // in the case when SP is not used.
1639 def : AddSubRegAlias<mnemonic, !cast<Instruction>(NAME#"Wrx"),
1640 GPR32, GPR32sp, GPR32, 16>; // UXTW #0
1641 def : AddSubRegAlias<mnemonic,
1642 !cast<Instruction>(NAME#"Xrx64"),
1643 GPR64, GPR64sp, GPR64, 24>; // UXTX #0
1649 def SDTA64EXTR : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>,
1651 def ARM64Extr : SDNode<"ARM64ISD::EXTR", SDTA64EXTR>;
1653 class BaseExtractImm<RegisterClass regtype, Operand imm_type, string asm,
1655 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, imm_type:$imm),
1656 asm, "\t$Rd, $Rn, $Rm, $imm", "", patterns>,
1657 Sched<[WriteExtr, ReadExtrHi]> {
1663 let Inst{30-23} = 0b00100111;
1665 let Inst{20-16} = Rm;
1666 let Inst{15-10} = imm;
1671 multiclass ExtractImm<string asm> {
1672 def Wrri : BaseExtractImm<GPR32, imm0_31, asm,
1674 (ARM64Extr GPR32:$Rn, GPR32:$Rm, imm0_31:$imm))]> {
1677 // imm<5> must be zero.
1680 def Xrri : BaseExtractImm<GPR64, imm0_63, asm,
1682 (ARM64Extr GPR64:$Rn, GPR64:$Rm, imm0_63:$imm))]> {
1693 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1694 class BaseBitfieldImm<bits<2> opc,
1695 RegisterClass regtype, Operand imm_type, string asm>
1696 : I<(outs regtype:$Rd), (ins regtype:$Rn, imm_type:$immr, imm_type:$imms),
1697 asm, "\t$Rd, $Rn, $immr, $imms", "", []>,
1704 let Inst{30-29} = opc;
1705 let Inst{28-23} = 0b100110;
1706 let Inst{21-16} = immr;
1707 let Inst{15-10} = imms;
1712 multiclass BitfieldImm<bits<2> opc, string asm> {
1713 def Wri : BaseBitfieldImm<opc, GPR32, imm0_31, asm> {
1716 // imms<5> and immr<5> must be zero, else ReservedValue().
1720 def Xri : BaseBitfieldImm<opc, GPR64, imm0_63, asm> {
1726 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1727 class BaseBitfieldImmWith2RegArgs<bits<2> opc,
1728 RegisterClass regtype, Operand imm_type, string asm>
1729 : I<(outs regtype:$Rd), (ins regtype:$src, regtype:$Rn, imm_type:$immr,
1731 asm, "\t$Rd, $Rn, $immr, $imms", "$src = $Rd", []>,
1738 let Inst{30-29} = opc;
1739 let Inst{28-23} = 0b100110;
1740 let Inst{21-16} = immr;
1741 let Inst{15-10} = imms;
1746 multiclass BitfieldImmWith2RegArgs<bits<2> opc, string asm> {
1747 def Wri : BaseBitfieldImmWith2RegArgs<opc, GPR32, imm0_31, asm> {
1750 // imms<5> and immr<5> must be zero, else ReservedValue().
1754 def Xri : BaseBitfieldImmWith2RegArgs<opc, GPR64, imm0_63, asm> {
1764 // Logical (immediate)
1765 class BaseLogicalImm<bits<2> opc, RegisterClass dregtype,
1766 RegisterClass sregtype, Operand imm_type, string asm,
1768 : I<(outs dregtype:$Rd), (ins sregtype:$Rn, imm_type:$imm),
1769 asm, "\t$Rd, $Rn, $imm", "", pattern>,
1774 let Inst{30-29} = opc;
1775 let Inst{28-23} = 0b100100;
1776 let Inst{22} = imm{12};
1777 let Inst{21-16} = imm{11-6};
1778 let Inst{15-10} = imm{5-0};
1782 let DecoderMethod = "DecodeLogicalImmInstruction";
1785 // Logical (shifted register)
1786 class BaseLogicalSReg<bits<2> opc, bit N, RegisterClass regtype,
1787 logical_shifted_reg shifted_regtype, string asm,
1789 : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
1790 asm, "\t$Rd, $Rn, $Rm", "", pattern>,
1791 Sched<[WriteISReg]> {
1792 // The operands are in order to match the 'addr' MI operands, so we
1793 // don't need an encoder method and by-name matching. Just use the default
1794 // in-order handling. Since we're using by-order, make sure the names
1800 let Inst{30-29} = opc;
1801 let Inst{28-24} = 0b01010;
1802 let Inst{23-22} = shift{7-6};
1804 let Inst{20-16} = src2;
1805 let Inst{15-10} = shift{5-0};
1806 let Inst{9-5} = src1;
1807 let Inst{4-0} = dst;
1809 let DecoderMethod = "DecodeThreeAddrSRegInstruction";
1812 // Aliases for register+register logical instructions.
1813 class LogicalRegAlias<string asm, Instruction inst, RegisterClass regtype>
1814 : InstAlias<asm#" $dst, $src1, $src2",
1815 (inst regtype:$dst, regtype:$src1, regtype:$src2, 0)>;
1817 let AddedComplexity = 6 in
1818 multiclass LogicalImm<bits<2> opc, string mnemonic, SDNode OpNode> {
1819 def Wri : BaseLogicalImm<opc, GPR32sp, GPR32, logical_imm32, mnemonic,
1820 [(set GPR32sp:$Rd, (OpNode GPR32:$Rn,
1821 logical_imm32:$imm))]> {
1823 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1825 def Xri : BaseLogicalImm<opc, GPR64sp, GPR64, logical_imm64, mnemonic,
1826 [(set GPR64sp:$Rd, (OpNode GPR64:$Rn,
1827 logical_imm64:$imm))]> {
1832 multiclass LogicalImmS<bits<2> opc, string mnemonic, SDNode OpNode> {
1833 let isCompare = 1, Defs = [NZCV] in {
1834 def Wri : BaseLogicalImm<opc, GPR32, GPR32, logical_imm32, mnemonic,
1835 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_imm32:$imm))]> {
1837 let Inst{22} = 0; // 64-bit version has an additional bit of immediate.
1839 def Xri : BaseLogicalImm<opc, GPR64, GPR64, logical_imm64, mnemonic,
1840 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_imm64:$imm))]> {
1843 } // end Defs = [NZCV]
1846 class BaseLogicalRegPseudo<RegisterClass regtype, SDPatternOperator OpNode>
1847 : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
1848 [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
1851 // Split from LogicalImm as not all instructions have both.
1852 multiclass LogicalReg<bits<2> opc, bit N, string mnemonic,
1853 SDPatternOperator OpNode> {
1854 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
1855 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
1857 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
1858 [(set GPR32:$Rd, (OpNode GPR32:$Rn,
1859 logical_shifted_reg32:$Rm))]> {
1862 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
1863 [(set GPR64:$Rd, (OpNode GPR64:$Rn,
1864 logical_shifted_reg64:$Rm))]> {
1868 def : LogicalRegAlias<mnemonic,
1869 !cast<Instruction>(NAME#"Wrs"), GPR32>;
1870 def : LogicalRegAlias<mnemonic,
1871 !cast<Instruction>(NAME#"Xrs"), GPR64>;
1874 // Split from LogicalReg to allow setting NZCV Defs
1875 multiclass LogicalRegS<bits<2> opc, bit N, string mnemonic,
1876 SDPatternOperator OpNode = null_frag> {
1877 let Defs = [NZCV], mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
1878 def Wrr : BaseLogicalRegPseudo<GPR32, OpNode>;
1879 def Xrr : BaseLogicalRegPseudo<GPR64, OpNode>;
1881 def Wrs : BaseLogicalSReg<opc, N, GPR32, logical_shifted_reg32, mnemonic,
1882 [(set GPR32:$Rd, (OpNode GPR32:$Rn, logical_shifted_reg32:$Rm))]> {
1885 def Xrs : BaseLogicalSReg<opc, N, GPR64, logical_shifted_reg64, mnemonic,
1886 [(set GPR64:$Rd, (OpNode GPR64:$Rn, logical_shifted_reg64:$Rm))]> {
1891 def : LogicalRegAlias<mnemonic,
1892 !cast<Instruction>(NAME#"Wrs"), GPR32>;
1893 def : LogicalRegAlias<mnemonic,
1894 !cast<Instruction>(NAME#"Xrs"), GPR64>;
1898 // Conditionally set flags
1902 // 4-bit immediate. Pretty-printed as <cc>
1903 def ccode : Operand<i32> {
1904 let PrintMethod = "printCondCode";
1907 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1908 class BaseCondSetFlagsImm<bit op, RegisterClass regtype, string asm>
1909 : I<(outs), (ins regtype:$Rn, imm0_31:$imm, imm0_15:$nzcv, ccode:$cond),
1910 asm, "\t$Rn, $imm, $nzcv, $cond", "", []>,
1921 let Inst{29-21} = 0b111010010;
1922 let Inst{20-16} = imm;
1923 let Inst{15-12} = cond;
1924 let Inst{11-10} = 0b10;
1927 let Inst{3-0} = nzcv;
1930 multiclass CondSetFlagsImm<bit op, string asm> {
1931 def Wi : BaseCondSetFlagsImm<op, GPR32, asm> {
1934 def Xi : BaseCondSetFlagsImm<op, GPR64, asm> {
1939 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1940 class BaseCondSetFlagsReg<bit op, RegisterClass regtype, string asm>
1941 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
1942 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
1953 let Inst{29-21} = 0b111010010;
1954 let Inst{20-16} = Rm;
1955 let Inst{15-12} = cond;
1956 let Inst{11-10} = 0b00;
1959 let Inst{3-0} = nzcv;
1962 multiclass CondSetFlagsReg<bit op, string asm> {
1963 def Wr : BaseCondSetFlagsReg<op, GPR32, asm> {
1966 def Xr : BaseCondSetFlagsReg<op, GPR64, asm> {
1972 // Conditional select
1975 class BaseCondSelect<bit op, bits<2> op2, RegisterClass regtype, string asm>
1976 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
1977 asm, "\t$Rd, $Rn, $Rm, $cond", "",
1979 (ARM64csel regtype:$Rn, regtype:$Rm, (i32 imm:$cond), NZCV))]>,
1989 let Inst{29-21} = 0b011010100;
1990 let Inst{20-16} = Rm;
1991 let Inst{15-12} = cond;
1992 let Inst{11-10} = op2;
1997 multiclass CondSelect<bit op, bits<2> op2, string asm> {
1998 def Wr : BaseCondSelect<op, op2, GPR32, asm> {
2001 def Xr : BaseCondSelect<op, op2, GPR64, asm> {
2006 class BaseCondSelectOp<bit op, bits<2> op2, RegisterClass regtype, string asm,
2008 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
2009 asm, "\t$Rd, $Rn, $Rm, $cond", "",
2011 (ARM64csel regtype:$Rn, (frag regtype:$Rm),
2012 (i32 imm:$cond), NZCV))]>,
2022 let Inst{29-21} = 0b011010100;
2023 let Inst{20-16} = Rm;
2024 let Inst{15-12} = cond;
2025 let Inst{11-10} = op2;
2030 def inv_cond_XFORM : SDNodeXForm<imm, [{
2031 ARM64CC::CondCode CC = static_cast<ARM64CC::CondCode>(N->getZExtValue());
2032 return CurDAG->getTargetConstant(ARM64CC::getInvertedCondCode(CC), MVT::i32);
2035 multiclass CondSelectOp<bit op, bits<2> op2, string asm, PatFrag frag> {
2036 def Wr : BaseCondSelectOp<op, op2, GPR32, asm, frag> {
2039 def Xr : BaseCondSelectOp<op, op2, GPR64, asm, frag> {
2043 def : Pat<(ARM64csel (frag GPR32:$Rm), GPR32:$Rn, (i32 imm:$cond), NZCV),
2044 (!cast<Instruction>(NAME # Wr) GPR32:$Rn, GPR32:$Rm,
2045 (inv_cond_XFORM imm:$cond))>;
2047 def : Pat<(ARM64csel (frag GPR64:$Rm), GPR64:$Rn, (i32 imm:$cond), NZCV),
2048 (!cast<Instruction>(NAME # Xr) GPR64:$Rn, GPR64:$Rm,
2049 (inv_cond_XFORM imm:$cond))>;
2053 // Special Mask Value
2055 def maski8_or_more : Operand<i32>,
2056 ImmLeaf<i32, [{ return (Imm & 0xff) == 0xff; }]> {
2058 def maski16_or_more : Operand<i32>,
2059 ImmLeaf<i32, [{ return (Imm & 0xffff) == 0xffff; }]> {
2067 // (unsigned immediate)
2068 // Indexed for 8-bit registers. offset is in range [0,4095].
2069 def MemoryIndexed8Operand : AsmOperandClass {
2070 let Name = "MemoryIndexed8";
2071 let DiagnosticType = "InvalidMemoryIndexed8";
2073 def am_indexed8 : Operand<i64>,
2074 ComplexPattern<i64, 2, "SelectAddrModeIndexed8", []> {
2075 let PrintMethod = "printAMIndexed<8>";
2077 = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale1>";
2078 let ParserMatchClass = MemoryIndexed8Operand;
2079 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
2082 // Indexed for 16-bit registers. offset is multiple of 2 in range [0,8190],
2083 // stored as immval/2 (the 12-bit literal that encodes directly into the insn).
2084 def MemoryIndexed16Operand : AsmOperandClass {
2085 let Name = "MemoryIndexed16";
2086 let DiagnosticType = "InvalidMemoryIndexed16";
2088 def am_indexed16 : Operand<i64>,
2089 ComplexPattern<i64, 2, "SelectAddrModeIndexed16", []> {
2090 let PrintMethod = "printAMIndexed<16>";
2092 = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale2>";
2093 let ParserMatchClass = MemoryIndexed16Operand;
2094 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
2097 // Indexed for 32-bit registers. offset is multiple of 4 in range [0,16380],
2098 // stored as immval/4 (the 12-bit literal that encodes directly into the insn).
2099 def MemoryIndexed32Operand : AsmOperandClass {
2100 let Name = "MemoryIndexed32";
2101 let DiagnosticType = "InvalidMemoryIndexed32";
2103 def am_indexed32 : Operand<i64>,
2104 ComplexPattern<i64, 2, "SelectAddrModeIndexed32", []> {
2105 let PrintMethod = "printAMIndexed<32>";
2107 = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale4>";
2108 let ParserMatchClass = MemoryIndexed32Operand;
2109 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
2112 // Indexed for 64-bit registers. offset is multiple of 8 in range [0,32760],
2113 // stored as immval/8 (the 12-bit literal that encodes directly into the insn).
2114 def MemoryIndexed64Operand : AsmOperandClass {
2115 let Name = "MemoryIndexed64";
2116 let DiagnosticType = "InvalidMemoryIndexed64";
2118 def am_indexed64 : Operand<i64>,
2119 ComplexPattern<i64, 2, "SelectAddrModeIndexed64", []> {
2120 let PrintMethod = "printAMIndexed<64>";
2122 = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale8>";
2123 let ParserMatchClass = MemoryIndexed64Operand;
2124 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
2127 // Indexed for 128-bit registers. offset is multiple of 16 in range [0,65520],
2128 // stored as immval/16 (the 12-bit literal that encodes directly into the insn).
2129 def MemoryIndexed128Operand : AsmOperandClass {
2130 let Name = "MemoryIndexed128";
2131 let DiagnosticType = "InvalidMemoryIndexed128";
2133 def am_indexed128 : Operand<i64>,
2134 ComplexPattern<i64, 2, "SelectAddrModeIndexed128", []> {
2135 let PrintMethod = "printAMIndexed<128>";
2137 = "getAMIndexed8OpValue<ARM64::fixup_arm64_ldst_imm12_scale16>";
2138 let ParserMatchClass = MemoryIndexed128Operand;
2139 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
2143 def MemoryNoIndexOperand : AsmOperandClass { let Name = "MemoryNoIndex"; }
2144 def am_noindex : Operand<i64>,
2145 ComplexPattern<i64, 1, "SelectAddrModeNoIndex", []> {
2146 let PrintMethod = "printAMNoIndex";
2147 let ParserMatchClass = MemoryNoIndexOperand;
2148 let MIOperandInfo = (ops GPR64sp:$base);
2151 class BaseLoadStoreUI<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2152 string asm, list<dag> pattern>
2153 : I<oops, iops, asm, "\t$Rt, $addr", "", pattern> {
2157 bits<5> base = addr{4-0};
2158 bits<12> offset = addr{16-5};
2160 let Inst{31-30} = sz;
2161 let Inst{29-27} = 0b111;
2163 let Inst{25-24} = 0b01;
2164 let Inst{23-22} = opc;
2165 let Inst{21-10} = offset;
2166 let Inst{9-5} = base;
2167 let Inst{4-0} = dst;
2169 let DecoderMethod = "DecodeUnsignedLdStInstruction";
2172 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2173 class LoadUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2174 Operand indextype, string asm, list<dag> pattern>
2175 : BaseLoadStoreUI<sz, V, opc,
2176 (outs regtype:$Rt), (ins indextype:$addr), asm, pattern>,
2179 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2180 class StoreUI<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2181 Operand indextype, string asm, list<dag> pattern>
2182 : BaseLoadStoreUI<sz, V, opc,
2183 (outs), (ins regtype:$Rt, indextype:$addr), asm, pattern>,
2186 def PrefetchOperand : AsmOperandClass {
2187 let Name = "Prefetch";
2188 let ParserMethod = "tryParsePrefetch";
2190 def prfop : Operand<i32> {
2191 let PrintMethod = "printPrefetchOp";
2192 let ParserMatchClass = PrefetchOperand;
2195 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2196 class PrefetchUI<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2197 : BaseLoadStoreUI<sz, V, opc,
2198 (outs), (ins prfop:$Rt, am_indexed64:$addr), asm, pat>,
2205 // Load literal address: 19-bit immediate. The low two bits of the target
2206 // offset are implied zero and so are not part of the immediate.
2207 def am_ldrlit : Operand<OtherVT> {
2208 let EncoderMethod = "getLoadLiteralOpValue";
2209 let DecoderMethod = "DecodePCRelLabel19";
2210 let PrintMethod = "printAlignedLabel";
2211 let ParserMatchClass = PCRelLabel19Operand;
2214 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2215 class LoadLiteral<bits<2> opc, bit V, RegisterClass regtype, string asm>
2216 : I<(outs regtype:$Rt), (ins am_ldrlit:$label),
2217 asm, "\t$Rt, $label", "", []>,
2221 let Inst{31-30} = opc;
2222 let Inst{29-27} = 0b011;
2224 let Inst{25-24} = 0b00;
2225 let Inst{23-5} = label;
2229 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2230 class PrefetchLiteral<bits<2> opc, bit V, string asm, list<dag> pat>
2231 : I<(outs), (ins prfop:$Rt, am_ldrlit:$label),
2232 asm, "\t$Rt, $label", "", pat>,
2236 let Inst{31-30} = opc;
2237 let Inst{29-27} = 0b011;
2239 let Inst{25-24} = 0b00;
2240 let Inst{23-5} = label;
2245 // Load/store register offset
2248 class MemROAsmOperand<int sz> : AsmOperandClass {
2249 let Name = "MemoryRegisterOffset"#sz;
2252 def MemROAsmOperand8 : MemROAsmOperand<8>;
2253 def MemROAsmOperand16 : MemROAsmOperand<16>;
2254 def MemROAsmOperand32 : MemROAsmOperand<32>;
2255 def MemROAsmOperand64 : MemROAsmOperand<64>;
2256 def MemROAsmOperand128 : MemROAsmOperand<128>;
2258 class ro_indexed<int sz> : Operand<i64> { // ComplexPattern<...>
2259 let PrintMethod = "printMemoryRegOffset<" # sz # ">";
2260 let MIOperandInfo = (ops GPR64sp:$base, GPR64:$offset, i32imm:$extend);
2263 def ro_indexed8 : ro_indexed<8>, ComplexPattern<i64, 3, "SelectAddrModeRO8", []> {
2264 let ParserMatchClass = MemROAsmOperand8;
2267 def ro_indexed16 : ro_indexed<16>, ComplexPattern<i64, 3, "SelectAddrModeRO16", []> {
2268 let ParserMatchClass = MemROAsmOperand16;
2271 def ro_indexed32 : ro_indexed<32>, ComplexPattern<i64, 3, "SelectAddrModeRO32", []> {
2272 let ParserMatchClass = MemROAsmOperand32;
2275 def ro_indexed64 : ro_indexed<64>, ComplexPattern<i64, 3, "SelectAddrModeRO64", []> {
2276 let ParserMatchClass = MemROAsmOperand64;
2279 def ro_indexed128 : ro_indexed<128>, ComplexPattern<i64, 3, "SelectAddrModeRO128", []> {
2280 let ParserMatchClass = MemROAsmOperand128;
2283 class LoadStore8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2284 string asm, dag ins, dag outs, list<dag> pat>
2285 : I<ins, outs, asm, "\t$Rt, $addr", "", pat> {
2286 // The operands are in order to match the 'addr' MI operands, so we
2287 // don't need an encoder method and by-name matching. Just use the default
2288 // in-order handling. Since we're using by-order, make sure the names
2294 let Inst{31-30} = sz;
2295 let Inst{29-27} = 0b111;
2297 let Inst{25-24} = 0b00;
2298 let Inst{23-22} = opc;
2300 let Inst{20-16} = offset;
2301 let Inst{15-13} = extend{3-1};
2303 let Inst{12} = extend{0};
2304 let Inst{11-10} = 0b10;
2305 let Inst{9-5} = base;
2306 let Inst{4-0} = dst;
2308 let DecoderMethod = "DecodeRegOffsetLdStInstruction";
2311 class Load8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2312 string asm, list<dag> pat>
2313 : LoadStore8RO<sz, V, opc, regtype, asm,
2314 (outs regtype:$Rt), (ins ro_indexed8:$addr), pat>,
2315 Sched<[WriteLDIdx, ReadAdrBase]>;
2317 class Store8RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2318 string asm, list<dag> pat>
2319 : LoadStore8RO<sz, V, opc, regtype, asm,
2320 (outs), (ins regtype:$Rt, ro_indexed8:$addr), pat>,
2321 Sched<[WriteSTIdx, ReadAdrBase]>;
2323 class LoadStore16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2324 string asm, dag ins, dag outs, list<dag> pat>
2325 : I<ins, outs, asm, "\t$Rt, $addr", "", pat> {
2326 // The operands are in order to match the 'addr' MI operands, so we
2327 // don't need an encoder method and by-name matching. Just use the default
2328 // in-order handling. Since we're using by-order, make sure the names
2334 let Inst{31-30} = sz;
2335 let Inst{29-27} = 0b111;
2337 let Inst{25-24} = 0b00;
2338 let Inst{23-22} = opc;
2340 let Inst{20-16} = offset;
2341 let Inst{15-13} = extend{3-1};
2343 let Inst{12} = extend{0};
2344 let Inst{11-10} = 0b10;
2345 let Inst{9-5} = base;
2346 let Inst{4-0} = dst;
2348 let DecoderMethod = "DecodeRegOffsetLdStInstruction";
2351 class Load16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2352 string asm, list<dag> pat>
2353 : LoadStore16RO<sz, V, opc, regtype, asm,
2354 (outs regtype:$Rt), (ins ro_indexed16:$addr), pat>,
2355 Sched<[WriteLDIdx, ReadAdrBase]>;
2357 class Store16RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2358 string asm, list<dag> pat>
2359 : LoadStore16RO<sz, V, opc, regtype, asm,
2360 (outs), (ins regtype:$Rt, ro_indexed16:$addr), pat>,
2361 Sched<[WriteSTIdx, ReadAdrBase]>;
2363 class LoadStore32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2364 string asm, dag ins, dag outs, list<dag> pat>
2365 : I<ins, outs, asm, "\t$Rt, $addr", "", pat> {
2366 // The operands are in order to match the 'addr' MI operands, so we
2367 // don't need an encoder method and by-name matching. Just use the default
2368 // in-order handling. Since we're using by-order, make sure the names
2374 let Inst{31-30} = sz;
2375 let Inst{29-27} = 0b111;
2377 let Inst{25-24} = 0b00;
2378 let Inst{23-22} = opc;
2380 let Inst{20-16} = offset;
2381 let Inst{15-13} = extend{3-1};
2383 let Inst{12} = extend{0};
2384 let Inst{11-10} = 0b10;
2385 let Inst{9-5} = base;
2386 let Inst{4-0} = dst;
2388 let DecoderMethod = "DecodeRegOffsetLdStInstruction";
2391 class Load32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2392 string asm, list<dag> pat>
2393 : LoadStore32RO<sz, V, opc, regtype, asm,
2394 (outs regtype:$Rt), (ins ro_indexed32:$addr), pat>,
2395 Sched<[WriteLDIdx, ReadAdrBase]>;
2397 class Store32RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2398 string asm, list<dag> pat>
2399 : LoadStore32RO<sz, V, opc, regtype, asm,
2400 (outs), (ins regtype:$Rt, ro_indexed32:$addr), pat>,
2401 Sched<[WriteSTIdx, ReadAdrBase]>;
2403 class LoadStore64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2404 string asm, dag ins, dag outs, list<dag> pat>
2405 : I<ins, outs, asm, "\t$Rt, $addr", "", pat> {
2406 // The operands are in order to match the 'addr' MI operands, so we
2407 // don't need an encoder method and by-name matching. Just use the default
2408 // in-order handling. Since we're using by-order, make sure the names
2414 let Inst{31-30} = sz;
2415 let Inst{29-27} = 0b111;
2417 let Inst{25-24} = 0b00;
2418 let Inst{23-22} = opc;
2420 let Inst{20-16} = offset;
2421 let Inst{15-13} = extend{3-1};
2423 let Inst{12} = extend{0};
2424 let Inst{11-10} = 0b10;
2425 let Inst{9-5} = base;
2426 let Inst{4-0} = dst;
2428 let DecoderMethod = "DecodeRegOffsetLdStInstruction";
2431 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2432 class Load64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2433 string asm, list<dag> pat>
2434 : LoadStore64RO<sz, V, opc, regtype, asm,
2435 (outs regtype:$Rt), (ins ro_indexed64:$addr), pat>,
2436 Sched<[WriteLDIdx, ReadAdrBase]>;
2438 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2439 class Store64RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2440 string asm, list<dag> pat>
2441 : LoadStore64RO<sz, V, opc, regtype, asm,
2442 (outs), (ins regtype:$Rt, ro_indexed64:$addr), pat>,
2443 Sched<[WriteSTIdx, ReadAdrBase]>;
2446 class LoadStore128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2447 string asm, dag ins, dag outs, list<dag> pat>
2448 : I<ins, outs, asm, "\t$Rt, $addr", "", pat> {
2449 // The operands are in order to match the 'addr' MI operands, so we
2450 // don't need an encoder method and by-name matching. Just use the default
2451 // in-order handling. Since we're using by-order, make sure the names
2457 let Inst{31-30} = sz;
2458 let Inst{29-27} = 0b111;
2460 let Inst{25-24} = 0b00;
2461 let Inst{23-22} = opc;
2463 let Inst{20-16} = offset;
2464 let Inst{15-13} = extend{3-1};
2466 let Inst{12} = extend{0};
2467 let Inst{11-10} = 0b10;
2468 let Inst{9-5} = base;
2469 let Inst{4-0} = dst;
2471 let DecoderMethod = "DecodeRegOffsetLdStInstruction";
2474 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
2475 class Load128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2476 string asm, list<dag> pat>
2477 : LoadStore128RO<sz, V, opc, regtype, asm,
2478 (outs regtype:$Rt), (ins ro_indexed128:$addr), pat>,
2479 Sched<[WriteLDIdx, ReadAdrBase]>;
2481 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
2482 class Store128RO<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2483 string asm, list<dag> pat>
2484 : LoadStore128RO<sz, V, opc, regtype, asm,
2485 (outs), (ins regtype:$Rt, ro_indexed128:$addr), pat>,
2486 Sched<[WriteSTIdx, ReadAdrBase]>;
2488 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2489 class PrefetchRO<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2490 : I<(outs), (ins prfop:$Rt, ro_indexed64:$addr), asm,
2491 "\t$Rt, $addr", "", pat>,
2493 // The operands are in order to match the 'addr' MI operands, so we
2494 // don't need an encoder method and by-name matching. Just use the default
2495 // in-order handling. Since we're using by-order, make sure the names
2501 let Inst{31-30} = sz;
2502 let Inst{29-27} = 0b111;
2504 let Inst{25-24} = 0b00;
2505 let Inst{23-22} = opc;
2507 let Inst{20-16} = offset;
2508 let Inst{15-13} = extend{3-1};
2510 let Inst{12} = extend{0};
2511 let Inst{11-10} = 0b10;
2512 let Inst{9-5} = base;
2513 let Inst{4-0} = dst;
2515 let DecoderMethod = "DecodeRegOffsetLdStInstruction";
2519 // Load/store unscaled immediate
2522 def MemoryUnscaledOperand : AsmOperandClass {
2523 let Name = "MemoryUnscaled";
2524 let DiagnosticType = "InvalidMemoryIndexedSImm9";
2526 class am_unscaled_operand : Operand<i64> {
2527 let PrintMethod = "printAMIndexed<8>";
2528 let ParserMatchClass = MemoryUnscaledOperand;
2529 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
2531 class am_unscaled_wb_operand : Operand<i64> {
2532 let PrintMethod = "printAMIndexedWB<8>";
2533 let ParserMatchClass = MemoryUnscaledOperand;
2534 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
2536 def am_unscaled : am_unscaled_operand;
2537 def am_unscaled_wb: am_unscaled_wb_operand;
2538 def am_unscaled8 : am_unscaled_operand,
2539 ComplexPattern<i64, 2, "SelectAddrModeUnscaled8", []>;
2540 def am_unscaled16 : am_unscaled_operand,
2541 ComplexPattern<i64, 2, "SelectAddrModeUnscaled16", []>;
2542 def am_unscaled32 : am_unscaled_operand,
2543 ComplexPattern<i64, 2, "SelectAddrModeUnscaled32", []>;
2544 def am_unscaled64 : am_unscaled_operand,
2545 ComplexPattern<i64, 2, "SelectAddrModeUnscaled64", []>;
2546 def am_unscaled128 : am_unscaled_operand,
2547 ComplexPattern<i64, 2, "SelectAddrModeUnscaled128", []>;
2549 class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2550 string asm, list<dag> pattern>
2551 : I<oops, iops, asm, "\t$Rt, $addr", "", pattern> {
2552 // The operands are in order to match the 'addr' MI operands, so we
2553 // don't need an encoder method and by-name matching. Just use the default
2554 // in-order handling. Since we're using by-order, make sure the names
2559 let Inst{31-30} = sz;
2560 let Inst{29-27} = 0b111;
2562 let Inst{25-24} = 0b00;
2563 let Inst{23-22} = opc;
2565 let Inst{20-12} = offset;
2566 let Inst{11-10} = 0b00;
2567 let Inst{9-5} = base;
2568 let Inst{4-0} = dst;
2570 let DecoderMethod = "DecodeSignedLdStInstruction";
2573 let AddedComplexity = 1 in // try this before LoadUI
2574 class LoadUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2575 Operand amtype, string asm, list<dag> pattern>
2576 : BaseLoadStoreUnscale<sz, V, opc, (outs regtype:$Rt),
2577 (ins amtype:$addr), asm, pattern>,
2580 let AddedComplexity = 1 in // try this before StoreUI
2581 class StoreUnscaled<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2582 Operand amtype, string asm, list<dag> pattern>
2583 : BaseLoadStoreUnscale<sz, V, opc, (outs),
2584 (ins regtype:$Rt, amtype:$addr), asm, pattern>,
2587 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
2588 class PrefetchUnscaled<bits<2> sz, bit V, bits<2> opc, string asm, list<dag> pat>
2589 : BaseLoadStoreUnscale<sz, V, opc, (outs),
2590 (ins prfop:$Rt, am_unscaled:$addr), asm, pat>,
2594 // Load/store unscaled immediate, unprivileged
2597 class BaseLoadStoreUnprivileged<bits<2> sz, bit V, bits<2> opc,
2598 dag oops, dag iops, string asm>
2599 : I<oops, iops, asm, "\t$Rt, $addr", "", []> {
2600 // The operands are in order to match the 'addr' MI operands, so we
2601 // don't need an encoder method and by-name matching. Just use the default
2602 // in-order handling. Since we're using by-order, make sure the names
2607 let Inst{31-30} = sz;
2608 let Inst{29-27} = 0b111;
2610 let Inst{25-24} = 0b00;
2611 let Inst{23-22} = opc;
2613 let Inst{20-12} = offset;
2614 let Inst{11-10} = 0b10;
2615 let Inst{9-5} = base;
2616 let Inst{4-0} = dst;
2618 let DecoderMethod = "DecodeSignedLdStInstruction";
2621 let mayStore = 0, mayLoad = 1, hasSideEffects = 0 in {
2622 class LoadUnprivileged<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2624 : BaseLoadStoreUnprivileged<sz, V, opc,
2625 (outs regtype:$Rt), (ins am_unscaled:$addr), asm>,
2629 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in {
2630 class StoreUnprivileged<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2632 : BaseLoadStoreUnprivileged<sz, V, opc,
2633 (outs), (ins regtype:$Rt, am_unscaled:$addr), asm>,
2638 // Load/store pre-indexed
2641 class BaseLoadStorePreIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2642 string asm, string cstr>
2643 : I<oops, iops, asm, "\t$Rt, $addr!", cstr, []> {
2644 // The operands are in order to match the 'addr' MI operands, so we
2645 // don't need an encoder method and by-name matching. Just use the default
2646 // in-order handling.
2650 let Inst{31-30} = sz;
2651 let Inst{29-27} = 0b111;
2653 let Inst{25-24} = 0;
2654 let Inst{23-22} = opc;
2656 let Inst{20-12} = offset;
2657 let Inst{11-10} = 0b11;
2658 let Inst{9-5} = base;
2659 let Inst{4-0} = dst;
2661 let DecoderMethod = "DecodeSignedLdStInstruction";
2664 let hasSideEffects = 0 in {
2665 let mayStore = 0, mayLoad = 1 in
2666 // FIXME: Modeling the write-back of these instructions for isel is tricky.
2667 // we need the complex addressing mode for the memory reference, but
2668 // we also need the write-back specified as a tied operand to the
2669 // base register. That combination does not play nicely with
2670 // the asm matcher and friends.
2671 class LoadPreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2673 : BaseLoadStorePreIdx<sz, V, opc,
2674 (outs regtype:$Rt/*, GPR64sp:$wback*/),
2675 (ins am_unscaled_wb:$addr), asm, ""/*"$addr.base = $wback"*/>,
2676 Sched<[WriteLD, WriteAdr]>;
2678 let mayStore = 1, mayLoad = 0 in
2679 class StorePreIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2681 : BaseLoadStorePreIdx<sz, V, opc,
2682 (outs/* GPR64sp:$wback*/),
2683 (ins regtype:$Rt, am_unscaled_wb:$addr),
2684 asm, ""/*"$addr.base = $wback"*/>,
2685 Sched<[WriteAdr, WriteST]>;
2686 } // hasSideEffects = 0
2688 // ISel pseudo-instructions which have the tied operands. When the MC lowering
2689 // logic finally gets smart enough to strip off tied operands that are just
2690 // for isel convenience, we can get rid of these pseudos and just reference
2691 // the real instructions directly.
2693 // Ironically, also because of the writeback operands, we can't put the
2694 // matcher pattern directly on the instruction, but need to define it
2697 // Loads aren't matched with patterns here at all, but rather in C++
2699 let mayStore = 0, mayLoad = 1, hasSideEffects = 0 in {
2700 class LoadPreIdxPseudo<RegisterClass regtype>
2701 : Pseudo<(outs regtype:$Rt, GPR64sp:$wback),
2702 (ins am_noindex:$addr, simm9:$offset), [],
2703 "$addr.base = $wback,@earlyclobber $wback">,
2704 Sched<[WriteLD, WriteAdr]>;
2705 class LoadPostIdxPseudo<RegisterClass regtype>
2706 : Pseudo<(outs regtype:$Rt, GPR64sp:$wback),
2707 (ins am_noindex:$addr, simm9:$offset), [],
2708 "$addr.base = $wback,@earlyclobber $wback">,
2709 Sched<[WriteLD, WriteI]>;
2711 multiclass StorePreIdxPseudo<RegisterClass regtype, ValueType Ty,
2712 SDPatternOperator OpNode> {
2713 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
2714 def _isel: Pseudo<(outs GPR64sp:$wback),
2715 (ins regtype:$Rt, am_noindex:$addr, simm9:$offset), [],
2716 "$addr.base = $wback,@earlyclobber $wback">,
2717 Sched<[WriteAdr, WriteST]>;
2719 def : Pat<(OpNode (Ty regtype:$Rt), am_noindex:$addr, simm9:$offset),
2720 (!cast<Instruction>(NAME#_isel) regtype:$Rt, am_noindex:$addr,
2725 // Load/store post-indexed
2728 // (pre-index) load/stores.
2729 class BaseLoadStorePostIdx<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
2730 string asm, string cstr>
2731 : I<oops, iops, asm, "\t$Rt, $addr, $idx", cstr, []> {
2732 // The operands are in order to match the 'addr' MI operands, so we
2733 // don't need an encoder method and by-name matching. Just use the default
2734 // in-order handling.
2738 let Inst{31-30} = sz;
2739 let Inst{29-27} = 0b111;
2741 let Inst{25-24} = 0b00;
2742 let Inst{23-22} = opc;
2744 let Inst{20-12} = offset;
2745 let Inst{11-10} = 0b01;
2746 let Inst{9-5} = base;
2747 let Inst{4-0} = dst;
2749 let DecoderMethod = "DecodeSignedLdStInstruction";
2752 let hasSideEffects = 0 in {
2753 let mayStore = 0, mayLoad = 1 in
2754 // FIXME: Modeling the write-back of these instructions for isel is tricky.
2755 // we need the complex addressing mode for the memory reference, but
2756 // we also need the write-back specified as a tied operand to the
2757 // base register. That combination does not play nicely with
2758 // the asm matcher and friends.
2759 class LoadPostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2761 : BaseLoadStorePostIdx<sz, V, opc,
2762 (outs regtype:$Rt/*, GPR64sp:$wback*/),
2763 (ins am_noindex:$addr, simm9:$idx),
2764 asm, ""/*"$addr.base = $wback"*/>,
2765 Sched<[WriteLD, WriteI]>;
2767 let mayStore = 1, mayLoad = 0 in
2768 class StorePostIdx<bits<2> sz, bit V, bits<2> opc, RegisterClass regtype,
2770 : BaseLoadStorePostIdx<sz, V, opc,
2771 (outs/* GPR64sp:$wback*/),
2772 (ins regtype:$Rt, am_noindex:$addr, simm9:$idx),
2773 asm, ""/*"$addr.base = $wback"*/>,
2774 Sched<[WriteAdr, WriteST, ReadAdrBase]>;
2775 } // hasSideEffects = 0
2777 // ISel pseudo-instructions which have the tied operands. When the MC lowering
2778 // logic finally gets smart enough to strip off tied operands that are just
2779 // for isel convenience, we can get rid of these pseudos and just reference
2780 // the real instructions directly.
2782 // Ironically, also because of the writeback operands, we can't put the
2783 // matcher pattern directly on the instruction, but need to define it
2785 multiclass StorePostIdxPseudo<RegisterClass regtype, ValueType Ty,
2786 SDPatternOperator OpNode, Instruction Insn> {
2787 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
2788 def _isel: Pseudo<(outs GPR64sp:$wback),
2789 (ins regtype:$Rt, am_noindex:$addr, simm9:$idx), [],
2790 "$addr.base = $wback,@earlyclobber $wback">,
2791 PseudoInstExpansion<(Insn regtype:$Rt, am_noindex:$addr, simm9:$idx)>,
2792 Sched<[WriteAdr, WriteST, ReadAdrBase]>;
2794 def : Pat<(OpNode (Ty regtype:$Rt), am_noindex:$addr, simm9:$idx),
2795 (!cast<Instruction>(NAME#_isel) regtype:$Rt, am_noindex:$addr,
2803 // (indexed, offset)
2805 class BaseLoadStorePairOffset<bits<2> opc, bit V, bit L, dag oops, dag iops,
2807 : I<oops, iops, asm, "\t$Rt, $Rt2, $addr", "", []> {
2808 // The operands are in order to match the 'addr' MI operands, so we
2809 // don't need an encoder method and by-name matching. Just use the default
2810 // in-order handling. Since we're using by-order, make sure the names
2816 let Inst{31-30} = opc;
2817 let Inst{29-27} = 0b101;
2819 let Inst{25-23} = 0b010;
2821 let Inst{21-15} = offset;
2822 let Inst{14-10} = dst2;
2823 let Inst{9-5} = base;
2824 let Inst{4-0} = dst;
2826 let DecoderMethod = "DecodePairLdStInstruction";
2829 let hasSideEffects = 0 in {
2830 let mayStore = 0, mayLoad = 1 in
2831 class LoadPairOffset<bits<2> opc, bit V, RegisterClass regtype,
2832 Operand indextype, string asm>
2833 : BaseLoadStorePairOffset<opc, V, 1,
2834 (outs regtype:$Rt, regtype:$Rt2),
2835 (ins indextype:$addr), asm>,
2836 Sched<[WriteLD, WriteLDHi]>;
2838 let mayLoad = 0, mayStore = 1 in
2839 class StorePairOffset<bits<2> opc, bit V, RegisterClass regtype,
2840 Operand indextype, string asm>
2841 : BaseLoadStorePairOffset<opc, V, 0, (outs),
2842 (ins regtype:$Rt, regtype:$Rt2, indextype:$addr),
2845 } // hasSideEffects = 0
2849 def MemoryIndexed32SImm7 : AsmOperandClass {
2850 let Name = "MemoryIndexed32SImm7";
2851 let DiagnosticType = "InvalidMemoryIndexed32SImm7";
2853 def am_indexed32simm7 : Operand<i32> { // ComplexPattern<...>
2854 let PrintMethod = "printAMIndexed<32>";
2855 let ParserMatchClass = MemoryIndexed32SImm7;
2856 let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
2858 def am_indexed32simm7_wb : Operand<i32> { // ComplexPattern<...>
2859 let PrintMethod = "printAMIndexedWB<32>";
2860 let ParserMatchClass = MemoryIndexed32SImm7;
2861 let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
2864 def MemoryIndexed64SImm7 : AsmOperandClass {
2865 let Name = "MemoryIndexed64SImm7";
2866 let DiagnosticType = "InvalidMemoryIndexed64SImm7";
2868 def am_indexed64simm7 : Operand<i32> { // ComplexPattern<...>
2869 let PrintMethod = "printAMIndexed<64>";
2870 let ParserMatchClass = MemoryIndexed64SImm7;
2871 let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
2873 def am_indexed64simm7_wb : Operand<i32> { // ComplexPattern<...>
2874 let PrintMethod = "printAMIndexedWB<64>";
2875 let ParserMatchClass = MemoryIndexed64SImm7;
2876 let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
2879 def MemoryIndexed128SImm7 : AsmOperandClass {
2880 let Name = "MemoryIndexed128SImm7";
2881 let DiagnosticType = "InvalidMemoryIndexed128SImm7";
2883 def am_indexed128simm7 : Operand<i32> { // ComplexPattern<...>
2884 let PrintMethod = "printAMIndexed<128>";
2885 let ParserMatchClass = MemoryIndexed128SImm7;
2886 let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
2888 def am_indexed128simm7_wb : Operand<i32> { // ComplexPattern<...>
2889 let PrintMethod = "printAMIndexedWB<128>";
2890 let ParserMatchClass = MemoryIndexed128SImm7;
2891 let MIOperandInfo = (ops GPR64sp:$base, i32imm:$offset);
2894 class BaseLoadStorePairPreIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
2896 : I<oops, iops, asm, "\t$Rt, $Rt2, $addr!", "", []> {
2897 // The operands are in order to match the 'addr' MI operands, so we
2898 // don't need an encoder method and by-name matching. Just use the default
2899 // in-order handling. Since we're using by-order, make sure the names
2905 let Inst{31-30} = opc;
2906 let Inst{29-27} = 0b101;
2908 let Inst{25-23} = 0b011;
2910 let Inst{21-15} = offset;
2911 let Inst{14-10} = dst2;
2912 let Inst{9-5} = base;
2913 let Inst{4-0} = dst;
2915 let DecoderMethod = "DecodePairLdStInstruction";
2918 let hasSideEffects = 0 in {
2919 let mayStore = 0, mayLoad = 1 in
2920 class LoadPairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
2921 Operand addrmode, string asm>
2922 : BaseLoadStorePairPreIdx<opc, V, 1,
2923 (outs regtype:$Rt, regtype:$Rt2),
2924 (ins addrmode:$addr), asm>,
2925 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
2927 let mayStore = 1, mayLoad = 0 in
2928 class StorePairPreIdx<bits<2> opc, bit V, RegisterClass regtype,
2929 Operand addrmode, string asm>
2930 : BaseLoadStorePairPreIdx<opc, V, 0, (outs),
2931 (ins regtype:$Rt, regtype:$Rt2, addrmode:$addr),
2933 Sched<[WriteAdr, WriteSTP]>;
2934 } // hasSideEffects = 0
2938 class BaseLoadStorePairPostIdx<bits<2> opc, bit V, bit L, dag oops, dag iops,
2940 : I<oops, iops, asm, "\t$Rt, $Rt2, $addr, $idx", "", []> {
2941 // The operands are in order to match the 'addr' MI operands, so we
2942 // don't need an encoder method and by-name matching. Just use the default
2943 // in-order handling. Since we're using by-order, make sure the names
2949 let Inst{31-30} = opc;
2950 let Inst{29-27} = 0b101;
2952 let Inst{25-23} = 0b001;
2954 let Inst{21-15} = offset;
2955 let Inst{14-10} = dst2;
2956 let Inst{9-5} = base;
2957 let Inst{4-0} = dst;
2959 let DecoderMethod = "DecodePairLdStInstruction";
2962 let hasSideEffects = 0 in {
2963 let mayStore = 0, mayLoad = 1 in
2964 class LoadPairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
2965 Operand idxtype, string asm>
2966 : BaseLoadStorePairPostIdx<opc, V, 1,
2967 (outs regtype:$Rt, regtype:$Rt2),
2968 (ins am_noindex:$addr, idxtype:$idx), asm>,
2969 Sched<[WriteLD, WriteLDHi, WriteAdr]>;
2971 let mayStore = 1, mayLoad = 0 in
2972 class StorePairPostIdx<bits<2> opc, bit V, RegisterClass regtype,
2973 Operand idxtype, string asm>
2974 : BaseLoadStorePairPostIdx<opc, V, 0, (outs),
2975 (ins regtype:$Rt, regtype:$Rt2,
2976 am_noindex:$addr, idxtype:$idx),
2978 Sched<[WriteAdr, WriteSTP]>;
2979 } // hasSideEffects = 0
2983 class BaseLoadStorePairNoAlloc<bits<2> opc, bit V, bit L, dag oops, dag iops,
2985 : I<oops, iops, asm, "\t$Rt, $Rt2, $addr", "", []> {
2986 // The operands are in order to match the 'addr' MI operands, so we
2987 // don't need an encoder method and by-name matching. Just use the default
2988 // in-order handling. Since we're using by-order, make sure the names
2994 let Inst{31-30} = opc;
2995 let Inst{29-27} = 0b101;
2997 let Inst{25-23} = 0b000;
2999 let Inst{21-15} = offset;
3000 let Inst{14-10} = dst2;
3001 let Inst{9-5} = base;
3002 let Inst{4-0} = dst;
3004 let DecoderMethod = "DecodePairLdStInstruction";
3007 let hasSideEffects = 0 in {
3008 let mayStore = 0, mayLoad = 1 in
3009 class LoadPairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3010 Operand indextype, string asm>
3011 : BaseLoadStorePairNoAlloc<opc, V, 1,
3012 (outs regtype:$Rt, regtype:$Rt2),
3013 (ins indextype:$addr), asm>,
3014 Sched<[WriteLD, WriteLDHi]>;
3016 let mayStore = 1, mayLoad = 0 in
3017 class StorePairNoAlloc<bits<2> opc, bit V, RegisterClass regtype,
3018 Operand indextype, string asm>
3019 : BaseLoadStorePairNoAlloc<opc, V, 0, (outs),
3020 (ins regtype:$Rt, regtype:$Rt2, indextype:$addr),
3023 } // hasSideEffects = 0
3026 // Load/store exclusive
3029 // True exclusive operations write to and/or read from the system's exclusive
3030 // monitors, which as far as a compiler is concerned can be modelled as a
3031 // random shared memory address. Hence LoadExclusive mayStore.
3033 // Since these instructions have the undefined register bits set to 1 in
3034 // their canonical form, we need a post encoder method to set those bits
3035 // to 1 when encoding these instructions. We do this using the
3036 // fixLoadStoreExclusive function. This function has template parameters:
3038 // fixLoadStoreExclusive<int hasRs, int hasRt2>
3040 // hasRs indicates that the instruction uses the Rs field, so we won't set
3041 // it to 1 (and the same for Rt2). We don't need template parameters for
3042 // the other register fields since Rt and Rn are always used.
3044 let hasSideEffects = 1, mayLoad = 1, mayStore = 1 in
3045 class BaseLoadStoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3046 dag oops, dag iops, string asm, string operands>
3047 : I<oops, iops, asm, operands, "", []> {
3048 let Inst{31-30} = sz;
3049 let Inst{29-24} = 0b001000;
3055 let DecoderMethod = "DecodeExclusiveLdStInstruction";
3058 // Neither Rs nor Rt2 operands.
3059 class LoadStoreExclusiveSimple<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3060 dag oops, dag iops, string asm, string operands>
3061 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, oops, iops, asm, operands> {
3064 let Inst{9-5} = base;
3065 let Inst{4-0} = reg;
3067 let PostEncoderMethod = "fixLoadStoreExclusive<0,0>";
3070 // Simple load acquires don't set the exclusive monitor
3071 let mayLoad = 1, mayStore = 0 in
3072 class LoadAcquire<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3073 RegisterClass regtype, string asm>
3074 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3075 (ins am_noindex:$addr), asm, "\t$Rt, $addr">,
3078 class LoadExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3079 RegisterClass regtype, string asm>
3080 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs regtype:$Rt),
3081 (ins am_noindex:$addr), asm, "\t$Rt, $addr">,
3084 class LoadExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3085 RegisterClass regtype, string asm>
3086 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3087 (outs regtype:$Rt, regtype:$Rt2),
3088 (ins am_noindex:$addr), asm,
3089 "\t$Rt, $Rt2, $addr">,
3090 Sched<[WriteLD, WriteLDHi]> {
3094 let Inst{14-10} = dst2;
3095 let Inst{9-5} = base;
3096 let Inst{4-0} = dst1;
3098 let PostEncoderMethod = "fixLoadStoreExclusive<0,1>";
3101 // Simple store release operations do not check the exclusive monitor.
3102 let mayLoad = 0, mayStore = 1 in
3103 class StoreRelease<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3104 RegisterClass regtype, string asm>
3105 : LoadStoreExclusiveSimple<sz, o2, L, o1, o0, (outs),
3106 (ins regtype:$Rt, am_noindex:$addr),
3107 asm, "\t$Rt, $addr">,
3110 let mayLoad = 1, mayStore = 1 in
3111 class StoreExclusive<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3112 RegisterClass regtype, string asm>
3113 : BaseLoadStoreExclusive<sz, o2, L, o1, o0, (outs GPR32:$Ws),
3114 (ins regtype:$Rt, am_noindex:$addr),
3115 asm, "\t$Ws, $Rt, $addr">,
3120 let Inst{20-16} = status;
3121 let Inst{9-5} = base;
3122 let Inst{4-0} = reg;
3124 let Constraints = "@earlyclobber $Ws";
3125 let PostEncoderMethod = "fixLoadStoreExclusive<1,0>";
3128 class StoreExclusivePair<bits<2> sz, bit o2, bit L, bit o1, bit o0,
3129 RegisterClass regtype, string asm>
3130 : BaseLoadStoreExclusive<sz, o2, L, o1, o0,
3132 (ins regtype:$Rt, regtype:$Rt2, am_noindex:$addr),
3133 asm, "\t$Ws, $Rt, $Rt2, $addr">,
3139 let Inst{20-16} = status;
3140 let Inst{14-10} = dst2;
3141 let Inst{9-5} = base;
3142 let Inst{4-0} = dst1;
3144 let Constraints = "@earlyclobber $Ws";
3148 // Exception generation
3151 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
3152 class ExceptionGeneration<bits<3> op1, bits<2> ll, string asm>
3153 : I<(outs), (ins imm0_65535:$imm), asm, "\t$imm", "", []>,
3156 let Inst{31-24} = 0b11010100;
3157 let Inst{23-21} = op1;
3158 let Inst{20-5} = imm;
3159 let Inst{4-2} = 0b000;
3163 let Predicates = [HasFPARMv8] in {
3166 // Floating point to integer conversion
3169 class BaseFPToIntegerUnscaled<bits<2> type, bits<2> rmode, bits<3> opcode,
3170 RegisterClass srcType, RegisterClass dstType,
3171 string asm, list<dag> pattern>
3172 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3173 asm, "\t$Rd, $Rn", "", pattern>,
3174 Sched<[WriteFCvt]> {
3177 let Inst{30-29} = 0b00;
3178 let Inst{28-24} = 0b11110;
3179 let Inst{23-22} = type;
3181 let Inst{20-19} = rmode;
3182 let Inst{18-16} = opcode;
3183 let Inst{15-10} = 0;
3188 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3189 class BaseFPToInteger<bits<2> type, bits<2> rmode, bits<3> opcode,
3190 RegisterClass srcType, RegisterClass dstType,
3191 Operand immType, string asm, list<dag> pattern>
3192 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3193 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3194 Sched<[WriteFCvt]> {
3198 let Inst{30-29} = 0b00;
3199 let Inst{28-24} = 0b11110;
3200 let Inst{23-22} = type;
3202 let Inst{20-19} = rmode;
3203 let Inst{18-16} = opcode;
3204 let Inst{15-10} = scale;
3209 multiclass FPToIntegerUnscaled<bits<2> rmode, bits<3> opcode, string asm,
3210 SDPatternOperator OpN> {
3211 // Unscaled single-precision to 32-bit
3212 def UWSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR32, asm,
3213 [(set GPR32:$Rd, (OpN FPR32:$Rn))]> {
3214 let Inst{31} = 0; // 32-bit GPR flag
3217 // Unscaled single-precision to 64-bit
3218 def UXSr : BaseFPToIntegerUnscaled<0b00, rmode, opcode, FPR32, GPR64, asm,
3219 [(set GPR64:$Rd, (OpN FPR32:$Rn))]> {
3220 let Inst{31} = 1; // 64-bit GPR flag
3223 // Unscaled double-precision to 32-bit
3224 def UWDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR32, asm,
3225 [(set GPR32:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3226 let Inst{31} = 0; // 32-bit GPR flag
3229 // Unscaled double-precision to 64-bit
3230 def UXDr : BaseFPToIntegerUnscaled<0b01, rmode, opcode, FPR64, GPR64, asm,
3231 [(set GPR64:$Rd, (OpN (f64 FPR64:$Rn)))]> {
3232 let Inst{31} = 1; // 64-bit GPR flag
3236 multiclass FPToIntegerScaled<bits<2> rmode, bits<3> opcode, string asm,
3237 SDPatternOperator OpN> {
3238 // Scaled single-precision to 32-bit
3239 def SWSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR32,
3240 fixedpoint_f32_i32, asm,
3241 [(set GPR32:$Rd, (OpN (fmul FPR32:$Rn,
3242 fixedpoint_f32_i32:$scale)))]> {
3243 let Inst{31} = 0; // 32-bit GPR flag
3247 // Scaled single-precision to 64-bit
3248 def SXSri : BaseFPToInteger<0b00, rmode, opcode, FPR32, GPR64,
3249 fixedpoint_f32_i64, asm,
3250 [(set GPR64:$Rd, (OpN (fmul FPR32:$Rn,
3251 fixedpoint_f32_i64:$scale)))]> {
3252 let Inst{31} = 1; // 64-bit GPR flag
3255 // Scaled double-precision to 32-bit
3256 def SWDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR32,
3257 fixedpoint_f64_i32, asm,
3258 [(set GPR32:$Rd, (OpN (fmul FPR64:$Rn,
3259 fixedpoint_f64_i32:$scale)))]> {
3260 let Inst{31} = 0; // 32-bit GPR flag
3264 // Scaled double-precision to 64-bit
3265 def SXDri : BaseFPToInteger<0b01, rmode, opcode, FPR64, GPR64,
3266 fixedpoint_f64_i64, asm,
3267 [(set GPR64:$Rd, (OpN (fmul FPR64:$Rn,
3268 fixedpoint_f64_i64:$scale)))]> {
3269 let Inst{31} = 1; // 64-bit GPR flag
3274 // Integer to floating point conversion
3277 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
3278 class BaseIntegerToFP<bit isUnsigned,
3279 RegisterClass srcType, RegisterClass dstType,
3280 Operand immType, string asm, list<dag> pattern>
3281 : I<(outs dstType:$Rd), (ins srcType:$Rn, immType:$scale),
3282 asm, "\t$Rd, $Rn, $scale", "", pattern>,
3283 Sched<[WriteFCvt]> {
3287 let Inst{30-23} = 0b00111100;
3288 let Inst{21-17} = 0b00001;
3289 let Inst{16} = isUnsigned;
3290 let Inst{15-10} = scale;
3295 class BaseIntegerToFPUnscaled<bit isUnsigned,
3296 RegisterClass srcType, RegisterClass dstType,
3297 ValueType dvt, string asm, SDNode node>
3298 : I<(outs dstType:$Rd), (ins srcType:$Rn),
3299 asm, "\t$Rd, $Rn", "", [(set (dvt dstType:$Rd), (node srcType:$Rn))]>,
3300 Sched<[WriteFCvt]> {
3304 let Inst{30-23} = 0b00111100;
3305 let Inst{21-17} = 0b10001;
3306 let Inst{16} = isUnsigned;
3307 let Inst{15-10} = 0b000000;
3312 multiclass IntegerToFP<bit isUnsigned, string asm, SDNode node> {
3314 def UWSri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR32, f32, asm, node> {
3315 let Inst{31} = 0; // 32-bit GPR flag
3316 let Inst{22} = 0; // 32-bit FPR flag
3319 def UWDri: BaseIntegerToFPUnscaled<isUnsigned, GPR32, FPR64, f64, asm, node> {
3320 let Inst{31} = 0; // 32-bit GPR flag
3321 let Inst{22} = 1; // 64-bit FPR flag
3324 def UXSri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR32, f32, asm, node> {
3325 let Inst{31} = 1; // 64-bit GPR flag
3326 let Inst{22} = 0; // 32-bit FPR flag
3329 def UXDri: BaseIntegerToFPUnscaled<isUnsigned, GPR64, FPR64, f64, asm, node> {
3330 let Inst{31} = 1; // 64-bit GPR flag
3331 let Inst{22} = 1; // 64-bit FPR flag
3335 def SWSri: BaseIntegerToFP<isUnsigned, GPR32, FPR32, fixedpoint_f32_i32, asm,
3337 (fdiv (node GPR32:$Rn),
3338 fixedpoint_f32_i32:$scale))]> {
3339 let Inst{31} = 0; // 32-bit GPR flag
3340 let Inst{22} = 0; // 32-bit FPR flag
3344 def SWDri: BaseIntegerToFP<isUnsigned, GPR32, FPR64, fixedpoint_f64_i32, asm,
3346 (fdiv (node GPR32:$Rn),
3347 fixedpoint_f64_i32:$scale))]> {
3348 let Inst{31} = 0; // 32-bit GPR flag
3349 let Inst{22} = 1; // 64-bit FPR flag
3353 def SXSri: BaseIntegerToFP<isUnsigned, GPR64, FPR32, fixedpoint_f32_i64, asm,
3355 (fdiv (node GPR64:$Rn),
3356 fixedpoint_f32_i64:$scale))]> {
3357 let Inst{31} = 1; // 64-bit GPR flag
3358 let Inst{22} = 0; // 32-bit FPR flag
3361 def SXDri: BaseIntegerToFP<isUnsigned, GPR64, FPR64, fixedpoint_f64_i64, asm,
3363 (fdiv (node GPR64:$Rn),
3364 fixedpoint_f64_i64:$scale))]> {
3365 let Inst{31} = 1; // 64-bit GPR flag
3366 let Inst{22} = 1; // 64-bit FPR flag
3371 // Unscaled integer <-> floating point conversion (i.e. FMOV)
3374 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3375 class BaseUnscaledConversion<bits<2> rmode, bits<3> opcode,
3376 RegisterClass srcType, RegisterClass dstType,
3378 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "",
3379 // We use COPY_TO_REGCLASS for these bitconvert operations.
3380 // copyPhysReg() expands the resultant COPY instructions after
3381 // regalloc is done. This gives greater freedom for the allocator
3382 // and related passes (coalescing, copy propagation, et. al.) to
3383 // be more effective.
3384 [/*(set (dvt dstType:$Rd), (bitconvert (svt srcType:$Rn)))*/]>,
3385 Sched<[WriteFCopy]> {
3388 let Inst{30-23} = 0b00111100;
3390 let Inst{20-19} = rmode;
3391 let Inst{18-16} = opcode;
3392 let Inst{15-10} = 0b000000;
3397 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3398 class BaseUnscaledConversionToHigh<bits<2> rmode, bits<3> opcode,
3399 RegisterClass srcType, RegisterOperand dstType, string asm,
3401 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm,
3402 "{\t$Rd"#kind#"[1], $Rn|"#kind#"\t$Rd[1], $Rn}", "", []>,
3403 Sched<[WriteFCopy]> {
3406 let Inst{30-23} = 0b00111101;
3408 let Inst{20-19} = rmode;
3409 let Inst{18-16} = opcode;
3410 let Inst{15-10} = 0b000000;
3415 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3416 class BaseUnscaledConversionFromHigh<bits<2> rmode, bits<3> opcode,
3417 RegisterOperand srcType, RegisterClass dstType, string asm,
3419 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm,
3420 "{\t$Rd, $Rn"#kind#"[1]|"#kind#"\t$Rd, $Rn[1]}", "", []>,
3421 Sched<[WriteFCopy]> {
3424 let Inst{30-23} = 0b00111101;
3426 let Inst{20-19} = rmode;
3427 let Inst{18-16} = opcode;
3428 let Inst{15-10} = 0b000000;
3435 multiclass UnscaledConversion<string asm> {
3436 def WSr : BaseUnscaledConversion<0b00, 0b111, GPR32, FPR32, asm> {
3437 let Inst{31} = 0; // 32-bit GPR flag
3438 let Inst{22} = 0; // 32-bit FPR flag
3441 def XDr : BaseUnscaledConversion<0b00, 0b111, GPR64, FPR64, asm> {
3442 let Inst{31} = 1; // 64-bit GPR flag
3443 let Inst{22} = 1; // 64-bit FPR flag
3446 def SWr : BaseUnscaledConversion<0b00, 0b110, FPR32, GPR32, asm> {
3447 let Inst{31} = 0; // 32-bit GPR flag
3448 let Inst{22} = 0; // 32-bit FPR flag
3451 def DXr : BaseUnscaledConversion<0b00, 0b110, FPR64, GPR64, asm> {
3452 let Inst{31} = 1; // 64-bit GPR flag
3453 let Inst{22} = 1; // 64-bit FPR flag
3456 def XDHighr : BaseUnscaledConversionToHigh<0b01, 0b111, GPR64, V128,
3462 def DXHighr : BaseUnscaledConversionFromHigh<0b01, 0b110, V128, GPR64,
3470 // Floating point conversion
3473 class BaseFPConversion<bits<2> type, bits<2> opcode, RegisterClass dstType,
3474 RegisterClass srcType, string asm, list<dag> pattern>
3475 : I<(outs dstType:$Rd), (ins srcType:$Rn), asm, "\t$Rd, $Rn", "", pattern>,
3476 Sched<[WriteFCvt]> {
3479 let Inst{31-24} = 0b00011110;
3480 let Inst{23-22} = type;
3481 let Inst{21-17} = 0b10001;
3482 let Inst{16-15} = opcode;
3483 let Inst{14-10} = 0b10000;
3488 multiclass FPConversion<string asm> {
3489 // Double-precision to Half-precision
3490 def HDr : BaseFPConversion<0b01, 0b11, FPR16, FPR64, asm,
3491 [(set FPR16:$Rd, (fround FPR64:$Rn))]>;
3493 // Double-precision to Single-precision
3494 def SDr : BaseFPConversion<0b01, 0b00, FPR32, FPR64, asm,
3495 [(set FPR32:$Rd, (fround FPR64:$Rn))]>;
3497 // Half-precision to Double-precision
3498 def DHr : BaseFPConversion<0b11, 0b01, FPR64, FPR16, asm,
3499 [(set FPR64:$Rd, (fextend FPR16:$Rn))]>;
3501 // Half-precision to Single-precision
3502 def SHr : BaseFPConversion<0b11, 0b00, FPR32, FPR16, asm,
3503 [(set FPR32:$Rd, (fextend FPR16:$Rn))]>;
3505 // Single-precision to Double-precision
3506 def DSr : BaseFPConversion<0b00, 0b01, FPR64, FPR32, asm,
3507 [(set FPR64:$Rd, (fextend FPR32:$Rn))]>;
3509 // Single-precision to Half-precision
3510 def HSr : BaseFPConversion<0b00, 0b11, FPR16, FPR32, asm,
3511 [(set FPR16:$Rd, (fround FPR32:$Rn))]>;
3515 // Single operand floating point data processing
3518 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3519 class BaseSingleOperandFPData<bits<4> opcode, RegisterClass regtype,
3520 ValueType vt, string asm, SDPatternOperator node>
3521 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
3522 [(set (vt regtype:$Rd), (node (vt regtype:$Rn)))]>,
3526 let Inst{31-23} = 0b000111100;
3527 let Inst{21-19} = 0b100;
3528 let Inst{18-15} = opcode;
3529 let Inst{14-10} = 0b10000;
3534 multiclass SingleOperandFPData<bits<4> opcode, string asm,
3535 SDPatternOperator node = null_frag> {
3536 def Sr : BaseSingleOperandFPData<opcode, FPR32, f32, asm, node> {
3537 let Inst{22} = 0; // 32-bit size flag
3540 def Dr : BaseSingleOperandFPData<opcode, FPR64, f64, asm, node> {
3541 let Inst{22} = 1; // 64-bit size flag
3546 // Two operand floating point data processing
3549 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3550 class BaseTwoOperandFPData<bits<4> opcode, RegisterClass regtype,
3551 string asm, list<dag> pat>
3552 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
3553 asm, "\t$Rd, $Rn, $Rm", "", pat>,
3558 let Inst{31-23} = 0b000111100;
3560 let Inst{20-16} = Rm;
3561 let Inst{15-12} = opcode;
3562 let Inst{11-10} = 0b10;
3567 multiclass TwoOperandFPData<bits<4> opcode, string asm,
3568 SDPatternOperator node = null_frag> {
3569 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3570 [(set (f32 FPR32:$Rd),
3571 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]> {
3572 let Inst{22} = 0; // 32-bit size flag
3575 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3576 [(set (f64 FPR64:$Rd),
3577 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]> {
3578 let Inst{22} = 1; // 64-bit size flag
3582 multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm, SDNode node> {
3583 def Srr : BaseTwoOperandFPData<opcode, FPR32, asm,
3584 [(set FPR32:$Rd, (fneg (node FPR32:$Rn, (f32 FPR32:$Rm))))]> {
3585 let Inst{22} = 0; // 32-bit size flag
3588 def Drr : BaseTwoOperandFPData<opcode, FPR64, asm,
3589 [(set FPR64:$Rd, (fneg (node FPR64:$Rn, (f64 FPR64:$Rm))))]> {
3590 let Inst{22} = 1; // 64-bit size flag
3596 // Three operand floating point data processing
3599 class BaseThreeOperandFPData<bit isNegated, bit isSub,
3600 RegisterClass regtype, string asm, list<dag> pat>
3601 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, regtype: $Ra),
3602 asm, "\t$Rd, $Rn, $Rm, $Ra", "", pat>,
3603 Sched<[WriteFMul]> {
3608 let Inst{31-23} = 0b000111110;
3609 let Inst{21} = isNegated;
3610 let Inst{20-16} = Rm;
3611 let Inst{15} = isSub;
3612 let Inst{14-10} = Ra;
3617 multiclass ThreeOperandFPData<bit isNegated, bit isSub,string asm,
3618 SDPatternOperator node> {
3619 def Srrr : BaseThreeOperandFPData<isNegated, isSub, FPR32, asm,
3621 (node (f32 FPR32:$Rn), (f32 FPR32:$Rm), (f32 FPR32:$Ra)))]> {
3622 let Inst{22} = 0; // 32-bit size flag
3625 def Drrr : BaseThreeOperandFPData<isNegated, isSub, FPR64, asm,
3627 (node (f64 FPR64:$Rn), (f64 FPR64:$Rm), (f64 FPR64:$Ra)))]> {
3628 let Inst{22} = 1; // 64-bit size flag
3633 // Floating point data comparisons
3636 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3637 class BaseOneOperandFPComparison<bit signalAllNans,
3638 RegisterClass regtype, string asm,
3640 : I<(outs), (ins regtype:$Rn), asm, "\t$Rn, #0.0", "", pat>,
3641 Sched<[WriteFCmp]> {
3643 let Inst{31-23} = 0b000111100;
3646 let Inst{15-10} = 0b001000;
3648 let Inst{4} = signalAllNans;
3649 let Inst{3-0} = 0b1000;
3651 // Rm should be 0b00000 canonically, but we need to accept any value.
3652 let PostEncoderMethod = "fixOneOperandFPComparison";
3655 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3656 class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
3657 string asm, list<dag> pat>
3658 : I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
3659 Sched<[WriteFCmp]> {
3662 let Inst{31-23} = 0b000111100;
3664 let Inst{20-16} = Rm;
3665 let Inst{15-10} = 0b001000;
3667 let Inst{4} = signalAllNans;
3668 let Inst{3-0} = 0b0000;
3671 multiclass FPComparison<bit signalAllNans, string asm,
3672 SDPatternOperator OpNode = null_frag> {
3673 let Defs = [NZCV] in {
3674 def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
3675 [(OpNode FPR32:$Rn, (f32 FPR32:$Rm)), (implicit NZCV)]> {
3679 def Sri : BaseOneOperandFPComparison<signalAllNans, FPR32, asm,
3680 [(OpNode (f32 FPR32:$Rn), fpimm0), (implicit NZCV)]> {
3684 def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
3685 [(OpNode FPR64:$Rn, (f64 FPR64:$Rm)), (implicit NZCV)]> {
3689 def Dri : BaseOneOperandFPComparison<signalAllNans, FPR64, asm,
3690 [(OpNode (f64 FPR64:$Rn), fpimm0), (implicit NZCV)]> {
3697 // Floating point conditional comparisons
3700 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3701 class BaseFPCondComparison<bit signalAllNans,
3702 RegisterClass regtype, string asm>
3703 : I<(outs), (ins regtype:$Rn, regtype:$Rm, imm0_15:$nzcv, ccode:$cond),
3704 asm, "\t$Rn, $Rm, $nzcv, $cond", "", []>,
3705 Sched<[WriteFCmp]> {
3711 let Inst{31-23} = 0b000111100;
3713 let Inst{20-16} = Rm;
3714 let Inst{15-12} = cond;
3715 let Inst{11-10} = 0b01;
3717 let Inst{4} = signalAllNans;
3718 let Inst{3-0} = nzcv;
3721 multiclass FPCondComparison<bit signalAllNans, string asm> {
3722 let Defs = [NZCV], Uses = [NZCV] in {
3723 def Srr : BaseFPCondComparison<signalAllNans, FPR32, asm> {
3727 def Drr : BaseFPCondComparison<signalAllNans, FPR64, asm> {
3730 } // Defs = [NZCV], Uses = [NZCV]
3734 // Floating point conditional select
3737 class BaseFPCondSelect<RegisterClass regtype, ValueType vt, string asm>
3738 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, ccode:$cond),
3739 asm, "\t$Rd, $Rn, $Rm, $cond", "",
3741 (ARM64csel (vt regtype:$Rn), regtype:$Rm,
3742 (i32 imm:$cond), NZCV))]>,
3749 let Inst{31-23} = 0b000111100;
3751 let Inst{20-16} = Rm;
3752 let Inst{15-12} = cond;
3753 let Inst{11-10} = 0b11;
3758 multiclass FPCondSelect<string asm> {
3759 let Uses = [NZCV] in {
3760 def Srrr : BaseFPCondSelect<FPR32, f32, asm> {
3764 def Drrr : BaseFPCondSelect<FPR64, f64, asm> {
3771 // Floating move immediate
3774 class BaseFPMoveImmediate<RegisterClass regtype, Operand fpimmtype, string asm>
3775 : I<(outs regtype:$Rd), (ins fpimmtype:$imm), asm, "\t$Rd, $imm", "",
3776 [(set regtype:$Rd, fpimmtype:$imm)]>,
3777 Sched<[WriteFImm]> {
3780 let Inst{31-23} = 0b000111100;
3782 let Inst{20-13} = imm;
3783 let Inst{12-5} = 0b10000000;
3787 multiclass FPMoveImmediate<string asm> {
3788 def Si : BaseFPMoveImmediate<FPR32, fpimm32, asm> {
3792 def Di : BaseFPMoveImmediate<FPR64, fpimm64, asm> {
3796 } // end of 'let Predicates = [HasFPARMv8]'
3798 //----------------------------------------------------------------------------
3800 //----------------------------------------------------------------------------
3802 class AsmVectorIndex<string Suffix> : AsmOperandClass {
3803 let Name = "VectorIndex" # Suffix;
3804 let DiagnosticType = "InvalidIndex" # Suffix;
3806 def VectorIndexBOperand : AsmVectorIndex<"B">;
3807 def VectorIndexHOperand : AsmVectorIndex<"H">;
3808 def VectorIndexSOperand : AsmVectorIndex<"S">;
3809 def VectorIndexDOperand : AsmVectorIndex<"D">;
3811 def VectorIndexB : Operand<i64>, ImmLeaf<i64, [{
3812 return ((uint64_t)Imm) < 16;
3814 let ParserMatchClass = VectorIndexBOperand;
3815 let PrintMethod = "printVectorIndex";
3816 let MIOperandInfo = (ops i64imm);
3818 def VectorIndexH : Operand<i64>, ImmLeaf<i64, [{
3819 return ((uint64_t)Imm) < 8;
3821 let ParserMatchClass = VectorIndexHOperand;
3822 let PrintMethod = "printVectorIndex";
3823 let MIOperandInfo = (ops i64imm);
3825 def VectorIndexS : Operand<i64>, ImmLeaf<i64, [{
3826 return ((uint64_t)Imm) < 4;
3828 let ParserMatchClass = VectorIndexSOperand;
3829 let PrintMethod = "printVectorIndex";
3830 let MIOperandInfo = (ops i64imm);
3832 def VectorIndexD : Operand<i64>, ImmLeaf<i64, [{
3833 return ((uint64_t)Imm) < 2;
3835 let ParserMatchClass = VectorIndexDOperand;
3836 let PrintMethod = "printVectorIndex";
3837 let MIOperandInfo = (ops i64imm);
3840 def MemorySIMDNoIndexOperand : AsmOperandClass {
3841 let Name = "MemorySIMDNoIndex";
3842 let ParserMethod = "tryParseNoIndexMemory";
3844 def am_simdnoindex : Operand<i64>,
3845 ComplexPattern<i64, 1, "SelectAddrModeNoIndex", []> {
3846 let PrintMethod = "printAMNoIndex";
3847 let ParserMatchClass = MemorySIMDNoIndexOperand;
3848 let MIOperandInfo = (ops GPR64sp:$base);
3849 let DecoderMethod = "DecodeGPR64spRegisterClass";
3852 let Predicates = [HasNEON] in {
3854 //----------------------------------------------------------------------------
3855 // AdvSIMD three register vector instructions
3856 //----------------------------------------------------------------------------
3858 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3859 class BaseSIMDThreeSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
3860 RegisterOperand regtype, string asm, string kind,
3862 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
3863 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
3864 "|" # kind # "\t$Rd, $Rn, $Rm|}", "", pattern>,
3872 let Inst{28-24} = 0b01110;
3873 let Inst{23-22} = size;
3875 let Inst{20-16} = Rm;
3876 let Inst{15-11} = opcode;
3882 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
3883 class BaseSIMDThreeSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
3884 RegisterOperand regtype, string asm, string kind,
3886 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn, regtype:$Rm), asm,
3887 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
3888 "|" # kind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
3896 let Inst{28-24} = 0b01110;
3897 let Inst{23-22} = size;
3899 let Inst{20-16} = Rm;
3900 let Inst{15-11} = opcode;
3906 // All operand sizes distinguished in the encoding.
3907 multiclass SIMDThreeSameVector<bit U, bits<5> opc, string asm,
3908 SDPatternOperator OpNode> {
3909 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
3911 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
3912 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
3914 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
3915 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
3917 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
3918 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
3920 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
3921 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
3923 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
3924 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
3926 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
3927 def v2i64 : BaseSIMDThreeSameVector<1, U, 0b11, opc, V128,
3929 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
3932 // As above, but D sized elements unsupported.
3933 multiclass SIMDThreeSameVectorBHS<bit U, bits<5> opc, string asm,
3934 SDPatternOperator OpNode> {
3935 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
3937 [(set V64:$Rd, (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))]>;
3938 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
3940 [(set V128:$Rd, (v16i8 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm))))]>;
3941 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
3943 [(set V64:$Rd, (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))]>;
3944 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
3946 [(set V128:$Rd, (v8i16 (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm))))]>;
3947 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
3949 [(set V64:$Rd, (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))]>;
3950 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
3952 [(set V128:$Rd, (v4i32 (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm))))]>;
3955 multiclass SIMDThreeSameVectorBHSTied<bit U, bits<5> opc, string asm,
3956 SDPatternOperator OpNode> {
3957 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, 0b00, opc, V64,
3959 [(set (v8i8 V64:$dst),
3960 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
3961 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, 0b00, opc, V128,
3963 [(set (v16i8 V128:$dst),
3964 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
3965 def v4i16 : BaseSIMDThreeSameVectorTied<0, U, 0b01, opc, V64,
3967 [(set (v4i16 V64:$dst),
3968 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
3969 def v8i16 : BaseSIMDThreeSameVectorTied<1, U, 0b01, opc, V128,
3971 [(set (v8i16 V128:$dst),
3972 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
3973 def v2i32 : BaseSIMDThreeSameVectorTied<0, U, 0b10, opc, V64,
3975 [(set (v2i32 V64:$dst),
3976 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
3977 def v4i32 : BaseSIMDThreeSameVectorTied<1, U, 0b10, opc, V128,
3979 [(set (v4i32 V128:$dst),
3980 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
3983 // As above, but only B sized elements supported.
3984 multiclass SIMDThreeSameVectorB<bit U, bits<5> opc, string asm,
3985 SDPatternOperator OpNode> {
3986 def v8i8 : BaseSIMDThreeSameVector<0, U, 0b00, opc, V64,
3988 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
3989 def v16i8 : BaseSIMDThreeSameVector<1, U, 0b00, opc, V128,
3991 [(set (v16i8 V128:$Rd),
3992 (OpNode (v16i8 V128:$Rn), (v16i8 V128:$Rm)))]>;
3995 // As above, but only S and D sized floating point elements supported.
3996 multiclass SIMDThreeSameVectorFP<bit U, bit S, bits<5> opc,
3997 string asm, SDPatternOperator OpNode> {
3998 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4000 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4001 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4003 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4004 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4006 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4009 multiclass SIMDThreeSameVectorFPCmp<bit U, bit S, bits<5> opc,
4011 SDPatternOperator OpNode> {
4012 def v2f32 : BaseSIMDThreeSameVector<0, U, {S,0}, opc, V64,
4014 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4015 def v4f32 : BaseSIMDThreeSameVector<1, U, {S,0}, opc, V128,
4017 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4018 def v2f64 : BaseSIMDThreeSameVector<1, U, {S,1}, opc, V128,
4020 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4023 multiclass SIMDThreeSameVectorFPTied<bit U, bit S, bits<5> opc,
4024 string asm, SDPatternOperator OpNode> {
4025 def v2f32 : BaseSIMDThreeSameVectorTied<0, U, {S,0}, opc, V64,
4027 [(set (v2f32 V64:$dst),
4028 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn), (v2f32 V64:$Rm)))]>;
4029 def v4f32 : BaseSIMDThreeSameVectorTied<1, U, {S,0}, opc, V128,
4031 [(set (v4f32 V128:$dst),
4032 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn), (v4f32 V128:$Rm)))]>;
4033 def v2f64 : BaseSIMDThreeSameVectorTied<1, U, {S,1}, opc, V128,
4035 [(set (v2f64 V128:$dst),
4036 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn), (v2f64 V128:$Rm)))]>;
4039 // As above, but D and B sized elements unsupported.
4040 multiclass SIMDThreeSameVectorHS<bit U, bits<5> opc, string asm,
4041 SDPatternOperator OpNode> {
4042 def v4i16 : BaseSIMDThreeSameVector<0, U, 0b01, opc, V64,
4044 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4045 def v8i16 : BaseSIMDThreeSameVector<1, U, 0b01, opc, V128,
4047 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4048 def v2i32 : BaseSIMDThreeSameVector<0, U, 0b10, opc, V64,
4050 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4051 def v4i32 : BaseSIMDThreeSameVector<1, U, 0b10, opc, V128,
4053 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4056 // Logical three vector ops share opcode bits, and only use B sized elements.
4057 multiclass SIMDLogicalThreeVector<bit U, bits<2> size, string asm,
4058 SDPatternOperator OpNode = null_frag> {
4059 def v8i8 : BaseSIMDThreeSameVector<0, U, size, 0b00011, V64,
4061 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn, V64:$Rm))]>;
4062 def v16i8 : BaseSIMDThreeSameVector<1, U, size, 0b00011, V128,
4064 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn, V128:$Rm))]>;
4066 def : Pat<(v4i16 (OpNode V64:$LHS, V64:$RHS)),
4067 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4068 def : Pat<(v2i32 (OpNode V64:$LHS, V64:$RHS)),
4069 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4070 def : Pat<(v1i64 (OpNode V64:$LHS, V64:$RHS)),
4071 (!cast<Instruction>(NAME#"v8i8") V64:$LHS, V64:$RHS)>;
4073 def : Pat<(v8i16 (OpNode V128:$LHS, V128:$RHS)),
4074 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4075 def : Pat<(v4i32 (OpNode V128:$LHS, V128:$RHS)),
4076 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4077 def : Pat<(v2i64 (OpNode V128:$LHS, V128:$RHS)),
4078 (!cast<Instruction>(NAME#"v16i8") V128:$LHS, V128:$RHS)>;
4081 multiclass SIMDLogicalThreeVectorTied<bit U, bits<2> size,
4082 string asm, SDPatternOperator OpNode> {
4083 def v8i8 : BaseSIMDThreeSameVectorTied<0, U, size, 0b00011, V64,
4085 [(set (v8i8 V64:$dst),
4086 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4087 def v16i8 : BaseSIMDThreeSameVectorTied<1, U, size, 0b00011, V128,
4089 [(set (v16i8 V128:$dst),
4090 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
4091 (v16i8 V128:$Rm)))]>;
4093 def : Pat<(v4i16 (OpNode (v4i16 V64:$LHS), (v4i16 V64:$MHS),
4095 (!cast<Instruction>(NAME#"v8i8")
4096 V64:$LHS, V64:$MHS, V64:$RHS)>;
4097 def : Pat<(v2i32 (OpNode (v2i32 V64:$LHS), (v2i32 V64:$MHS),
4099 (!cast<Instruction>(NAME#"v8i8")
4100 V64:$LHS, V64:$MHS, V64:$RHS)>;
4101 def : Pat<(v1i64 (OpNode (v1i64 V64:$LHS), (v1i64 V64:$MHS),
4103 (!cast<Instruction>(NAME#"v8i8")
4104 V64:$LHS, V64:$MHS, V64:$RHS)>;
4106 def : Pat<(v8i16 (OpNode (v8i16 V128:$LHS), (v8i16 V128:$MHS),
4107 (v8i16 V128:$RHS))),
4108 (!cast<Instruction>(NAME#"v16i8")
4109 V128:$LHS, V128:$MHS, V128:$RHS)>;
4110 def : Pat<(v4i32 (OpNode (v4i32 V128:$LHS), (v4i32 V128:$MHS),
4111 (v4i32 V128:$RHS))),
4112 (!cast<Instruction>(NAME#"v16i8")
4113 V128:$LHS, V128:$MHS, V128:$RHS)>;
4114 def : Pat<(v2i64 (OpNode (v2i64 V128:$LHS), (v2i64 V128:$MHS),
4115 (v2i64 V128:$RHS))),
4116 (!cast<Instruction>(NAME#"v16i8")
4117 V128:$LHS, V128:$MHS, V128:$RHS)>;
4121 //----------------------------------------------------------------------------
4122 // AdvSIMD two register vector instructions.
4123 //----------------------------------------------------------------------------
4125 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4126 class BaseSIMDTwoSameVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4127 RegisterOperand regtype, string asm, string dstkind,
4128 string srckind, list<dag> pattern>
4129 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4130 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4131 "|" # dstkind # "\t$Rd, $Rn}", "", pattern>,
4138 let Inst{28-24} = 0b01110;
4139 let Inst{23-22} = size;
4140 let Inst{21-17} = 0b10000;
4141 let Inst{16-12} = opcode;
4142 let Inst{11-10} = 0b10;
4147 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4148 class BaseSIMDTwoSameVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4149 RegisterOperand regtype, string asm, string dstkind,
4150 string srckind, list<dag> pattern>
4151 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype:$Rn), asm,
4152 "{\t$Rd" # dstkind # ", $Rn" # srckind #
4153 "|" # dstkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4160 let Inst{28-24} = 0b01110;
4161 let Inst{23-22} = size;
4162 let Inst{21-17} = 0b10000;
4163 let Inst{16-12} = opcode;
4164 let Inst{11-10} = 0b10;
4169 // Supports B, H, and S element sizes.
4170 multiclass SIMDTwoVectorBHS<bit U, bits<5> opc, string asm,
4171 SDPatternOperator OpNode> {
4172 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4174 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4175 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4176 asm, ".16b", ".16b",
4177 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4178 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4180 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4181 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4183 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4184 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4186 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4187 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4189 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4192 class BaseSIMDVectorLShiftLongBySize<bit Q, bits<2> size,
4193 RegisterOperand regtype, string asm, string dstkind,
4194 string srckind, string amount>
4195 : I<(outs V128:$Rd), (ins regtype:$Rn), asm,
4196 "{\t$Rd" # dstkind # ", $Rn" # srckind # ", #" # amount #
4197 "|" # dstkind # "\t$Rd, $Rn, #" # amount # "}", "", []>,
4203 let Inst{29-24} = 0b101110;
4204 let Inst{23-22} = size;
4205 let Inst{21-10} = 0b100001001110;
4210 multiclass SIMDVectorLShiftLongBySizeBHS {
4211 let neverHasSideEffects = 1 in {
4212 def v8i8 : BaseSIMDVectorLShiftLongBySize<0, 0b00, V64,
4213 "shll", ".8h", ".8b", "8">;
4214 def v16i8 : BaseSIMDVectorLShiftLongBySize<1, 0b00, V128,
4215 "shll2", ".8h", ".16b", "8">;
4216 def v4i16 : BaseSIMDVectorLShiftLongBySize<0, 0b01, V64,
4217 "shll", ".4s", ".4h", "16">;
4218 def v8i16 : BaseSIMDVectorLShiftLongBySize<1, 0b01, V128,
4219 "shll2", ".4s", ".8h", "16">;
4220 def v2i32 : BaseSIMDVectorLShiftLongBySize<0, 0b10, V64,
4221 "shll", ".2d", ".2s", "32">;
4222 def v4i32 : BaseSIMDVectorLShiftLongBySize<1, 0b10, V128,
4223 "shll2", ".2d", ".4s", "32">;
4227 // Supports all element sizes.
4228 multiclass SIMDLongTwoVector<bit U, bits<5> opc, string asm,
4229 SDPatternOperator OpNode> {
4230 def v8i8_v4i16 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4232 [(set (v4i16 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4233 def v16i8_v8i16 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4235 [(set (v8i16 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4236 def v4i16_v2i32 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4238 [(set (v2i32 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4239 def v8i16_v4i32 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4241 [(set (v4i32 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4242 def v2i32_v1i64 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4244 [(set (v1i64 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4245 def v4i32_v2i64 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4247 [(set (v2i64 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4250 multiclass SIMDLongTwoVectorTied<bit U, bits<5> opc, string asm,
4251 SDPatternOperator OpNode> {
4252 def v8i8_v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4254 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd),
4256 def v16i8_v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4258 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd),
4259 (v16i8 V128:$Rn)))]>;
4260 def v4i16_v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4262 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd),
4263 (v4i16 V64:$Rn)))]>;
4264 def v8i16_v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4266 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd),
4267 (v8i16 V128:$Rn)))]>;
4268 def v2i32_v1i64 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4270 [(set (v1i64 V64:$dst), (OpNode (v1i64 V64:$Rd),
4271 (v2i32 V64:$Rn)))]>;
4272 def v4i32_v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4274 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd),
4275 (v4i32 V128:$Rn)))]>;
4278 // Supports all element sizes, except 1xD.
4279 multiclass SIMDTwoVectorBHSDTied<bit U, bits<5> opc, string asm,
4280 SDPatternOperator OpNode> {
4281 def v8i8 : BaseSIMDTwoSameVectorTied<0, U, 0b00, opc, V64,
4283 [(set (v8i8 V64:$dst), (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn)))]>;
4284 def v16i8 : BaseSIMDTwoSameVectorTied<1, U, 0b00, opc, V128,
4285 asm, ".16b", ".16b",
4286 [(set (v16i8 V128:$dst), (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
4287 def v4i16 : BaseSIMDTwoSameVectorTied<0, U, 0b01, opc, V64,
4289 [(set (v4i16 V64:$dst), (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn)))]>;
4290 def v8i16 : BaseSIMDTwoSameVectorTied<1, U, 0b01, opc, V128,
4292 [(set (v8i16 V128:$dst), (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn)))]>;
4293 def v2i32 : BaseSIMDTwoSameVectorTied<0, U, 0b10, opc, V64,
4295 [(set (v2i32 V64:$dst), (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn)))]>;
4296 def v4i32 : BaseSIMDTwoSameVectorTied<1, U, 0b10, opc, V128,
4298 [(set (v4i32 V128:$dst), (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
4299 def v2i64 : BaseSIMDTwoSameVectorTied<1, U, 0b11, opc, V128,
4301 [(set (v2i64 V128:$dst), (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn)))]>;
4304 multiclass SIMDTwoVectorBHSD<bit U, bits<5> opc, string asm,
4305 SDPatternOperator OpNode = null_frag> {
4306 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4308 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4309 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4310 asm, ".16b", ".16b",
4311 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4312 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4314 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn)))]>;
4315 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4317 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4318 def v2i32 : BaseSIMDTwoSameVector<0, U, 0b10, opc, V64,
4320 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4321 def v4i32 : BaseSIMDTwoSameVector<1, U, 0b10, opc, V128,
4323 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4324 def v2i64 : BaseSIMDTwoSameVector<1, U, 0b11, opc, V128,
4326 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4330 // Supports only B element sizes.
4331 multiclass SIMDTwoVectorB<bit U, bits<2> size, bits<5> opc, string asm,
4332 SDPatternOperator OpNode> {
4333 def v8i8 : BaseSIMDTwoSameVector<0, U, size, opc, V64,
4335 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn)))]>;
4336 def v16i8 : BaseSIMDTwoSameVector<1, U, size, opc, V128,
4337 asm, ".16b", ".16b",
4338 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
4342 // Supports only B and H element sizes.
4343 multiclass SIMDTwoVectorBH<bit U, bits<5> opc, string asm,
4344 SDPatternOperator OpNode> {
4345 def v8i8 : BaseSIMDTwoSameVector<0, U, 0b00, opc, V64,
4347 [(set (v8i8 V64:$Rd), (OpNode V64:$Rn))]>;
4348 def v16i8 : BaseSIMDTwoSameVector<1, U, 0b00, opc, V128,
4349 asm, ".16b", ".16b",
4350 [(set (v16i8 V128:$Rd), (OpNode V128:$Rn))]>;
4351 def v4i16 : BaseSIMDTwoSameVector<0, U, 0b01, opc, V64,
4353 [(set (v4i16 V64:$Rd), (OpNode V64:$Rn))]>;
4354 def v8i16 : BaseSIMDTwoSameVector<1, U, 0b01, opc, V128,
4356 [(set (v8i16 V128:$Rd), (OpNode V128:$Rn))]>;
4359 // Supports only S and D element sizes, uses high bit of the size field
4360 // as an extra opcode bit.
4361 multiclass SIMDTwoVectorFP<bit U, bit S, bits<5> opc, string asm,
4362 SDPatternOperator OpNode> {
4363 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4365 [(set (v2f32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4366 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4368 [(set (v4f32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4369 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4371 [(set (v2f64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4374 // Supports only S element size.
4375 multiclass SIMDTwoVectorS<bit U, bit S, bits<5> opc, string asm,
4376 SDPatternOperator OpNode> {
4377 def v2i32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4379 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4380 def v4i32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4382 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4386 multiclass SIMDTwoVectorFPToInt<bit U, bit S, bits<5> opc, string asm,
4387 SDPatternOperator OpNode> {
4388 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4390 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn)))]>;
4391 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4393 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn)))]>;
4394 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4396 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4399 multiclass SIMDTwoVectorIntToFP<bit U, bit S, bits<5> opc, string asm,
4400 SDPatternOperator OpNode> {
4401 def v2f32 : BaseSIMDTwoSameVector<0, U, {S,0}, opc, V64,
4403 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn)))]>;
4404 def v4f32 : BaseSIMDTwoSameVector<1, U, {S,0}, opc, V128,
4406 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4407 def v2f64 : BaseSIMDTwoSameVector<1, U, {S,1}, opc, V128,
4409 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4413 class BaseSIMDMixedTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4414 RegisterOperand inreg, RegisterOperand outreg,
4415 string asm, string outkind, string inkind,
4417 : I<(outs outreg:$Rd), (ins inreg:$Rn), asm,
4418 "{\t$Rd" # outkind # ", $Rn" # inkind #
4419 "|" # outkind # "\t$Rd, $Rn}", "", pattern>,
4426 let Inst{28-24} = 0b01110;
4427 let Inst{23-22} = size;
4428 let Inst{21-17} = 0b10000;
4429 let Inst{16-12} = opcode;
4430 let Inst{11-10} = 0b10;
4435 class BaseSIMDMixedTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4436 RegisterOperand inreg, RegisterOperand outreg,
4437 string asm, string outkind, string inkind,
4439 : I<(outs outreg:$dst), (ins outreg:$Rd, inreg:$Rn), asm,
4440 "{\t$Rd" # outkind # ", $Rn" # inkind #
4441 "|" # outkind # "\t$Rd, $Rn}", "$Rd = $dst", pattern>,
4448 let Inst{28-24} = 0b01110;
4449 let Inst{23-22} = size;
4450 let Inst{21-17} = 0b10000;
4451 let Inst{16-12} = opcode;
4452 let Inst{11-10} = 0b10;
4457 multiclass SIMDMixedTwoVector<bit U, bits<5> opc, string asm,
4458 SDPatternOperator OpNode> {
4459 def v8i8 : BaseSIMDMixedTwoVector<0, U, 0b00, opc, V128, V64,
4461 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn)))]>;
4462 def v16i8 : BaseSIMDMixedTwoVectorTied<1, U, 0b00, opc, V128, V128,
4463 asm#"2", ".16b", ".8h", []>;
4464 def v4i16 : BaseSIMDMixedTwoVector<0, U, 0b01, opc, V128, V64,
4466 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn)))]>;
4467 def v8i16 : BaseSIMDMixedTwoVectorTied<1, U, 0b01, opc, V128, V128,
4468 asm#"2", ".8h", ".4s", []>;
4469 def v2i32 : BaseSIMDMixedTwoVector<0, U, 0b10, opc, V128, V64,
4471 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn)))]>;
4472 def v4i32 : BaseSIMDMixedTwoVectorTied<1, U, 0b10, opc, V128, V128,
4473 asm#"2", ".4s", ".2d", []>;
4475 def : Pat<(concat_vectors (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn))),
4476 (!cast<Instruction>(NAME # "v16i8")
4477 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4478 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn))),
4479 (!cast<Instruction>(NAME # "v8i16")
4480 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4481 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn))),
4482 (!cast<Instruction>(NAME # "v4i32")
4483 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4486 class BaseSIMDCmpTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4487 RegisterOperand regtype,
4488 string asm, string kind, string zero,
4489 ValueType dty, ValueType sty, SDNode OpNode>
4490 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
4491 "{\t$Rd" # kind # ", $Rn" # kind # ", #" # zero #
4492 "|" # kind # "\t$Rd, $Rn, #" # zero # "}", "",
4493 [(set (dty regtype:$Rd), (OpNode (sty regtype:$Rn)))]>,
4500 let Inst{28-24} = 0b01110;
4501 let Inst{23-22} = size;
4502 let Inst{21-17} = 0b10000;
4503 let Inst{16-12} = opcode;
4504 let Inst{11-10} = 0b10;
4509 // Comparisons support all element sizes, except 1xD.
4510 multiclass SIMDCmpTwoVector<bit U, bits<5> opc, string asm,
4512 def v8i8rz : BaseSIMDCmpTwoVector<0, U, 0b00, opc, V64,
4514 v8i8, v8i8, OpNode>;
4515 def v16i8rz : BaseSIMDCmpTwoVector<1, U, 0b00, opc, V128,
4517 v16i8, v16i8, OpNode>;
4518 def v4i16rz : BaseSIMDCmpTwoVector<0, U, 0b01, opc, V64,
4520 v4i16, v4i16, OpNode>;
4521 def v8i16rz : BaseSIMDCmpTwoVector<1, U, 0b01, opc, V128,
4523 v8i16, v8i16, OpNode>;
4524 def v2i32rz : BaseSIMDCmpTwoVector<0, U, 0b10, opc, V64,
4526 v2i32, v2i32, OpNode>;
4527 def v4i32rz : BaseSIMDCmpTwoVector<1, U, 0b10, opc, V128,
4529 v4i32, v4i32, OpNode>;
4530 def v2i64rz : BaseSIMDCmpTwoVector<1, U, 0b11, opc, V128,
4532 v2i64, v2i64, OpNode>;
4535 // FP Comparisons support only S and D element sizes.
4536 multiclass SIMDFPCmpTwoVector<bit U, bit S, bits<5> opc,
4537 string asm, SDNode OpNode> {
4539 def v2i32rz : BaseSIMDCmpTwoVector<0, U, {S,0}, opc, V64,
4541 v2i32, v2f32, OpNode>;
4542 def v4i32rz : BaseSIMDCmpTwoVector<1, U, {S,0}, opc, V128,
4544 v4i32, v4f32, OpNode>;
4545 def v2i64rz : BaseSIMDCmpTwoVector<1, U, {S,1}, opc, V128,
4547 v2i64, v2f64, OpNode>;
4549 def : InstAlias<asm # " $Vd.2s, $Vn.2s, #0",
4550 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4551 def : InstAlias<asm # " $Vd.4s, $Vn.4s, #0",
4552 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4553 def : InstAlias<asm # " $Vd.2d, $Vn.2d, #0",
4554 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4555 def : InstAlias<asm # ".2s $Vd, $Vn, #0",
4556 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4557 def : InstAlias<asm # ".4s $Vd, $Vn, #0",
4558 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4559 def : InstAlias<asm # ".2d $Vd, $Vn, #0",
4560 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4563 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4564 class BaseSIMDFPCvtTwoVector<bit Q, bit U, bits<2> size, bits<5> opcode,
4565 RegisterOperand outtype, RegisterOperand intype,
4566 string asm, string VdTy, string VnTy,
4568 : I<(outs outtype:$Rd), (ins intype:$Rn), asm,
4569 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "", pattern>,
4576 let Inst{28-24} = 0b01110;
4577 let Inst{23-22} = size;
4578 let Inst{21-17} = 0b10000;
4579 let Inst{16-12} = opcode;
4580 let Inst{11-10} = 0b10;
4585 class BaseSIMDFPCvtTwoVectorTied<bit Q, bit U, bits<2> size, bits<5> opcode,
4586 RegisterOperand outtype, RegisterOperand intype,
4587 string asm, string VdTy, string VnTy,
4589 : I<(outs outtype:$dst), (ins outtype:$Rd, intype:$Rn), asm,
4590 !strconcat("\t$Rd", VdTy, ", $Rn", VnTy), "$Rd = $dst", pattern>,
4597 let Inst{28-24} = 0b01110;
4598 let Inst{23-22} = size;
4599 let Inst{21-17} = 0b10000;
4600 let Inst{16-12} = opcode;
4601 let Inst{11-10} = 0b10;
4606 multiclass SIMDFPWidenTwoVector<bit U, bit S, bits<5> opc, string asm> {
4607 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V128, V64,
4608 asm, ".4s", ".4h", []>;
4609 def v8i16 : BaseSIMDFPCvtTwoVector<1, U, {S,0}, opc, V128, V128,
4610 asm#"2", ".4s", ".8h", []>;
4611 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V128, V64,
4612 asm, ".2d", ".2s", []>;
4613 def v4i32 : BaseSIMDFPCvtTwoVector<1, U, {S,1}, opc, V128, V128,
4614 asm#"2", ".2d", ".4s", []>;
4617 multiclass SIMDFPNarrowTwoVector<bit U, bit S, bits<5> opc, string asm> {
4618 def v4i16 : BaseSIMDFPCvtTwoVector<0, U, {S,0}, opc, V64, V128,
4619 asm, ".4h", ".4s", []>;
4620 def v8i16 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,0}, opc, V128, V128,
4621 asm#"2", ".8h", ".4s", []>;
4622 def v2i32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4623 asm, ".2s", ".2d", []>;
4624 def v4i32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4625 asm#"2", ".4s", ".2d", []>;
4628 multiclass SIMDFPInexactCvtTwoVector<bit U, bit S, bits<5> opc, string asm,
4630 def v2f32 : BaseSIMDFPCvtTwoVector<0, U, {S,1}, opc, V64, V128,
4632 [(set (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn)))]>;
4633 def v4f32 : BaseSIMDFPCvtTwoVectorTied<1, U, {S,1}, opc, V128, V128,
4634 asm#"2", ".4s", ".2d", []>;
4636 def : Pat<(concat_vectors (v2f32 V64:$Rd), (OpNode (v2f64 V128:$Rn))),
4637 (!cast<Instruction>(NAME # "v4f32")
4638 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
4641 //----------------------------------------------------------------------------
4642 // AdvSIMD three register different-size vector instructions.
4643 //----------------------------------------------------------------------------
4645 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4646 class BaseSIMDDifferentThreeVector<bit U, bits<3> size, bits<4> opcode,
4647 RegisterOperand outtype, RegisterOperand intype1,
4648 RegisterOperand intype2, string asm,
4649 string outkind, string inkind1, string inkind2,
4651 : I<(outs outtype:$Rd), (ins intype1:$Rn, intype2:$Rm), asm,
4652 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4653 "|" # outkind # "\t$Rd, $Rn, $Rm}", "", pattern>,
4659 let Inst{30} = size{0};
4661 let Inst{28-24} = 0b01110;
4662 let Inst{23-22} = size{2-1};
4664 let Inst{20-16} = Rm;
4665 let Inst{15-12} = opcode;
4666 let Inst{11-10} = 0b00;
4671 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
4672 class BaseSIMDDifferentThreeVectorTied<bit U, bits<3> size, bits<4> opcode,
4673 RegisterOperand outtype, RegisterOperand intype1,
4674 RegisterOperand intype2, string asm,
4675 string outkind, string inkind1, string inkind2,
4677 : I<(outs outtype:$dst), (ins outtype:$Rd, intype1:$Rn, intype2:$Rm), asm,
4678 "{\t$Rd" # outkind # ", $Rn" # inkind1 # ", $Rm" # inkind2 #
4679 "|" # outkind # "\t$Rd, $Rn, $Rm}", "$Rd = $dst", pattern>,
4685 let Inst{30} = size{0};
4687 let Inst{28-24} = 0b01110;
4688 let Inst{23-22} = size{2-1};
4690 let Inst{20-16} = Rm;
4691 let Inst{15-12} = opcode;
4692 let Inst{11-10} = 0b00;
4697 // FIXME: TableGen doesn't know how to deal with expanded types that also
4698 // change the element count (in this case, placing the results in
4699 // the high elements of the result register rather than the low
4700 // elements). Until that's fixed, we can't code-gen those.
4701 multiclass SIMDNarrowThreeVectorBHS<bit U, bits<4> opc, string asm,
4703 def v8i16_v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4705 asm, ".8b", ".8h", ".8h",
4706 [(set (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn), (v8i16 V128:$Rm)))]>;
4707 def v8i16_v16i8 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4709 asm#"2", ".16b", ".8h", ".8h",
4711 def v4i32_v4i16 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4713 asm, ".4h", ".4s", ".4s",
4714 [(set (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn), (v4i32 V128:$Rm)))]>;
4715 def v4i32_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4717 asm#"2", ".8h", ".4s", ".4s",
4719 def v2i64_v2i32 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4721 asm, ".2s", ".2d", ".2d",
4722 [(set (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn), (v2i64 V128:$Rm)))]>;
4723 def v2i64_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4725 asm#"2", ".4s", ".2d", ".2d",
4729 // Patterns for the '2' variants involve INSERT_SUBREG, which you can't put in
4730 // a version attached to an instruction.
4731 def : Pat<(concat_vectors (v8i8 V64:$Rd), (IntOp (v8i16 V128:$Rn),
4733 (!cast<Instruction>(NAME # "v8i16_v16i8")
4734 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4735 V128:$Rn, V128:$Rm)>;
4736 def : Pat<(concat_vectors (v4i16 V64:$Rd), (IntOp (v4i32 V128:$Rn),
4738 (!cast<Instruction>(NAME # "v4i32_v8i16")
4739 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4740 V128:$Rn, V128:$Rm)>;
4741 def : Pat<(concat_vectors (v2i32 V64:$Rd), (IntOp (v2i64 V128:$Rn),
4743 (!cast<Instruction>(NAME # "v2i64_v4i32")
4744 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4745 V128:$Rn, V128:$Rm)>;
4748 multiclass SIMDDifferentThreeVectorBD<bit U, bits<4> opc, string asm,
4750 def v8i8 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4752 asm, ".8h", ".8b", ".8b",
4753 [(set (v8i16 V128:$Rd), (IntOp (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4754 def v16i8 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4756 asm#"2", ".8h", ".16b", ".16b", []>;
4757 let Predicates = [HasCrypto] in {
4758 def v1i64 : BaseSIMDDifferentThreeVector<U, 0b110, opc,
4760 asm, ".1q", ".1d", ".1d", []>;
4761 def v2i64 : BaseSIMDDifferentThreeVector<U, 0b111, opc,
4763 asm#"2", ".1q", ".2d", ".2d", []>;
4766 def : Pat<(v8i16 (IntOp (v8i8 (extract_high_v16i8 V128:$Rn)),
4767 (v8i8 (extract_high_v16i8 V128:$Rm)))),
4768 (!cast<Instruction>(NAME#"v16i8") V128:$Rn, V128:$Rm)>;
4771 multiclass SIMDLongThreeVectorHS<bit U, bits<4> opc, string asm,
4772 SDPatternOperator OpNode> {
4773 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4775 asm, ".4s", ".4h", ".4h",
4776 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4777 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4779 asm#"2", ".4s", ".8h", ".8h",
4780 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
4781 (extract_high_v8i16 V128:$Rm)))]>;
4782 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4784 asm, ".2d", ".2s", ".2s",
4785 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4786 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4788 asm#"2", ".2d", ".4s", ".4s",
4789 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
4790 (extract_high_v4i32 V128:$Rm)))]>;
4793 multiclass SIMDLongThreeVectorBHSabdl<bit U, bits<4> opc, string asm,
4794 SDPatternOperator OpNode = null_frag> {
4795 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4797 asm, ".8h", ".8b", ".8b",
4798 [(set (v8i16 V128:$Rd),
4799 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))))]>;
4800 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4802 asm#"2", ".8h", ".16b", ".16b",
4803 [(set (v8i16 V128:$Rd),
4804 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
4805 (extract_high_v16i8 V128:$Rm)))))]>;
4806 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4808 asm, ".4s", ".4h", ".4h",
4809 [(set (v4i32 V128:$Rd),
4810 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))))]>;
4811 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4813 asm#"2", ".4s", ".8h", ".8h",
4814 [(set (v4i32 V128:$Rd),
4815 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
4816 (extract_high_v8i16 V128:$Rm)))))]>;
4817 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4819 asm, ".2d", ".2s", ".2s",
4820 [(set (v2i64 V128:$Rd),
4821 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))))]>;
4822 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4824 asm#"2", ".2d", ".4s", ".4s",
4825 [(set (v2i64 V128:$Rd),
4826 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
4827 (extract_high_v4i32 V128:$Rm)))))]>;
4830 multiclass SIMDLongThreeVectorTiedBHSabal<bit U, bits<4> opc,
4832 SDPatternOperator OpNode> {
4833 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
4835 asm, ".8h", ".8b", ".8b",
4836 [(set (v8i16 V128:$dst),
4837 (add (v8i16 V128:$Rd),
4838 (zext (v8i8 (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm))))))]>;
4839 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4841 asm#"2", ".8h", ".16b", ".16b",
4842 [(set (v8i16 V128:$dst),
4843 (add (v8i16 V128:$Rd),
4844 (zext (v8i8 (OpNode (extract_high_v16i8 V128:$Rn),
4845 (extract_high_v16i8 V128:$Rm))))))]>;
4846 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
4848 asm, ".4s", ".4h", ".4h",
4849 [(set (v4i32 V128:$dst),
4850 (add (v4i32 V128:$Rd),
4851 (zext (v4i16 (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm))))))]>;
4852 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4854 asm#"2", ".4s", ".8h", ".8h",
4855 [(set (v4i32 V128:$dst),
4856 (add (v4i32 V128:$Rd),
4857 (zext (v4i16 (OpNode (extract_high_v8i16 V128:$Rn),
4858 (extract_high_v8i16 V128:$Rm))))))]>;
4859 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
4861 asm, ".2d", ".2s", ".2s",
4862 [(set (v2i64 V128:$dst),
4863 (add (v2i64 V128:$Rd),
4864 (zext (v2i32 (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm))))))]>;
4865 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4867 asm#"2", ".2d", ".4s", ".4s",
4868 [(set (v2i64 V128:$dst),
4869 (add (v2i64 V128:$Rd),
4870 (zext (v2i32 (OpNode (extract_high_v4i32 V128:$Rn),
4871 (extract_high_v4i32 V128:$Rm))))))]>;
4874 multiclass SIMDLongThreeVectorBHS<bit U, bits<4> opc, string asm,
4875 SDPatternOperator OpNode = null_frag> {
4876 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4878 asm, ".8h", ".8b", ".8b",
4879 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4880 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4882 asm#"2", ".8h", ".16b", ".16b",
4883 [(set (v8i16 V128:$Rd), (OpNode (extract_high_v16i8 V128:$Rn),
4884 (extract_high_v16i8 V128:$Rm)))]>;
4885 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4887 asm, ".4s", ".4h", ".4h",
4888 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4889 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4891 asm#"2", ".4s", ".8h", ".8h",
4892 [(set (v4i32 V128:$Rd), (OpNode (extract_high_v8i16 V128:$Rn),
4893 (extract_high_v8i16 V128:$Rm)))]>;
4894 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
4896 asm, ".2d", ".2s", ".2s",
4897 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4898 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
4900 asm#"2", ".2d", ".4s", ".4s",
4901 [(set (v2i64 V128:$Rd), (OpNode (extract_high_v4i32 V128:$Rn),
4902 (extract_high_v4i32 V128:$Rm)))]>;
4905 multiclass SIMDLongThreeVectorTiedBHS<bit U, bits<4> opc,
4907 SDPatternOperator OpNode> {
4908 def v8i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b000, opc,
4910 asm, ".8h", ".8b", ".8b",
4911 [(set (v8i16 V128:$dst),
4912 (OpNode (v8i16 V128:$Rd), (v8i8 V64:$Rn), (v8i8 V64:$Rm)))]>;
4913 def v16i8_v8i16 : BaseSIMDDifferentThreeVectorTied<U, 0b001, opc,
4915 asm#"2", ".8h", ".16b", ".16b",
4916 [(set (v8i16 V128:$dst),
4917 (OpNode (v8i16 V128:$Rd),
4918 (extract_high_v16i8 V128:$Rn),
4919 (extract_high_v16i8 V128:$Rm)))]>;
4920 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
4922 asm, ".4s", ".4h", ".4h",
4923 [(set (v4i32 V128:$dst),
4924 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn), (v4i16 V64:$Rm)))]>;
4925 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4927 asm#"2", ".4s", ".8h", ".8h",
4928 [(set (v4i32 V128:$dst),
4929 (OpNode (v4i32 V128:$Rd),
4930 (extract_high_v8i16 V128:$Rn),
4931 (extract_high_v8i16 V128:$Rm)))]>;
4932 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
4934 asm, ".2d", ".2s", ".2s",
4935 [(set (v2i64 V128:$dst),
4936 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn), (v2i32 V64:$Rm)))]>;
4937 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4939 asm#"2", ".2d", ".4s", ".4s",
4940 [(set (v2i64 V128:$dst),
4941 (OpNode (v2i64 V128:$Rd),
4942 (extract_high_v4i32 V128:$Rn),
4943 (extract_high_v4i32 V128:$Rm)))]>;
4946 multiclass SIMDLongThreeVectorSQDMLXTiedHS<bit U, bits<4> opc, string asm,
4947 SDPatternOperator Accum> {
4948 def v4i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b010, opc,
4950 asm, ".4s", ".4h", ".4h",
4951 [(set (v4i32 V128:$dst),
4952 (Accum (v4i32 V128:$Rd),
4953 (v4i32 (int_arm64_neon_sqdmull (v4i16 V64:$Rn),
4954 (v4i16 V64:$Rm)))))]>;
4955 def v8i16_v4i32 : BaseSIMDDifferentThreeVectorTied<U, 0b011, opc,
4957 asm#"2", ".4s", ".8h", ".8h",
4958 [(set (v4i32 V128:$dst),
4959 (Accum (v4i32 V128:$Rd),
4960 (v4i32 (int_arm64_neon_sqdmull (extract_high_v8i16 V128:$Rn),
4961 (extract_high_v8i16 V128:$Rm)))))]>;
4962 def v2i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b100, opc,
4964 asm, ".2d", ".2s", ".2s",
4965 [(set (v2i64 V128:$dst),
4966 (Accum (v2i64 V128:$Rd),
4967 (v2i64 (int_arm64_neon_sqdmull (v2i32 V64:$Rn),
4968 (v2i32 V64:$Rm)))))]>;
4969 def v4i32_v2i64 : BaseSIMDDifferentThreeVectorTied<U, 0b101, opc,
4971 asm#"2", ".2d", ".4s", ".4s",
4972 [(set (v2i64 V128:$dst),
4973 (Accum (v2i64 V128:$Rd),
4974 (v2i64 (int_arm64_neon_sqdmull (extract_high_v4i32 V128:$Rn),
4975 (extract_high_v4i32 V128:$Rm)))))]>;
4978 multiclass SIMDWideThreeVectorBHS<bit U, bits<4> opc, string asm,
4979 SDPatternOperator OpNode> {
4980 def v8i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b000, opc,
4982 asm, ".8h", ".8h", ".8b",
4983 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn), (v8i8 V64:$Rm)))]>;
4984 def v16i8_v8i16 : BaseSIMDDifferentThreeVector<U, 0b001, opc,
4986 asm#"2", ".8h", ".8h", ".16b",
4987 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
4988 (extract_high_v16i8 V128:$Rm)))]>;
4989 def v4i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b010, opc,
4991 asm, ".4s", ".4s", ".4h",
4992 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (v4i16 V64:$Rm)))]>;
4993 def v8i16_v4i32 : BaseSIMDDifferentThreeVector<U, 0b011, opc,
4995 asm#"2", ".4s", ".4s", ".8h",
4996 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
4997 (extract_high_v8i16 V128:$Rm)))]>;
4998 def v2i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b100, opc,
5000 asm, ".2d", ".2d", ".2s",
5001 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (v2i32 V64:$Rm)))]>;
5002 def v4i32_v2i64 : BaseSIMDDifferentThreeVector<U, 0b101, opc,
5004 asm#"2", ".2d", ".2d", ".4s",
5005 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
5006 (extract_high_v4i32 V128:$Rm)))]>;
5009 //----------------------------------------------------------------------------
5010 // AdvSIMD bitwise extract from vector
5011 //----------------------------------------------------------------------------
5013 class BaseSIMDBitwiseExtract<bit size, RegisterOperand regtype, ValueType vty,
5014 string asm, string kind>
5015 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm, i32imm:$imm), asm,
5016 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind # ", $imm" #
5017 "|" # kind # "\t$Rd, $Rn, $Rm, $imm}", "",
5018 [(set (vty regtype:$Rd),
5019 (ARM64ext regtype:$Rn, regtype:$Rm, (i32 imm:$imm)))]>,
5026 let Inst{30} = size;
5027 let Inst{29-21} = 0b101110000;
5028 let Inst{20-16} = Rm;
5030 let Inst{14-11} = imm;
5037 multiclass SIMDBitwiseExtract<string asm> {
5038 def v8i8 : BaseSIMDBitwiseExtract<0, V64, v8i8, asm, ".8b"> {
5041 def v16i8 : BaseSIMDBitwiseExtract<1, V128, v16i8, asm, ".16b">;
5044 //----------------------------------------------------------------------------
5045 // AdvSIMD zip vector
5046 //----------------------------------------------------------------------------
5048 class BaseSIMDZipVector<bits<3> size, bits<3> opc, RegisterOperand regtype,
5049 string asm, string kind, SDNode OpNode, ValueType valty>
5050 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5051 "{\t$Rd" # kind # ", $Rn" # kind # ", $Rm" # kind #
5052 "|" # kind # "\t$Rd, $Rn, $Rm}", "",
5053 [(set (valty regtype:$Rd), (OpNode regtype:$Rn, regtype:$Rm))]>,
5059 let Inst{30} = size{0};
5060 let Inst{29-24} = 0b001110;
5061 let Inst{23-22} = size{2-1};
5063 let Inst{20-16} = Rm;
5065 let Inst{14-12} = opc;
5066 let Inst{11-10} = 0b10;
5071 multiclass SIMDZipVector<bits<3>opc, string asm,
5073 def v8i8 : BaseSIMDZipVector<0b000, opc, V64,
5074 asm, ".8b", OpNode, v8i8>;
5075 def v16i8 : BaseSIMDZipVector<0b001, opc, V128,
5076 asm, ".16b", OpNode, v16i8>;
5077 def v4i16 : BaseSIMDZipVector<0b010, opc, V64,
5078 asm, ".4h", OpNode, v4i16>;
5079 def v8i16 : BaseSIMDZipVector<0b011, opc, V128,
5080 asm, ".8h", OpNode, v8i16>;
5081 def v2i32 : BaseSIMDZipVector<0b100, opc, V64,
5082 asm, ".2s", OpNode, v2i32>;
5083 def v4i32 : BaseSIMDZipVector<0b101, opc, V128,
5084 asm, ".4s", OpNode, v4i32>;
5085 def v2i64 : BaseSIMDZipVector<0b111, opc, V128,
5086 asm, ".2d", OpNode, v2i64>;
5088 def : Pat<(v2f32 (OpNode V64:$Rn, V64:$Rm)),
5089 (!cast<Instruction>(NAME#"v2i32") V64:$Rn, V64:$Rm)>;
5090 def : Pat<(v4f32 (OpNode V128:$Rn, V128:$Rm)),
5091 (!cast<Instruction>(NAME#"v4i32") V128:$Rn, V128:$Rm)>;
5092 def : Pat<(v2f64 (OpNode V128:$Rn, V128:$Rm)),
5093 (!cast<Instruction>(NAME#"v2i64") V128:$Rn, V128:$Rm)>;
5096 //----------------------------------------------------------------------------
5097 // AdvSIMD three register scalar instructions
5098 //----------------------------------------------------------------------------
5100 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5101 class BaseSIMDThreeScalar<bit U, bits<2> size, bits<5> opcode,
5102 RegisterClass regtype, string asm,
5104 : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm), asm,
5105 "\t$Rd, $Rn, $Rm", "", pattern>,
5110 let Inst{31-30} = 0b01;
5112 let Inst{28-24} = 0b11110;
5113 let Inst{23-22} = size;
5115 let Inst{20-16} = Rm;
5116 let Inst{15-11} = opcode;
5122 multiclass SIMDThreeScalarD<bit U, bits<5> opc, string asm,
5123 SDPatternOperator OpNode> {
5124 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5125 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5128 multiclass SIMDThreeScalarBHSD<bit U, bits<5> opc, string asm,
5129 SDPatternOperator OpNode> {
5130 def v1i64 : BaseSIMDThreeScalar<U, 0b11, opc, FPR64, asm,
5131 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn), (v1i64 FPR64:$Rm)))]>;
5132 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm, []>;
5133 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5134 def v1i8 : BaseSIMDThreeScalar<U, 0b00, opc, FPR8 , asm, []>;
5136 def : Pat<(i64 (OpNode (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5137 (!cast<Instruction>(NAME#"v1i64") FPR64:$Rn, FPR64:$Rm)>;
5138 def : Pat<(i32 (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm))),
5139 (!cast<Instruction>(NAME#"v1i32") FPR32:$Rn, FPR32:$Rm)>;
5142 multiclass SIMDThreeScalarHS<bit U, bits<5> opc, string asm,
5143 SDPatternOperator OpNode> {
5144 def v1i32 : BaseSIMDThreeScalar<U, 0b10, opc, FPR32, asm,
5145 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5146 def v1i16 : BaseSIMDThreeScalar<U, 0b01, opc, FPR16, asm, []>;
5149 multiclass SIMDThreeScalarSD<bit U, bit S, bits<5> opc, string asm,
5150 SDPatternOperator OpNode = null_frag> {
5151 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5152 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5153 [(set (f64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5154 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5155 [(set FPR32:$Rd, (OpNode FPR32:$Rn, FPR32:$Rm))]>;
5158 def : Pat<(v1f64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5159 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5162 multiclass SIMDThreeScalarFPCmp<bit U, bit S, bits<5> opc, string asm,
5163 SDPatternOperator OpNode = null_frag> {
5164 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5165 def #NAME#64 : BaseSIMDThreeScalar<U, {S,1}, opc, FPR64, asm,
5166 [(set (i64 FPR64:$Rd), (OpNode (f64 FPR64:$Rn), (f64 FPR64:$Rm)))]>;
5167 def #NAME#32 : BaseSIMDThreeScalar<U, {S,0}, opc, FPR32, asm,
5168 [(set (i32 FPR32:$Rd), (OpNode (f32 FPR32:$Rn), (f32 FPR32:$Rm)))]>;
5171 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
5172 (!cast<Instruction>(NAME # "64") FPR64:$Rn, FPR64:$Rm)>;
5175 class BaseSIMDThreeScalarMixed<bit U, bits<2> size, bits<5> opcode,
5176 dag oops, dag iops, string asm, string cstr, list<dag> pat>
5177 : I<oops, iops, asm,
5178 "\t$Rd, $Rn, $Rm", cstr, pat>,
5183 let Inst{31-30} = 0b01;
5185 let Inst{28-24} = 0b11110;
5186 let Inst{23-22} = size;
5188 let Inst{20-16} = Rm;
5189 let Inst{15-11} = opcode;
5195 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5196 multiclass SIMDThreeScalarMixedHS<bit U, bits<5> opc, string asm,
5197 SDPatternOperator OpNode = null_frag> {
5198 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5200 (ins FPR16:$Rn, FPR16:$Rm), asm, "", []>;
5201 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5203 (ins FPR32:$Rn, FPR32:$Rm), asm, "",
5204 [(set (i64 FPR64:$Rd), (OpNode (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5207 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5208 multiclass SIMDThreeScalarMixedTiedHS<bit U, bits<5> opc, string asm,
5209 SDPatternOperator OpNode = null_frag> {
5210 def i16 : BaseSIMDThreeScalarMixed<U, 0b01, opc,
5212 (ins FPR32:$Rd, FPR16:$Rn, FPR16:$Rm),
5213 asm, "$Rd = $dst", []>;
5214 def i32 : BaseSIMDThreeScalarMixed<U, 0b10, opc,
5216 (ins FPR64:$Rd, FPR32:$Rn, FPR32:$Rm),
5218 [(set (i64 FPR64:$dst),
5219 (OpNode (i64 FPR64:$Rd), (i32 FPR32:$Rn), (i32 FPR32:$Rm)))]>;
5222 //----------------------------------------------------------------------------
5223 // AdvSIMD two register scalar instructions
5224 //----------------------------------------------------------------------------
5226 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5227 class BaseSIMDTwoScalar<bit U, bits<2> size, bits<5> opcode,
5228 RegisterClass regtype, RegisterClass regtype2,
5229 string asm, list<dag> pat>
5230 : I<(outs regtype:$Rd), (ins regtype2:$Rn), asm,
5231 "\t$Rd, $Rn", "", pat>,
5235 let Inst{31-30} = 0b01;
5237 let Inst{28-24} = 0b11110;
5238 let Inst{23-22} = size;
5239 let Inst{21-17} = 0b10000;
5240 let Inst{16-12} = opcode;
5241 let Inst{11-10} = 0b10;
5246 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5247 class BaseSIMDTwoScalarTied<bit U, bits<2> size, bits<5> opcode,
5248 RegisterClass regtype, RegisterClass regtype2,
5249 string asm, list<dag> pat>
5250 : I<(outs regtype:$dst), (ins regtype:$Rd, regtype2:$Rn), asm,
5251 "\t$Rd, $Rn", "$Rd = $dst", pat>,
5255 let Inst{31-30} = 0b01;
5257 let Inst{28-24} = 0b11110;
5258 let Inst{23-22} = size;
5259 let Inst{21-17} = 0b10000;
5260 let Inst{16-12} = opcode;
5261 let Inst{11-10} = 0b10;
5267 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5268 class BaseSIMDCmpTwoScalar<bit U, bits<2> size, bits<5> opcode,
5269 RegisterClass regtype, string asm, string zero>
5270 : I<(outs regtype:$Rd), (ins regtype:$Rn), asm,
5271 "\t$Rd, $Rn, #" # zero, "", []>,
5275 let Inst{31-30} = 0b01;
5277 let Inst{28-24} = 0b11110;
5278 let Inst{23-22} = size;
5279 let Inst{21-17} = 0b10000;
5280 let Inst{16-12} = opcode;
5281 let Inst{11-10} = 0b10;
5286 class SIMDInexactCvtTwoScalar<bits<5> opcode, string asm>
5287 : I<(outs FPR32:$Rd), (ins FPR64:$Rn), asm, "\t$Rd, $Rn", "",
5288 [(set (f32 FPR32:$Rd), (int_arm64_sisd_fcvtxn (f64 FPR64:$Rn)))]>,
5292 let Inst{31-17} = 0b011111100110000;
5293 let Inst{16-12} = opcode;
5294 let Inst{11-10} = 0b10;
5299 multiclass SIMDCmpTwoScalarD<bit U, bits<5> opc, string asm,
5300 SDPatternOperator OpNode> {
5301 def v1i64rz : BaseSIMDCmpTwoScalar<U, 0b11, opc, FPR64, asm, "0">;
5303 def : Pat<(v1i64 (OpNode FPR64:$Rn)),
5304 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5307 multiclass SIMDCmpTwoScalarSD<bit U, bit S, bits<5> opc, string asm,
5308 SDPatternOperator OpNode> {
5309 def v1i64rz : BaseSIMDCmpTwoScalar<U, {S,1}, opc, FPR64, asm, "0.0">;
5310 def v1i32rz : BaseSIMDCmpTwoScalar<U, {S,0}, opc, FPR32, asm, "0.0">;
5312 def : InstAlias<asm # " $Rd, $Rn, #0",
5313 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rd, FPR64:$Rn)>;
5314 def : InstAlias<asm # " $Rd, $Rn, #0",
5315 (!cast<Instruction>(NAME # v1i32rz) FPR32:$Rd, FPR32:$Rn)>;
5317 def : Pat<(v1i64 (OpNode (v1f64 FPR64:$Rn))),
5318 (!cast<Instruction>(NAME # v1i64rz) FPR64:$Rn)>;
5321 multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
5322 SDPatternOperator OpNode = null_frag> {
5323 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5324 [(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
5326 def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
5327 (!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
5330 multiclass SIMDTwoScalarSD<bit U, bit S, bits<5> opc, string asm> {
5331 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,[]>;
5332 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,[]>;
5335 multiclass SIMDTwoScalarCVTSD<bit U, bit S, bits<5> opc, string asm,
5336 SDPatternOperator OpNode> {
5337 def v1i64 : BaseSIMDTwoScalar<U, {S,1}, opc, FPR64, FPR64, asm,
5338 [(set FPR64:$Rd, (OpNode (f64 FPR64:$Rn)))]>;
5339 def v1i32 : BaseSIMDTwoScalar<U, {S,0}, opc, FPR32, FPR32, asm,
5340 [(set FPR32:$Rd, (OpNode (f32 FPR32:$Rn)))]>;
5343 multiclass SIMDTwoScalarBHSD<bit U, bits<5> opc, string asm,
5344 SDPatternOperator OpNode = null_frag> {
5345 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5346 def v1i64 : BaseSIMDTwoScalar<U, 0b11, opc, FPR64, FPR64, asm,
5347 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5348 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR32, asm,
5349 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
5350 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR16, asm, []>;
5351 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5354 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn))),
5355 (!cast<Instruction>(NAME # v1i64) FPR64:$Rn)>;
5358 multiclass SIMDTwoScalarBHSDTied<bit U, bits<5> opc, string asm,
5360 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
5361 def v1i64 : BaseSIMDTwoScalarTied<U, 0b11, opc, FPR64, FPR64, asm,
5362 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn)))]>;
5363 def v1i32 : BaseSIMDTwoScalarTied<U, 0b10, opc, FPR32, FPR32, asm,
5364 [(set (i32 FPR32:$dst), (OpNode (i32 FPR32:$Rd), (i32 FPR32:$Rn)))]>;
5365 def v1i16 : BaseSIMDTwoScalarTied<U, 0b01, opc, FPR16, FPR16, asm, []>;
5366 def v1i8 : BaseSIMDTwoScalarTied<U, 0b00, opc, FPR8 , FPR8 , asm, []>;
5369 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn))),
5370 (!cast<Instruction>(NAME # v1i64) FPR64:$Rd, FPR64:$Rn)>;
5375 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5376 multiclass SIMDTwoScalarMixedBHS<bit U, bits<5> opc, string asm,
5377 SDPatternOperator OpNode = null_frag> {
5378 def v1i32 : BaseSIMDTwoScalar<U, 0b10, opc, FPR32, FPR64, asm,
5379 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn)))]>;
5380 def v1i16 : BaseSIMDTwoScalar<U, 0b01, opc, FPR16, FPR32, asm, []>;
5381 def v1i8 : BaseSIMDTwoScalar<U, 0b00, opc, FPR8 , FPR16, asm, []>;
5384 //----------------------------------------------------------------------------
5385 // AdvSIMD scalar pairwise instructions
5386 //----------------------------------------------------------------------------
5388 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5389 class BaseSIMDPairwiseScalar<bit U, bits<2> size, bits<5> opcode,
5390 RegisterOperand regtype, RegisterOperand vectype,
5391 string asm, string kind>
5392 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5393 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", []>,
5397 let Inst{31-30} = 0b01;
5399 let Inst{28-24} = 0b11110;
5400 let Inst{23-22} = size;
5401 let Inst{21-17} = 0b11000;
5402 let Inst{16-12} = opcode;
5403 let Inst{11-10} = 0b10;
5408 multiclass SIMDPairwiseScalarD<bit U, bits<5> opc, string asm> {
5409 def v2i64p : BaseSIMDPairwiseScalar<U, 0b11, opc, FPR64Op, V128,
5413 multiclass SIMDPairwiseScalarSD<bit U, bit S, bits<5> opc, string asm> {
5414 def v2i32p : BaseSIMDPairwiseScalar<U, {S,0}, opc, FPR32Op, V64,
5416 def v2i64p : BaseSIMDPairwiseScalar<U, {S,1}, opc, FPR64Op, V128,
5420 //----------------------------------------------------------------------------
5421 // AdvSIMD across lanes instructions
5422 //----------------------------------------------------------------------------
5424 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5425 class BaseSIMDAcrossLanes<bit Q, bit U, bits<2> size, bits<5> opcode,
5426 RegisterClass regtype, RegisterOperand vectype,
5427 string asm, string kind, list<dag> pattern>
5428 : I<(outs regtype:$Rd), (ins vectype:$Rn), asm,
5429 "{\t$Rd, $Rn" # kind # "|" # kind # "\t$Rd, $Rn}", "", pattern>,
5436 let Inst{28-24} = 0b01110;
5437 let Inst{23-22} = size;
5438 let Inst{21-17} = 0b11000;
5439 let Inst{16-12} = opcode;
5440 let Inst{11-10} = 0b10;
5445 multiclass SIMDAcrossLanesBHS<bit U, bits<5> opcode,
5447 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR8, V64,
5449 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR8, V128,
5451 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR16, V64,
5453 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR16, V128,
5455 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR32, V128,
5459 multiclass SIMDAcrossLanesHSD<bit U, bits<5> opcode, string asm> {
5460 def v8i8v : BaseSIMDAcrossLanes<0, U, 0b00, opcode, FPR16, V64,
5462 def v16i8v : BaseSIMDAcrossLanes<1, U, 0b00, opcode, FPR16, V128,
5464 def v4i16v : BaseSIMDAcrossLanes<0, U, 0b01, opcode, FPR32, V64,
5466 def v8i16v : BaseSIMDAcrossLanes<1, U, 0b01, opcode, FPR32, V128,
5468 def v4i32v : BaseSIMDAcrossLanes<1, U, 0b10, opcode, FPR64, V128,
5472 multiclass SIMDAcrossLanesS<bits<5> opcode, bit sz1, string asm,
5474 def v4i32v : BaseSIMDAcrossLanes<1, 1, {sz1, 0}, opcode, FPR32, V128,
5476 [(set FPR32:$Rd, (intOp (v4f32 V128:$Rn)))]>;
5479 //----------------------------------------------------------------------------
5480 // AdvSIMD INS/DUP instructions
5481 //----------------------------------------------------------------------------
5483 // FIXME: There has got to be a better way to factor these. ugh.
5485 class BaseSIMDInsDup<bit Q, bit op, dag outs, dag ins, string asm,
5486 string operands, string constraints, list<dag> pattern>
5487 : I<outs, ins, asm, operands, constraints, pattern>,
5494 let Inst{28-21} = 0b01110000;
5501 class SIMDDupFromMain<bit Q, bits<5> imm5, string size, ValueType vectype,
5502 RegisterOperand vecreg, RegisterClass regtype>
5503 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins regtype:$Rn), "dup",
5504 "{\t$Rd" # size # ", $Rn" #
5505 "|" # size # "\t$Rd, $Rn}", "",
5506 [(set (vectype vecreg:$Rd), (ARM64dup regtype:$Rn))]> {
5507 let Inst{20-16} = imm5;
5508 let Inst{14-11} = 0b0001;
5511 class SIMDDupFromElement<bit Q, string dstkind, string srckind,
5512 ValueType vectype, ValueType insreg,
5513 RegisterOperand vecreg, Operand idxtype,
5514 ValueType elttype, SDNode OpNode>
5515 : BaseSIMDInsDup<Q, 0, (outs vecreg:$Rd), (ins V128:$Rn, idxtype:$idx), "dup",
5516 "{\t$Rd" # dstkind # ", $Rn" # srckind # "$idx" #
5517 "|" # dstkind # "\t$Rd, $Rn$idx}", "",
5518 [(set (vectype vecreg:$Rd),
5519 (OpNode (insreg V128:$Rn), idxtype:$idx))]> {
5520 let Inst{14-11} = 0b0000;
5523 class SIMDDup64FromElement
5524 : SIMDDupFromElement<1, ".2d", ".d", v2i64, v2i64, V128,
5525 VectorIndexD, i64, ARM64duplane64> {
5528 let Inst{19-16} = 0b1000;
5531 class SIMDDup32FromElement<bit Q, string size, ValueType vectype,
5532 RegisterOperand vecreg>
5533 : SIMDDupFromElement<Q, size, ".s", vectype, v4i32, vecreg,
5534 VectorIndexS, i64, ARM64duplane32> {
5536 let Inst{20-19} = idx;
5537 let Inst{18-16} = 0b100;
5540 class SIMDDup16FromElement<bit Q, string size, ValueType vectype,
5541 RegisterOperand vecreg>
5542 : SIMDDupFromElement<Q, size, ".h", vectype, v8i16, vecreg,
5543 VectorIndexH, i64, ARM64duplane16> {
5545 let Inst{20-18} = idx;
5546 let Inst{17-16} = 0b10;
5549 class SIMDDup8FromElement<bit Q, string size, ValueType vectype,
5550 RegisterOperand vecreg>
5551 : SIMDDupFromElement<Q, size, ".b", vectype, v16i8, vecreg,
5552 VectorIndexB, i64, ARM64duplane8> {
5554 let Inst{20-17} = idx;
5558 class BaseSIMDMov<bit Q, string size, bits<4> imm4, RegisterClass regtype,
5559 Operand idxtype, string asm, list<dag> pattern>
5560 : BaseSIMDInsDup<Q, 0, (outs regtype:$Rd), (ins V128:$Rn, idxtype:$idx), asm,
5561 "{\t$Rd, $Rn" # size # "$idx" #
5562 "|" # size # "\t$Rd, $Rn$idx}", "", pattern> {
5563 let Inst{14-11} = imm4;
5566 class SIMDSMov<bit Q, string size, RegisterClass regtype,
5568 : BaseSIMDMov<Q, size, 0b0101, regtype, idxtype, "smov", []>;
5569 class SIMDUMov<bit Q, string size, ValueType vectype, RegisterClass regtype,
5571 : BaseSIMDMov<Q, size, 0b0111, regtype, idxtype, "umov",
5572 [(set regtype:$Rd, (vector_extract (vectype V128:$Rn), idxtype:$idx))]>;
5574 class SIMDMovAlias<string asm, string size, Instruction inst,
5575 RegisterClass regtype, Operand idxtype>
5576 : InstAlias<asm#"{\t$dst, $src"#size#"$idx" #
5577 "|" # size # "\t$dst, $src$idx}",
5578 (inst regtype:$dst, V128:$src, idxtype:$idx)>;
5581 def vi8to32 : SIMDSMov<0, ".b", GPR32, VectorIndexB> {
5583 let Inst{20-17} = idx;
5586 def vi8to64 : SIMDSMov<1, ".b", GPR64, VectorIndexB> {
5588 let Inst{20-17} = idx;
5591 def vi16to32 : SIMDSMov<0, ".h", GPR32, VectorIndexH> {
5593 let Inst{20-18} = idx;
5594 let Inst{17-16} = 0b10;
5596 def vi16to64 : SIMDSMov<1, ".h", GPR64, VectorIndexH> {
5598 let Inst{20-18} = idx;
5599 let Inst{17-16} = 0b10;
5601 def vi32to64 : SIMDSMov<1, ".s", GPR64, VectorIndexS> {
5603 let Inst{20-19} = idx;
5604 let Inst{18-16} = 0b100;
5609 def vi8 : SIMDUMov<0, ".b", v16i8, GPR32, VectorIndexB> {
5611 let Inst{20-17} = idx;
5614 def vi16 : SIMDUMov<0, ".h", v8i16, GPR32, VectorIndexH> {
5616 let Inst{20-18} = idx;
5617 let Inst{17-16} = 0b10;
5619 def vi32 : SIMDUMov<0, ".s", v4i32, GPR32, VectorIndexS> {
5621 let Inst{20-19} = idx;
5622 let Inst{18-16} = 0b100;
5624 def vi64 : SIMDUMov<1, ".d", v2i64, GPR64, VectorIndexD> {
5627 let Inst{19-16} = 0b1000;
5629 def : SIMDMovAlias<"mov", ".s",
5630 !cast<Instruction>(NAME#"vi32"),
5631 GPR32, VectorIndexS>;
5632 def : SIMDMovAlias<"mov", ".d",
5633 !cast<Instruction>(NAME#"vi64"),
5634 GPR64, VectorIndexD>;
5637 class SIMDInsFromMain<string size, ValueType vectype,
5638 RegisterClass regtype, Operand idxtype>
5639 : BaseSIMDInsDup<1, 0, (outs V128:$dst),
5640 (ins V128:$Rd, idxtype:$idx, regtype:$Rn), "ins",
5641 "{\t$Rd" # size # "$idx, $Rn" #
5642 "|" # size # "\t$Rd$idx, $Rn}",
5645 (vector_insert (vectype V128:$Rd), regtype:$Rn, idxtype:$idx))]> {
5646 let Inst{14-11} = 0b0011;
5649 class SIMDInsFromElement<string size, ValueType vectype,
5650 ValueType elttype, Operand idxtype>
5651 : BaseSIMDInsDup<1, 1, (outs V128:$dst),
5652 (ins V128:$Rd, idxtype:$idx, V128:$Rn, idxtype:$idx2), "ins",
5653 "{\t$Rd" # size # "$idx, $Rn" # size # "$idx2" #
5654 "|" # size # "\t$Rd$idx, $Rn$idx2}",
5659 (elttype (vector_extract (vectype V128:$Rn), idxtype:$idx2)),
5662 class SIMDInsMainMovAlias<string size, Instruction inst,
5663 RegisterClass regtype, Operand idxtype>
5664 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" #
5665 "|" # size #"\t$dst$idx, $src}",
5666 (inst V128:$dst, idxtype:$idx, regtype:$src)>;
5667 class SIMDInsElementMovAlias<string size, Instruction inst,
5669 : InstAlias<"mov" # "{\t$dst" # size # "$idx, $src" # size # "$idx2" #
5670 # "|" # size #" $dst$idx, $src$idx2}",
5671 (inst V128:$dst, idxtype:$idx, V128:$src, idxtype:$idx2)>;
5674 multiclass SIMDIns {
5675 def vi8gpr : SIMDInsFromMain<".b", v16i8, GPR32, VectorIndexB> {
5677 let Inst{20-17} = idx;
5680 def vi16gpr : SIMDInsFromMain<".h", v8i16, GPR32, VectorIndexH> {
5682 let Inst{20-18} = idx;
5683 let Inst{17-16} = 0b10;
5685 def vi32gpr : SIMDInsFromMain<".s", v4i32, GPR32, VectorIndexS> {
5687 let Inst{20-19} = idx;
5688 let Inst{18-16} = 0b100;
5690 def vi64gpr : SIMDInsFromMain<".d", v2i64, GPR64, VectorIndexD> {
5693 let Inst{19-16} = 0b1000;
5696 def vi8lane : SIMDInsFromElement<".b", v16i8, i32, VectorIndexB> {
5699 let Inst{20-17} = idx;
5701 let Inst{14-11} = idx2;
5703 def vi16lane : SIMDInsFromElement<".h", v8i16, i32, VectorIndexH> {
5706 let Inst{20-18} = idx;
5707 let Inst{17-16} = 0b10;
5708 let Inst{14-12} = idx2;
5711 def vi32lane : SIMDInsFromElement<".s", v4i32, i32, VectorIndexS> {
5714 let Inst{20-19} = idx;
5715 let Inst{18-16} = 0b100;
5716 let Inst{14-13} = idx2;
5717 let Inst{12-11} = 0;
5719 def vi64lane : SIMDInsFromElement<".d", v2i64, i64, VectorIndexD> {
5723 let Inst{19-16} = 0b1000;
5724 let Inst{14} = idx2;
5725 let Inst{13-11} = 0;
5728 // For all forms of the INS instruction, the "mov" mnemonic is the
5729 // preferred alias. Why they didn't just call the instruction "mov" in
5730 // the first place is a very good question indeed...
5731 def : SIMDInsMainMovAlias<".b", !cast<Instruction>(NAME#"vi8gpr"),
5732 GPR32, VectorIndexB>;
5733 def : SIMDInsMainMovAlias<".h", !cast<Instruction>(NAME#"vi16gpr"),
5734 GPR32, VectorIndexH>;
5735 def : SIMDInsMainMovAlias<".s", !cast<Instruction>(NAME#"vi32gpr"),
5736 GPR32, VectorIndexS>;
5737 def : SIMDInsMainMovAlias<".d", !cast<Instruction>(NAME#"vi64gpr"),
5738 GPR64, VectorIndexD>;
5740 def : SIMDInsElementMovAlias<".b", !cast<Instruction>(NAME#"vi8lane"),
5742 def : SIMDInsElementMovAlias<".h", !cast<Instruction>(NAME#"vi16lane"),
5744 def : SIMDInsElementMovAlias<".s", !cast<Instruction>(NAME#"vi32lane"),
5746 def : SIMDInsElementMovAlias<".d", !cast<Instruction>(NAME#"vi64lane"),
5750 //----------------------------------------------------------------------------
5752 //----------------------------------------------------------------------------
5754 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5755 class BaseSIMDTableLookup<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5756 RegisterOperand listtype, string asm, string kind>
5757 : I<(outs vectype:$Vd), (ins listtype:$Vn, vectype:$Vm), asm,
5758 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "", []>,
5765 let Inst{29-21} = 0b001110000;
5766 let Inst{20-16} = Vm;
5768 let Inst{14-13} = len;
5770 let Inst{11-10} = 0b00;
5775 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
5776 class BaseSIMDTableLookupTied<bit Q, bits<2> len, bit op, RegisterOperand vectype,
5777 RegisterOperand listtype, string asm, string kind>
5778 : I<(outs vectype:$dst), (ins vectype:$Vd, listtype:$Vn, vectype:$Vm), asm,
5779 "\t$Vd" # kind # ", $Vn, $Vm" # kind, "$Vd = $dst", []>,
5786 let Inst{29-21} = 0b001110000;
5787 let Inst{20-16} = Vm;
5789 let Inst{14-13} = len;
5791 let Inst{11-10} = 0b00;
5796 class SIMDTableLookupAlias<string asm, Instruction inst,
5797 RegisterOperand vectype, RegisterOperand listtype>
5798 : InstAlias<!strconcat(asm, "\t$dst, $lst, $index"),
5799 (inst vectype:$dst, listtype:$lst, vectype:$index), 0>;
5801 multiclass SIMDTableLookup<bit op, string asm> {
5802 def v8i8One : BaseSIMDTableLookup<0, 0b00, op, V64, VecListOne16b,
5804 def v8i8Two : BaseSIMDTableLookup<0, 0b01, op, V64, VecListTwo16b,
5806 def v8i8Three : BaseSIMDTableLookup<0, 0b10, op, V64, VecListThree16b,
5808 def v8i8Four : BaseSIMDTableLookup<0, 0b11, op, V64, VecListFour16b,
5810 def v16i8One : BaseSIMDTableLookup<1, 0b00, op, V128, VecListOne16b,
5812 def v16i8Two : BaseSIMDTableLookup<1, 0b01, op, V128, VecListTwo16b,
5814 def v16i8Three: BaseSIMDTableLookup<1, 0b10, op, V128, VecListThree16b,
5816 def v16i8Four : BaseSIMDTableLookup<1, 0b11, op, V128, VecListFour16b,
5819 def : SIMDTableLookupAlias<asm # ".8b",
5820 !cast<Instruction>(NAME#"v8i8One"),
5821 V64, VecListOne128>;
5822 def : SIMDTableLookupAlias<asm # ".8b",
5823 !cast<Instruction>(NAME#"v8i8Two"),
5824 V64, VecListTwo128>;
5825 def : SIMDTableLookupAlias<asm # ".8b",
5826 !cast<Instruction>(NAME#"v8i8Three"),
5827 V64, VecListThree128>;
5828 def : SIMDTableLookupAlias<asm # ".8b",
5829 !cast<Instruction>(NAME#"v8i8Four"),
5830 V64, VecListFour128>;
5831 def : SIMDTableLookupAlias<asm # ".16b",
5832 !cast<Instruction>(NAME#"v16i8One"),
5833 V128, VecListOne128>;
5834 def : SIMDTableLookupAlias<asm # ".16b",
5835 !cast<Instruction>(NAME#"v16i8Two"),
5836 V128, VecListTwo128>;
5837 def : SIMDTableLookupAlias<asm # ".16b",
5838 !cast<Instruction>(NAME#"v16i8Three"),
5839 V128, VecListThree128>;
5840 def : SIMDTableLookupAlias<asm # ".16b",
5841 !cast<Instruction>(NAME#"v16i8Four"),
5842 V128, VecListFour128>;
5845 multiclass SIMDTableLookupTied<bit op, string asm> {
5846 def v8i8One : BaseSIMDTableLookupTied<0, 0b00, op, V64, VecListOne16b,
5848 def v8i8Two : BaseSIMDTableLookupTied<0, 0b01, op, V64, VecListTwo16b,
5850 def v8i8Three : BaseSIMDTableLookupTied<0, 0b10, op, V64, VecListThree16b,
5852 def v8i8Four : BaseSIMDTableLookupTied<0, 0b11, op, V64, VecListFour16b,
5854 def v16i8One : BaseSIMDTableLookupTied<1, 0b00, op, V128, VecListOne16b,
5856 def v16i8Two : BaseSIMDTableLookupTied<1, 0b01, op, V128, VecListTwo16b,
5858 def v16i8Three: BaseSIMDTableLookupTied<1, 0b10, op, V128, VecListThree16b,
5860 def v16i8Four : BaseSIMDTableLookupTied<1, 0b11, op, V128, VecListFour16b,
5863 def : SIMDTableLookupAlias<asm # ".8b",
5864 !cast<Instruction>(NAME#"v8i8One"),
5865 V64, VecListOne128>;
5866 def : SIMDTableLookupAlias<asm # ".8b",
5867 !cast<Instruction>(NAME#"v8i8Two"),
5868 V64, VecListTwo128>;
5869 def : SIMDTableLookupAlias<asm # ".8b",
5870 !cast<Instruction>(NAME#"v8i8Three"),
5871 V64, VecListThree128>;
5872 def : SIMDTableLookupAlias<asm # ".8b",
5873 !cast<Instruction>(NAME#"v8i8Four"),
5874 V64, VecListFour128>;
5875 def : SIMDTableLookupAlias<asm # ".16b",
5876 !cast<Instruction>(NAME#"v16i8One"),
5877 V128, VecListOne128>;
5878 def : SIMDTableLookupAlias<asm # ".16b",
5879 !cast<Instruction>(NAME#"v16i8Two"),
5880 V128, VecListTwo128>;
5881 def : SIMDTableLookupAlias<asm # ".16b",
5882 !cast<Instruction>(NAME#"v16i8Three"),
5883 V128, VecListThree128>;
5884 def : SIMDTableLookupAlias<asm # ".16b",
5885 !cast<Instruction>(NAME#"v16i8Four"),
5886 V128, VecListFour128>;
5890 //----------------------------------------------------------------------------
5891 // AdvSIMD scalar CPY
5892 //----------------------------------------------------------------------------
5893 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
5894 class BaseSIMDScalarCPY<RegisterClass regtype, RegisterOperand vectype,
5895 string kind, Operand idxtype>
5896 : I<(outs regtype:$dst), (ins vectype:$src, idxtype:$idx), "mov",
5897 "{\t$dst, $src" # kind # "$idx" #
5898 "|\t$dst, $src$idx}", "", []>,
5902 let Inst{31-21} = 0b01011110000;
5903 let Inst{15-10} = 0b000001;
5904 let Inst{9-5} = src;
5905 let Inst{4-0} = dst;
5908 class SIMDScalarCPYAlias<string asm, string size, Instruction inst,
5909 RegisterClass regtype, RegisterOperand vectype, Operand idxtype>
5910 : InstAlias<asm # "{\t$dst, $src" # size # "$index" #
5911 # "|\t$dst, $src$index}",
5912 (inst regtype:$dst, vectype:$src, idxtype:$index)>;
5915 multiclass SIMDScalarCPY<string asm> {
5916 def i8 : BaseSIMDScalarCPY<FPR8, V128, ".b", VectorIndexB> {
5918 let Inst{20-17} = idx;
5921 def i16 : BaseSIMDScalarCPY<FPR16, V128, ".h", VectorIndexH> {
5923 let Inst{20-18} = idx;
5924 let Inst{17-16} = 0b10;
5926 def i32 : BaseSIMDScalarCPY<FPR32, V128, ".s", VectorIndexS> {
5928 let Inst{20-19} = idx;
5929 let Inst{18-16} = 0b100;
5931 def i64 : BaseSIMDScalarCPY<FPR64, V128, ".d", VectorIndexD> {
5934 let Inst{19-16} = 0b1000;
5937 def : Pat<(v1i64 (scalar_to_vector (i64 (vector_extract (v2i64 V128:$src),
5938 VectorIndexD:$idx)))),
5939 (!cast<Instruction>(NAME # i64) V128:$src, VectorIndexD:$idx)>;
5941 // 'DUP' mnemonic aliases.
5942 def : SIMDScalarCPYAlias<"dup", ".b",
5943 !cast<Instruction>(NAME#"i8"),
5944 FPR8, V128, VectorIndexB>;
5945 def : SIMDScalarCPYAlias<"dup", ".h",
5946 !cast<Instruction>(NAME#"i16"),
5947 FPR16, V128, VectorIndexH>;
5948 def : SIMDScalarCPYAlias<"dup", ".s",
5949 !cast<Instruction>(NAME#"i32"),
5950 FPR32, V128, VectorIndexS>;
5951 def : SIMDScalarCPYAlias<"dup", ".d",
5952 !cast<Instruction>(NAME#"i64"),
5953 FPR64, V128, VectorIndexD>;
5956 //----------------------------------------------------------------------------
5957 // AdvSIMD modified immediate instructions
5958 //----------------------------------------------------------------------------
5960 class BaseSIMDModifiedImm<bit Q, bit op, dag oops, dag iops,
5961 string asm, string op_string,
5962 string cstr, list<dag> pattern>
5963 : I<oops, iops, asm, op_string, cstr, pattern>,
5970 let Inst{28-19} = 0b0111100000;
5971 let Inst{18-16} = imm8{7-5};
5972 let Inst{11-10} = 0b01;
5973 let Inst{9-5} = imm8{4-0};
5977 class BaseSIMDModifiedImmVector<bit Q, bit op, RegisterOperand vectype,
5978 Operand immtype, dag opt_shift_iop,
5979 string opt_shift, string asm, string kind,
5981 : BaseSIMDModifiedImm<Q, op, (outs vectype:$Rd),
5982 !con((ins immtype:$imm8), opt_shift_iop), asm,
5983 "{\t$Rd" # kind # ", $imm8" # opt_shift #
5984 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
5986 let DecoderMethod = "DecodeModImmInstruction";
5989 class BaseSIMDModifiedImmVectorTied<bit Q, bit op, RegisterOperand vectype,
5990 Operand immtype, dag opt_shift_iop,
5991 string opt_shift, string asm, string kind,
5993 : BaseSIMDModifiedImm<Q, op, (outs vectype:$dst),
5994 !con((ins vectype:$Rd, immtype:$imm8), opt_shift_iop),
5995 asm, "{\t$Rd" # kind # ", $imm8" # opt_shift #
5996 "|" # kind # "\t$Rd, $imm8" # opt_shift # "}",
5997 "$Rd = $dst", pattern> {
5998 let DecoderMethod = "DecodeModImmTiedInstruction";
6001 class BaseSIMDModifiedImmVectorShift<bit Q, bit op, bits<2> b15_b12,
6002 RegisterOperand vectype, string asm,
6003 string kind, list<dag> pattern>
6004 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6005 (ins logical_vec_shift:$shift),
6006 "$shift", asm, kind, pattern> {
6008 let Inst{15} = b15_b12{1};
6009 let Inst{14-13} = shift;
6010 let Inst{12} = b15_b12{0};
6013 class BaseSIMDModifiedImmVectorShiftTied<bit Q, bit op, bits<2> b15_b12,
6014 RegisterOperand vectype, string asm,
6015 string kind, list<dag> pattern>
6016 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6017 (ins logical_vec_shift:$shift),
6018 "$shift", asm, kind, pattern> {
6020 let Inst{15} = b15_b12{1};
6021 let Inst{14-13} = shift;
6022 let Inst{12} = b15_b12{0};
6026 class BaseSIMDModifiedImmVectorShiftHalf<bit Q, bit op, bits<2> b15_b12,
6027 RegisterOperand vectype, string asm,
6028 string kind, list<dag> pattern>
6029 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6030 (ins logical_vec_hw_shift:$shift),
6031 "$shift", asm, kind, pattern> {
6033 let Inst{15} = b15_b12{1};
6035 let Inst{13} = shift{0};
6036 let Inst{12} = b15_b12{0};
6039 class BaseSIMDModifiedImmVectorShiftHalfTied<bit Q, bit op, bits<2> b15_b12,
6040 RegisterOperand vectype, string asm,
6041 string kind, list<dag> pattern>
6042 : BaseSIMDModifiedImmVectorTied<Q, op, vectype, imm0_255,
6043 (ins logical_vec_hw_shift:$shift),
6044 "$shift", asm, kind, pattern> {
6046 let Inst{15} = b15_b12{1};
6048 let Inst{13} = shift{0};
6049 let Inst{12} = b15_b12{0};
6052 multiclass SIMDModifiedImmVectorShift<bit op, bits<2> hw_cmode, bits<2> w_cmode,
6054 def v4i16 : BaseSIMDModifiedImmVectorShiftHalf<0, op, hw_cmode, V64,
6056 def v8i16 : BaseSIMDModifiedImmVectorShiftHalf<1, op, hw_cmode, V128,
6059 def v2i32 : BaseSIMDModifiedImmVectorShift<0, op, w_cmode, V64,
6061 def v4i32 : BaseSIMDModifiedImmVectorShift<1, op, w_cmode, V128,
6065 multiclass SIMDModifiedImmVectorShiftTied<bit op, bits<2> hw_cmode,
6066 bits<2> w_cmode, string asm,
6068 def v4i16 : BaseSIMDModifiedImmVectorShiftHalfTied<0, op, hw_cmode, V64,
6070 [(set (v4i16 V64:$dst), (OpNode V64:$Rd,
6072 (i32 imm:$shift)))]>;
6073 def v8i16 : BaseSIMDModifiedImmVectorShiftHalfTied<1, op, hw_cmode, V128,
6075 [(set (v8i16 V128:$dst), (OpNode V128:$Rd,
6077 (i32 imm:$shift)))]>;
6079 def v2i32 : BaseSIMDModifiedImmVectorShiftTied<0, op, w_cmode, V64,
6081 [(set (v2i32 V64:$dst), (OpNode V64:$Rd,
6083 (i32 imm:$shift)))]>;
6084 def v4i32 : BaseSIMDModifiedImmVectorShiftTied<1, op, w_cmode, V128,
6086 [(set (v4i32 V128:$dst), (OpNode V128:$Rd,
6088 (i32 imm:$shift)))]>;
6091 class SIMDModifiedImmMoveMSL<bit Q, bit op, bits<4> cmode,
6092 RegisterOperand vectype, string asm,
6093 string kind, list<dag> pattern>
6094 : BaseSIMDModifiedImmVector<Q, op, vectype, imm0_255,
6095 (ins move_vec_shift:$shift),
6096 "$shift", asm, kind, pattern> {
6098 let Inst{15-13} = cmode{3-1};
6099 let Inst{12} = shift;
6102 class SIMDModifiedImmVectorNoShift<bit Q, bit op, bits<4> cmode,
6103 RegisterOperand vectype,
6104 Operand imm_type, string asm,
6105 string kind, list<dag> pattern>
6106 : BaseSIMDModifiedImmVector<Q, op, vectype, imm_type, (ins), "",
6107 asm, kind, pattern> {
6108 let Inst{15-12} = cmode;
6111 class SIMDModifiedImmScalarNoShift<bit Q, bit op, bits<4> cmode, string asm,
6113 : BaseSIMDModifiedImm<Q, op, (outs FPR64:$Rd), (ins simdimmtype10:$imm8), asm,
6114 "\t$Rd, $imm8", "", pattern> {
6115 let Inst{15-12} = cmode;
6116 let DecoderMethod = "DecodeModImmInstruction";
6119 //----------------------------------------------------------------------------
6120 // AdvSIMD indexed element
6121 //----------------------------------------------------------------------------
6123 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6124 class BaseSIMDIndexed<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6125 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6126 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6127 string apple_kind, string dst_kind, string lhs_kind,
6128 string rhs_kind, list<dag> pattern>
6129 : I<(outs dst_reg:$Rd), (ins lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx),
6131 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6132 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "", pattern>,
6141 let Inst{28} = Scalar;
6142 let Inst{27-24} = 0b1111;
6143 let Inst{23-22} = size;
6144 // Bit 21 must be set by the derived class.
6145 let Inst{20-16} = Rm;
6146 let Inst{15-12} = opc;
6147 // Bit 11 must be set by the derived class.
6153 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
6154 class BaseSIMDIndexedTied<bit Q, bit U, bit Scalar, bits<2> size, bits<4> opc,
6155 RegisterOperand dst_reg, RegisterOperand lhs_reg,
6156 RegisterOperand rhs_reg, Operand vec_idx, string asm,
6157 string apple_kind, string dst_kind, string lhs_kind,
6158 string rhs_kind, list<dag> pattern>
6159 : I<(outs dst_reg:$dst),
6160 (ins dst_reg:$Rd, lhs_reg:$Rn, rhs_reg:$Rm, vec_idx:$idx), asm,
6161 "{\t$Rd" # dst_kind # ", $Rn" # lhs_kind # ", $Rm" # rhs_kind # "$idx" #
6162 "|" # apple_kind # "\t$Rd, $Rn, $Rm$idx}", "$Rd = $dst", pattern>,
6171 let Inst{28} = Scalar;
6172 let Inst{27-24} = 0b1111;
6173 let Inst{23-22} = size;
6174 // Bit 21 must be set by the derived class.
6175 let Inst{20-16} = Rm;
6176 let Inst{15-12} = opc;
6177 // Bit 11 must be set by the derived class.
6183 multiclass SIMDFPIndexedSD<bit U, bits<4> opc, string asm,
6184 SDPatternOperator OpNode> {
6185 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6188 asm, ".2s", ".2s", ".2s", ".s",
6189 [(set (v2f32 V64:$Rd),
6190 (OpNode (v2f32 V64:$Rn),
6191 (v2f32 (ARM64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6193 let Inst{11} = idx{1};
6194 let Inst{21} = idx{0};
6197 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6200 asm, ".4s", ".4s", ".4s", ".s",
6201 [(set (v4f32 V128:$Rd),
6202 (OpNode (v4f32 V128:$Rn),
6203 (v4f32 (ARM64duplane32 (v4f32 V128:$Rm), VectorIndexS:$idx))))]> {
6205 let Inst{11} = idx{1};
6206 let Inst{21} = idx{0};
6209 def v2i64_indexed : BaseSIMDIndexed<1, U, 0, 0b11, opc,
6212 asm, ".2d", ".2d", ".2d", ".d",
6213 [(set (v2f64 V128:$Rd),
6214 (OpNode (v2f64 V128:$Rn),
6215 (v2f64 (ARM64duplane64 (v2f64 V128:$Rm), VectorIndexD:$idx))))]> {
6217 let Inst{11} = idx{0};
6221 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6222 FPR32Op, FPR32Op, V128, VectorIndexS,
6223 asm, ".s", "", "", ".s",
6224 [(set (f32 FPR32Op:$Rd),
6225 (OpNode (f32 FPR32Op:$Rn),
6226 (f32 (vector_extract (v4f32 V128:$Rm),
6227 VectorIndexS:$idx))))]> {
6229 let Inst{11} = idx{1};
6230 let Inst{21} = idx{0};
6233 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b11, opc,
6234 FPR64Op, FPR64Op, V128, VectorIndexD,
6235 asm, ".d", "", "", ".d",
6236 [(set (f64 FPR64Op:$Rd),
6237 (OpNode (f64 FPR64Op:$Rn),
6238 (f64 (vector_extract (v2f64 V128:$Rm),
6239 VectorIndexD:$idx))))]> {
6241 let Inst{11} = idx{0};
6246 multiclass SIMDFPIndexedSDTiedPatterns<string INST, SDPatternOperator OpNode> {
6247 // 2 variants for the .2s version: DUPLANE from 128-bit and DUP scalar.
6248 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6249 (ARM64duplane32 (v4f32 V128:$Rm),
6250 VectorIndexS:$idx))),
6251 (!cast<Instruction>(INST # v2i32_indexed)
6252 V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6253 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
6254 (ARM64dup (f32 FPR32Op:$Rm)))),
6255 (!cast<Instruction>(INST # "v2i32_indexed") V64:$Rd, V64:$Rn,
6256 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6259 // 2 variants for the .4s version: DUPLANE from 128-bit and DUP scalar.
6260 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6261 (ARM64duplane32 (v4f32 V128:$Rm),
6262 VectorIndexS:$idx))),
6263 (!cast<Instruction>(INST # "v4i32_indexed")
6264 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6265 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
6266 (ARM64dup (f32 FPR32Op:$Rm)))),
6267 (!cast<Instruction>(INST # "v4i32_indexed") V128:$Rd, V128:$Rn,
6268 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
6270 // 2 variants for the .2d version: DUPLANE from 128-bit and DUP scalar.
6271 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6272 (ARM64duplane64 (v2f64 V128:$Rm),
6273 VectorIndexD:$idx))),
6274 (!cast<Instruction>(INST # "v2i64_indexed")
6275 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
6276 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
6277 (ARM64dup (f64 FPR64Op:$Rm)))),
6278 (!cast<Instruction>(INST # "v2i64_indexed") V128:$Rd, V128:$Rn,
6279 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
6281 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
6282 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6283 (vector_extract (v4f32 V128:$Rm), VectorIndexS:$idx))),
6284 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6285 V128:$Rm, VectorIndexS:$idx)>;
6286 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
6287 (vector_extract (v2f32 V64:$Rm), VectorIndexS:$idx))),
6288 (!cast<Instruction>(INST # "v1i32_indexed") FPR32:$Rd, FPR32:$Rn,
6289 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
6291 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
6292 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
6293 (vector_extract (v2f64 V128:$Rm), VectorIndexD:$idx))),
6294 (!cast<Instruction>(INST # "v1i64_indexed") FPR64:$Rd, FPR64:$Rn,
6295 V128:$Rm, VectorIndexD:$idx)>;
6298 multiclass SIMDFPIndexedSDTied<bit U, bits<4> opc, string asm> {
6299 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc, V64, V64,
6301 asm, ".2s", ".2s", ".2s", ".s", []> {
6303 let Inst{11} = idx{1};
6304 let Inst{21} = idx{0};
6307 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6310 asm, ".4s", ".4s", ".4s", ".s", []> {
6312 let Inst{11} = idx{1};
6313 let Inst{21} = idx{0};
6316 def v2i64_indexed : BaseSIMDIndexedTied<1, U, 0, 0b11, opc,
6319 asm, ".2d", ".2d", ".2d", ".d", []> {
6321 let Inst{11} = idx{0};
6326 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6327 FPR32Op, FPR32Op, V128, VectorIndexS,
6328 asm, ".s", "", "", ".s", []> {
6330 let Inst{11} = idx{1};
6331 let Inst{21} = idx{0};
6334 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b11, opc,
6335 FPR64Op, FPR64Op, V128, VectorIndexD,
6336 asm, ".d", "", "", ".d", []> {
6338 let Inst{11} = idx{0};
6343 multiclass SIMDIndexedHS<bit U, bits<4> opc, string asm,
6344 SDPatternOperator OpNode> {
6345 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc, V64, V64,
6346 V128_lo, VectorIndexH,
6347 asm, ".4h", ".4h", ".4h", ".h",
6348 [(set (v4i16 V64:$Rd),
6349 (OpNode (v4i16 V64:$Rn),
6350 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6352 let Inst{11} = idx{2};
6353 let Inst{21} = idx{1};
6354 let Inst{20} = idx{0};
6357 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6359 V128_lo, VectorIndexH,
6360 asm, ".8h", ".8h", ".8h", ".h",
6361 [(set (v8i16 V128:$Rd),
6362 (OpNode (v8i16 V128:$Rn),
6363 (v8i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6365 let Inst{11} = idx{2};
6366 let Inst{21} = idx{1};
6367 let Inst{20} = idx{0};
6370 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6373 asm, ".2s", ".2s", ".2s", ".s",
6374 [(set (v2i32 V64:$Rd),
6375 (OpNode (v2i32 V64:$Rn),
6376 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6378 let Inst{11} = idx{1};
6379 let Inst{21} = idx{0};
6382 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6385 asm, ".4s", ".4s", ".4s", ".s",
6386 [(set (v4i32 V128:$Rd),
6387 (OpNode (v4i32 V128:$Rn),
6388 (v4i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6390 let Inst{11} = idx{1};
6391 let Inst{21} = idx{0};
6394 def v1i16_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6395 FPR16Op, FPR16Op, V128_lo, VectorIndexH,
6396 asm, ".h", "", "", ".h", []> {
6398 let Inst{11} = idx{2};
6399 let Inst{21} = idx{1};
6400 let Inst{20} = idx{0};
6403 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6404 FPR32Op, FPR32Op, V128, VectorIndexS,
6405 asm, ".s", "", "", ".s",
6406 [(set (i32 FPR32Op:$Rd),
6407 (OpNode FPR32Op:$Rn,
6408 (i32 (vector_extract (v4i32 V128:$Rm),
6409 VectorIndexS:$idx))))]> {
6411 let Inst{11} = idx{1};
6412 let Inst{21} = idx{0};
6416 multiclass SIMDVectorIndexedHS<bit U, bits<4> opc, string asm,
6417 SDPatternOperator OpNode> {
6418 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6420 V128_lo, VectorIndexH,
6421 asm, ".4h", ".4h", ".4h", ".h",
6422 [(set (v4i16 V64:$Rd),
6423 (OpNode (v4i16 V64:$Rn),
6424 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6426 let Inst{11} = idx{2};
6427 let Inst{21} = idx{1};
6428 let Inst{20} = idx{0};
6431 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6433 V128_lo, VectorIndexH,
6434 asm, ".8h", ".8h", ".8h", ".h",
6435 [(set (v8i16 V128:$Rd),
6436 (OpNode (v8i16 V128:$Rn),
6437 (v8i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6439 let Inst{11} = idx{2};
6440 let Inst{21} = idx{1};
6441 let Inst{20} = idx{0};
6444 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6447 asm, ".2s", ".2s", ".2s", ".s",
6448 [(set (v2i32 V64:$Rd),
6449 (OpNode (v2i32 V64:$Rn),
6450 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6452 let Inst{11} = idx{1};
6453 let Inst{21} = idx{0};
6456 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6459 asm, ".4s", ".4s", ".4s", ".s",
6460 [(set (v4i32 V128:$Rd),
6461 (OpNode (v4i32 V128:$Rn),
6462 (v4i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6464 let Inst{11} = idx{1};
6465 let Inst{21} = idx{0};
6469 multiclass SIMDVectorIndexedHSTied<bit U, bits<4> opc, string asm,
6470 SDPatternOperator OpNode> {
6471 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc, V64, V64,
6472 V128_lo, VectorIndexH,
6473 asm, ".4h", ".4h", ".4h", ".h",
6474 [(set (v4i16 V64:$dst),
6475 (OpNode (v4i16 V64:$Rd),(v4i16 V64:$Rn),
6476 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6478 let Inst{11} = idx{2};
6479 let Inst{21} = idx{1};
6480 let Inst{20} = idx{0};
6483 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6485 V128_lo, VectorIndexH,
6486 asm, ".8h", ".8h", ".8h", ".h",
6487 [(set (v8i16 V128:$dst),
6488 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
6489 (v8i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6491 let Inst{11} = idx{2};
6492 let Inst{21} = idx{1};
6493 let Inst{20} = idx{0};
6496 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6499 asm, ".2s", ".2s", ".2s", ".s",
6500 [(set (v2i32 V64:$dst),
6501 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
6502 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6504 let Inst{11} = idx{1};
6505 let Inst{21} = idx{0};
6508 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6511 asm, ".4s", ".4s", ".4s", ".s",
6512 [(set (v4i32 V128:$dst),
6513 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
6514 (v4i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6516 let Inst{11} = idx{1};
6517 let Inst{21} = idx{0};
6521 multiclass SIMDIndexedLongSD<bit U, bits<4> opc, string asm,
6522 SDPatternOperator OpNode> {
6523 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6525 V128_lo, VectorIndexH,
6526 asm, ".4s", ".4s", ".4h", ".h",
6527 [(set (v4i32 V128:$Rd),
6528 (OpNode (v4i16 V64:$Rn),
6529 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6531 let Inst{11} = idx{2};
6532 let Inst{21} = idx{1};
6533 let Inst{20} = idx{0};
6536 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6538 V128_lo, VectorIndexH,
6539 asm#"2", ".4s", ".4s", ".8h", ".h",
6540 [(set (v4i32 V128:$Rd),
6541 (OpNode (extract_high_v8i16 V128:$Rn),
6542 (extract_high_v8i16 (ARM64duplane16 (v8i16 V128_lo:$Rm),
6543 VectorIndexH:$idx))))]> {
6546 let Inst{11} = idx{2};
6547 let Inst{21} = idx{1};
6548 let Inst{20} = idx{0};
6551 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6554 asm, ".2d", ".2d", ".2s", ".s",
6555 [(set (v2i64 V128:$Rd),
6556 (OpNode (v2i32 V64:$Rn),
6557 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6559 let Inst{11} = idx{1};
6560 let Inst{21} = idx{0};
6563 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6566 asm#"2", ".2d", ".2d", ".4s", ".s",
6567 [(set (v2i64 V128:$Rd),
6568 (OpNode (extract_high_v4i32 V128:$Rn),
6569 (extract_high_v4i32 (ARM64duplane32 (v4i32 V128:$Rm),
6570 VectorIndexS:$idx))))]> {
6572 let Inst{11} = idx{1};
6573 let Inst{21} = idx{0};
6576 def v1i32_indexed : BaseSIMDIndexed<1, U, 1, 0b01, opc,
6577 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6578 asm, ".h", "", "", ".h", []> {
6580 let Inst{11} = idx{2};
6581 let Inst{21} = idx{1};
6582 let Inst{20} = idx{0};
6585 def v1i64_indexed : BaseSIMDIndexed<1, U, 1, 0b10, opc,
6586 FPR64Op, FPR32Op, V128, VectorIndexS,
6587 asm, ".s", "", "", ".s", []> {
6589 let Inst{11} = idx{1};
6590 let Inst{21} = idx{0};
6594 multiclass SIMDIndexedLongSQDMLXSDTied<bit U, bits<4> opc, string asm,
6595 SDPatternOperator Accum> {
6596 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6598 V128_lo, VectorIndexH,
6599 asm, ".4s", ".4s", ".4h", ".h",
6600 [(set (v4i32 V128:$dst),
6601 (Accum (v4i32 V128:$Rd),
6602 (v4i32 (int_arm64_neon_sqdmull
6604 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm),
6605 VectorIndexH:$idx))))))]> {
6607 let Inst{11} = idx{2};
6608 let Inst{21} = idx{1};
6609 let Inst{20} = idx{0};
6612 // FIXME: it would be nice to use the scalar (v1i32) instruction here, but an
6613 // intermediate EXTRACT_SUBREG would be untyped.
6614 def : Pat<(i32 (Accum (i32 FPR32Op:$Rd),
6615 (i32 (vector_extract (v4i32
6616 (int_arm64_neon_sqdmull (v4i16 V64:$Rn),
6617 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm),
6618 VectorIndexH:$idx)))),
6621 (!cast<Instruction>(NAME # v4i16_indexed)
6622 (SUBREG_TO_REG (i32 0), FPR32Op:$Rd, ssub), V64:$Rn,
6623 V128_lo:$Rm, VectorIndexH:$idx),
6626 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6628 V128_lo, VectorIndexH,
6629 asm#"2", ".4s", ".4s", ".8h", ".h",
6630 [(set (v4i32 V128:$dst),
6631 (Accum (v4i32 V128:$Rd),
6632 (v4i32 (int_arm64_neon_sqdmull
6633 (extract_high_v8i16 V128:$Rn),
6635 (ARM64duplane16 (v8i16 V128_lo:$Rm),
6636 VectorIndexH:$idx))))))]> {
6638 let Inst{11} = idx{2};
6639 let Inst{21} = idx{1};
6640 let Inst{20} = idx{0};
6643 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6646 asm, ".2d", ".2d", ".2s", ".s",
6647 [(set (v2i64 V128:$dst),
6648 (Accum (v2i64 V128:$Rd),
6649 (v2i64 (int_arm64_neon_sqdmull
6651 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm),
6652 VectorIndexS:$idx))))))]> {
6654 let Inst{11} = idx{1};
6655 let Inst{21} = idx{0};
6658 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6661 asm#"2", ".2d", ".2d", ".4s", ".s",
6662 [(set (v2i64 V128:$dst),
6663 (Accum (v2i64 V128:$Rd),
6664 (v2i64 (int_arm64_neon_sqdmull
6665 (extract_high_v4i32 V128:$Rn),
6667 (ARM64duplane32 (v4i32 V128:$Rm),
6668 VectorIndexS:$idx))))))]> {
6670 let Inst{11} = idx{1};
6671 let Inst{21} = idx{0};
6674 def v1i32_indexed : BaseSIMDIndexedTied<1, U, 1, 0b01, opc,
6675 FPR32Op, FPR16Op, V128_lo, VectorIndexH,
6676 asm, ".h", "", "", ".h", []> {
6678 let Inst{11} = idx{2};
6679 let Inst{21} = idx{1};
6680 let Inst{20} = idx{0};
6684 def v1i64_indexed : BaseSIMDIndexedTied<1, U, 1, 0b10, opc,
6685 FPR64Op, FPR32Op, V128, VectorIndexS,
6686 asm, ".s", "", "", ".s",
6687 [(set (i64 FPR64Op:$dst),
6688 (Accum (i64 FPR64Op:$Rd),
6689 (i64 (int_arm64_neon_sqdmulls_scalar
6691 (i32 (vector_extract (v4i32 V128:$Rm),
6692 VectorIndexS:$idx))))))]> {
6695 let Inst{11} = idx{1};
6696 let Inst{21} = idx{0};
6700 multiclass SIMDVectorIndexedLongSD<bit U, bits<4> opc, string asm,
6701 SDPatternOperator OpNode> {
6702 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6703 def v4i16_indexed : BaseSIMDIndexed<0, U, 0, 0b01, opc,
6705 V128_lo, VectorIndexH,
6706 asm, ".4s", ".4s", ".4h", ".h",
6707 [(set (v4i32 V128:$Rd),
6708 (OpNode (v4i16 V64:$Rn),
6709 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6711 let Inst{11} = idx{2};
6712 let Inst{21} = idx{1};
6713 let Inst{20} = idx{0};
6716 def v8i16_indexed : BaseSIMDIndexed<1, U, 0, 0b01, opc,
6718 V128_lo, VectorIndexH,
6719 asm#"2", ".4s", ".4s", ".8h", ".h",
6720 [(set (v4i32 V128:$Rd),
6721 (OpNode (extract_high_v8i16 V128:$Rn),
6722 (extract_high_v8i16 (ARM64duplane16 (v8i16 V128_lo:$Rm),
6723 VectorIndexH:$idx))))]> {
6726 let Inst{11} = idx{2};
6727 let Inst{21} = idx{1};
6728 let Inst{20} = idx{0};
6731 def v2i32_indexed : BaseSIMDIndexed<0, U, 0, 0b10, opc,
6734 asm, ".2d", ".2d", ".2s", ".s",
6735 [(set (v2i64 V128:$Rd),
6736 (OpNode (v2i32 V64:$Rn),
6737 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6739 let Inst{11} = idx{1};
6740 let Inst{21} = idx{0};
6743 def v4i32_indexed : BaseSIMDIndexed<1, U, 0, 0b10, opc,
6746 asm#"2", ".2d", ".2d", ".4s", ".s",
6747 [(set (v2i64 V128:$Rd),
6748 (OpNode (extract_high_v4i32 V128:$Rn),
6749 (extract_high_v4i32 (ARM64duplane32 (v4i32 V128:$Rm),
6750 VectorIndexS:$idx))))]> {
6752 let Inst{11} = idx{1};
6753 let Inst{21} = idx{0};
6758 multiclass SIMDVectorIndexedLongSDTied<bit U, bits<4> opc, string asm,
6759 SDPatternOperator OpNode> {
6760 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
6761 def v4i16_indexed : BaseSIMDIndexedTied<0, U, 0, 0b01, opc,
6763 V128_lo, VectorIndexH,
6764 asm, ".4s", ".4s", ".4h", ".h",
6765 [(set (v4i32 V128:$dst),
6766 (OpNode (v4i32 V128:$Rd), (v4i16 V64:$Rn),
6767 (v4i16 (ARM64duplane16 (v8i16 V128_lo:$Rm), VectorIndexH:$idx))))]> {
6769 let Inst{11} = idx{2};
6770 let Inst{21} = idx{1};
6771 let Inst{20} = idx{0};
6774 def v8i16_indexed : BaseSIMDIndexedTied<1, U, 0, 0b01, opc,
6776 V128_lo, VectorIndexH,
6777 asm#"2", ".4s", ".4s", ".8h", ".h",
6778 [(set (v4i32 V128:$dst),
6779 (OpNode (v4i32 V128:$Rd),
6780 (extract_high_v8i16 V128:$Rn),
6781 (extract_high_v8i16 (ARM64duplane16 (v8i16 V128_lo:$Rm),
6782 VectorIndexH:$idx))))]> {
6784 let Inst{11} = idx{2};
6785 let Inst{21} = idx{1};
6786 let Inst{20} = idx{0};
6789 def v2i32_indexed : BaseSIMDIndexedTied<0, U, 0, 0b10, opc,
6792 asm, ".2d", ".2d", ".2s", ".s",
6793 [(set (v2i64 V128:$dst),
6794 (OpNode (v2i64 V128:$Rd), (v2i32 V64:$Rn),
6795 (v2i32 (ARM64duplane32 (v4i32 V128:$Rm), VectorIndexS:$idx))))]> {
6797 let Inst{11} = idx{1};
6798 let Inst{21} = idx{0};
6801 def v4i32_indexed : BaseSIMDIndexedTied<1, U, 0, 0b10, opc,
6804 asm#"2", ".2d", ".2d", ".4s", ".s",
6805 [(set (v2i64 V128:$dst),
6806 (OpNode (v2i64 V128:$Rd),
6807 (extract_high_v4i32 V128:$Rn),
6808 (extract_high_v4i32 (ARM64duplane32 (v4i32 V128:$Rm),
6809 VectorIndexS:$idx))))]> {
6811 let Inst{11} = idx{1};
6812 let Inst{21} = idx{0};
6817 //----------------------------------------------------------------------------
6818 // AdvSIMD scalar shift by immediate
6819 //----------------------------------------------------------------------------
6821 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6822 class BaseSIMDScalarShift<bit U, bits<5> opc, bits<7> fixed_imm,
6823 RegisterClass regtype1, RegisterClass regtype2,
6824 Operand immtype, string asm, list<dag> pattern>
6825 : I<(outs regtype1:$Rd), (ins regtype2:$Rn, immtype:$imm),
6826 asm, "\t$Rd, $Rn, $imm", "", pattern>,
6831 let Inst{31-30} = 0b01;
6833 let Inst{28-23} = 0b111110;
6834 let Inst{22-16} = fixed_imm;
6835 let Inst{15-11} = opc;
6841 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6842 class BaseSIMDScalarShiftTied<bit U, bits<5> opc, bits<7> fixed_imm,
6843 RegisterClass regtype1, RegisterClass regtype2,
6844 Operand immtype, string asm, list<dag> pattern>
6845 : I<(outs regtype1:$dst), (ins regtype1:$Rd, regtype2:$Rn, immtype:$imm),
6846 asm, "\t$Rd, $Rn, $imm", "$Rd = $dst", pattern>,
6851 let Inst{31-30} = 0b01;
6853 let Inst{28-23} = 0b111110;
6854 let Inst{22-16} = fixed_imm;
6855 let Inst{15-11} = opc;
6862 multiclass SIMDScalarRShiftSD<bit U, bits<5> opc, string asm> {
6863 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
6864 FPR32, FPR32, vecshiftR32, asm, []> {
6865 let Inst{20-16} = imm{4-0};
6868 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
6869 FPR64, FPR64, vecshiftR64, asm, []> {
6870 let Inst{21-16} = imm{5-0};
6874 multiclass SIMDScalarRShiftD<bit U, bits<5> opc, string asm,
6875 SDPatternOperator OpNode> {
6876 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
6877 FPR64, FPR64, vecshiftR64, asm,
6878 [(set (i64 FPR64:$Rd),
6879 (OpNode (i64 FPR64:$Rn), (i32 vecshiftR64:$imm)))]> {
6880 let Inst{21-16} = imm{5-0};
6883 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftR64:$imm))),
6884 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftR64:$imm)>;
6887 multiclass SIMDScalarRShiftDTied<bit U, bits<5> opc, string asm,
6888 SDPatternOperator OpNode = null_frag> {
6889 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
6890 FPR64, FPR64, vecshiftR64, asm,
6891 [(set (i64 FPR64:$dst), (OpNode (i64 FPR64:$Rd), (i64 FPR64:$Rn),
6892 (i32 vecshiftR64:$imm)))]> {
6893 let Inst{21-16} = imm{5-0};
6896 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
6897 (i32 vecshiftR64:$imm))),
6898 (!cast<Instruction>(NAME # "d") FPR64:$Rd, FPR64:$Rn,
6902 multiclass SIMDScalarLShiftD<bit U, bits<5> opc, string asm,
6903 SDPatternOperator OpNode> {
6904 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
6905 FPR64, FPR64, vecshiftL64, asm,
6906 [(set (v1i64 FPR64:$Rd),
6907 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
6908 let Inst{21-16} = imm{5-0};
6912 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6913 multiclass SIMDScalarLShiftDTied<bit U, bits<5> opc, string asm> {
6914 def d : BaseSIMDScalarShiftTied<U, opc, {1,?,?,?,?,?,?},
6915 FPR64, FPR64, vecshiftL64, asm, []> {
6916 let Inst{21-16} = imm{5-0};
6920 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6921 multiclass SIMDScalarRShiftBHS<bit U, bits<5> opc, string asm,
6922 SDPatternOperator OpNode = null_frag> {
6923 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
6924 FPR8, FPR16, vecshiftR8, asm, []> {
6925 let Inst{18-16} = imm{2-0};
6928 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
6929 FPR16, FPR32, vecshiftR16, asm, []> {
6930 let Inst{19-16} = imm{3-0};
6933 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
6934 FPR32, FPR64, vecshiftR32, asm,
6935 [(set (i32 FPR32:$Rd), (OpNode (i64 FPR64:$Rn), vecshiftR32:$imm))]> {
6936 let Inst{20-16} = imm{4-0};
6940 multiclass SIMDScalarLShiftBHSD<bit U, bits<5> opc, string asm,
6941 SDPatternOperator OpNode> {
6942 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
6943 FPR8, FPR8, vecshiftL8, asm, []> {
6944 let Inst{18-16} = imm{2-0};
6947 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
6948 FPR16, FPR16, vecshiftL16, asm, []> {
6949 let Inst{19-16} = imm{3-0};
6952 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
6953 FPR32, FPR32, vecshiftL32, asm,
6954 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn), (i32 vecshiftL32:$imm)))]> {
6955 let Inst{20-16} = imm{4-0};
6958 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
6959 FPR64, FPR64, vecshiftL64, asm,
6960 [(set (i64 FPR64:$Rd), (OpNode (i64 FPR64:$Rn), (i32 vecshiftL64:$imm)))]> {
6961 let Inst{21-16} = imm{5-0};
6964 def : Pat<(v1i64 (OpNode (v1i64 FPR64:$Rn), (i32 vecshiftL64:$imm))),
6965 (!cast<Instruction>(NAME # "d") FPR64:$Rn, vecshiftL64:$imm)>;
6968 multiclass SIMDScalarRShiftBHSD<bit U, bits<5> opc, string asm> {
6969 def b : BaseSIMDScalarShift<U, opc, {0,0,0,1,?,?,?},
6970 FPR8, FPR8, vecshiftR8, asm, []> {
6971 let Inst{18-16} = imm{2-0};
6974 def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},
6975 FPR16, FPR16, vecshiftR16, asm, []> {
6976 let Inst{19-16} = imm{3-0};
6979 def s : BaseSIMDScalarShift<U, opc, {0,1,?,?,?,?,?},
6980 FPR32, FPR32, vecshiftR32, asm, []> {
6981 let Inst{20-16} = imm{4-0};
6984 def d : BaseSIMDScalarShift<U, opc, {1,?,?,?,?,?,?},
6985 FPR64, FPR64, vecshiftR64, asm, []> {
6986 let Inst{21-16} = imm{5-0};
6990 //----------------------------------------------------------------------------
6991 // AdvSIMD vector x indexed element
6992 //----------------------------------------------------------------------------
6994 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
6995 class BaseSIMDVectorShift<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
6996 RegisterOperand dst_reg, RegisterOperand src_reg,
6998 string asm, string dst_kind, string src_kind,
7000 : I<(outs dst_reg:$Rd), (ins src_reg:$Rn, immtype:$imm),
7001 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7002 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "", pattern>,
7009 let Inst{28-23} = 0b011110;
7010 let Inst{22-16} = fixed_imm;
7011 let Inst{15-11} = opc;
7017 let mayStore = 0, mayLoad = 0, hasSideEffects = 0 in
7018 class BaseSIMDVectorShiftTied<bit Q, bit U, bits<5> opc, bits<7> fixed_imm,
7019 RegisterOperand vectype1, RegisterOperand vectype2,
7021 string asm, string dst_kind, string src_kind,
7023 : I<(outs vectype1:$dst), (ins vectype1:$Rd, vectype2:$Rn, immtype:$imm),
7024 asm, "{\t$Rd" # dst_kind # ", $Rn" # src_kind # ", $imm" #
7025 "|" # dst_kind # "\t$Rd, $Rn, $imm}", "$Rd = $dst", pattern>,
7032 let Inst{28-23} = 0b011110;
7033 let Inst{22-16} = fixed_imm;
7034 let Inst{15-11} = opc;
7040 multiclass SIMDVectorRShiftSD<bit U, bits<5> opc, string asm,
7042 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7043 V64, V64, vecshiftR32,
7045 [(set (v2i32 V64:$Rd), (OpNode (v2f32 V64:$Rn), (i32 imm:$imm)))]> {
7047 let Inst{20-16} = imm;
7050 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7051 V128, V128, vecshiftR32,
7053 [(set (v4i32 V128:$Rd), (OpNode (v4f32 V128:$Rn), (i32 imm:$imm)))]> {
7055 let Inst{20-16} = imm;
7058 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7059 V128, V128, vecshiftR64,
7061 [(set (v2i64 V128:$Rd), (OpNode (v2f64 V128:$Rn), (i32 imm:$imm)))]> {
7063 let Inst{21-16} = imm;
7067 multiclass SIMDVectorRShiftSDToFP<bit U, bits<5> opc, string asm,
7069 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7070 V64, V64, vecshiftR32,
7072 [(set (v2f32 V64:$Rd), (OpNode (v2i32 V64:$Rn), (i32 imm:$imm)))]> {
7074 let Inst{20-16} = imm;
7077 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7078 V128, V128, vecshiftR32,
7080 [(set (v4f32 V128:$Rd), (OpNode (v4i32 V128:$Rn), (i32 imm:$imm)))]> {
7082 let Inst{20-16} = imm;
7085 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7086 V128, V128, vecshiftR64,
7088 [(set (v2f64 V128:$Rd), (OpNode (v2i64 V128:$Rn), (i32 imm:$imm)))]> {
7090 let Inst{21-16} = imm;
7094 multiclass SIMDVectorRShiftNarrowBHS<bit U, bits<5> opc, string asm,
7095 SDPatternOperator OpNode> {
7096 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7097 V64, V128, vecshiftR16Narrow,
7099 [(set (v8i8 V64:$Rd), (OpNode (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))]> {
7101 let Inst{18-16} = imm;
7104 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7105 V128, V128, vecshiftR16Narrow,
7106 asm#"2", ".16b", ".8h", []> {
7108 let Inst{18-16} = imm;
7109 let hasSideEffects = 0;
7112 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7113 V64, V128, vecshiftR32Narrow,
7115 [(set (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))]> {
7117 let Inst{19-16} = imm;
7120 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7121 V128, V128, vecshiftR32Narrow,
7122 asm#"2", ".8h", ".4s", []> {
7124 let Inst{19-16} = imm;
7125 let hasSideEffects = 0;
7128 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7129 V64, V128, vecshiftR64Narrow,
7131 [(set (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))]> {
7133 let Inst{20-16} = imm;
7136 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7137 V128, V128, vecshiftR64Narrow,
7138 asm#"2", ".4s", ".2d", []> {
7140 let Inst{20-16} = imm;
7141 let hasSideEffects = 0;
7144 // TableGen doesn't like patters w/ INSERT_SUBREG on the instructions
7145 // themselves, so put them here instead.
7147 // Patterns involving what's effectively an insert high and a normal
7148 // intrinsic, represented by CONCAT_VECTORS.
7149 def : Pat<(concat_vectors (v8i8 V64:$Rd),(OpNode (v8i16 V128:$Rn),
7150 vecshiftR16Narrow:$imm)),
7151 (!cast<Instruction>(NAME # "v16i8_shift")
7152 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7153 V128:$Rn, vecshiftR16Narrow:$imm)>;
7154 def : Pat<(concat_vectors (v4i16 V64:$Rd), (OpNode (v4i32 V128:$Rn),
7155 vecshiftR32Narrow:$imm)),
7156 (!cast<Instruction>(NAME # "v8i16_shift")
7157 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7158 V128:$Rn, vecshiftR32Narrow:$imm)>;
7159 def : Pat<(concat_vectors (v2i32 V64:$Rd), (OpNode (v2i64 V128:$Rn),
7160 vecshiftR64Narrow:$imm)),
7161 (!cast<Instruction>(NAME # "v4i32_shift")
7162 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
7163 V128:$Rn, vecshiftR64Narrow:$imm)>;
7166 multiclass SIMDVectorLShiftBHSD<bit U, bits<5> opc, string asm,
7167 SDPatternOperator OpNode> {
7168 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7169 V64, V64, vecshiftL8,
7171 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7172 (i32 vecshiftL8:$imm)))]> {
7174 let Inst{18-16} = imm;
7177 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7178 V128, V128, vecshiftL8,
7179 asm, ".16b", ".16b",
7180 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7181 (i32 vecshiftL8:$imm)))]> {
7183 let Inst{18-16} = imm;
7186 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7187 V64, V64, vecshiftL16,
7189 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7190 (i32 vecshiftL16:$imm)))]> {
7192 let Inst{19-16} = imm;
7195 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7196 V128, V128, vecshiftL16,
7198 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7199 (i32 vecshiftL16:$imm)))]> {
7201 let Inst{19-16} = imm;
7204 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7205 V64, V64, vecshiftL32,
7207 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7208 (i32 vecshiftL32:$imm)))]> {
7210 let Inst{20-16} = imm;
7213 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7214 V128, V128, vecshiftL32,
7216 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7217 (i32 vecshiftL32:$imm)))]> {
7219 let Inst{20-16} = imm;
7222 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7223 V128, V128, vecshiftL64,
7225 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7226 (i32 vecshiftL64:$imm)))]> {
7228 let Inst{21-16} = imm;
7232 multiclass SIMDVectorRShiftBHSD<bit U, bits<5> opc, string asm,
7233 SDPatternOperator OpNode> {
7234 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7235 V64, V64, vecshiftR8,
7237 [(set (v8i8 V64:$Rd), (OpNode (v8i8 V64:$Rn),
7238 (i32 vecshiftR8:$imm)))]> {
7240 let Inst{18-16} = imm;
7243 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7244 V128, V128, vecshiftR8,
7245 asm, ".16b", ".16b",
7246 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn),
7247 (i32 vecshiftR8:$imm)))]> {
7249 let Inst{18-16} = imm;
7252 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7253 V64, V64, vecshiftR16,
7255 [(set (v4i16 V64:$Rd), (OpNode (v4i16 V64:$Rn),
7256 (i32 vecshiftR16:$imm)))]> {
7258 let Inst{19-16} = imm;
7261 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7262 V128, V128, vecshiftR16,
7264 [(set (v8i16 V128:$Rd), (OpNode (v8i16 V128:$Rn),
7265 (i32 vecshiftR16:$imm)))]> {
7267 let Inst{19-16} = imm;
7270 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7271 V64, V64, vecshiftR32,
7273 [(set (v2i32 V64:$Rd), (OpNode (v2i32 V64:$Rn),
7274 (i32 vecshiftR32:$imm)))]> {
7276 let Inst{20-16} = imm;
7279 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7280 V128, V128, vecshiftR32,
7282 [(set (v4i32 V128:$Rd), (OpNode (v4i32 V128:$Rn),
7283 (i32 vecshiftR32:$imm)))]> {
7285 let Inst{20-16} = imm;
7288 def v2i64_shift : BaseSIMDVectorShift<1, U, opc, {1,?,?,?,?,?,?},
7289 V128, V128, vecshiftR64,
7291 [(set (v2i64 V128:$Rd), (OpNode (v2i64 V128:$Rn),
7292 (i32 vecshiftR64:$imm)))]> {
7294 let Inst{21-16} = imm;
7298 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
7299 multiclass SIMDVectorRShiftBHSDTied<bit U, bits<5> opc, string asm,
7300 SDPatternOperator OpNode = null_frag> {
7301 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7302 V64, V64, vecshiftR8, asm, ".8b", ".8b",
7303 [(set (v8i8 V64:$dst),
7304 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7305 (i32 vecshiftR8:$imm)))]> {
7307 let Inst{18-16} = imm;
7310 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7311 V128, V128, vecshiftR8, asm, ".16b", ".16b",
7312 [(set (v16i8 V128:$dst),
7313 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7314 (i32 vecshiftR8:$imm)))]> {
7316 let Inst{18-16} = imm;
7319 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7320 V64, V64, vecshiftR16, asm, ".4h", ".4h",
7321 [(set (v4i16 V64:$dst),
7322 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7323 (i32 vecshiftR16:$imm)))]> {
7325 let Inst{19-16} = imm;
7328 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7329 V128, V128, vecshiftR16, asm, ".8h", ".8h",
7330 [(set (v8i16 V128:$dst),
7331 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7332 (i32 vecshiftR16:$imm)))]> {
7334 let Inst{19-16} = imm;
7337 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7338 V64, V64, vecshiftR32, asm, ".2s", ".2s",
7339 [(set (v2i32 V64:$dst),
7340 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7341 (i32 vecshiftR32:$imm)))]> {
7343 let Inst{20-16} = imm;
7346 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7347 V128, V128, vecshiftR32, asm, ".4s", ".4s",
7348 [(set (v4i32 V128:$dst),
7349 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7350 (i32 vecshiftR32:$imm)))]> {
7352 let Inst{20-16} = imm;
7355 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7356 V128, V128, vecshiftR64,
7357 asm, ".2d", ".2d", [(set (v2i64 V128:$dst),
7358 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7359 (i32 vecshiftR64:$imm)))]> {
7361 let Inst{21-16} = imm;
7365 multiclass SIMDVectorLShiftBHSDTied<bit U, bits<5> opc, string asm,
7366 SDPatternOperator OpNode = null_frag> {
7367 def v8i8_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,0,1,?,?,?},
7368 V64, V64, vecshiftL8,
7370 [(set (v8i8 V64:$dst),
7371 (OpNode (v8i8 V64:$Rd), (v8i8 V64:$Rn),
7372 (i32 vecshiftL8:$imm)))]> {
7374 let Inst{18-16} = imm;
7377 def v16i8_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,0,1,?,?,?},
7378 V128, V128, vecshiftL8,
7379 asm, ".16b", ".16b",
7380 [(set (v16i8 V128:$dst),
7381 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn),
7382 (i32 vecshiftL8:$imm)))]> {
7384 let Inst{18-16} = imm;
7387 def v4i16_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,0,1,?,?,?,?},
7388 V64, V64, vecshiftL16,
7390 [(set (v4i16 V64:$dst),
7391 (OpNode (v4i16 V64:$Rd), (v4i16 V64:$Rn),
7392 (i32 vecshiftL16:$imm)))]> {
7394 let Inst{19-16} = imm;
7397 def v8i16_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,0,1,?,?,?,?},
7398 V128, V128, vecshiftL16,
7400 [(set (v8i16 V128:$dst),
7401 (OpNode (v8i16 V128:$Rd), (v8i16 V128:$Rn),
7402 (i32 vecshiftL16:$imm)))]> {
7404 let Inst{19-16} = imm;
7407 def v2i32_shift : BaseSIMDVectorShiftTied<0, U, opc, {0,1,?,?,?,?,?},
7408 V64, V64, vecshiftL32,
7410 [(set (v2i32 V64:$dst),
7411 (OpNode (v2i32 V64:$Rd), (v2i32 V64:$Rn),
7412 (i32 vecshiftL32:$imm)))]> {
7414 let Inst{20-16} = imm;
7417 def v4i32_shift : BaseSIMDVectorShiftTied<1, U, opc, {0,1,?,?,?,?,?},
7418 V128, V128, vecshiftL32,
7420 [(set (v4i32 V128:$dst),
7421 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
7422 (i32 vecshiftL32:$imm)))]> {
7424 let Inst{20-16} = imm;
7427 def v2i64_shift : BaseSIMDVectorShiftTied<1, U, opc, {1,?,?,?,?,?,?},
7428 V128, V128, vecshiftL64,
7430 [(set (v2i64 V128:$dst),
7431 (OpNode (v2i64 V128:$Rd), (v2i64 V128:$Rn),
7432 (i32 vecshiftL64:$imm)))]> {
7434 let Inst{21-16} = imm;
7438 multiclass SIMDVectorLShiftLongBHSD<bit U, bits<5> opc, string asm,
7439 SDPatternOperator OpNode> {
7440 def v8i8_shift : BaseSIMDVectorShift<0, U, opc, {0,0,0,1,?,?,?},
7441 V128, V64, vecshiftL8, asm, ".8h", ".8b",
7442 [(set (v8i16 V128:$Rd), (OpNode (v8i8 V64:$Rn), vecshiftL8:$imm))]> {
7444 let Inst{18-16} = imm;
7447 def v16i8_shift : BaseSIMDVectorShift<1, U, opc, {0,0,0,1,?,?,?},
7448 V128, V128, vecshiftL8,
7449 asm#"2", ".8h", ".16b",
7450 [(set (v8i16 V128:$Rd),
7451 (OpNode (extract_high_v16i8 V128:$Rn), vecshiftL8:$imm))]> {
7453 let Inst{18-16} = imm;
7456 def v4i16_shift : BaseSIMDVectorShift<0, U, opc, {0,0,1,?,?,?,?},
7457 V128, V64, vecshiftL16, asm, ".4s", ".4h",
7458 [(set (v4i32 V128:$Rd), (OpNode (v4i16 V64:$Rn), vecshiftL16:$imm))]> {
7460 let Inst{19-16} = imm;
7463 def v8i16_shift : BaseSIMDVectorShift<1, U, opc, {0,0,1,?,?,?,?},
7464 V128, V128, vecshiftL16,
7465 asm#"2", ".4s", ".8h",
7466 [(set (v4i32 V128:$Rd),
7467 (OpNode (extract_high_v8i16 V128:$Rn), vecshiftL16:$imm))]> {
7470 let Inst{19-16} = imm;
7473 def v2i32_shift : BaseSIMDVectorShift<0, U, opc, {0,1,?,?,?,?,?},
7474 V128, V64, vecshiftL32, asm, ".2d", ".2s",
7475 [(set (v2i64 V128:$Rd), (OpNode (v2i32 V64:$Rn), vecshiftL32:$imm))]> {
7477 let Inst{20-16} = imm;
7480 def v4i32_shift : BaseSIMDVectorShift<1, U, opc, {0,1,?,?,?,?,?},
7481 V128, V128, vecshiftL32,
7482 asm#"2", ".2d", ".4s",
7483 [(set (v2i64 V128:$Rd),
7484 (OpNode (extract_high_v4i32 V128:$Rn), vecshiftL32:$imm))]> {
7486 let Inst{20-16} = imm;
7492 // Vector load/store
7494 // SIMD ldX/stX no-index memory references don't allow the optional
7495 // ", #0" constant and handle post-indexing explicitly, so we use
7496 // a more specialized parse method for them. Otherwise, it's the same as
7497 // the general am_noindex handling.
7499 class BaseSIMDLdSt<bit Q, bit L, bits<4> opcode, bits<2> size,
7500 string asm, dag oops, dag iops, list<dag> pattern>
7501 : I<oops, iops, asm, "\t$Vt, $vaddr", "", pattern> {
7506 let Inst{29-23} = 0b0011000;
7508 let Inst{21-16} = 0b000000;
7509 let Inst{15-12} = opcode;
7510 let Inst{11-10} = size;
7511 let Inst{9-5} = vaddr;
7515 class BaseSIMDLdStPost<bit Q, bit L, bits<4> opcode, bits<2> size,
7516 string asm, dag oops, dag iops>
7517 : I<oops, iops, asm, "\t$Vt, $vaddr, $Xm", "$vaddr = $wback", []> {
7523 let Inst{29-23} = 0b0011001;
7526 let Inst{20-16} = Xm;
7527 let Inst{15-12} = opcode;
7528 let Inst{11-10} = size;
7529 let Inst{9-5} = vaddr;
7533 // The immediate form of AdvSIMD post-indexed addressing is encoded with
7534 // register post-index addressing from the zero register.
7535 multiclass SIMDLdStAliases<string asm, string layout, string Count,
7536 int Offset, int Size> {
7537 // E.g. "ld1 { v0.8b, v1.8b }, [x1], #16"
7538 // "ld1\t$Vt, $vaddr, #16"
7539 // may get mapped to
7540 // (LD1Twov8b_POST VecListTwo8b:$Vt, am_simdnoindex:$vaddr, XZR)
7541 def : InstAlias<asm # "\t$Vt, $vaddr, #" # Offset,
7542 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7543 am_simdnoindex:$vaddr,
7544 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
7547 // E.g. "ld1.8b { v0, v1 }, [x1], #16"
7548 // "ld1.8b\t$Vt, $vaddr, #16"
7549 // may get mapped to
7550 // (LD1Twov8b_POST VecListTwo64:$Vt, am_simdnoindex:$vaddr, XZR)
7551 def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr, #" # Offset,
7552 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7553 am_simdnoindex:$vaddr,
7554 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7557 // E.g. "ld1.8b { v0, v1 }, [x1]"
7558 // "ld1\t$Vt, $vaddr"
7559 // may get mapped to
7560 // (LD1Twov8b VecListTwo64:$Vt, am_simdnoindex:$vaddr)
7561 def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr",
7562 (!cast<Instruction>(NAME # Count # "v" # layout)
7563 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7564 am_simdnoindex:$vaddr), 0>;
7566 // E.g. "ld1.8b { v0, v1 }, [x1], x2"
7567 // "ld1\t$Vt, $vaddr, $Xm"
7568 // may get mapped to
7569 // (LD1Twov8b_POST VecListTwo64:$Vt, am_simdnoindex:$vaddr, GPR64pi8:$Xm)
7570 def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr, $Xm",
7571 (!cast<Instruction>(NAME # Count # "v" # layout # "_POST")
7572 am_simdnoindex:$vaddr,
7573 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7574 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
7577 multiclass BaseSIMDLdN<string Count, string asm, string veclist, int Offset128,
7578 int Offset64, bits<4> opcode> {
7579 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7580 def v16b: BaseSIMDLdSt<1, 1, opcode, 0b00, asm,
7581 (outs !cast<RegisterOperand>(veclist # "16b"):$Vt),
7582 (ins am_simdnoindex:$vaddr), []>;
7583 def v8h : BaseSIMDLdSt<1, 1, opcode, 0b01, asm,
7584 (outs !cast<RegisterOperand>(veclist # "8h"):$Vt),
7585 (ins am_simdnoindex:$vaddr), []>;
7586 def v4s : BaseSIMDLdSt<1, 1, opcode, 0b10, asm,
7587 (outs !cast<RegisterOperand>(veclist # "4s"):$Vt),
7588 (ins am_simdnoindex:$vaddr), []>;
7589 def v2d : BaseSIMDLdSt<1, 1, opcode, 0b11, asm,
7590 (outs !cast<RegisterOperand>(veclist # "2d"):$Vt),
7591 (ins am_simdnoindex:$vaddr), []>;
7592 def v8b : BaseSIMDLdSt<0, 1, opcode, 0b00, asm,
7593 (outs !cast<RegisterOperand>(veclist # "8b"):$Vt),
7594 (ins am_simdnoindex:$vaddr), []>;
7595 def v4h : BaseSIMDLdSt<0, 1, opcode, 0b01, asm,
7596 (outs !cast<RegisterOperand>(veclist # "4h"):$Vt),
7597 (ins am_simdnoindex:$vaddr), []>;
7598 def v2s : BaseSIMDLdSt<0, 1, opcode, 0b10, asm,
7599 (outs !cast<RegisterOperand>(veclist # "2s"):$Vt),
7600 (ins am_simdnoindex:$vaddr), []>;
7603 def v16b_POST: BaseSIMDLdStPost<1, 1, opcode, 0b00, asm,
7604 (outs am_simdnoindex:$wback,
7605 !cast<RegisterOperand>(veclist # "16b"):$Vt),
7606 (ins am_simdnoindex:$vaddr,
7607 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7608 def v8h_POST : BaseSIMDLdStPost<1, 1, opcode, 0b01, asm,
7609 (outs am_simdnoindex:$wback,
7610 !cast<RegisterOperand>(veclist # "8h"):$Vt),
7611 (ins am_simdnoindex:$vaddr,
7612 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7613 def v4s_POST : BaseSIMDLdStPost<1, 1, opcode, 0b10, asm,
7614 (outs am_simdnoindex:$wback,
7615 !cast<RegisterOperand>(veclist # "4s"):$Vt),
7616 (ins am_simdnoindex:$vaddr,
7617 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7618 def v2d_POST : BaseSIMDLdStPost<1, 1, opcode, 0b11, asm,
7619 (outs am_simdnoindex:$wback,
7620 !cast<RegisterOperand>(veclist # "2d"):$Vt),
7621 (ins am_simdnoindex:$vaddr,
7622 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7623 def v8b_POST : BaseSIMDLdStPost<0, 1, opcode, 0b00, asm,
7624 (outs am_simdnoindex:$wback,
7625 !cast<RegisterOperand>(veclist # "8b"):$Vt),
7626 (ins am_simdnoindex:$vaddr,
7627 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7628 def v4h_POST : BaseSIMDLdStPost<0, 1, opcode, 0b01, asm,
7629 (outs am_simdnoindex:$wback,
7630 !cast<RegisterOperand>(veclist # "4h"):$Vt),
7631 (ins am_simdnoindex:$vaddr,
7632 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7633 def v2s_POST : BaseSIMDLdStPost<0, 1, opcode, 0b10, asm,
7634 (outs am_simdnoindex:$wback,
7635 !cast<RegisterOperand>(veclist # "2s"):$Vt),
7636 (ins am_simdnoindex:$vaddr,
7637 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7640 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7641 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7642 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7643 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7644 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7645 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7646 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7649 // Only ld1/st1 has a v1d version.
7650 multiclass BaseSIMDStN<string Count, string asm, string veclist, int Offset128,
7651 int Offset64, bits<4> opcode> {
7652 let hasSideEffects = 0, mayStore = 1, mayLoad = 0 in {
7653 def v16b : BaseSIMDLdSt<1, 0, opcode, 0b00, asm, (outs),
7654 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7655 am_simdnoindex:$vaddr), []>;
7656 def v8h : BaseSIMDLdSt<1, 0, opcode, 0b01, asm, (outs),
7657 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7658 am_simdnoindex:$vaddr), []>;
7659 def v4s : BaseSIMDLdSt<1, 0, opcode, 0b10, asm, (outs),
7660 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7661 am_simdnoindex:$vaddr), []>;
7662 def v2d : BaseSIMDLdSt<1, 0, opcode, 0b11, asm, (outs),
7663 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7664 am_simdnoindex:$vaddr), []>;
7665 def v8b : BaseSIMDLdSt<0, 0, opcode, 0b00, asm, (outs),
7666 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7667 am_simdnoindex:$vaddr), []>;
7668 def v4h : BaseSIMDLdSt<0, 0, opcode, 0b01, asm, (outs),
7669 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7670 am_simdnoindex:$vaddr), []>;
7671 def v2s : BaseSIMDLdSt<0, 0, opcode, 0b10, asm, (outs),
7672 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7673 am_simdnoindex:$vaddr), []>;
7675 def v16b_POST : BaseSIMDLdStPost<1, 0, opcode, 0b00, asm,
7676 (outs am_simdnoindex:$wback),
7677 (ins !cast<RegisterOperand>(veclist # "16b"):$Vt,
7678 am_simdnoindex:$vaddr,
7679 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7680 def v8h_POST : BaseSIMDLdStPost<1, 0, opcode, 0b01, asm,
7681 (outs am_simdnoindex:$wback),
7682 (ins !cast<RegisterOperand>(veclist # "8h"):$Vt,
7683 am_simdnoindex:$vaddr,
7684 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7685 def v4s_POST : BaseSIMDLdStPost<1, 0, opcode, 0b10, asm,
7686 (outs am_simdnoindex:$wback),
7687 (ins !cast<RegisterOperand>(veclist # "4s"):$Vt,
7688 am_simdnoindex:$vaddr,
7689 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7690 def v2d_POST : BaseSIMDLdStPost<1, 0, opcode, 0b11, asm,
7691 (outs am_simdnoindex:$wback),
7692 (ins !cast<RegisterOperand>(veclist # "2d"):$Vt,
7693 am_simdnoindex:$vaddr,
7694 !cast<RegisterOperand>("GPR64pi" # Offset128):$Xm)>;
7695 def v8b_POST : BaseSIMDLdStPost<0, 0, opcode, 0b00, asm,
7696 (outs am_simdnoindex:$wback),
7697 (ins !cast<RegisterOperand>(veclist # "8b"):$Vt,
7698 am_simdnoindex:$vaddr,
7699 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7700 def v4h_POST : BaseSIMDLdStPost<0, 0, opcode, 0b01, asm,
7701 (outs am_simdnoindex:$wback),
7702 (ins !cast<RegisterOperand>(veclist # "4h"):$Vt,
7703 am_simdnoindex:$vaddr,
7704 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7705 def v2s_POST : BaseSIMDLdStPost<0, 0, opcode, 0b10, asm,
7706 (outs am_simdnoindex:$wback),
7707 (ins !cast<RegisterOperand>(veclist # "2s"):$Vt,
7708 am_simdnoindex:$vaddr,
7709 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7712 defm : SIMDLdStAliases<asm, "16b", Count, Offset128, 128>;
7713 defm : SIMDLdStAliases<asm, "8h", Count, Offset128, 128>;
7714 defm : SIMDLdStAliases<asm, "4s", Count, Offset128, 128>;
7715 defm : SIMDLdStAliases<asm, "2d", Count, Offset128, 128>;
7716 defm : SIMDLdStAliases<asm, "8b", Count, Offset64, 64>;
7717 defm : SIMDLdStAliases<asm, "4h", Count, Offset64, 64>;
7718 defm : SIMDLdStAliases<asm, "2s", Count, Offset64, 64>;
7721 multiclass BaseSIMDLd1<string Count, string asm, string veclist,
7722 int Offset128, int Offset64, bits<4> opcode>
7723 : BaseSIMDLdN<Count, asm, veclist, Offset128, Offset64, opcode> {
7725 // LD1 instructions have extra "1d" variants.
7726 let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
7727 def v1d : BaseSIMDLdSt<0, 1, opcode, 0b11, asm,
7728 (outs !cast<RegisterOperand>(veclist # "1d"):$Vt),
7729 (ins am_simdnoindex:$vaddr), []>;
7731 def v1d_POST : BaseSIMDLdStPost<0, 1, opcode, 0b11, asm,
7732 (outs am_simdnoindex:$wback,
7733 !cast<RegisterOperand>(veclist # "1d"):$Vt),
7734 (ins am_simdnoindex:$vaddr,
7735 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7738 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7741 multiclass BaseSIMDSt1<string Count, string asm, string veclist,
7742 int Offset128, int Offset64, bits<4> opcode>
7743 : BaseSIMDStN<Count, asm, veclist, Offset128, Offset64, opcode> {
7745 // ST1 instructions have extra "1d" variants.
7746 let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
7747 def v1d : BaseSIMDLdSt<0, 0, opcode, 0b11, asm, (outs),
7748 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7749 am_simdnoindex:$vaddr), []>;
7751 def v1d_POST : BaseSIMDLdStPost<0, 0, opcode, 0b11, asm,
7752 (outs am_simdnoindex:$wback),
7753 (ins !cast<RegisterOperand>(veclist # "1d"):$Vt,
7754 am_simdnoindex:$vaddr,
7755 !cast<RegisterOperand>("GPR64pi" # Offset64):$Xm)>;
7758 defm : SIMDLdStAliases<asm, "1d", Count, Offset64, 64>;
7761 multiclass SIMDLd1Multiple<string asm> {
7762 defm One : BaseSIMDLd1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7763 defm Two : BaseSIMDLd1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7764 defm Three : BaseSIMDLd1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7765 defm Four : BaseSIMDLd1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7768 multiclass SIMDSt1Multiple<string asm> {
7769 defm One : BaseSIMDSt1<"One", asm, "VecListOne", 16, 8, 0b0111>;
7770 defm Two : BaseSIMDSt1<"Two", asm, "VecListTwo", 32, 16, 0b1010>;
7771 defm Three : BaseSIMDSt1<"Three", asm, "VecListThree", 48, 24, 0b0110>;
7772 defm Four : BaseSIMDSt1<"Four", asm, "VecListFour", 64, 32, 0b0010>;
7775 multiclass SIMDLd2Multiple<string asm> {
7776 defm Two : BaseSIMDLdN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7779 multiclass SIMDSt2Multiple<string asm> {
7780 defm Two : BaseSIMDStN<"Two", asm, "VecListTwo", 32, 16, 0b1000>;
7783 multiclass SIMDLd3Multiple<string asm> {
7784 defm Three : BaseSIMDLdN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
7787 multiclass SIMDSt3Multiple<string asm> {
7788 defm Three : BaseSIMDStN<"Three", asm, "VecListThree", 48, 24, 0b0100>;
7791 multiclass SIMDLd4Multiple<string asm> {
7792 defm Four : BaseSIMDLdN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
7795 multiclass SIMDSt4Multiple<string asm> {
7796 defm Four : BaseSIMDStN<"Four", asm, "VecListFour", 64, 32, 0b0000>;
7800 // AdvSIMD Load/store single-element
7803 class BaseSIMDLdStSingle<bit L, bit R, bits<3> opcode,
7804 string asm, string operands, string cst,
7805 dag oops, dag iops, list<dag> pattern>
7806 : I<oops, iops, asm, operands, cst, pattern> {
7810 let Inst{29-24} = 0b001101;
7813 let Inst{15-13} = opcode;
7814 let Inst{9-5} = vaddr;
7818 class BaseSIMDLdStSingleTied<bit L, bit R, bits<3> opcode,
7819 string asm, string operands, string cst,
7820 dag oops, dag iops, list<dag> pattern>
7821 : I<oops, iops, asm, operands, "$Vt = $dst," # cst, pattern> {
7825 let Inst{29-24} = 0b001101;
7828 let Inst{15-13} = opcode;
7829 let Inst{9-5} = vaddr;
7834 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7835 class BaseSIMDLdR<bit Q, bit R, bits<3> opcode, bit S, bits<2> size, string asm,
7837 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, $vaddr", "",
7838 (outs listtype:$Vt), (ins am_simdnoindex:$vaddr),
7842 let Inst{20-16} = 0b00000;
7844 let Inst{11-10} = size;
7846 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
7847 class BaseSIMDLdRPost<bit Q, bit R, bits<3> opcode, bit S, bits<2> size,
7848 string asm, Operand listtype, Operand GPR64pi>
7849 : BaseSIMDLdStSingle<1, R, opcode, asm, "\t$Vt, $vaddr, $Xm",
7851 (outs am_simdnoindex:$wback, listtype:$Vt),
7852 (ins am_simdnoindex:$vaddr, GPR64pi:$Xm), []> {
7856 let Inst{20-16} = Xm;
7858 let Inst{11-10} = size;
7861 multiclass SIMDLdrAliases<string asm, string layout, string Count,
7862 int Offset, int Size> {
7863 // E.g. "ld1r { v0.8b }, [x1], #1"
7864 // "ld1r.8b\t$Vt, $vaddr, #1"
7865 // may get mapped to
7866 // (LD1Rv8b_POST VecListOne8b:$Vt, am_simdnoindex:$vaddr, XZR)
7867 def : InstAlias<asm # "\t$Vt, $vaddr, #" # Offset,
7868 (!cast<Instruction>(NAME # "v" # layout # "_POST")
7869 am_simdnoindex:$vaddr,
7870 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
7873 // E.g. "ld1r.8b { v0 }, [x1], #1"
7874 // "ld1r.8b\t$Vt, $vaddr, #1"
7875 // may get mapped to
7876 // (LD1Rv8b_POST VecListOne64:$Vt, am_simdnoindex:$vaddr, XZR)
7877 def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr, #" # Offset,
7878 (!cast<Instruction>(NAME # "v" # layout # "_POST")
7879 am_simdnoindex:$vaddr,
7880 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7883 // E.g. "ld1r.8b { v0 }, [x1]"
7884 // "ld1r.8b\t$Vt, $vaddr"
7885 // may get mapped to
7886 // (LD1Rv8b VecListOne64:$Vt, am_simdnoindex:$vaddr)
7887 def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr",
7888 (!cast<Instruction>(NAME # "v" # layout)
7889 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7890 am_simdnoindex:$vaddr), 0>;
7892 // E.g. "ld1r.8b { v0 }, [x1], x2"
7893 // "ld1r.8b\t$Vt, $vaddr, $Xm"
7894 // may get mapped to
7895 // (LD1Rv8b_POST VecListOne64:$Vt, am_simdnoindex:$vaddr, GPR64pi1:$Xm)
7896 def : InstAlias<asm # "." # layout # "\t$Vt, $vaddr, $Xm",
7897 (!cast<Instruction>(NAME # "v" # layout # "_POST")
7898 am_simdnoindex:$vaddr,
7899 !cast<RegisterOperand>("VecList" # Count # Size):$Vt,
7900 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
7903 multiclass SIMDLdR<bit R, bits<3> opcode, bit S, string asm, string Count,
7904 int Offset1, int Offset2, int Offset4, int Offset8> {
7905 def v8b : BaseSIMDLdR<0, R, opcode, S, 0b00, asm,
7906 !cast<Operand>("VecList" # Count # "8b")>;
7907 def v16b: BaseSIMDLdR<1, R, opcode, S, 0b00, asm,
7908 !cast<Operand>("VecList" # Count #"16b")>;
7909 def v4h : BaseSIMDLdR<0, R, opcode, S, 0b01, asm,
7910 !cast<Operand>("VecList" # Count #"4h")>;
7911 def v8h : BaseSIMDLdR<1, R, opcode, S, 0b01, asm,
7912 !cast<Operand>("VecList" # Count #"8h")>;
7913 def v2s : BaseSIMDLdR<0, R, opcode, S, 0b10, asm,
7914 !cast<Operand>("VecList" # Count #"2s")>;
7915 def v4s : BaseSIMDLdR<1, R, opcode, S, 0b10, asm,
7916 !cast<Operand>("VecList" # Count #"4s")>;
7917 def v1d : BaseSIMDLdR<0, R, opcode, S, 0b11, asm,
7918 !cast<Operand>("VecList" # Count #"1d")>;
7919 def v2d : BaseSIMDLdR<1, R, opcode, S, 0b11, asm,
7920 !cast<Operand>("VecList" # Count #"2d")>;
7922 def v8b_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b00, asm,
7923 !cast<Operand>("VecList" # Count # "8b"),
7924 !cast<Operand>("GPR64pi" # Offset1)>;
7925 def v16b_POST: BaseSIMDLdRPost<1, R, opcode, S, 0b00, asm,
7926 !cast<Operand>("VecList" # Count # "16b"),
7927 !cast<Operand>("GPR64pi" # Offset1)>;
7928 def v4h_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b01, asm,
7929 !cast<Operand>("VecList" # Count # "4h"),
7930 !cast<Operand>("GPR64pi" # Offset2)>;
7931 def v8h_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b01, asm,
7932 !cast<Operand>("VecList" # Count # "8h"),
7933 !cast<Operand>("GPR64pi" # Offset2)>;
7934 def v2s_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b10, asm,
7935 !cast<Operand>("VecList" # Count # "2s"),
7936 !cast<Operand>("GPR64pi" # Offset4)>;
7937 def v4s_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b10, asm,
7938 !cast<Operand>("VecList" # Count # "4s"),
7939 !cast<Operand>("GPR64pi" # Offset4)>;
7940 def v1d_POST : BaseSIMDLdRPost<0, R, opcode, S, 0b11, asm,
7941 !cast<Operand>("VecList" # Count # "1d"),
7942 !cast<Operand>("GPR64pi" # Offset8)>;
7943 def v2d_POST : BaseSIMDLdRPost<1, R, opcode, S, 0b11, asm,
7944 !cast<Operand>("VecList" # Count # "2d"),
7945 !cast<Operand>("GPR64pi" # Offset8)>;
7947 defm : SIMDLdrAliases<asm, "8b", Count, Offset1, 64>;
7948 defm : SIMDLdrAliases<asm, "16b", Count, Offset1, 128>;
7949 defm : SIMDLdrAliases<asm, "4h", Count, Offset2, 64>;
7950 defm : SIMDLdrAliases<asm, "8h", Count, Offset2, 128>;
7951 defm : SIMDLdrAliases<asm, "2s", Count, Offset4, 64>;
7952 defm : SIMDLdrAliases<asm, "4s", Count, Offset4, 128>;
7953 defm : SIMDLdrAliases<asm, "1d", Count, Offset8, 64>;
7954 defm : SIMDLdrAliases<asm, "2d", Count, Offset8, 128>;
7957 class SIMDLdStSingleB<bit L, bit R, bits<3> opcode, string asm,
7958 dag oops, dag iops, list<dag> pattern>
7959 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "", oops, iops,
7961 // idx encoded in Q:S:size fields.
7963 let Inst{30} = idx{3};
7965 let Inst{20-16} = 0b00000;
7966 let Inst{12} = idx{2};
7967 let Inst{11-10} = idx{1-0};
7969 class SIMDLdStSingleBTied<bit L, bit R, bits<3> opcode, string asm,
7970 dag oops, dag iops, list<dag> pattern>
7971 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "",
7972 oops, iops, pattern> {
7973 // idx encoded in Q:S:size fields.
7975 let Inst{30} = idx{3};
7977 let Inst{20-16} = 0b00000;
7978 let Inst{12} = idx{2};
7979 let Inst{11-10} = idx{1-0};
7981 class SIMDLdStSingleBPost<bit L, bit R, bits<3> opcode, string asm,
7983 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
7984 "$vaddr = $wback", oops, iops, []> {
7985 // idx encoded in Q:S:size fields.
7988 let Inst{30} = idx{3};
7990 let Inst{20-16} = Xm;
7991 let Inst{12} = idx{2};
7992 let Inst{11-10} = idx{1-0};
7994 class SIMDLdStSingleBTiedPost<bit L, bit R, bits<3> opcode, string asm,
7996 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
7997 "$vaddr = $wback", oops, iops, []> {
7998 // idx encoded in Q:S:size fields.
8001 let Inst{30} = idx{3};
8003 let Inst{20-16} = Xm;
8004 let Inst{12} = idx{2};
8005 let Inst{11-10} = idx{1-0};
8008 class SIMDLdStSingleH<bit L, bit R, bits<3> opcode, bit size, string asm,
8009 dag oops, dag iops, list<dag> pattern>
8010 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "", oops, iops,
8012 // idx encoded in Q:S:size<1> fields.
8014 let Inst{30} = idx{2};
8016 let Inst{20-16} = 0b00000;
8017 let Inst{12} = idx{1};
8018 let Inst{11} = idx{0};
8019 let Inst{10} = size;
8021 class SIMDLdStSingleHTied<bit L, bit R, bits<3> opcode, bit size, string asm,
8022 dag oops, dag iops, list<dag> pattern>
8023 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "",
8024 oops, iops, pattern> {
8025 // idx encoded in Q:S:size<1> fields.
8027 let Inst{30} = idx{2};
8029 let Inst{20-16} = 0b00000;
8030 let Inst{12} = idx{1};
8031 let Inst{11} = idx{0};
8032 let Inst{10} = size;
8035 class SIMDLdStSingleHPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8037 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
8038 "$vaddr = $wback", oops, iops, []> {
8039 // idx encoded in Q:S:size<1> fields.
8042 let Inst{30} = idx{2};
8044 let Inst{20-16} = Xm;
8045 let Inst{12} = idx{1};
8046 let Inst{11} = idx{0};
8047 let Inst{10} = size;
8049 class SIMDLdStSingleHTiedPost<bit L, bit R, bits<3> opcode, bit size, string asm,
8051 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
8052 "$vaddr = $wback", oops, iops, []> {
8053 // idx encoded in Q:S:size<1> fields.
8056 let Inst{30} = idx{2};
8058 let Inst{20-16} = Xm;
8059 let Inst{12} = idx{1};
8060 let Inst{11} = idx{0};
8061 let Inst{10} = size;
8063 class SIMDLdStSingleS<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8064 dag oops, dag iops, list<dag> pattern>
8065 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "", oops, iops,
8067 // idx encoded in Q:S fields.
8069 let Inst{30} = idx{1};
8071 let Inst{20-16} = 0b00000;
8072 let Inst{12} = idx{0};
8073 let Inst{11-10} = size;
8075 class SIMDLdStSingleSTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8076 dag oops, dag iops, list<dag> pattern>
8077 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "",
8078 oops, iops, pattern> {
8079 // idx encoded in Q:S fields.
8081 let Inst{30} = idx{1};
8083 let Inst{20-16} = 0b00000;
8084 let Inst{12} = idx{0};
8085 let Inst{11-10} = size;
8087 class SIMDLdStSingleSPost<bit L, bit R, bits<3> opcode, bits<2> size,
8088 string asm, dag oops, dag iops>
8089 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
8090 "$vaddr = $wback", oops, iops, []> {
8091 // idx encoded in Q:S fields.
8094 let Inst{30} = idx{1};
8096 let Inst{20-16} = Xm;
8097 let Inst{12} = idx{0};
8098 let Inst{11-10} = size;
8100 class SIMDLdStSingleSTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8101 string asm, dag oops, dag iops>
8102 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
8103 "$vaddr = $wback", oops, iops, []> {
8104 // idx encoded in Q:S fields.
8107 let Inst{30} = idx{1};
8109 let Inst{20-16} = Xm;
8110 let Inst{12} = idx{0};
8111 let Inst{11-10} = size;
8113 class SIMDLdStSingleD<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8114 dag oops, dag iops, list<dag> pattern>
8115 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "", oops, iops,
8117 // idx encoded in Q field.
8121 let Inst{20-16} = 0b00000;
8123 let Inst{11-10} = size;
8125 class SIMDLdStSingleDTied<bit L, bit R, bits<3> opcode, bits<2> size, string asm,
8126 dag oops, dag iops, list<dag> pattern>
8127 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr", "",
8128 oops, iops, pattern> {
8129 // idx encoded in Q field.
8133 let Inst{20-16} = 0b00000;
8135 let Inst{11-10} = size;
8137 class SIMDLdStSingleDPost<bit L, bit R, bits<3> opcode, bits<2> size,
8138 string asm, dag oops, dag iops>
8139 : BaseSIMDLdStSingle<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
8140 "$vaddr = $wback", oops, iops, []> {
8141 // idx encoded in Q field.
8146 let Inst{20-16} = Xm;
8148 let Inst{11-10} = size;
8150 class SIMDLdStSingleDTiedPost<bit L, bit R, bits<3> opcode, bits<2> size,
8151 string asm, dag oops, dag iops>
8152 : BaseSIMDLdStSingleTied<L, R, opcode, asm, "\t$Vt$idx, $vaddr, $Xm",
8153 "$vaddr = $wback", oops, iops, []> {
8154 // idx encoded in Q field.
8159 let Inst{20-16} = Xm;
8161 let Inst{11-10} = size;
8164 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8165 multiclass SIMDLdSingleBTied<bit R, bits<3> opcode, string asm,
8166 RegisterOperand listtype,
8167 RegisterOperand GPR64pi> {
8168 def i8 : SIMDLdStSingleBTied<1, R, opcode, asm,
8169 (outs listtype:$dst),
8170 (ins listtype:$Vt, VectorIndexB:$idx,
8171 am_simdnoindex:$vaddr), []>;
8173 def i8_POST : SIMDLdStSingleBTiedPost<1, R, opcode, asm,
8174 (outs am_simdnoindex:$wback, listtype:$dst),
8175 (ins listtype:$Vt, VectorIndexB:$idx,
8176 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
8178 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8179 multiclass SIMDLdSingleHTied<bit R, bits<3> opcode, bit size, string asm,
8180 RegisterOperand listtype,
8181 RegisterOperand GPR64pi> {
8182 def i16 : SIMDLdStSingleHTied<1, R, opcode, size, asm,
8183 (outs listtype:$dst),
8184 (ins listtype:$Vt, VectorIndexH:$idx,
8185 am_simdnoindex:$vaddr), []>;
8187 def i16_POST : SIMDLdStSingleHTiedPost<1, R, opcode, size, asm,
8188 (outs am_simdnoindex:$wback, listtype:$dst),
8189 (ins listtype:$Vt, VectorIndexH:$idx,
8190 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
8192 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8193 multiclass SIMDLdSingleSTied<bit R, bits<3> opcode, bits<2> size,string asm,
8194 RegisterOperand listtype,
8195 RegisterOperand GPR64pi> {
8196 def i32 : SIMDLdStSingleSTied<1, R, opcode, size, asm,
8197 (outs listtype:$dst),
8198 (ins listtype:$Vt, VectorIndexS:$idx,
8199 am_simdnoindex:$vaddr), []>;
8201 def i32_POST : SIMDLdStSingleSTiedPost<1, R, opcode, size, asm,
8202 (outs am_simdnoindex:$wback, listtype:$dst),
8203 (ins listtype:$Vt, VectorIndexS:$idx,
8204 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
8206 let mayLoad = 1, mayStore = 0, hasSideEffects = 0 in
8207 multiclass SIMDLdSingleDTied<bit R, bits<3> opcode, bits<2> size, string asm,
8208 RegisterOperand listtype, RegisterOperand GPR64pi> {
8209 def i64 : SIMDLdStSingleDTied<1, R, opcode, size, asm,
8210 (outs listtype:$dst),
8211 (ins listtype:$Vt, VectorIndexD:$idx,
8212 am_simdnoindex:$vaddr), []>;
8214 def i64_POST : SIMDLdStSingleDTiedPost<1, R, opcode, size, asm,
8215 (outs am_simdnoindex:$wback, listtype:$dst),
8216 (ins listtype:$Vt, VectorIndexD:$idx,
8217 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
8219 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8220 multiclass SIMDStSingleB<bit R, bits<3> opcode, string asm,
8221 RegisterOperand listtype, RegisterOperand GPR64pi> {
8222 def i8 : SIMDLdStSingleB<0, R, opcode, asm,
8223 (outs), (ins listtype:$Vt, VectorIndexB:$idx,
8224 am_simdnoindex:$vaddr), []>;
8226 def i8_POST : SIMDLdStSingleBPost<0, R, opcode, asm,
8227 (outs am_simdnoindex:$wback),
8228 (ins listtype:$Vt, VectorIndexB:$idx,
8229 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
8231 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8232 multiclass SIMDStSingleH<bit R, bits<3> opcode, bit size, string asm,
8233 RegisterOperand listtype, RegisterOperand GPR64pi> {
8234 def i16 : SIMDLdStSingleH<0, R, opcode, size, asm,
8235 (outs), (ins listtype:$Vt, VectorIndexH:$idx,
8236 am_simdnoindex:$vaddr), []>;
8238 def i16_POST : SIMDLdStSingleHPost<0, R, opcode, size, asm,
8239 (outs am_simdnoindex:$wback),
8240 (ins listtype:$Vt, VectorIndexH:$idx,
8241 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
8243 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8244 multiclass SIMDStSingleS<bit R, bits<3> opcode, bits<2> size,string asm,
8245 RegisterOperand listtype, RegisterOperand GPR64pi> {
8246 def i32 : SIMDLdStSingleS<0, R, opcode, size, asm,
8247 (outs), (ins listtype:$Vt, VectorIndexS:$idx,
8248 am_simdnoindex:$vaddr), []>;
8250 def i32_POST : SIMDLdStSingleSPost<0, R, opcode, size, asm,
8251 (outs am_simdnoindex:$wback),
8252 (ins listtype:$Vt, VectorIndexS:$idx,
8253 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
8255 let mayLoad = 0, mayStore = 1, hasSideEffects = 0 in
8256 multiclass SIMDStSingleD<bit R, bits<3> opcode, bits<2> size, string asm,
8257 RegisterOperand listtype, RegisterOperand GPR64pi> {
8258 def i64 : SIMDLdStSingleD<0, R, opcode, size, asm,
8259 (outs), (ins listtype:$Vt, VectorIndexD:$idx,
8260 am_simdnoindex:$vaddr), []>;
8262 def i64_POST : SIMDLdStSingleDPost<0, R, opcode, size, asm,
8263 (outs am_simdnoindex:$wback),
8264 (ins listtype:$Vt, VectorIndexD:$idx,
8265 am_simdnoindex:$vaddr, GPR64pi:$Xm)>;
8268 multiclass SIMDLdStSingleAliases<string asm, string layout, string Type,
8269 string Count, int Offset, Operand idxtype> {
8270 // E.g. "ld1 { v0.8b }[0], [x1], #1"
8271 // "ld1\t$Vt, $vaddr, #1"
8272 // may get mapped to
8273 // (LD1Rv8b_POST VecListOne8b:$Vt, am_simdnoindex:$vaddr, XZR)
8274 def : InstAlias<asm # "\t$Vt$idx, $vaddr, #" # Offset,
8275 (!cast<Instruction>(NAME # Type # "_POST")
8276 am_simdnoindex:$vaddr,
8277 !cast<RegisterOperand>("VecList" # Count # layout):$Vt,
8278 idxtype:$idx, XZR), 1>;
8280 // E.g. "ld1.8b { v0 }[0], [x1], #1"
8281 // "ld1.8b\t$Vt, $vaddr, #1"
8282 // may get mapped to
8283 // (LD1Rv8b_POST VecListOne64:$Vt, am_simdnoindex:$vaddr, XZR)
8284 def : InstAlias<asm # "." # layout # "\t$Vt$idx, $vaddr, #" # Offset,
8285 (!cast<Instruction>(NAME # Type # "_POST")
8286 am_simdnoindex:$vaddr,
8287 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8288 idxtype:$idx, XZR), 0>;
8290 // E.g. "ld1.8b { v0 }[0], [x1]"
8291 // "ld1.8b\t$Vt, $vaddr"
8292 // may get mapped to
8293 // (LD1Rv8b VecListOne64:$Vt, am_simdnoindex:$vaddr)
8294 def : InstAlias<asm # "." # layout # "\t$Vt$idx, $vaddr",
8295 (!cast<Instruction>(NAME # Type)
8296 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8297 idxtype:$idx, am_simdnoindex:$vaddr), 0>;
8299 // E.g. "ld1.8b { v0 }[0], [x1], x2"
8300 // "ld1.8b\t$Vt, $vaddr, $Xm"
8301 // may get mapped to
8302 // (LD1Rv8b_POST VecListOne64:$Vt, am_simdnoindex:$vaddr, GPR64pi1:$Xm)
8303 def : InstAlias<asm # "." # layout # "\t$Vt$idx, $vaddr, $Xm",
8304 (!cast<Instruction>(NAME # Type # "_POST")
8305 am_simdnoindex:$vaddr,
8306 !cast<RegisterOperand>("VecList" # Count # "128"):$Vt,
8308 !cast<RegisterOperand>("GPR64pi" # Offset):$Xm), 0>;
8311 multiclass SIMDLdSt1SingleAliases<string asm> {
8312 defm : SIMDLdStSingleAliases<asm, "b", "i8", "One", 1, VectorIndexB>;
8313 defm : SIMDLdStSingleAliases<asm, "h", "i16", "One", 2, VectorIndexH>;
8314 defm : SIMDLdStSingleAliases<asm, "s", "i32", "One", 4, VectorIndexS>;
8315 defm : SIMDLdStSingleAliases<asm, "d", "i64", "One", 8, VectorIndexD>;
8318 multiclass SIMDLdSt2SingleAliases<string asm> {
8319 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Two", 2, VectorIndexB>;
8320 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Two", 4, VectorIndexH>;
8321 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Two", 8, VectorIndexS>;
8322 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Two", 16, VectorIndexD>;
8325 multiclass SIMDLdSt3SingleAliases<string asm> {
8326 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Three", 3, VectorIndexB>;
8327 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Three", 6, VectorIndexH>;
8328 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Three", 12, VectorIndexS>;
8329 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Three", 24, VectorIndexD>;
8332 multiclass SIMDLdSt4SingleAliases<string asm> {
8333 defm : SIMDLdStSingleAliases<asm, "b", "i8", "Four", 4, VectorIndexB>;
8334 defm : SIMDLdStSingleAliases<asm, "h", "i16", "Four", 8, VectorIndexH>;
8335 defm : SIMDLdStSingleAliases<asm, "s", "i32", "Four", 16, VectorIndexS>;
8336 defm : SIMDLdStSingleAliases<asm, "d", "i64", "Four", 32, VectorIndexD>;
8338 } // end of 'let Predicates = [HasNEON]'
8340 //----------------------------------------------------------------------------
8341 // Crypto extensions
8342 //----------------------------------------------------------------------------
8344 let Predicates = [HasCrypto] in {
8345 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8346 class AESBase<bits<4> opc, string asm, dag outs, dag ins, string cstr,
8348 : I<outs, ins, asm, "{\t$Rd.16b, $Rn.16b|.16b\t$Rd, $Rn}", cstr, pat>,
8352 let Inst{31-16} = 0b0100111000101000;
8353 let Inst{15-12} = opc;
8354 let Inst{11-10} = 0b10;
8359 class AESInst<bits<4> opc, string asm, Intrinsic OpNode>
8360 : AESBase<opc, asm, (outs V128:$Rd), (ins V128:$Rn), "",
8361 [(set (v16i8 V128:$Rd), (OpNode (v16i8 V128:$Rn)))]>;
8363 class AESTiedInst<bits<4> opc, string asm, Intrinsic OpNode>
8364 : AESBase<opc, asm, (outs V128:$dst), (ins V128:$Rd, V128:$Rn),
8366 [(set (v16i8 V128:$dst),
8367 (OpNode (v16i8 V128:$Rd), (v16i8 V128:$Rn)))]>;
8369 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8370 class SHA3OpTiedInst<bits<3> opc, string asm, string dst_lhs_kind,
8371 dag oops, dag iops, list<dag> pat>
8372 : I<oops, iops, asm,
8373 "{\t$Rd" # dst_lhs_kind # ", $Rn" # dst_lhs_kind # ", $Rm.4s" #
8374 "|.4s\t$Rd, $Rn, $Rm}", "$Rd = $dst", pat>,
8379 let Inst{31-21} = 0b01011110000;
8380 let Inst{20-16} = Rm;
8382 let Inst{14-12} = opc;
8383 let Inst{11-10} = 0b00;
8388 class SHATiedInstQSV<bits<3> opc, string asm, Intrinsic OpNode>
8389 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8390 (ins FPR128:$Rd, FPR32:$Rn, V128:$Rm),
8391 [(set (v4i32 FPR128:$dst),
8392 (OpNode (v4i32 FPR128:$Rd), (i32 FPR32:$Rn),
8393 (v4i32 V128:$Rm)))]>;
8395 class SHATiedInstVVV<bits<3> opc, string asm, Intrinsic OpNode>
8396 : SHA3OpTiedInst<opc, asm, ".4s", (outs V128:$dst),
8397 (ins V128:$Rd, V128:$Rn, V128:$Rm),
8398 [(set (v4i32 V128:$dst),
8399 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn),
8400 (v4i32 V128:$Rm)))]>;
8402 class SHATiedInstQQV<bits<3> opc, string asm, Intrinsic OpNode>
8403 : SHA3OpTiedInst<opc, asm, "", (outs FPR128:$dst),
8404 (ins FPR128:$Rd, FPR128:$Rn, V128:$Rm),
8405 [(set (v4i32 FPR128:$dst),
8406 (OpNode (v4i32 FPR128:$Rd), (v4i32 FPR128:$Rn),
8407 (v4i32 V128:$Rm)))]>;
8409 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
8410 class SHA2OpInst<bits<4> opc, string asm, string kind,
8411 string cstr, dag oops, dag iops,
8413 : I<oops, iops, asm, "{\t$Rd" # kind # ", $Rn" # kind #
8414 "|" # kind # "\t$Rd, $Rn}", cstr, pat>,
8418 let Inst{31-16} = 0b0101111000101000;
8419 let Inst{15-12} = opc;
8420 let Inst{11-10} = 0b10;
8425 class SHATiedInstVV<bits<4> opc, string asm, Intrinsic OpNode>
8426 : SHA2OpInst<opc, asm, ".4s", "$Rd = $dst", (outs V128:$dst),
8427 (ins V128:$Rd, V128:$Rn),
8428 [(set (v4i32 V128:$dst),
8429 (OpNode (v4i32 V128:$Rd), (v4i32 V128:$Rn)))]>;
8431 class SHAInstSS<bits<4> opc, string asm, Intrinsic OpNode>
8432 : SHA2OpInst<opc, asm, "", "", (outs FPR32:$Rd), (ins FPR32:$Rn),
8433 [(set (i32 FPR32:$Rd), (OpNode (i32 FPR32:$Rn)))]>;
8434 } // end of 'let Predicates = [HasCrypto]'
8436 // Allow the size specifier tokens to be upper case, not just lower.
8437 def : TokenAlias<".8B", ".8b">;
8438 def : TokenAlias<".4H", ".4h">;
8439 def : TokenAlias<".2S", ".2s">;
8440 def : TokenAlias<".1D", ".1d">;
8441 def : TokenAlias<".16B", ".16b">;
8442 def : TokenAlias<".8H", ".8h">;
8443 def : TokenAlias<".4S", ".4s">;
8444 def : TokenAlias<".2D", ".2d">;
8445 def : TokenAlias<".1Q", ".1q">;
8446 def : TokenAlias<".B", ".b">;
8447 def : TokenAlias<".H", ".h">;
8448 def : TokenAlias<".S", ".s">;
8449 def : TokenAlias<".D", ".d">;
8450 def : TokenAlias<".Q", ".q">;