1 //===- ARM64InstrInfo.cpp - ARM64 Instruction Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARM64InstrInfo.h"
15 #include "ARM64Subtarget.h"
16 #include "MCTargetDesc/ARM64AddressingModes.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineMemOperand.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/TargetRegistry.h"
26 #define GET_INSTRINFO_CTOR_DTOR
27 #include "ARM64GenInstrInfo.inc"
31 ARM64InstrInfo::ARM64InstrInfo(const ARM64Subtarget &STI)
32 : ARM64GenInstrInfo(ARM64::ADJCALLSTACKDOWN, ARM64::ADJCALLSTACKUP),
33 RI(this, &STI), Subtarget(STI) {}
35 /// GetInstSize - Return the number of bytes of code the specified
36 /// instruction may be. This returns the maximum number of bytes.
37 unsigned ARM64InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
38 const MCInstrDesc &Desc = MI->getDesc();
40 switch (Desc.getOpcode()) {
42 // Anything not explicitly designated otherwise is a nomal 4-byte insn.
44 case TargetOpcode::DBG_VALUE:
45 case TargetOpcode::EH_LABEL:
46 case TargetOpcode::IMPLICIT_DEF:
47 case TargetOpcode::KILL:
51 llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");
54 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
55 SmallVectorImpl<MachineOperand> &Cond) {
56 // Block ends with fall-through condbranch.
57 switch (LastInst->getOpcode()) {
59 llvm_unreachable("Unknown branch instruction?");
61 Target = LastInst->getOperand(1).getMBB();
62 Cond.push_back(LastInst->getOperand(0));
68 Target = LastInst->getOperand(1).getMBB();
69 Cond.push_back(MachineOperand::CreateImm(-1));
70 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
71 Cond.push_back(LastInst->getOperand(0));
75 Target = LastInst->getOperand(2).getMBB();
76 Cond.push_back(MachineOperand::CreateImm(-1));
77 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
78 Cond.push_back(LastInst->getOperand(0));
79 Cond.push_back(LastInst->getOperand(1));
84 bool ARM64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
85 MachineBasicBlock *&TBB,
86 MachineBasicBlock *&FBB,
87 SmallVectorImpl<MachineOperand> &Cond,
88 bool AllowModify) const {
89 // If the block has no terminators, it just falls into the block after it.
90 MachineBasicBlock::iterator I = MBB.end();
94 while (I->isDebugValue()) {
99 if (!isUnpredicatedTerminator(I))
102 // Get the last instruction in the block.
103 MachineInstr *LastInst = I;
105 // If there is only one terminator instruction, process it.
106 unsigned LastOpc = LastInst->getOpcode();
107 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
108 if (isUncondBranchOpcode(LastOpc)) {
109 TBB = LastInst->getOperand(0).getMBB();
112 if (isCondBranchOpcode(LastOpc)) {
113 // Block ends with fall-through condbranch.
114 parseCondBranch(LastInst, TBB, Cond);
117 return true; // Can't handle indirect branch.
120 // Get the instruction before it if it is a terminator.
121 MachineInstr *SecondLastInst = I;
122 unsigned SecondLastOpc = SecondLastInst->getOpcode();
124 // If AllowModify is true and the block ends with two or more unconditional
125 // branches, delete all but the first unconditional branch.
126 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
127 while (isUncondBranchOpcode(SecondLastOpc)) {
128 LastInst->eraseFromParent();
129 LastInst = SecondLastInst;
130 LastOpc = LastInst->getOpcode();
131 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
132 // Return now the only terminator is an unconditional branch.
133 TBB = LastInst->getOperand(0).getMBB();
137 SecondLastOpc = SecondLastInst->getOpcode();
142 // If there are three terminators, we don't know what sort of block this is.
143 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
146 // If the block ends with a B and a Bcc, handle it.
147 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
148 parseCondBranch(SecondLastInst, TBB, Cond);
149 FBB = LastInst->getOperand(0).getMBB();
153 // If the block ends with two unconditional branches, handle it. The second
154 // one is not executed, so remove it.
155 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
156 TBB = SecondLastInst->getOperand(0).getMBB();
159 I->eraseFromParent();
163 // ...likewise if it ends with an indirect branch followed by an unconditional
165 if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
168 I->eraseFromParent();
172 // Otherwise, can't handle this.
176 bool ARM64InstrInfo::ReverseBranchCondition(
177 SmallVectorImpl<MachineOperand> &Cond) const {
178 if (Cond[0].getImm() != -1) {
180 ARM64CC::CondCode CC = (ARM64CC::CondCode)(int)Cond[0].getImm();
181 Cond[0].setImm(ARM64CC::getInvertedCondCode(CC));
183 // Folded compare-and-branch
184 switch (Cond[1].getImm()) {
186 llvm_unreachable("Unknown conditional branch!");
188 Cond[1].setImm(ARM64::CBNZW);
191 Cond[1].setImm(ARM64::CBZW);
194 Cond[1].setImm(ARM64::CBNZX);
197 Cond[1].setImm(ARM64::CBZX);
200 Cond[1].setImm(ARM64::TBNZ);
203 Cond[1].setImm(ARM64::TBZ);
211 unsigned ARM64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
212 MachineBasicBlock::iterator I = MBB.end();
213 if (I == MBB.begin())
216 while (I->isDebugValue()) {
217 if (I == MBB.begin())
221 if (!isUncondBranchOpcode(I->getOpcode()) &&
222 !isCondBranchOpcode(I->getOpcode()))
225 // Remove the branch.
226 I->eraseFromParent();
230 if (I == MBB.begin())
233 if (!isCondBranchOpcode(I->getOpcode()))
236 // Remove the branch.
237 I->eraseFromParent();
241 void ARM64InstrInfo::instantiateCondBranch(
242 MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB,
243 const SmallVectorImpl<MachineOperand> &Cond) const {
244 if (Cond[0].getImm() != -1) {
246 BuildMI(&MBB, DL, get(ARM64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
248 // Folded compare-and-branch
249 const MachineInstrBuilder MIB =
250 BuildMI(&MBB, DL, get(Cond[1].getImm())).addReg(Cond[2].getReg());
252 MIB.addImm(Cond[3].getImm());
257 unsigned ARM64InstrInfo::InsertBranch(
258 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
259 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
260 // Shouldn't be a fall through.
261 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
264 if (Cond.empty()) // Unconditional branch?
265 BuildMI(&MBB, DL, get(ARM64::B)).addMBB(TBB);
267 instantiateCondBranch(MBB, DL, TBB, Cond);
271 // Two-way conditional branch.
272 instantiateCondBranch(MBB, DL, TBB, Cond);
273 BuildMI(&MBB, DL, get(ARM64::B)).addMBB(FBB);
277 // Find the original register that VReg is copied from.
278 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) {
279 while (TargetRegisterInfo::isVirtualRegister(VReg)) {
280 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
281 if (!DefMI->isFullCopy())
283 VReg = DefMI->getOperand(1).getReg();
288 // Determine if VReg is defined by an instruction that can be folded into a
289 // csel instruction. If so, return the folded opcode, and the replacement
291 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
292 unsigned *NewVReg = 0) {
293 VReg = removeCopies(MRI, VReg);
294 if (!TargetRegisterInfo::isVirtualRegister(VReg))
297 bool Is64Bit = ARM64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
298 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
300 unsigned SrcOpNum = 0;
301 switch (DefMI->getOpcode()) {
304 // if CPSR is used, do not fold.
305 if (DefMI->findRegisterDefOperandIdx(ARM64::CPSR, true) == -1)
307 // fall-through to ADDXri and ADDWri.
310 // add x, 1 -> csinc.
311 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 ||
312 DefMI->getOperand(3).getImm() != 0)
315 Opc = Is64Bit ? ARM64::CSINCXr : ARM64::CSINCWr;
319 case ARM64::ORNWrr: {
320 // not x -> csinv, represented as orn dst, xzr, src.
321 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
322 if (ZReg != ARM64::XZR && ZReg != ARM64::WZR)
325 Opc = Is64Bit ? ARM64::CSINVXr : ARM64::CSINVWr;
331 // if CPSR is used, do not fold.
332 if (DefMI->findRegisterDefOperandIdx(ARM64::CPSR, true) == -1)
334 // fall-through to SUBXrr and SUBWrr.
336 case ARM64::SUBWrr: {
337 // neg x -> csneg, represented as sub dst, xzr, src.
338 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
339 if (ZReg != ARM64::XZR && ZReg != ARM64::WZR)
342 Opc = Is64Bit ? ARM64::CSNEGXr : ARM64::CSNEGWr;
348 assert(Opc && SrcOpNum && "Missing parameters");
351 *NewVReg = DefMI->getOperand(SrcOpNum).getReg();
355 bool ARM64InstrInfo::canInsertSelect(
356 const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond,
357 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles,
358 int &FalseCycles) const {
359 // Check register classes.
360 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
361 const TargetRegisterClass *RC =
362 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
366 // Expanding cbz/tbz requires an extra cycle of latency on the condition.
367 unsigned ExtraCondLat = Cond.size() != 1;
369 // GPRs are handled by csel.
370 // FIXME: Fold in x+1, -x, and ~x when applicable.
371 if (ARM64::GPR64allRegClass.hasSubClassEq(RC) ||
372 ARM64::GPR32allRegClass.hasSubClassEq(RC)) {
373 // Single-cycle csel, csinc, csinv, and csneg.
374 CondCycles = 1 + ExtraCondLat;
375 TrueCycles = FalseCycles = 1;
376 if (canFoldIntoCSel(MRI, TrueReg))
378 else if (canFoldIntoCSel(MRI, FalseReg))
383 // Scalar floating point is handled by fcsel.
384 // FIXME: Form fabs, fmin, and fmax when applicable.
385 if (ARM64::FPR64RegClass.hasSubClassEq(RC) ||
386 ARM64::FPR32RegClass.hasSubClassEq(RC)) {
387 CondCycles = 5 + ExtraCondLat;
388 TrueCycles = FalseCycles = 2;
396 void ARM64InstrInfo::insertSelect(MachineBasicBlock &MBB,
397 MachineBasicBlock::iterator I, DebugLoc DL,
399 const SmallVectorImpl<MachineOperand> &Cond,
400 unsigned TrueReg, unsigned FalseReg) const {
401 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
403 // Parse the condition code, see parseCondBranch() above.
404 ARM64CC::CondCode CC;
405 switch (Cond.size()) {
407 llvm_unreachable("Unknown condition opcode in Cond");
409 CC = ARM64CC::CondCode(Cond[0].getImm());
411 case 3: { // cbz/cbnz
412 // We must insert a compare against 0.
414 switch (Cond[1].getImm()) {
416 llvm_unreachable("Unknown branch opcode in Cond");
434 unsigned SrcReg = Cond[2].getReg();
436 // cmp reg, #0 is actually subs xzr, reg, #0.
437 MRI.constrainRegClass(SrcReg, &ARM64::GPR64spRegClass);
438 BuildMI(MBB, I, DL, get(ARM64::SUBSXri), ARM64::XZR)
443 MRI.constrainRegClass(SrcReg, &ARM64::GPR32spRegClass);
444 BuildMI(MBB, I, DL, get(ARM64::SUBSWri), ARM64::WZR)
451 case 4: { // tbz/tbnz
452 // We must insert a tst instruction.
453 switch (Cond[1].getImm()) {
455 llvm_unreachable("Unknown branch opcode in Cond");
463 // cmp reg, #foo is actually ands xzr, reg, #1<<foo.
464 BuildMI(MBB, I, DL, get(ARM64::ANDSXri), ARM64::XZR)
465 .addReg(Cond[2].getReg())
466 .addImm(ARM64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 64));
472 const TargetRegisterClass *RC = 0;
473 bool TryFold = false;
474 if (MRI.constrainRegClass(DstReg, &ARM64::GPR64RegClass)) {
475 RC = &ARM64::GPR64RegClass;
478 } else if (MRI.constrainRegClass(DstReg, &ARM64::GPR32RegClass)) {
479 RC = &ARM64::GPR32RegClass;
482 } else if (MRI.constrainRegClass(DstReg, &ARM64::FPR64RegClass)) {
483 RC = &ARM64::FPR64RegClass;
484 Opc = ARM64::FCSELDrrr;
485 } else if (MRI.constrainRegClass(DstReg, &ARM64::FPR32RegClass)) {
486 RC = &ARM64::FPR32RegClass;
487 Opc = ARM64::FCSELSrrr;
489 assert(RC && "Unsupported regclass");
491 // Try folding simple instructions into the csel.
493 unsigned NewVReg = 0;
494 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg);
496 // The folded opcodes csinc, csinc and csneg apply the operation to
497 // FalseReg, so we need to invert the condition.
498 CC = ARM64CC::getInvertedCondCode(CC);
501 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg);
503 // Fold the operation. Leave any dead instructions for DCE to clean up.
507 // The extends the live range of NewVReg.
508 MRI.clearKillFlags(NewVReg);
512 // Pull all virtual register into the appropriate class.
513 MRI.constrainRegClass(TrueReg, RC);
514 MRI.constrainRegClass(FalseReg, RC);
517 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm(
521 bool ARM64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
522 unsigned &SrcReg, unsigned &DstReg,
523 unsigned &SubIdx) const {
524 switch (MI.getOpcode()) {
527 case ARM64::SBFMXri: // aka sxtw
528 case ARM64::UBFMXri: // aka uxtw
529 // Check for the 32 -> 64 bit extension case, these instructions can do
531 if (MI.getOperand(2).getImm() != 0 || MI.getOperand(3).getImm() != 31)
533 // This is a signed or unsigned 32 -> 64 bit extension.
534 SrcReg = MI.getOperand(1).getReg();
535 DstReg = MI.getOperand(0).getReg();
536 SubIdx = ARM64::sub_32;
541 /// analyzeCompare - For a comparison instruction, return the source registers
542 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
543 /// Return true if the comparison instruction can be analyzed.
544 bool ARM64InstrInfo::analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
545 unsigned &SrcReg2, int &CmpMask,
546 int &CmpValue) const {
547 switch (MI->getOpcode()) {
562 // Replace SUBSWrr with SUBWrr if CPSR is not used.
563 SrcReg = MI->getOperand(1).getReg();
564 SrcReg2 = MI->getOperand(2).getReg();
574 SrcReg = MI->getOperand(1).getReg();
577 CmpValue = MI->getOperand(2).getImm();
584 static bool UpdateOperandRegClass(MachineInstr *Instr) {
585 MachineBasicBlock *MBB = Instr->getParent();
586 assert(MBB && "Can't get MachineBasicBlock here");
587 MachineFunction *MF = MBB->getParent();
588 assert(MF && "Can't get MachineFunction here");
589 const TargetMachine *TM = &MF->getTarget();
590 const TargetInstrInfo *TII = TM->getInstrInfo();
591 const TargetRegisterInfo *TRI = TM->getRegisterInfo();
592 MachineRegisterInfo *MRI = &MF->getRegInfo();
594 for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx;
596 MachineOperand &MO = Instr->getOperand(OpIdx);
597 const TargetRegisterClass *OpRegCstraints =
598 Instr->getRegClassConstraint(OpIdx, TII, TRI);
600 // If there's no constraint, there's nothing to do.
603 // If the operand is a frame index, there's nothing to do here.
604 // A frame index operand will resolve correctly during PEI.
609 "Operand has register constraints without being a register!");
611 unsigned Reg = MO.getReg();
612 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
613 if (!OpRegCstraints->contains(Reg))
615 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
616 !MRI->constrainRegClass(Reg, OpRegCstraints))
623 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
624 /// comparison into one that sets the zero bit in the flags register.
625 bool ARM64InstrInfo::optimizeCompareInstr(
626 MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
627 int CmpValue, const MachineRegisterInfo *MRI) const {
629 // Replace SUBSWrr with SUBWrr if CPSR is not used.
630 int Cmp_CPSR = CmpInstr->findRegisterDefOperandIdx(ARM64::CPSR, true);
631 if (Cmp_CPSR != -1) {
633 switch (CmpInstr->getOpcode()) {
636 case ARM64::ADDSWrr: NewOpc = ARM64::ADDWrr; break;
637 case ARM64::ADDSWri: NewOpc = ARM64::ADDWri; break;
638 case ARM64::ADDSWrs: NewOpc = ARM64::ADDWrs; break;
639 case ARM64::ADDSWrx: NewOpc = ARM64::ADDWrx; break;
640 case ARM64::ADDSXrr: NewOpc = ARM64::ADDXrr; break;
641 case ARM64::ADDSXri: NewOpc = ARM64::ADDXri; break;
642 case ARM64::ADDSXrs: NewOpc = ARM64::ADDXrs; break;
643 case ARM64::ADDSXrx: NewOpc = ARM64::ADDXrx; break;
644 case ARM64::SUBSWrr: NewOpc = ARM64::SUBWrr; break;
645 case ARM64::SUBSWri: NewOpc = ARM64::SUBWri; break;
646 case ARM64::SUBSWrs: NewOpc = ARM64::SUBWrs; break;
647 case ARM64::SUBSWrx: NewOpc = ARM64::SUBWrx; break;
648 case ARM64::SUBSXrr: NewOpc = ARM64::SUBXrr; break;
649 case ARM64::SUBSXri: NewOpc = ARM64::SUBXri; break;
650 case ARM64::SUBSXrs: NewOpc = ARM64::SUBXrs; break;
651 case ARM64::SUBSXrx: NewOpc = ARM64::SUBXrx; break;
654 const MCInstrDesc &MCID = get(NewOpc);
655 CmpInstr->setDesc(MCID);
656 CmpInstr->RemoveOperand(Cmp_CPSR);
657 bool succeeded = UpdateOperandRegClass(CmpInstr);
659 assert(succeeded && "Some operands reg class are incompatible!");
663 // Continue only if we have a "ri" where immediate is zero.
664 if (CmpValue != 0 || SrcReg2 != 0)
667 // CmpInstr is a Compare instruction if destination register is not used.
668 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
671 // Get the unique definition of SrcReg.
672 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
676 // We iterate backward, starting from the instruction before CmpInstr and
677 // stop when reaching the definition of the source register or done with the
678 // basic block, to check whether CPSR is used or modified in between.
679 MachineBasicBlock::iterator I = CmpInstr, E = MI,
680 B = CmpInstr->getParent()->begin();
682 // Early exit if CmpInstr is at the beginning of the BB.
686 // Check whether the definition of SrcReg is in the same basic block as
687 // Compare. If not, we can't optimize away the Compare.
688 if (MI->getParent() != CmpInstr->getParent())
691 // Check that CPSR isn't set between the comparison instruction and the one we
693 const TargetRegisterInfo *TRI = &getRegisterInfo();
694 for (--I; I != E; --I) {
695 const MachineInstr &Instr = *I;
697 if (Instr.modifiesRegister(ARM64::CPSR, TRI) ||
698 Instr.readsRegister(ARM64::CPSR, TRI))
699 // This instruction modifies or uses CPSR after the one we want to
700 // change. We can't do this transformation.
703 // The 'and' is below the comparison instruction.
707 unsigned NewOpc = MI->getOpcode();
708 switch (MI->getOpcode()) {
720 case ARM64::ADDWrr: NewOpc = ARM64::ADDSWrr; break;
721 case ARM64::ADDWri: NewOpc = ARM64::ADDSWri; break;
722 case ARM64::ADDXrr: NewOpc = ARM64::ADDSXrr; break;
723 case ARM64::ADDXri: NewOpc = ARM64::ADDSXri; break;
724 case ARM64::ADCWr: NewOpc = ARM64::ADCSWr; break;
725 case ARM64::ADCXr: NewOpc = ARM64::ADCSXr; break;
726 case ARM64::SUBWrr: NewOpc = ARM64::SUBSWrr; break;
727 case ARM64::SUBWri: NewOpc = ARM64::SUBSWri; break;
728 case ARM64::SUBXrr: NewOpc = ARM64::SUBSXrr; break;
729 case ARM64::SUBXri: NewOpc = ARM64::SUBSXri; break;
730 case ARM64::SBCWr: NewOpc = ARM64::SBCSWr; break;
731 case ARM64::SBCXr: NewOpc = ARM64::SBCSXr; break;
732 case ARM64::ANDWri: NewOpc = ARM64::ANDSWri; break;
733 case ARM64::ANDXri: NewOpc = ARM64::ANDSXri; break;
736 // Scan forward for the use of CPSR.
737 // When checking against MI: if it's a conditional code requires
738 // checking of V bit, then this is not safe to do.
739 // It is safe to remove CmpInstr if CPSR is redefined or killed.
740 // If we are done with the basic block, we need to check whether CPSR is
743 for (MachineBasicBlock::iterator I = CmpInstr,
744 E = CmpInstr->getParent()->end();
745 !IsSafe && ++I != E;) {
746 const MachineInstr &Instr = *I;
747 for (unsigned IO = 0, EO = Instr.getNumOperands(); !IsSafe && IO != EO;
749 const MachineOperand &MO = Instr.getOperand(IO);
750 if (MO.isRegMask() && MO.clobbersPhysReg(ARM64::CPSR)) {
754 if (!MO.isReg() || MO.getReg() != ARM64::CPSR)
761 // Decode the condition code.
762 unsigned Opc = Instr.getOpcode();
763 ARM64CC::CondCode CC;
768 CC = (ARM64CC::CondCode)Instr.getOperand(IO - 2).getImm();
778 case ARM64::FCSELSrrr:
779 case ARM64::FCSELDrrr:
780 CC = (ARM64CC::CondCode)Instr.getOperand(IO - 1).getImm();
784 // It is not safe to remove Compare instruction if Overflow(V) is used.
787 // CPSR can be used multiple times, we should continue.
800 // If CPSR is not killed nor re-defined, we should check whether it is
801 // live-out. If it is live-out, do not optimize.
803 MachineBasicBlock *ParentBlock = CmpInstr->getParent();
804 for (auto *MBB : ParentBlock->successors())
805 if (MBB->isLiveIn(ARM64::CPSR))
809 // Update the instruction to set CPSR.
810 MI->setDesc(get(NewOpc));
811 CmpInstr->eraseFromParent();
812 bool succeeded = UpdateOperandRegClass(MI);
814 assert(succeeded && "Some operands reg class are incompatible!");
815 MI->addRegisterDefined(ARM64::CPSR, TRI);
819 // Return true if this instruction simply sets its single destination register
820 // to zero. This is equivalent to a register rename of the zero-register.
821 bool ARM64InstrInfo::isGPRZero(const MachineInstr *MI) const {
822 switch (MI->getOpcode()) {
826 case ARM64::MOVZXi: // movz Rd, #0 (LSL #0)
827 if (MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0) {
828 assert(MI->getDesc().getNumOperands() == 3 &&
829 MI->getOperand(2).getImm() == 0 && "invalid MOVZi operands");
833 case ARM64::ANDWri: // and Rd, Rzr, #imm
834 return MI->getOperand(1).getReg() == ARM64::WZR;
836 return MI->getOperand(1).getReg() == ARM64::XZR;
837 case TargetOpcode::COPY:
838 return MI->getOperand(1).getReg() == ARM64::WZR;
843 // Return true if this instruction simply renames a general register without
845 bool ARM64InstrInfo::isGPRCopy(const MachineInstr *MI) const {
846 switch (MI->getOpcode()) {
849 case TargetOpcode::COPY: {
850 // GPR32 copies will by lowered to ORRXrs
851 unsigned DstReg = MI->getOperand(0).getReg();
852 return (ARM64::GPR32RegClass.contains(DstReg) ||
853 ARM64::GPR64RegClass.contains(DstReg));
855 case ARM64::ORRXrs: // orr Xd, Xzr, Xm (LSL #0)
856 if (MI->getOperand(1).getReg() == ARM64::XZR) {
857 assert(MI->getDesc().getNumOperands() == 4 &&
858 MI->getOperand(3).getImm() == 0 && "invalid ORRrs operands");
861 case ARM64::ADDXri: // add Xd, Xn, #0 (LSL #0)
862 if (MI->getOperand(2).getImm() == 0) {
863 assert(MI->getDesc().getNumOperands() == 4 &&
864 MI->getOperand(3).getImm() == 0 && "invalid ADDXri operands");
871 // Return true if this instruction simply renames a general register without
873 bool ARM64InstrInfo::isFPRCopy(const MachineInstr *MI) const {
874 switch (MI->getOpcode()) {
877 case TargetOpcode::COPY: {
878 // FPR64 copies will by lowered to ORR.16b
879 unsigned DstReg = MI->getOperand(0).getReg();
880 return (ARM64::FPR64RegClass.contains(DstReg) ||
881 ARM64::FPR128RegClass.contains(DstReg));
883 case ARM64::ORRv16i8:
884 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
885 assert(MI->getDesc().getNumOperands() == 3 && MI->getOperand(0).isReg() &&
886 "invalid ORRv16i8 operands");
893 unsigned ARM64InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
894 int &FrameIndex) const {
895 switch (MI->getOpcode()) {
905 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() &&
906 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) {
907 FrameIndex = MI->getOperand(1).getIndex();
908 return MI->getOperand(0).getReg();
916 unsigned ARM64InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
917 int &FrameIndex) const {
918 switch (MI->getOpcode()) {
928 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() &&
929 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) {
930 FrameIndex = MI->getOperand(1).getIndex();
931 return MI->getOperand(0).getReg();
938 /// Return true if this is load/store scales or extends its register offset.
939 /// This refers to scaling a dynamic index as opposed to scaled immediates.
940 /// MI should be a memory op that allows scaled addressing.
941 bool ARM64InstrInfo::isScaledAddr(const MachineInstr *MI) const {
942 switch (MI->getOpcode()) {
951 case ARM64::LDRSBWro:
952 case ARM64::LDRSBXro:
953 case ARM64::LDRSHWro:
954 case ARM64::LDRSHXro:
968 unsigned Val = MI->getOperand(3).getImm();
969 ARM64_AM::ExtendType ExtType = ARM64_AM::getMemExtendType(Val);
970 return (ExtType != ARM64_AM::UXTX) || ARM64_AM::getMemDoShift(Val);
975 /// Check all MachineMemOperands for a hint to suppress pairing.
976 bool ARM64InstrInfo::isLdStPairSuppressed(const MachineInstr *MI) const {
977 assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
978 "Too many target MO flags");
979 for (auto *MM : MI->memoperands()) {
981 (MOSuppressPair << MachineMemOperand::MOTargetStartBit)) {
988 /// Set a flag on the first MachineMemOperand to suppress pairing.
989 void ARM64InstrInfo::suppressLdStPair(MachineInstr *MI) const {
990 if (MI->memoperands_empty())
993 assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
994 "Too many target MO flags");
995 (*MI->memoperands_begin())
996 ->setFlags(MOSuppressPair << MachineMemOperand::MOTargetStartBit);
999 bool ARM64InstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
1001 const TargetRegisterInfo *TRI) const {
1002 switch (LdSt->getOpcode()) {
1015 if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm())
1017 BaseReg = LdSt->getOperand(1).getReg();
1018 MachineFunction &MF = *LdSt->getParent()->getParent();
1019 unsigned Width = getRegClass(LdSt->getDesc(), 0, TRI, MF)->getSize();
1020 Offset = LdSt->getOperand(2).getImm() * Width;
1025 /// Detect opportunities for ldp/stp formation.
1027 /// Only called for LdSt for which getLdStBaseRegImmOfs returns true.
1028 bool ARM64InstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
1029 MachineInstr *SecondLdSt,
1030 unsigned NumLoads) const {
1031 // Only cluster up to a single pair.
1034 if (FirstLdSt->getOpcode() != SecondLdSt->getOpcode())
1036 // getLdStBaseRegImmOfs guarantees that oper 2 isImm.
1037 unsigned Ofs1 = FirstLdSt->getOperand(2).getImm();
1038 // Allow 6 bits of positive range.
1041 // The caller should already have ordered First/SecondLdSt by offset.
1042 unsigned Ofs2 = SecondLdSt->getOperand(2).getImm();
1043 return Ofs1 + 1 == Ofs2;
1046 bool ARM64InstrInfo::shouldScheduleAdjacent(MachineInstr *First,
1047 MachineInstr *Second) const {
1048 // Cyclone can fuse CMN, CMP followed by Bcc.
1050 // FIXME: B0 can also fuse:
1051 // AND, BIC, ORN, ORR, or EOR (optional S) followed by Bcc or CBZ or CBNZ.
1052 if (Second->getOpcode() != ARM64::Bcc)
1054 switch (First->getOpcode()) {
1057 case ARM64::SUBSWri:
1058 case ARM64::ADDSWri:
1059 case ARM64::ANDSWri:
1060 case ARM64::SUBSXri:
1061 case ARM64::ADDSXri:
1062 case ARM64::ANDSXri:
1067 MachineInstr *ARM64InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1070 const MDNode *MDPtr,
1071 DebugLoc DL) const {
1072 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM64::DBG_VALUE))
1073 .addFrameIndex(FrameIx)
1076 .addMetadata(MDPtr);
1080 static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
1081 unsigned Reg, unsigned SubIdx,
1083 const TargetRegisterInfo *TRI) {
1085 return MIB.addReg(Reg, State);
1087 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1088 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1089 return MIB.addReg(Reg, State, SubIdx);
1092 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg,
1094 // We really want the positive remainder mod 32 here, that happens to be
1095 // easily obtainable with a mask.
1096 return ((DestReg - SrcReg) & 0x1f) < NumRegs;
1099 void ARM64InstrInfo::copyPhysRegTuple(MachineBasicBlock &MBB,
1100 MachineBasicBlock::iterator I,
1101 DebugLoc DL, unsigned DestReg,
1102 unsigned SrcReg, bool KillSrc,
1104 llvm::ArrayRef<unsigned> Indices) const {
1105 const TargetRegisterInfo *TRI = &getRegisterInfo();
1106 uint16_t DestEncoding = TRI->getEncodingValue(DestReg);
1107 uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg);
1108 unsigned NumRegs = Indices.size();
1110 int SubReg = 0, End = NumRegs, Incr = 1;
1111 if (forwardCopyWillClobberTuple(DestEncoding, SrcEncoding, NumRegs)) {
1112 SubReg = NumRegs - 1;
1117 for (; SubReg != End; SubReg += Incr) {
1118 const MachineInstrBuilder &MIB = BuildMI(MBB, I, DL, get(Opcode));
1119 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
1120 AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI);
1121 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
1125 void ARM64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1126 MachineBasicBlock::iterator I, DebugLoc DL,
1127 unsigned DestReg, unsigned SrcReg,
1128 bool KillSrc) const {
1129 if (ARM64::GPR32spRegClass.contains(DestReg) &&
1130 (ARM64::GPR32spRegClass.contains(SrcReg) || SrcReg == ARM64::WZR)) {
1131 const TargetRegisterInfo *TRI = &getRegisterInfo();
1133 if (DestReg == ARM64::WSP || SrcReg == ARM64::WSP) {
1134 // If either operand is WSP, expand to ADD #0.
1135 if (Subtarget.hasZeroCycleRegMove()) {
1136 // Cyclone recognizes "ADD Xd, Xn, #0" as a zero-cycle register move.
1137 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, ARM64::sub_32,
1138 &ARM64::GPR64spRegClass);
1139 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, ARM64::sub_32,
1140 &ARM64::GPR64spRegClass);
1141 // This instruction is reading and writing X registers. This may upset
1142 // the register scavenger and machine verifier, so we need to indicate
1143 // that we are reading an undefined value from SrcRegX, but a proper
1144 // value from SrcReg.
1145 BuildMI(MBB, I, DL, get(ARM64::ADDXri), DestRegX)
1146 .addReg(SrcRegX, RegState::Undef)
1148 .addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, 0))
1149 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1151 BuildMI(MBB, I, DL, get(ARM64::ADDWri), DestReg)
1152 .addReg(SrcReg, getKillRegState(KillSrc))
1154 .addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, 0));
1156 } else if (SrcReg == ARM64::WZR && Subtarget.hasZeroCycleZeroing()) {
1157 BuildMI(MBB, I, DL, get(ARM64::MOVZWi), DestReg).addImm(0).addImm(
1158 ARM64_AM::getShifterImm(ARM64_AM::LSL, 0));
1160 if (Subtarget.hasZeroCycleRegMove()) {
1161 // Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
1162 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, ARM64::sub_32,
1163 &ARM64::GPR64spRegClass);
1164 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, ARM64::sub_32,
1165 &ARM64::GPR64spRegClass);
1166 // This instruction is reading and writing X registers. This may upset
1167 // the register scavenger and machine verifier, so we need to indicate
1168 // that we are reading an undefined value from SrcRegX, but a proper
1169 // value from SrcReg.
1170 BuildMI(MBB, I, DL, get(ARM64::ORRXrr), DestRegX)
1172 .addReg(SrcRegX, RegState::Undef)
1173 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1175 // Otherwise, expand to ORR WZR.
1176 BuildMI(MBB, I, DL, get(ARM64::ORRWrr), DestReg)
1178 .addReg(SrcReg, getKillRegState(KillSrc));
1184 if (ARM64::GPR64spRegClass.contains(DestReg) &&
1185 (ARM64::GPR64spRegClass.contains(SrcReg) || SrcReg == ARM64::XZR)) {
1186 if (DestReg == ARM64::SP || SrcReg == ARM64::SP) {
1187 // If either operand is SP, expand to ADD #0.
1188 BuildMI(MBB, I, DL, get(ARM64::ADDXri), DestReg)
1189 .addReg(SrcReg, getKillRegState(KillSrc))
1191 .addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, 0));
1192 } else if (SrcReg == ARM64::XZR && Subtarget.hasZeroCycleZeroing()) {
1193 BuildMI(MBB, I, DL, get(ARM64::MOVZXi), DestReg).addImm(0).addImm(
1194 ARM64_AM::getShifterImm(ARM64_AM::LSL, 0));
1196 // Otherwise, expand to ORR XZR.
1197 BuildMI(MBB, I, DL, get(ARM64::ORRXrr), DestReg)
1199 .addReg(SrcReg, getKillRegState(KillSrc));
1204 // Copy a DDDD register quad by copying the individual sub-registers.
1205 if (ARM64::DDDDRegClass.contains(DestReg) &&
1206 ARM64::DDDDRegClass.contains(SrcReg)) {
1207 static const unsigned Indices[] = { ARM64::dsub0, ARM64::dsub1,
1208 ARM64::dsub2, ARM64::dsub3 };
1209 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, ARM64::ORRv8i8,
1214 // Copy a DDD register triple by copying the individual sub-registers.
1215 if (ARM64::DDDRegClass.contains(DestReg) &&
1216 ARM64::DDDRegClass.contains(SrcReg)) {
1217 static const unsigned Indices[] = { ARM64::dsub0, ARM64::dsub1,
1219 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, ARM64::ORRv8i8,
1224 // Copy a DD register pair by copying the individual sub-registers.
1225 if (ARM64::DDRegClass.contains(DestReg) &&
1226 ARM64::DDRegClass.contains(SrcReg)) {
1227 static const unsigned Indices[] = { ARM64::dsub0, ARM64::dsub1 };
1228 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, ARM64::ORRv8i8,
1233 // Copy a QQQQ register quad by copying the individual sub-registers.
1234 if (ARM64::QQQQRegClass.contains(DestReg) &&
1235 ARM64::QQQQRegClass.contains(SrcReg)) {
1236 static const unsigned Indices[] = { ARM64::qsub0, ARM64::qsub1,
1237 ARM64::qsub2, ARM64::qsub3 };
1238 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, ARM64::ORRv16i8,
1243 // Copy a QQQ register triple by copying the individual sub-registers.
1244 if (ARM64::QQQRegClass.contains(DestReg) &&
1245 ARM64::QQQRegClass.contains(SrcReg)) {
1246 static const unsigned Indices[] = { ARM64::qsub0, ARM64::qsub1,
1248 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, ARM64::ORRv16i8,
1253 // Copy a QQ register pair by copying the individual sub-registers.
1254 if (ARM64::QQRegClass.contains(DestReg) &&
1255 ARM64::QQRegClass.contains(SrcReg)) {
1256 static const unsigned Indices[] = { ARM64::qsub0, ARM64::qsub1 };
1257 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, ARM64::ORRv16i8,
1262 if (ARM64::FPR128RegClass.contains(DestReg) &&
1263 ARM64::FPR128RegClass.contains(SrcReg)) {
1264 BuildMI(MBB, I, DL, get(ARM64::ORRv16i8), DestReg).addReg(SrcReg).addReg(
1265 SrcReg, getKillRegState(KillSrc));
1269 if (ARM64::FPR64RegClass.contains(DestReg) &&
1270 ARM64::FPR64RegClass.contains(SrcReg)) {
1272 RI.getMatchingSuperReg(DestReg, ARM64::dsub, &ARM64::FPR128RegClass);
1274 RI.getMatchingSuperReg(SrcReg, ARM64::dsub, &ARM64::FPR128RegClass);
1275 BuildMI(MBB, I, DL, get(ARM64::ORRv16i8), DestReg).addReg(SrcReg).addReg(
1276 SrcReg, getKillRegState(KillSrc));
1280 if (ARM64::FPR32RegClass.contains(DestReg) &&
1281 ARM64::FPR32RegClass.contains(SrcReg)) {
1283 RI.getMatchingSuperReg(DestReg, ARM64::ssub, &ARM64::FPR128RegClass);
1285 RI.getMatchingSuperReg(SrcReg, ARM64::ssub, &ARM64::FPR128RegClass);
1286 BuildMI(MBB, I, DL, get(ARM64::ORRv16i8), DestReg).addReg(SrcReg).addReg(
1287 SrcReg, getKillRegState(KillSrc));
1291 if (ARM64::FPR16RegClass.contains(DestReg) &&
1292 ARM64::FPR16RegClass.contains(SrcReg)) {
1294 RI.getMatchingSuperReg(DestReg, ARM64::hsub, &ARM64::FPR128RegClass);
1296 RI.getMatchingSuperReg(SrcReg, ARM64::hsub, &ARM64::FPR128RegClass);
1297 BuildMI(MBB, I, DL, get(ARM64::ORRv16i8), DestReg).addReg(SrcReg).addReg(
1298 SrcReg, getKillRegState(KillSrc));
1302 if (ARM64::FPR8RegClass.contains(DestReg) &&
1303 ARM64::FPR8RegClass.contains(SrcReg)) {
1305 RI.getMatchingSuperReg(DestReg, ARM64::bsub, &ARM64::FPR128RegClass);
1307 RI.getMatchingSuperReg(SrcReg, ARM64::bsub, &ARM64::FPR128RegClass);
1308 BuildMI(MBB, I, DL, get(ARM64::ORRv16i8), DestReg).addReg(SrcReg).addReg(
1309 SrcReg, getKillRegState(KillSrc));
1313 // Copies between GPR64 and FPR64.
1314 if (ARM64::FPR64RegClass.contains(DestReg) &&
1315 ARM64::GPR64RegClass.contains(SrcReg)) {
1316 BuildMI(MBB, I, DL, get(ARM64::FMOVXDr), DestReg)
1317 .addReg(SrcReg, getKillRegState(KillSrc));
1320 if (ARM64::GPR64RegClass.contains(DestReg) &&
1321 ARM64::FPR64RegClass.contains(SrcReg)) {
1322 BuildMI(MBB, I, DL, get(ARM64::FMOVDXr), DestReg)
1323 .addReg(SrcReg, getKillRegState(KillSrc));
1326 // Copies between GPR32 and FPR32.
1327 if (ARM64::FPR32RegClass.contains(DestReg) &&
1328 ARM64::GPR32RegClass.contains(SrcReg)) {
1329 BuildMI(MBB, I, DL, get(ARM64::FMOVWSr), DestReg)
1330 .addReg(SrcReg, getKillRegState(KillSrc));
1333 if (ARM64::GPR32RegClass.contains(DestReg) &&
1334 ARM64::FPR32RegClass.contains(SrcReg)) {
1335 BuildMI(MBB, I, DL, get(ARM64::FMOVSWr), DestReg)
1336 .addReg(SrcReg, getKillRegState(KillSrc));
1340 assert(0 && "unimplemented reg-to-reg copy");
1343 void ARM64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1344 MachineBasicBlock::iterator MBBI,
1345 unsigned SrcReg, bool isKill, int FI,
1346 const TargetRegisterClass *RC,
1347 const TargetRegisterInfo *TRI) const {
1349 if (MBBI != MBB.end())
1350 DL = MBBI->getDebugLoc();
1351 MachineFunction &MF = *MBB.getParent();
1352 MachineFrameInfo &MFI = *MF.getFrameInfo();
1353 unsigned Align = MFI.getObjectAlignment(FI);
1355 MachinePointerInfo PtrInfo(PseudoSourceValue::getFixedStack(FI));
1356 MachineMemOperand *MMO = MF.getMachineMemOperand(
1357 PtrInfo, MachineMemOperand::MOStore, MFI.getObjectSize(FI), Align);
1360 switch (RC->getSize()) {
1362 if (ARM64::FPR8RegClass.hasSubClassEq(RC))
1363 Opc = ARM64::STRBui;
1366 if (ARM64::FPR16RegClass.hasSubClassEq(RC))
1367 Opc = ARM64::STRHui;
1370 if (ARM64::GPR32allRegClass.hasSubClassEq(RC)) {
1371 Opc = ARM64::STRWui;
1372 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
1373 MF.getRegInfo().constrainRegClass(SrcReg, &ARM64::GPR32RegClass);
1375 assert(SrcReg != ARM64::WSP);
1376 } else if (ARM64::FPR32RegClass.hasSubClassEq(RC))
1377 Opc = ARM64::STRSui;
1380 if (ARM64::GPR64allRegClass.hasSubClassEq(RC)) {
1381 Opc = ARM64::STRXui;
1382 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
1383 MF.getRegInfo().constrainRegClass(SrcReg, &ARM64::GPR64RegClass);
1385 assert(SrcReg != ARM64::SP);
1386 } else if (ARM64::FPR64RegClass.hasSubClassEq(RC))
1387 Opc = ARM64::STRDui;
1390 if (ARM64::FPR128RegClass.hasSubClassEq(RC))
1391 Opc = ARM64::STRQui;
1392 else if (ARM64::DDRegClass.hasSubClassEq(RC))
1393 Opc = ARM64::ST1Twov1d, Offset = false;
1396 if (ARM64::DDDRegClass.hasSubClassEq(RC))
1397 Opc = ARM64::ST1Threev1d, Offset = false;
1400 if (ARM64::DDDDRegClass.hasSubClassEq(RC))
1401 Opc = ARM64::ST1Fourv1d, Offset = false;
1402 else if (ARM64::QQRegClass.hasSubClassEq(RC))
1403 Opc = ARM64::ST1Twov2d, Offset = false;
1406 if (ARM64::QQQRegClass.hasSubClassEq(RC))
1407 Opc = ARM64::ST1Threev2d, Offset = false;
1410 if (ARM64::QQQQRegClass.hasSubClassEq(RC))
1411 Opc = ARM64::ST1Fourv2d, Offset = false;
1414 assert(Opc && "Unknown register class");
1416 const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc))
1417 .addReg(SrcReg, getKillRegState(isKill))
1422 MI.addMemOperand(MMO);
1425 void ARM64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1426 MachineBasicBlock::iterator MBBI,
1427 unsigned DestReg, int FI,
1428 const TargetRegisterClass *RC,
1429 const TargetRegisterInfo *TRI) const {
1431 if (MBBI != MBB.end())
1432 DL = MBBI->getDebugLoc();
1433 MachineFunction &MF = *MBB.getParent();
1434 MachineFrameInfo &MFI = *MF.getFrameInfo();
1435 unsigned Align = MFI.getObjectAlignment(FI);
1436 MachinePointerInfo PtrInfo(PseudoSourceValue::getFixedStack(FI));
1437 MachineMemOperand *MMO = MF.getMachineMemOperand(
1438 PtrInfo, MachineMemOperand::MOLoad, MFI.getObjectSize(FI), Align);
1442 switch (RC->getSize()) {
1444 if (ARM64::FPR8RegClass.hasSubClassEq(RC))
1445 Opc = ARM64::LDRBui;
1448 if (ARM64::FPR16RegClass.hasSubClassEq(RC))
1449 Opc = ARM64::LDRHui;
1452 if (ARM64::GPR32allRegClass.hasSubClassEq(RC)) {
1453 Opc = ARM64::LDRWui;
1454 if (TargetRegisterInfo::isVirtualRegister(DestReg))
1455 MF.getRegInfo().constrainRegClass(DestReg, &ARM64::GPR32RegClass);
1457 assert(DestReg != ARM64::WSP);
1458 } else if (ARM64::FPR32RegClass.hasSubClassEq(RC))
1459 Opc = ARM64::LDRSui;
1462 if (ARM64::GPR64allRegClass.hasSubClassEq(RC)) {
1463 Opc = ARM64::LDRXui;
1464 if (TargetRegisterInfo::isVirtualRegister(DestReg))
1465 MF.getRegInfo().constrainRegClass(DestReg, &ARM64::GPR64RegClass);
1467 assert(DestReg != ARM64::SP);
1468 } else if (ARM64::FPR64RegClass.hasSubClassEq(RC))
1469 Opc = ARM64::LDRDui;
1472 if (ARM64::FPR128RegClass.hasSubClassEq(RC))
1473 Opc = ARM64::LDRQui;
1474 else if (ARM64::DDRegClass.hasSubClassEq(RC))
1475 Opc = ARM64::LD1Twov1d, Offset = false;
1478 if (ARM64::DDDRegClass.hasSubClassEq(RC))
1479 Opc = ARM64::LD1Threev1d, Offset = false;
1482 if (ARM64::DDDDRegClass.hasSubClassEq(RC))
1483 Opc = ARM64::LD1Fourv1d, Offset = false;
1484 else if (ARM64::QQRegClass.hasSubClassEq(RC))
1485 Opc = ARM64::LD1Twov2d, Offset = false;
1488 if (ARM64::QQQRegClass.hasSubClassEq(RC))
1489 Opc = ARM64::LD1Threev2d, Offset = false;
1492 if (ARM64::QQQQRegClass.hasSubClassEq(RC))
1493 Opc = ARM64::LD1Fourv2d, Offset = false;
1496 assert(Opc && "Unknown register class");
1498 const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc))
1499 .addReg(DestReg, getDefRegState(true))
1503 MI.addMemOperand(MMO);
1506 void llvm::emitFrameOffset(MachineBasicBlock &MBB,
1507 MachineBasicBlock::iterator MBBI, DebugLoc DL,
1508 unsigned DestReg, unsigned SrcReg, int Offset,
1509 const ARM64InstrInfo *TII, MachineInstr::MIFlag Flag,
1511 if (DestReg == SrcReg && Offset == 0)
1514 bool isSub = Offset < 0;
1518 // FIXME: If the offset won't fit in 24-bits, compute the offset into a
1519 // scratch register. If DestReg is a virtual register, use it as the
1520 // scratch register; otherwise, create a new virtual register (to be
1521 // replaced by the scavenger at the end of PEI). That case can be optimized
1522 // slightly if DestReg is SP which is always 16-byte aligned, so the scratch
1523 // register can be loaded with offset%8 and the add/sub can use an extending
1524 // instruction with LSL#3.
1525 // Currently the function handles any offsets but generates a poor sequence
1527 // assert(Offset < (1 << 24) && "unimplemented reg plus immediate");
1531 Opc = isSub ? ARM64::SUBSXri : ARM64::ADDSXri;
1533 Opc = isSub ? ARM64::SUBXri : ARM64::ADDXri;
1534 const unsigned MaxEncoding = 0xfff;
1535 const unsigned ShiftSize = 12;
1536 const unsigned MaxEncodableValue = MaxEncoding << ShiftSize;
1537 while (((unsigned)Offset) >= (1 << ShiftSize)) {
1539 if (((unsigned)Offset) > MaxEncodableValue) {
1540 ThisVal = MaxEncodableValue;
1542 ThisVal = Offset & MaxEncodableValue;
1544 assert((ThisVal >> ShiftSize) <= MaxEncoding &&
1545 "Encoding cannot handle value that big");
1546 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
1548 .addImm(ThisVal >> ShiftSize)
1549 .addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, ShiftSize))
1557 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
1560 .addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, 0))
1565 ARM64InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
1566 const SmallVectorImpl<unsigned> &Ops,
1567 int FrameIndex) const {
1568 // This is a bit of a hack. Consider this instruction:
1570 // %vreg0<def> = COPY %SP; GPR64all:%vreg0
1572 // We explicitly chose GPR64all for the virtual register so such a copy might
1573 // be eliminated by RegisterCoalescer. However, that may not be possible, and
1574 // %vreg0 may even spill. We can't spill %SP, and since it is in the GPR64all
1575 // register class, TargetInstrInfo::foldMemoryOperand() is going to try.
1577 // To prevent that, we are going to constrain the %vreg0 register class here.
1579 // <rdar://problem/11522048>
1582 unsigned DstReg = MI->getOperand(0).getReg();
1583 unsigned SrcReg = MI->getOperand(1).getReg();
1584 if (SrcReg == ARM64::SP && TargetRegisterInfo::isVirtualRegister(DstReg)) {
1585 MF.getRegInfo().constrainRegClass(DstReg, &ARM64::GPR64RegClass);
1588 if (DstReg == ARM64::SP && TargetRegisterInfo::isVirtualRegister(SrcReg)) {
1589 MF.getRegInfo().constrainRegClass(SrcReg, &ARM64::GPR64RegClass);
1598 int llvm::isARM64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
1599 bool *OutUseUnscaledOp,
1600 unsigned *OutUnscaledOp,
1601 int *EmittableOffset) {
1603 bool IsSigned = false;
1604 // The ImmIdx should be changed case by case if it is not 2.
1605 unsigned ImmIdx = 2;
1606 unsigned UnscaledOp = 0;
1607 // Set output values in case of early exit.
1608 if (EmittableOffset)
1609 *EmittableOffset = 0;
1610 if (OutUseUnscaledOp)
1611 *OutUseUnscaledOp = false;
1614 switch (MI.getOpcode()) {
1616 assert(0 && "unhandled opcode in rewriteARM64FrameIndex");
1617 // Vector spills/fills can't take an immediate offset.
1618 case ARM64::LD1Twov2d:
1619 case ARM64::LD1Threev2d:
1620 case ARM64::LD1Fourv2d:
1621 case ARM64::LD1Twov1d:
1622 case ARM64::LD1Threev1d:
1623 case ARM64::LD1Fourv1d:
1624 case ARM64::ST1Twov2d:
1625 case ARM64::ST1Threev2d:
1626 case ARM64::ST1Fourv2d:
1627 case ARM64::ST1Twov1d:
1628 case ARM64::ST1Threev1d:
1629 case ARM64::ST1Fourv1d:
1630 return ARM64FrameOffsetCannotUpdate;
1633 UnscaledOp = ARM64::PRFUMi;
1637 UnscaledOp = ARM64::LDURXi;
1641 UnscaledOp = ARM64::LDURWi;
1645 UnscaledOp = ARM64::LDURBi;
1649 UnscaledOp = ARM64::LDURHi;
1653 UnscaledOp = ARM64::LDURSi;
1657 UnscaledOp = ARM64::LDURDi;
1661 UnscaledOp = ARM64::LDURQi;
1663 case ARM64::LDRBBui:
1665 UnscaledOp = ARM64::LDURBBi;
1667 case ARM64::LDRHHui:
1669 UnscaledOp = ARM64::LDURHHi;
1671 case ARM64::LDRSBXui:
1673 UnscaledOp = ARM64::LDURSBXi;
1675 case ARM64::LDRSBWui:
1677 UnscaledOp = ARM64::LDURSBWi;
1679 case ARM64::LDRSHXui:
1681 UnscaledOp = ARM64::LDURSHXi;
1683 case ARM64::LDRSHWui:
1685 UnscaledOp = ARM64::LDURSHWi;
1687 case ARM64::LDRSWui:
1689 UnscaledOp = ARM64::LDURSWi;
1694 UnscaledOp = ARM64::STURXi;
1698 UnscaledOp = ARM64::STURWi;
1702 UnscaledOp = ARM64::STURBi;
1706 UnscaledOp = ARM64::STURHi;
1710 UnscaledOp = ARM64::STURSi;
1714 UnscaledOp = ARM64::STURDi;
1718 UnscaledOp = ARM64::STURQi;
1720 case ARM64::STRBBui:
1722 UnscaledOp = ARM64::STURBBi;
1724 case ARM64::STRHHui:
1726 UnscaledOp = ARM64::STURHHi;
1756 case ARM64::LDURHHi:
1757 case ARM64::LDURBBi:
1758 case ARM64::LDURSBXi:
1759 case ARM64::LDURSBWi:
1760 case ARM64::LDURSHXi:
1761 case ARM64::LDURSHWi:
1762 case ARM64::LDURSWi:
1770 case ARM64::STURBBi:
1771 case ARM64::STURHHi:
1776 Offset += MI.getOperand(ImmIdx).getImm() * Scale;
1778 bool useUnscaledOp = false;
1779 // If the offset doesn't match the scale, we rewrite the instruction to
1780 // use the unscaled instruction instead. Likewise, if we have a negative
1781 // offset (and have an unscaled op to use).
1782 if ((Offset & (Scale - 1)) != 0 || (Offset < 0 && UnscaledOp != 0))
1783 useUnscaledOp = true;
1785 // Use an unscaled addressing mode if the instruction has a negative offset
1786 // (or if the instruction is already using an unscaled addressing mode).
1789 // ldp/stp instructions.
1792 } else if (UnscaledOp == 0 || useUnscaledOp) {
1802 // Attempt to fold address computation.
1803 int MaxOff = (1 << (MaskBits - IsSigned)) - 1;
1804 int MinOff = (IsSigned ? (-MaxOff - 1) : 0);
1805 if (Offset >= MinOff && Offset <= MaxOff) {
1806 if (EmittableOffset)
1807 *EmittableOffset = Offset;
1810 int NewOff = Offset < 0 ? MinOff : MaxOff;
1811 if (EmittableOffset)
1812 *EmittableOffset = NewOff;
1813 Offset = (Offset - NewOff) * Scale;
1815 if (OutUseUnscaledOp)
1816 *OutUseUnscaledOp = useUnscaledOp;
1818 *OutUnscaledOp = UnscaledOp;
1819 return ARM64FrameOffsetCanUpdate |
1820 (Offset == 0 ? ARM64FrameOffsetIsLegal : 0);
1823 bool llvm::rewriteARM64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1824 unsigned FrameReg, int &Offset,
1825 const ARM64InstrInfo *TII) {
1826 unsigned Opcode = MI.getOpcode();
1827 unsigned ImmIdx = FrameRegIdx + 1;
1829 if (Opcode == ARM64::ADDSXri || Opcode == ARM64::ADDXri) {
1830 Offset += MI.getOperand(ImmIdx).getImm();
1831 emitFrameOffset(*MI.getParent(), MI, MI.getDebugLoc(),
1832 MI.getOperand(0).getReg(), FrameReg, Offset, TII,
1833 MachineInstr::NoFlags, (Opcode == ARM64::ADDSXri));
1834 MI.eraseFromParent();
1840 unsigned UnscaledOp;
1842 int Status = isARM64FrameOffsetLegal(MI, Offset, &UseUnscaledOp, &UnscaledOp,
1844 if (Status & ARM64FrameOffsetCanUpdate) {
1845 if (Status & ARM64FrameOffsetIsLegal)
1846 // Replace the FrameIndex with FrameReg.
1847 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1849 MI.setDesc(TII->get(UnscaledOp));
1851 MI.getOperand(ImmIdx).ChangeToImmediate(NewOffset);
1858 void ARM64InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
1859 NopInst.setOpcode(ARM64::HINT);
1860 NopInst.addOperand(MCOperand::CreateImm(0));