1 //===- ARM64InstrInfo.cpp - ARM64 Instruction Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARM64InstrInfo.h"
15 #include "ARM64Subtarget.h"
16 #include "MCTargetDesc/ARM64AddressingModes.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineMemOperand.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/CodeGen/PseudoSourceValue.h"
22 #include "llvm/MC/MCInst.h"
23 #include "llvm/Support/ErrorHandling.h"
24 #include "llvm/Support/TargetRegistry.h"
26 #define GET_INSTRINFO_CTOR_DTOR
27 #include "ARM64GenInstrInfo.inc"
31 ARM64InstrInfo::ARM64InstrInfo(const ARM64Subtarget &STI)
32 : ARM64GenInstrInfo(ARM64::ADJCALLSTACKDOWN, ARM64::ADJCALLSTACKUP),
33 RI(this, &STI), Subtarget(STI) {}
35 /// GetInstSize - Return the number of bytes of code the specified
36 /// instruction may be. This returns the maximum number of bytes.
37 unsigned ARM64InstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
38 const MCInstrDesc &Desc = MI->getDesc();
40 switch (Desc.getOpcode()) {
42 // Anything not explicitly designated otherwise is a nomal 4-byte insn.
44 case TargetOpcode::DBG_VALUE:
45 case TargetOpcode::EH_LABEL:
46 case TargetOpcode::IMPLICIT_DEF:
47 case TargetOpcode::KILL:
51 llvm_unreachable("GetInstSizeInBytes()- Unable to determin insn size");
54 static void parseCondBranch(MachineInstr *LastInst, MachineBasicBlock *&Target,
55 SmallVectorImpl<MachineOperand> &Cond) {
56 // Block ends with fall-through condbranch.
57 switch (LastInst->getOpcode()) {
59 llvm_unreachable("Unknown branch instruction?");
61 Target = LastInst->getOperand(1).getMBB();
62 Cond.push_back(LastInst->getOperand(0));
68 Target = LastInst->getOperand(1).getMBB();
69 Cond.push_back(MachineOperand::CreateImm(-1));
70 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
71 Cond.push_back(LastInst->getOperand(0));
75 Target = LastInst->getOperand(2).getMBB();
76 Cond.push_back(MachineOperand::CreateImm(-1));
77 Cond.push_back(MachineOperand::CreateImm(LastInst->getOpcode()));
78 Cond.push_back(LastInst->getOperand(0));
79 Cond.push_back(LastInst->getOperand(1));
84 bool ARM64InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
85 MachineBasicBlock *&TBB,
86 MachineBasicBlock *&FBB,
87 SmallVectorImpl<MachineOperand> &Cond,
88 bool AllowModify) const {
89 // If the block has no terminators, it just falls into the block after it.
90 MachineBasicBlock::iterator I = MBB.end();
94 while (I->isDebugValue()) {
99 if (!isUnpredicatedTerminator(I))
102 // Get the last instruction in the block.
103 MachineInstr *LastInst = I;
105 // If there is only one terminator instruction, process it.
106 unsigned LastOpc = LastInst->getOpcode();
107 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
108 if (isUncondBranchOpcode(LastOpc)) {
109 TBB = LastInst->getOperand(0).getMBB();
112 if (isCondBranchOpcode(LastOpc)) {
113 // Block ends with fall-through condbranch.
114 parseCondBranch(LastInst, TBB, Cond);
117 return true; // Can't handle indirect branch.
120 // Get the instruction before it if it is a terminator.
121 MachineInstr *SecondLastInst = I;
122 unsigned SecondLastOpc = SecondLastInst->getOpcode();
124 // If AllowModify is true and the block ends with two or more unconditional
125 // branches, delete all but the first unconditional branch.
126 if (AllowModify && isUncondBranchOpcode(LastOpc)) {
127 while (isUncondBranchOpcode(SecondLastOpc)) {
128 LastInst->eraseFromParent();
129 LastInst = SecondLastInst;
130 LastOpc = LastInst->getOpcode();
131 if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
132 // Return now the only terminator is an unconditional branch.
133 TBB = LastInst->getOperand(0).getMBB();
137 SecondLastOpc = SecondLastInst->getOpcode();
142 // If there are three terminators, we don't know what sort of block this is.
143 if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
146 // If the block ends with a B and a Bcc, handle it.
147 if (isCondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
148 parseCondBranch(SecondLastInst, TBB, Cond);
149 FBB = LastInst->getOperand(0).getMBB();
153 // If the block ends with two unconditional branches, handle it. The second
154 // one is not executed, so remove it.
155 if (isUncondBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
156 TBB = SecondLastInst->getOperand(0).getMBB();
159 I->eraseFromParent();
163 // ...likewise if it ends with an indirect branch followed by an unconditional
165 if (isIndirectBranchOpcode(SecondLastOpc) && isUncondBranchOpcode(LastOpc)) {
168 I->eraseFromParent();
172 // Otherwise, can't handle this.
176 bool ARM64InstrInfo::ReverseBranchCondition(
177 SmallVectorImpl<MachineOperand> &Cond) const {
178 if (Cond[0].getImm() != -1) {
180 ARM64CC::CondCode CC = (ARM64CC::CondCode)(int)Cond[0].getImm();
181 Cond[0].setImm(ARM64CC::getInvertedCondCode(CC));
183 // Folded compare-and-branch
184 switch (Cond[1].getImm()) {
186 llvm_unreachable("Unknown conditional branch!");
188 Cond[1].setImm(ARM64::CBNZW);
191 Cond[1].setImm(ARM64::CBZW);
194 Cond[1].setImm(ARM64::CBNZX);
197 Cond[1].setImm(ARM64::CBZX);
200 Cond[1].setImm(ARM64::TBNZ);
203 Cond[1].setImm(ARM64::TBZ);
211 unsigned ARM64InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
212 MachineBasicBlock::iterator I = MBB.end();
213 if (I == MBB.begin())
216 while (I->isDebugValue()) {
217 if (I == MBB.begin())
221 if (!isUncondBranchOpcode(I->getOpcode()) &&
222 !isCondBranchOpcode(I->getOpcode()))
225 // Remove the branch.
226 I->eraseFromParent();
230 if (I == MBB.begin())
233 if (!isCondBranchOpcode(I->getOpcode()))
236 // Remove the branch.
237 I->eraseFromParent();
241 void ARM64InstrInfo::instantiateCondBranch(
242 MachineBasicBlock &MBB, DebugLoc DL, MachineBasicBlock *TBB,
243 const SmallVectorImpl<MachineOperand> &Cond) const {
244 if (Cond[0].getImm() != -1) {
246 BuildMI(&MBB, DL, get(ARM64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
248 // Folded compare-and-branch
249 const MachineInstrBuilder MIB =
250 BuildMI(&MBB, DL, get(Cond[1].getImm())).addReg(Cond[2].getReg());
252 MIB.addImm(Cond[3].getImm());
257 unsigned ARM64InstrInfo::InsertBranch(
258 MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
259 const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const {
260 // Shouldn't be a fall through.
261 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
264 if (Cond.empty()) // Unconditional branch?
265 BuildMI(&MBB, DL, get(ARM64::B)).addMBB(TBB);
267 instantiateCondBranch(MBB, DL, TBB, Cond);
271 // Two-way conditional branch.
272 instantiateCondBranch(MBB, DL, TBB, Cond);
273 BuildMI(&MBB, DL, get(ARM64::B)).addMBB(FBB);
277 // Find the original register that VReg is copied from.
278 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) {
279 while (TargetRegisterInfo::isVirtualRegister(VReg)) {
280 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
281 if (!DefMI->isFullCopy())
283 VReg = DefMI->getOperand(1).getReg();
288 // Determine if VReg is defined by an instruction that can be folded into a
289 // csel instruction. If so, return the folded opcode, and the replacement
291 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg,
292 unsigned *NewVReg = 0) {
293 VReg = removeCopies(MRI, VReg);
294 if (!TargetRegisterInfo::isVirtualRegister(VReg))
297 bool Is64Bit = ARM64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg));
298 const MachineInstr *DefMI = MRI.getVRegDef(VReg);
300 unsigned SrcOpNum = 0;
301 switch (DefMI->getOpcode()) {
304 // if CPSR is used, do not fold.
305 if (DefMI->findRegisterDefOperandIdx(ARM64::CPSR, true) == -1)
307 // fall-through to ADDXri and ADDWri.
310 // add x, 1 -> csinc.
311 if (!DefMI->getOperand(2).isImm() || DefMI->getOperand(2).getImm() != 1 ||
312 DefMI->getOperand(3).getImm() != 0)
315 Opc = Is64Bit ? ARM64::CSINCXr : ARM64::CSINCWr;
319 case ARM64::ORNWrr: {
320 // not x -> csinv, represented as orn dst, xzr, src.
321 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
322 if (ZReg != ARM64::XZR && ZReg != ARM64::WZR)
325 Opc = Is64Bit ? ARM64::CSINVXr : ARM64::CSINVWr;
331 // if CPSR is used, do not fold.
332 if (DefMI->findRegisterDefOperandIdx(ARM64::CPSR, true) == -1)
334 // fall-through to SUBXrr and SUBWrr.
336 case ARM64::SUBWrr: {
337 // neg x -> csneg, represented as sub dst, xzr, src.
338 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
339 if (ZReg != ARM64::XZR && ZReg != ARM64::WZR)
342 Opc = Is64Bit ? ARM64::CSNEGXr : ARM64::CSNEGWr;
348 assert(Opc && SrcOpNum && "Missing parameters");
351 *NewVReg = DefMI->getOperand(SrcOpNum).getReg();
355 bool ARM64InstrInfo::canInsertSelect(
356 const MachineBasicBlock &MBB, const SmallVectorImpl<MachineOperand> &Cond,
357 unsigned TrueReg, unsigned FalseReg, int &CondCycles, int &TrueCycles,
358 int &FalseCycles) const {
359 // Check register classes.
360 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
361 const TargetRegisterClass *RC =
362 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
366 // Expanding cbz/tbz requires an extra cycle of latency on the condition.
367 unsigned ExtraCondLat = Cond.size() != 1;
369 // GPRs are handled by csel.
370 // FIXME: Fold in x+1, -x, and ~x when applicable.
371 if (ARM64::GPR64allRegClass.hasSubClassEq(RC) ||
372 ARM64::GPR32allRegClass.hasSubClassEq(RC)) {
373 // Single-cycle csel, csinc, csinv, and csneg.
374 CondCycles = 1 + ExtraCondLat;
375 TrueCycles = FalseCycles = 1;
376 if (canFoldIntoCSel(MRI, TrueReg))
378 else if (canFoldIntoCSel(MRI, FalseReg))
383 // Scalar floating point is handled by fcsel.
384 // FIXME: Form fabs, fmin, and fmax when applicable.
385 if (ARM64::FPR64RegClass.hasSubClassEq(RC) ||
386 ARM64::FPR32RegClass.hasSubClassEq(RC)) {
387 CondCycles = 5 + ExtraCondLat;
388 TrueCycles = FalseCycles = 2;
396 void ARM64InstrInfo::insertSelect(MachineBasicBlock &MBB,
397 MachineBasicBlock::iterator I, DebugLoc DL,
399 const SmallVectorImpl<MachineOperand> &Cond,
400 unsigned TrueReg, unsigned FalseReg) const {
401 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
403 // Parse the condition code, see parseCondBranch() above.
404 ARM64CC::CondCode CC;
405 switch (Cond.size()) {
407 llvm_unreachable("Unknown condition opcode in Cond");
409 CC = ARM64CC::CondCode(Cond[0].getImm());
411 case 3: { // cbz/cbnz
412 // We must insert a compare against 0.
414 switch (Cond[1].getImm()) {
416 llvm_unreachable("Unknown branch opcode in Cond");
434 unsigned SrcReg = Cond[2].getReg();
436 // cmp reg, #0 is actually subs xzr, reg, #0.
437 MRI.constrainRegClass(SrcReg, &ARM64::GPR64spRegClass);
438 BuildMI(MBB, I, DL, get(ARM64::SUBSXri), ARM64::XZR)
443 MRI.constrainRegClass(SrcReg, &ARM64::GPR32spRegClass);
444 BuildMI(MBB, I, DL, get(ARM64::SUBSWri), ARM64::WZR)
451 case 4: { // tbz/tbnz
452 // We must insert a tst instruction.
453 switch (Cond[1].getImm()) {
455 llvm_unreachable("Unknown branch opcode in Cond");
463 // cmp reg, #foo is actually ands xzr, reg, #1<<foo.
464 BuildMI(MBB, I, DL, get(ARM64::ANDSXri), ARM64::XZR)
465 .addReg(Cond[2].getReg())
466 .addImm(ARM64_AM::encodeLogicalImmediate(1ull << Cond[3].getImm(), 64));
472 const TargetRegisterClass *RC = 0;
473 bool TryFold = false;
474 if (MRI.constrainRegClass(DstReg, &ARM64::GPR64RegClass)) {
475 RC = &ARM64::GPR64RegClass;
478 } else if (MRI.constrainRegClass(DstReg, &ARM64::GPR32RegClass)) {
479 RC = &ARM64::GPR32RegClass;
482 } else if (MRI.constrainRegClass(DstReg, &ARM64::FPR64RegClass)) {
483 RC = &ARM64::FPR64RegClass;
484 Opc = ARM64::FCSELDrrr;
485 } else if (MRI.constrainRegClass(DstReg, &ARM64::FPR32RegClass)) {
486 RC = &ARM64::FPR32RegClass;
487 Opc = ARM64::FCSELSrrr;
489 assert(RC && "Unsupported regclass");
491 // Try folding simple instructions into the csel.
493 unsigned NewVReg = 0;
494 unsigned FoldedOpc = canFoldIntoCSel(MRI, TrueReg, &NewVReg);
496 // The folded opcodes csinc, csinc and csneg apply the operation to
497 // FalseReg, so we need to invert the condition.
498 CC = ARM64CC::getInvertedCondCode(CC);
501 FoldedOpc = canFoldIntoCSel(MRI, FalseReg, &NewVReg);
503 // Fold the operation. Leave any dead instructions for DCE to clean up.
507 // The extends the live range of NewVReg.
508 MRI.clearKillFlags(NewVReg);
512 // Pull all virtual register into the appropriate class.
513 MRI.constrainRegClass(TrueReg, RC);
514 MRI.constrainRegClass(FalseReg, RC);
517 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(TrueReg).addReg(FalseReg).addImm(
521 bool ARM64InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
522 unsigned &SrcReg, unsigned &DstReg,
523 unsigned &SubIdx) const {
524 switch (MI.getOpcode()) {
527 case ARM64::SBFMXri: // aka sxtw
528 case ARM64::UBFMXri: // aka uxtw
529 // Check for the 32 -> 64 bit extension case, these instructions can do
531 if (MI.getOperand(2).getImm() != 0 || MI.getOperand(3).getImm() != 31)
533 // This is a signed or unsigned 32 -> 64 bit extension.
534 SrcReg = MI.getOperand(1).getReg();
535 DstReg = MI.getOperand(0).getReg();
536 SubIdx = ARM64::sub_32;
541 /// analyzeCompare - For a comparison instruction, return the source registers
542 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
543 /// Return true if the comparison instruction can be analyzed.
544 bool ARM64InstrInfo::analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
545 unsigned &SrcReg2, int &CmpMask,
546 int &CmpValue) const {
547 switch (MI->getOpcode()) {
562 // Replace SUBSWrr with SUBWrr if CPSR is not used.
563 SrcReg = MI->getOperand(1).getReg();
564 SrcReg2 = MI->getOperand(2).getReg();
574 SrcReg = MI->getOperand(1).getReg();
577 CmpValue = MI->getOperand(2).getImm();
584 static bool UpdateOperandRegClass(MachineInstr *Instr) {
585 MachineBasicBlock *MBB = Instr->getParent();
586 assert(MBB && "Can't get MachineBasicBlock here");
587 MachineFunction *MF = MBB->getParent();
588 assert(MF && "Can't get MachineFunction here");
589 const TargetMachine *TM = &MF->getTarget();
590 const TargetInstrInfo *TII = TM->getInstrInfo();
591 const TargetRegisterInfo *TRI = TM->getRegisterInfo();
592 MachineRegisterInfo *MRI = &MF->getRegInfo();
594 for (unsigned OpIdx = 0, EndIdx = Instr->getNumOperands(); OpIdx < EndIdx;
596 MachineOperand &MO = Instr->getOperand(OpIdx);
597 const TargetRegisterClass *OpRegCstraints =
598 Instr->getRegClassConstraint(OpIdx, TII, TRI);
600 // If there's no constraint, there's nothing to do.
603 // If the operand is a frame index, there's nothing to do here.
604 // A frame index operand will resolve correctly during PEI.
609 "Operand has register constraints without being a register!");
611 unsigned Reg = MO.getReg();
612 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
613 if (!OpRegCstraints->contains(Reg))
615 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) &&
616 !MRI->constrainRegClass(Reg, OpRegCstraints))
623 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
624 /// comparison into one that sets the zero bit in the flags register.
625 bool ARM64InstrInfo::optimizeCompareInstr(
626 MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
627 int CmpValue, const MachineRegisterInfo *MRI) const {
629 // Replace SUBSWrr with SUBWrr if CPSR is not used.
630 int Cmp_CPSR = CmpInstr->findRegisterDefOperandIdx(ARM64::CPSR, true);
631 if (Cmp_CPSR != -1) {
633 switch (CmpInstr->getOpcode()) {
636 case ARM64::ADDSWrr: NewOpc = ARM64::ADDWrr; break;
637 case ARM64::ADDSWri: NewOpc = ARM64::ADDWri; break;
638 case ARM64::ADDSWrs: NewOpc = ARM64::ADDWrs; break;
639 case ARM64::ADDSWrx: NewOpc = ARM64::ADDWrx; break;
640 case ARM64::ADDSXrr: NewOpc = ARM64::ADDXrr; break;
641 case ARM64::ADDSXri: NewOpc = ARM64::ADDXri; break;
642 case ARM64::ADDSXrs: NewOpc = ARM64::ADDXrs; break;
643 case ARM64::ADDSXrx: NewOpc = ARM64::ADDXrx; break;
644 case ARM64::SUBSWrr: NewOpc = ARM64::SUBWrr; break;
645 case ARM64::SUBSWri: NewOpc = ARM64::SUBWri; break;
646 case ARM64::SUBSWrs: NewOpc = ARM64::SUBWrs; break;
647 case ARM64::SUBSWrx: NewOpc = ARM64::SUBWrx; break;
648 case ARM64::SUBSXrr: NewOpc = ARM64::SUBXrr; break;
649 case ARM64::SUBSXri: NewOpc = ARM64::SUBXri; break;
650 case ARM64::SUBSXrs: NewOpc = ARM64::SUBXrs; break;
651 case ARM64::SUBSXrx: NewOpc = ARM64::SUBXrx; break;
654 const MCInstrDesc &MCID = get(NewOpc);
655 CmpInstr->setDesc(MCID);
656 CmpInstr->RemoveOperand(Cmp_CPSR);
657 bool succeeded = UpdateOperandRegClass(CmpInstr);
659 assert(succeeded && "Some operands reg class are incompatible!");
663 // Continue only if we have a "ri" where immediate is zero.
664 if (CmpValue != 0 || SrcReg2 != 0)
667 // CmpInstr is a Compare instruction if destination register is not used.
668 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
671 // Get the unique definition of SrcReg.
672 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
676 // We iterate backward, starting from the instruction before CmpInstr and
677 // stop when reaching the definition of the source register or done with the
678 // basic block, to check whether CPSR is used or modified in between.
679 MachineBasicBlock::iterator I = CmpInstr, E = MI,
680 B = CmpInstr->getParent()->begin();
682 // Early exit if CmpInstr is at the beginning of the BB.
686 // Check whether the definition of SrcReg is in the same basic block as
687 // Compare. If not, we can't optimize away the Compare.
688 if (MI->getParent() != CmpInstr->getParent())
691 // Check that CPSR isn't set between the comparison instruction and the one we
693 const TargetRegisterInfo *TRI = &getRegisterInfo();
694 for (--I; I != E; --I) {
695 const MachineInstr &Instr = *I;
697 if (Instr.modifiesRegister(ARM64::CPSR, TRI) ||
698 Instr.readsRegister(ARM64::CPSR, TRI))
699 // This instruction modifies or uses CPSR after the one we want to
700 // change. We can't do this transformation.
703 // The 'and' is below the comparison instruction.
707 unsigned NewOpc = MI->getOpcode();
708 switch (MI->getOpcode()) {
720 case ARM64::ADDWrr: NewOpc = ARM64::ADDSWrr; break;
721 case ARM64::ADDWri: NewOpc = ARM64::ADDSWri; break;
722 case ARM64::ADDXrr: NewOpc = ARM64::ADDSXrr; break;
723 case ARM64::ADDXri: NewOpc = ARM64::ADDSXri; break;
724 case ARM64::ADCWr: NewOpc = ARM64::ADCSWr; break;
725 case ARM64::ADCXr: NewOpc = ARM64::ADCSXr; break;
726 case ARM64::SUBWrr: NewOpc = ARM64::SUBSWrr; break;
727 case ARM64::SUBWri: NewOpc = ARM64::SUBSWri; break;
728 case ARM64::SUBXrr: NewOpc = ARM64::SUBSXrr; break;
729 case ARM64::SUBXri: NewOpc = ARM64::SUBSXri; break;
730 case ARM64::SBCWr: NewOpc = ARM64::SBCSWr; break;
731 case ARM64::SBCXr: NewOpc = ARM64::SBCSXr; break;
732 case ARM64::ANDWri: NewOpc = ARM64::ANDSWri; break;
733 case ARM64::ANDXri: NewOpc = ARM64::ANDSXri; break;
736 // Scan forward for the use of CPSR.
737 // When checking against MI: if it's a conditional code requires
738 // checking of V bit, then this is not safe to do.
739 // It is safe to remove CmpInstr if CPSR is redefined or killed.
740 // If we are done with the basic block, we need to check whether CPSR is
743 for (MachineBasicBlock::iterator I = CmpInstr,
744 E = CmpInstr->getParent()->end();
745 !IsSafe && ++I != E;) {
746 const MachineInstr &Instr = *I;
747 for (unsigned IO = 0, EO = Instr.getNumOperands(); !IsSafe && IO != EO;
749 const MachineOperand &MO = Instr.getOperand(IO);
750 if (MO.isRegMask() && MO.clobbersPhysReg(ARM64::CPSR)) {
754 if (!MO.isReg() || MO.getReg() != ARM64::CPSR)
761 // Decode the condition code.
762 unsigned Opc = Instr.getOpcode();
763 ARM64CC::CondCode CC;
768 CC = (ARM64CC::CondCode)Instr.getOperand(IO - 2).getImm();
778 CC = (ARM64CC::CondCode)Instr.getOperand(IO - 1).getImm();
782 // It is not safe to remove Compare instruction if Overflow(V) is used.
785 // CPSR can be used multiple times, we should continue.
798 // If CPSR is not killed nor re-defined, we should check whether it is
799 // live-out. If it is live-out, do not optimize.
801 MachineBasicBlock *MBB = CmpInstr->getParent();
802 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
803 SE = MBB->succ_end();
805 if ((*SI)->isLiveIn(ARM64::CPSR))
809 // Update the instruction to set CPSR.
810 MI->setDesc(get(NewOpc));
811 CmpInstr->eraseFromParent();
812 bool succeeded = UpdateOperandRegClass(MI);
814 assert(succeeded && "Some operands reg class are incompatible!");
815 MI->addRegisterDefined(ARM64::CPSR, TRI);
819 // Return true if this instruction simply sets its single destination register
820 // to zero. This is equivalent to a register rename of the zero-register.
821 bool ARM64InstrInfo::isGPRZero(const MachineInstr *MI) const {
822 switch (MI->getOpcode()) {
826 case ARM64::MOVZXi: // movz Rd, #0 (LSL #0)
827 if (MI->getOperand(1).isImm() && MI->getOperand(1).getImm() == 0) {
828 assert(MI->getDesc().getNumOperands() == 3 &&
829 MI->getOperand(2).getImm() == 0 && "invalid MOVZi operands");
833 case ARM64::ANDWri: // and Rd, Rzr, #imm
834 return MI->getOperand(1).getReg() == ARM64::WZR;
836 return MI->getOperand(1).getReg() == ARM64::XZR;
837 case TargetOpcode::COPY:
838 return MI->getOperand(1).getReg() == ARM64::WZR;
843 // Return true if this instruction simply renames a general register without
845 bool ARM64InstrInfo::isGPRCopy(const MachineInstr *MI) const {
846 switch (MI->getOpcode()) {
849 case TargetOpcode::COPY: {
850 // GPR32 copies will by lowered to ORRXrs
851 unsigned DstReg = MI->getOperand(0).getReg();
852 return (ARM64::GPR32RegClass.contains(DstReg) ||
853 ARM64::GPR64RegClass.contains(DstReg));
855 case ARM64::ORRXrs: // orr Xd, Xzr, Xm (LSL #0)
856 if (MI->getOperand(1).getReg() == ARM64::XZR) {
857 assert(MI->getDesc().getNumOperands() == 4 &&
858 MI->getOperand(3).getImm() == 0 && "invalid ORRrs operands");
861 case ARM64::ADDXri: // add Xd, Xn, #0 (LSL #0)
862 if (MI->getOperand(2).getImm() == 0) {
863 assert(MI->getDesc().getNumOperands() == 4 &&
864 MI->getOperand(3).getImm() == 0 && "invalid ADDXri operands");
871 // Return true if this instruction simply renames a general register without
873 bool ARM64InstrInfo::isFPRCopy(const MachineInstr *MI) const {
874 switch (MI->getOpcode()) {
877 case TargetOpcode::COPY: {
878 // FPR64 copies will by lowered to ORR.16b
879 unsigned DstReg = MI->getOperand(0).getReg();
880 return (ARM64::FPR64RegClass.contains(DstReg) ||
881 ARM64::FPR128RegClass.contains(DstReg));
883 case ARM64::ORRv16i8:
884 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) {
885 assert(MI->getDesc().getNumOperands() == 3 && MI->getOperand(0).isReg() &&
886 "invalid ORRv16i8 operands");
893 unsigned ARM64InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
894 int &FrameIndex) const {
895 switch (MI->getOpcode()) {
905 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() &&
906 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) {
907 FrameIndex = MI->getOperand(1).getIndex();
908 return MI->getOperand(0).getReg();
916 unsigned ARM64InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
917 int &FrameIndex) const {
918 switch (MI->getOpcode()) {
928 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() &&
929 MI->getOperand(2).isImm() && MI->getOperand(2).getImm() == 0) {
930 FrameIndex = MI->getOperand(1).getIndex();
931 return MI->getOperand(0).getReg();
938 /// Return true if this is load/store scales or extends its register offset.
939 /// This refers to scaling a dynamic index as opposed to scaled immediates.
940 /// MI should be a memory op that allows scaled addressing.
941 bool ARM64InstrInfo::isScaledAddr(const MachineInstr *MI) const {
942 switch (MI->getOpcode()) {
951 case ARM64::LDRSBWro:
952 case ARM64::LDRSBXro:
953 case ARM64::LDRSHWro:
954 case ARM64::LDRSHXro:
968 unsigned Val = MI->getOperand(3).getImm();
969 ARM64_AM::ExtendType ExtType = ARM64_AM::getMemExtendType(Val);
970 return (ExtType != ARM64_AM::UXTX) || ARM64_AM::getMemDoShift(Val);
975 /// Check all MachineMemOperands for a hint to suppress pairing.
976 bool ARM64InstrInfo::isLdStPairSuppressed(const MachineInstr *MI) const {
977 assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
978 "Too many target MO flags");
979 for (MachineInstr::mmo_iterator MM = MI->memoperands_begin(),
980 E = MI->memoperands_end();
983 if ((*MM)->getFlags() &
984 (MOSuppressPair << MachineMemOperand::MOTargetStartBit)) {
991 /// Set a flag on the first MachineMemOperand to suppress pairing.
992 void ARM64InstrInfo::suppressLdStPair(MachineInstr *MI) const {
993 if (MI->memoperands_empty())
996 assert(MOSuppressPair < (1 << MachineMemOperand::MOTargetNumBits) &&
997 "Too many target MO flags");
998 (*MI->memoperands_begin())
999 ->setFlags(MOSuppressPair << MachineMemOperand::MOTargetStartBit);
1002 bool ARM64InstrInfo::getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
1004 const TargetRegisterInfo *TRI) const {
1005 switch (LdSt->getOpcode()) {
1018 if (!LdSt->getOperand(1).isReg() || !LdSt->getOperand(2).isImm())
1020 BaseReg = LdSt->getOperand(1).getReg();
1021 MachineFunction &MF = *LdSt->getParent()->getParent();
1022 unsigned Width = getRegClass(LdSt->getDesc(), 0, TRI, MF)->getSize();
1023 Offset = LdSt->getOperand(2).getImm() * Width;
1028 /// Detect opportunities for ldp/stp formation.
1030 /// Only called for LdSt for which getLdStBaseRegImmOfs returns true.
1031 bool ARM64InstrInfo::shouldClusterLoads(MachineInstr *FirstLdSt,
1032 MachineInstr *SecondLdSt,
1033 unsigned NumLoads) const {
1034 // Only cluster up to a single pair.
1037 if (FirstLdSt->getOpcode() != SecondLdSt->getOpcode())
1039 // getLdStBaseRegImmOfs guarantees that oper 2 isImm.
1040 unsigned Ofs1 = FirstLdSt->getOperand(2).getImm();
1041 // Allow 6 bits of positive range.
1044 // The caller should already have ordered First/SecondLdSt by offset.
1045 unsigned Ofs2 = SecondLdSt->getOperand(2).getImm();
1046 return Ofs1 + 1 == Ofs2;
1049 bool ARM64InstrInfo::shouldScheduleAdjacent(MachineInstr *First,
1050 MachineInstr *Second) const {
1051 // Cyclone can fuse CMN, CMP followed by Bcc.
1053 // FIXME: B0 can also fuse:
1054 // AND, BIC, ORN, ORR, or EOR (optional S) followed by Bcc or CBZ or CBNZ.
1055 if (Second->getOpcode() != ARM64::Bcc)
1057 switch (First->getOpcode()) {
1060 case ARM64::SUBSWri:
1061 case ARM64::ADDSWri:
1062 case ARM64::ANDSWri:
1063 case ARM64::SUBSXri:
1064 case ARM64::ADDSXri:
1065 case ARM64::ANDSXri:
1070 MachineInstr *ARM64InstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
1073 const MDNode *MDPtr,
1074 DebugLoc DL) const {
1075 MachineInstrBuilder MIB = BuildMI(MF, DL, get(ARM64::DBG_VALUE))
1076 .addFrameIndex(FrameIx)
1079 .addMetadata(MDPtr);
1083 static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
1084 unsigned Reg, unsigned SubIdx,
1086 const TargetRegisterInfo *TRI) {
1088 return MIB.addReg(Reg, State);
1090 if (TargetRegisterInfo::isPhysicalRegister(Reg))
1091 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1092 return MIB.addReg(Reg, State, SubIdx);
1095 static bool forwardCopyWillClobberTuple(unsigned DestReg, unsigned SrcReg,
1097 // We really want the positive remainder mod 32 here, that happens to be
1098 // easily obtainable with a mask.
1099 return ((DestReg - SrcReg) & 0x1f) < NumRegs;
1102 void ARM64InstrInfo::copyPhysRegTuple(MachineBasicBlock &MBB,
1103 MachineBasicBlock::iterator I,
1104 DebugLoc DL, unsigned DestReg,
1105 unsigned SrcReg, bool KillSrc,
1107 llvm::ArrayRef<unsigned> Indices) const {
1108 const TargetRegisterInfo *TRI = &getRegisterInfo();
1109 uint16_t DestEncoding = TRI->getEncodingValue(DestReg);
1110 uint16_t SrcEncoding = TRI->getEncodingValue(SrcReg);
1111 unsigned NumRegs = Indices.size();
1113 int SubReg = 0, End = NumRegs, Incr = 1;
1114 if (forwardCopyWillClobberTuple(DestEncoding, SrcEncoding, NumRegs)) {
1115 SubReg = NumRegs - 1;
1120 for (; SubReg != End; SubReg += Incr) {
1121 const MachineInstrBuilder &MIB = BuildMI(MBB, I, DL, get(Opcode));
1122 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
1123 AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI);
1124 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
1128 void ARM64InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
1129 MachineBasicBlock::iterator I, DebugLoc DL,
1130 unsigned DestReg, unsigned SrcReg,
1131 bool KillSrc) const {
1132 if (ARM64::GPR32spRegClass.contains(DestReg) &&
1133 (ARM64::GPR32spRegClass.contains(SrcReg) || SrcReg == ARM64::WZR)) {
1134 const TargetRegisterInfo *TRI = &getRegisterInfo();
1136 if (DestReg == ARM64::WSP || SrcReg == ARM64::WSP) {
1137 // If either operand is WSP, expand to ADD #0.
1138 if (Subtarget.hasZeroCycleRegMove()) {
1139 // Cyclone recognizes "ADD Xd, Xn, #0" as a zero-cycle register move.
1140 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, ARM64::sub_32,
1141 &ARM64::GPR64spRegClass);
1142 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, ARM64::sub_32,
1143 &ARM64::GPR64spRegClass);
1144 // This instruction is reading and writing X registers. This may upset
1145 // the register scavenger and machine verifier, so we need to indicate
1146 // that we are reading an undefined value from SrcRegX, but a proper
1147 // value from SrcReg.
1148 BuildMI(MBB, I, DL, get(ARM64::ADDXri), DestRegX)
1149 .addReg(SrcRegX, RegState::Undef)
1151 .addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, 0))
1152 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1154 BuildMI(MBB, I, DL, get(ARM64::ADDWri), DestReg)
1155 .addReg(SrcReg, getKillRegState(KillSrc))
1157 .addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, 0));
1159 } else if (SrcReg == ARM64::WZR && Subtarget.hasZeroCycleZeroing()) {
1160 BuildMI(MBB, I, DL, get(ARM64::MOVZWi), DestReg).addImm(0).addImm(
1161 ARM64_AM::getShifterImm(ARM64_AM::LSL, 0));
1163 if (Subtarget.hasZeroCycleRegMove()) {
1164 // Cyclone recognizes "ORR Xd, XZR, Xm" as a zero-cycle register move.
1165 unsigned DestRegX = TRI->getMatchingSuperReg(DestReg, ARM64::sub_32,
1166 &ARM64::GPR64spRegClass);
1167 unsigned SrcRegX = TRI->getMatchingSuperReg(SrcReg, ARM64::sub_32,
1168 &ARM64::GPR64spRegClass);
1169 // This instruction is reading and writing X registers. This may upset
1170 // the register scavenger and machine verifier, so we need to indicate
1171 // that we are reading an undefined value from SrcRegX, but a proper
1172 // value from SrcReg.
1173 BuildMI(MBB, I, DL, get(ARM64::ORRXrr), DestRegX)
1175 .addReg(SrcRegX, RegState::Undef)
1176 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
1178 // Otherwise, expand to ORR WZR.
1179 BuildMI(MBB, I, DL, get(ARM64::ORRWrr), DestReg)
1181 .addReg(SrcReg, getKillRegState(KillSrc));
1187 if (ARM64::GPR64spRegClass.contains(DestReg) &&
1188 (ARM64::GPR64spRegClass.contains(SrcReg) || SrcReg == ARM64::XZR)) {
1189 if (DestReg == ARM64::SP || SrcReg == ARM64::SP) {
1190 // If either operand is SP, expand to ADD #0.
1191 BuildMI(MBB, I, DL, get(ARM64::ADDXri), DestReg)
1192 .addReg(SrcReg, getKillRegState(KillSrc))
1194 .addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, 0));
1195 } else if (SrcReg == ARM64::XZR && Subtarget.hasZeroCycleZeroing()) {
1196 BuildMI(MBB, I, DL, get(ARM64::MOVZXi), DestReg).addImm(0).addImm(
1197 ARM64_AM::getShifterImm(ARM64_AM::LSL, 0));
1199 // Otherwise, expand to ORR XZR.
1200 BuildMI(MBB, I, DL, get(ARM64::ORRXrr), DestReg)
1202 .addReg(SrcReg, getKillRegState(KillSrc));
1207 // Copy a DDDD register quad by copying the individual sub-registers.
1208 if (ARM64::DDDDRegClass.contains(DestReg) &&
1209 ARM64::DDDDRegClass.contains(SrcReg)) {
1210 static const unsigned Indices[] = { ARM64::dsub0, ARM64::dsub1,
1211 ARM64::dsub2, ARM64::dsub3 };
1212 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, ARM64::ORRv8i8,
1217 // Copy a DDD register triple by copying the individual sub-registers.
1218 if (ARM64::DDDRegClass.contains(DestReg) &&
1219 ARM64::DDDRegClass.contains(SrcReg)) {
1220 static const unsigned Indices[] = { ARM64::dsub0, ARM64::dsub1,
1222 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, ARM64::ORRv8i8,
1227 // Copy a DD register pair by copying the individual sub-registers.
1228 if (ARM64::DDRegClass.contains(DestReg) &&
1229 ARM64::DDRegClass.contains(SrcReg)) {
1230 static const unsigned Indices[] = { ARM64::dsub0, ARM64::dsub1 };
1231 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, ARM64::ORRv8i8,
1236 // Copy a QQQQ register quad by copying the individual sub-registers.
1237 if (ARM64::QQQQRegClass.contains(DestReg) &&
1238 ARM64::QQQQRegClass.contains(SrcReg)) {
1239 static const unsigned Indices[] = { ARM64::qsub0, ARM64::qsub1,
1240 ARM64::qsub2, ARM64::qsub3 };
1241 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, ARM64::ORRv16i8,
1246 // Copy a QQQ register triple by copying the individual sub-registers.
1247 if (ARM64::QQQRegClass.contains(DestReg) &&
1248 ARM64::QQQRegClass.contains(SrcReg)) {
1249 static const unsigned Indices[] = { ARM64::qsub0, ARM64::qsub1,
1251 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, ARM64::ORRv16i8,
1256 // Copy a QQ register pair by copying the individual sub-registers.
1257 if (ARM64::QQRegClass.contains(DestReg) &&
1258 ARM64::QQRegClass.contains(SrcReg)) {
1259 static const unsigned Indices[] = { ARM64::qsub0, ARM64::qsub1 };
1260 copyPhysRegTuple(MBB, I, DL, DestReg, SrcReg, KillSrc, ARM64::ORRv16i8,
1265 if (ARM64::FPR128RegClass.contains(DestReg) &&
1266 ARM64::FPR128RegClass.contains(SrcReg)) {
1267 BuildMI(MBB, I, DL, get(ARM64::ORRv16i8), DestReg).addReg(SrcReg).addReg(
1268 SrcReg, getKillRegState(KillSrc));
1272 if (ARM64::FPR64RegClass.contains(DestReg) &&
1273 ARM64::FPR64RegClass.contains(SrcReg)) {
1275 RI.getMatchingSuperReg(DestReg, ARM64::dsub, &ARM64::FPR128RegClass);
1277 RI.getMatchingSuperReg(SrcReg, ARM64::dsub, &ARM64::FPR128RegClass);
1278 BuildMI(MBB, I, DL, get(ARM64::ORRv16i8), DestReg).addReg(SrcReg).addReg(
1279 SrcReg, getKillRegState(KillSrc));
1283 if (ARM64::FPR32RegClass.contains(DestReg) &&
1284 ARM64::FPR32RegClass.contains(SrcReg)) {
1286 RI.getMatchingSuperReg(DestReg, ARM64::ssub, &ARM64::FPR128RegClass);
1288 RI.getMatchingSuperReg(SrcReg, ARM64::ssub, &ARM64::FPR128RegClass);
1289 BuildMI(MBB, I, DL, get(ARM64::ORRv16i8), DestReg).addReg(SrcReg).addReg(
1290 SrcReg, getKillRegState(KillSrc));
1294 if (ARM64::FPR16RegClass.contains(DestReg) &&
1295 ARM64::FPR16RegClass.contains(SrcReg)) {
1297 RI.getMatchingSuperReg(DestReg, ARM64::hsub, &ARM64::FPR128RegClass);
1299 RI.getMatchingSuperReg(SrcReg, ARM64::hsub, &ARM64::FPR128RegClass);
1300 BuildMI(MBB, I, DL, get(ARM64::ORRv16i8), DestReg).addReg(SrcReg).addReg(
1301 SrcReg, getKillRegState(KillSrc));
1305 if (ARM64::FPR8RegClass.contains(DestReg) &&
1306 ARM64::FPR8RegClass.contains(SrcReg)) {
1308 RI.getMatchingSuperReg(DestReg, ARM64::bsub, &ARM64::FPR128RegClass);
1310 RI.getMatchingSuperReg(SrcReg, ARM64::bsub, &ARM64::FPR128RegClass);
1311 BuildMI(MBB, I, DL, get(ARM64::ORRv16i8), DestReg).addReg(SrcReg).addReg(
1312 SrcReg, getKillRegState(KillSrc));
1316 // Copies between GPR64 and FPR64.
1317 if (ARM64::FPR64RegClass.contains(DestReg) &&
1318 ARM64::GPR64RegClass.contains(SrcReg)) {
1319 BuildMI(MBB, I, DL, get(ARM64::FMOVXDr), DestReg)
1320 .addReg(SrcReg, getKillRegState(KillSrc));
1323 if (ARM64::GPR64RegClass.contains(DestReg) &&
1324 ARM64::FPR64RegClass.contains(SrcReg)) {
1325 BuildMI(MBB, I, DL, get(ARM64::FMOVDXr), DestReg)
1326 .addReg(SrcReg, getKillRegState(KillSrc));
1329 // Copies between GPR32 and FPR32.
1330 if (ARM64::FPR32RegClass.contains(DestReg) &&
1331 ARM64::GPR32RegClass.contains(SrcReg)) {
1332 BuildMI(MBB, I, DL, get(ARM64::FMOVWSr), DestReg)
1333 .addReg(SrcReg, getKillRegState(KillSrc));
1336 if (ARM64::GPR32RegClass.contains(DestReg) &&
1337 ARM64::FPR32RegClass.contains(SrcReg)) {
1338 BuildMI(MBB, I, DL, get(ARM64::FMOVSWr), DestReg)
1339 .addReg(SrcReg, getKillRegState(KillSrc));
1343 assert(0 && "unimplemented reg-to-reg copy");
1346 void ARM64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
1347 MachineBasicBlock::iterator MBBI,
1348 unsigned SrcReg, bool isKill, int FI,
1349 const TargetRegisterClass *RC,
1350 const TargetRegisterInfo *TRI) const {
1352 if (MBBI != MBB.end())
1353 DL = MBBI->getDebugLoc();
1354 MachineFunction &MF = *MBB.getParent();
1355 MachineFrameInfo &MFI = *MF.getFrameInfo();
1356 unsigned Align = MFI.getObjectAlignment(FI);
1358 MachinePointerInfo PtrInfo(PseudoSourceValue::getFixedStack(FI));
1359 MachineMemOperand *MMO = MF.getMachineMemOperand(
1360 PtrInfo, MachineMemOperand::MOStore, MFI.getObjectSize(FI), Align);
1363 switch (RC->getSize()) {
1365 if (ARM64::FPR8RegClass.hasSubClassEq(RC))
1366 Opc = ARM64::STRBui;
1369 if (ARM64::FPR16RegClass.hasSubClassEq(RC))
1370 Opc = ARM64::STRHui;
1373 if (ARM64::GPR32allRegClass.hasSubClassEq(RC)) {
1374 Opc = ARM64::STRWui;
1375 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
1376 MF.getRegInfo().constrainRegClass(SrcReg, &ARM64::GPR32RegClass);
1378 assert(SrcReg != ARM64::WSP);
1379 } else if (ARM64::FPR32RegClass.hasSubClassEq(RC))
1380 Opc = ARM64::STRSui;
1383 if (ARM64::GPR64allRegClass.hasSubClassEq(RC)) {
1384 Opc = ARM64::STRXui;
1385 if (TargetRegisterInfo::isVirtualRegister(SrcReg))
1386 MF.getRegInfo().constrainRegClass(SrcReg, &ARM64::GPR64RegClass);
1388 assert(SrcReg != ARM64::SP);
1389 } else if (ARM64::FPR64RegClass.hasSubClassEq(RC))
1390 Opc = ARM64::STRDui;
1393 if (ARM64::FPR128RegClass.hasSubClassEq(RC))
1394 Opc = ARM64::STRQui;
1395 else if (ARM64::DDRegClass.hasSubClassEq(RC))
1396 Opc = ARM64::ST1Twov1d, Offset = false;
1399 if (ARM64::DDDRegClass.hasSubClassEq(RC))
1400 Opc = ARM64::ST1Threev1d, Offset = false;
1403 if (ARM64::DDDDRegClass.hasSubClassEq(RC))
1404 Opc = ARM64::ST1Fourv1d, Offset = false;
1405 else if (ARM64::QQRegClass.hasSubClassEq(RC))
1406 Opc = ARM64::ST1Twov2d, Offset = false;
1409 if (ARM64::QQQRegClass.hasSubClassEq(RC))
1410 Opc = ARM64::ST1Threev2d, Offset = false;
1413 if (ARM64::QQQQRegClass.hasSubClassEq(RC))
1414 Opc = ARM64::ST1Fourv2d, Offset = false;
1417 assert(Opc && "Unknown register class");
1419 const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc))
1420 .addReg(SrcReg, getKillRegState(isKill))
1425 MI.addMemOperand(MMO);
1428 void ARM64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
1429 MachineBasicBlock::iterator MBBI,
1430 unsigned DestReg, int FI,
1431 const TargetRegisterClass *RC,
1432 const TargetRegisterInfo *TRI) const {
1434 if (MBBI != MBB.end())
1435 DL = MBBI->getDebugLoc();
1436 MachineFunction &MF = *MBB.getParent();
1437 MachineFrameInfo &MFI = *MF.getFrameInfo();
1438 unsigned Align = MFI.getObjectAlignment(FI);
1439 MachinePointerInfo PtrInfo(PseudoSourceValue::getFixedStack(FI));
1440 MachineMemOperand *MMO = MF.getMachineMemOperand(
1441 PtrInfo, MachineMemOperand::MOLoad, MFI.getObjectSize(FI), Align);
1445 switch (RC->getSize()) {
1447 if (ARM64::FPR8RegClass.hasSubClassEq(RC))
1448 Opc = ARM64::LDRBui;
1451 if (ARM64::FPR16RegClass.hasSubClassEq(RC))
1452 Opc = ARM64::LDRHui;
1455 if (ARM64::GPR32allRegClass.hasSubClassEq(RC)) {
1456 Opc = ARM64::LDRWui;
1457 if (TargetRegisterInfo::isVirtualRegister(DestReg))
1458 MF.getRegInfo().constrainRegClass(DestReg, &ARM64::GPR32RegClass);
1460 assert(DestReg != ARM64::WSP);
1461 } else if (ARM64::FPR32RegClass.hasSubClassEq(RC))
1462 Opc = ARM64::LDRSui;
1465 if (ARM64::GPR64allRegClass.hasSubClassEq(RC)) {
1466 Opc = ARM64::LDRXui;
1467 if (TargetRegisterInfo::isVirtualRegister(DestReg))
1468 MF.getRegInfo().constrainRegClass(DestReg, &ARM64::GPR64RegClass);
1470 assert(DestReg != ARM64::SP);
1471 } else if (ARM64::FPR64RegClass.hasSubClassEq(RC))
1472 Opc = ARM64::LDRDui;
1475 if (ARM64::FPR128RegClass.hasSubClassEq(RC))
1476 Opc = ARM64::LDRQui;
1477 else if (ARM64::DDRegClass.hasSubClassEq(RC))
1478 Opc = ARM64::LD1Twov1d, Offset = false;
1481 if (ARM64::DDDRegClass.hasSubClassEq(RC))
1482 Opc = ARM64::LD1Threev1d, Offset = false;
1485 if (ARM64::DDDDRegClass.hasSubClassEq(RC))
1486 Opc = ARM64::LD1Fourv1d, Offset = false;
1487 else if (ARM64::QQRegClass.hasSubClassEq(RC))
1488 Opc = ARM64::LD1Twov2d, Offset = false;
1491 if (ARM64::QQQRegClass.hasSubClassEq(RC))
1492 Opc = ARM64::LD1Threev2d, Offset = false;
1495 if (ARM64::QQQQRegClass.hasSubClassEq(RC))
1496 Opc = ARM64::LD1Fourv2d, Offset = false;
1499 assert(Opc && "Unknown register class");
1501 const MachineInstrBuilder &MI = BuildMI(MBB, MBBI, DL, get(Opc))
1502 .addReg(DestReg, getDefRegState(true))
1506 MI.addMemOperand(MMO);
1509 void llvm::emitFrameOffset(MachineBasicBlock &MBB,
1510 MachineBasicBlock::iterator MBBI, DebugLoc DL,
1511 unsigned DestReg, unsigned SrcReg, int Offset,
1512 const ARM64InstrInfo *TII, MachineInstr::MIFlag Flag,
1514 if (DestReg == SrcReg && Offset == 0)
1517 bool isSub = Offset < 0;
1521 // FIXME: If the offset won't fit in 24-bits, compute the offset into a
1522 // scratch register. If DestReg is a virtual register, use it as the
1523 // scratch register; otherwise, create a new virtual register (to be
1524 // replaced by the scavenger at the end of PEI). That case can be optimized
1525 // slightly if DestReg is SP which is always 16-byte aligned, so the scratch
1526 // register can be loaded with offset%8 and the add/sub can use an extending
1527 // instruction with LSL#3.
1528 // Currently the function handles any offsets but generates a poor sequence
1530 // assert(Offset < (1 << 24) && "unimplemented reg plus immediate");
1534 Opc = isSub ? ARM64::SUBSXri : ARM64::ADDSXri;
1536 Opc = isSub ? ARM64::SUBXri : ARM64::ADDXri;
1537 const unsigned MaxEncoding = 0xfff;
1538 const unsigned ShiftSize = 12;
1539 const unsigned MaxEncodableValue = MaxEncoding << ShiftSize;
1540 while (((unsigned)Offset) >= (1 << ShiftSize)) {
1542 if (((unsigned)Offset) > MaxEncodableValue) {
1543 ThisVal = MaxEncodableValue;
1545 ThisVal = Offset & MaxEncodableValue;
1547 assert((ThisVal >> ShiftSize) <= MaxEncoding &&
1548 "Encoding cannot handle value that big");
1549 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
1551 .addImm(ThisVal >> ShiftSize)
1552 .addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, ShiftSize))
1560 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
1563 .addImm(ARM64_AM::getShifterImm(ARM64_AM::LSL, 0))
1568 ARM64InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
1569 const SmallVectorImpl<unsigned> &Ops,
1570 int FrameIndex) const {
1571 // This is a bit of a hack. Consider this instruction:
1573 // %vreg0<def> = COPY %SP; GPR64all:%vreg0
1575 // We explicitly chose GPR64all for the virtual register so such a copy might
1576 // be eliminated by RegisterCoalescer. However, that may not be possible, and
1577 // %vreg0 may even spill. We can't spill %SP, and since it is in the GPR64all
1578 // register class, TargetInstrInfo::foldMemoryOperand() is going to try.
1580 // To prevent that, we are going to constrain the %vreg0 register class here.
1582 // <rdar://problem/11522048>
1585 unsigned DstReg = MI->getOperand(0).getReg();
1586 unsigned SrcReg = MI->getOperand(1).getReg();
1587 if (SrcReg == ARM64::SP && TargetRegisterInfo::isVirtualRegister(DstReg)) {
1588 MF.getRegInfo().constrainRegClass(DstReg, &ARM64::GPR64RegClass);
1591 if (DstReg == ARM64::SP && TargetRegisterInfo::isVirtualRegister(SrcReg)) {
1592 MF.getRegInfo().constrainRegClass(SrcReg, &ARM64::GPR64RegClass);
1601 int llvm::isARM64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
1602 bool *OutUseUnscaledOp,
1603 unsigned *OutUnscaledOp,
1604 int *EmittableOffset) {
1606 bool IsSigned = false;
1607 // The ImmIdx should be changed case by case if it is not 2.
1608 unsigned ImmIdx = 2;
1609 unsigned UnscaledOp = 0;
1610 // Set output values in case of early exit.
1611 if (EmittableOffset)
1612 *EmittableOffset = 0;
1613 if (OutUseUnscaledOp)
1614 *OutUseUnscaledOp = false;
1617 switch (MI.getOpcode()) {
1619 assert(0 && "unhandled opcode in rewriteARM64FrameIndex");
1620 // Vector spills/fills can't take an immediate offset.
1621 case ARM64::LD1Twov2d:
1622 case ARM64::LD1Threev2d:
1623 case ARM64::LD1Fourv2d:
1624 case ARM64::LD1Twov1d:
1625 case ARM64::LD1Threev1d:
1626 case ARM64::LD1Fourv1d:
1627 case ARM64::ST1Twov2d:
1628 case ARM64::ST1Threev2d:
1629 case ARM64::ST1Fourv2d:
1630 case ARM64::ST1Twov1d:
1631 case ARM64::ST1Threev1d:
1632 case ARM64::ST1Fourv1d:
1633 return ARM64FrameOffsetCannotUpdate;
1636 UnscaledOp = ARM64::PRFUMi;
1640 UnscaledOp = ARM64::LDURXi;
1644 UnscaledOp = ARM64::LDURWi;
1648 UnscaledOp = ARM64::LDURBi;
1652 UnscaledOp = ARM64::LDURHi;
1656 UnscaledOp = ARM64::LDURSi;
1660 UnscaledOp = ARM64::LDURDi;
1664 UnscaledOp = ARM64::LDURQi;
1666 case ARM64::LDRBBui:
1668 UnscaledOp = ARM64::LDURBBi;
1670 case ARM64::LDRHHui:
1672 UnscaledOp = ARM64::LDURHHi;
1674 case ARM64::LDRSBXui:
1676 UnscaledOp = ARM64::LDURSBXi;
1678 case ARM64::LDRSBWui:
1680 UnscaledOp = ARM64::LDURSBWi;
1682 case ARM64::LDRSHXui:
1684 UnscaledOp = ARM64::LDURSHXi;
1686 case ARM64::LDRSHWui:
1688 UnscaledOp = ARM64::LDURSHWi;
1690 case ARM64::LDRSWui:
1692 UnscaledOp = ARM64::LDURSWi;
1697 UnscaledOp = ARM64::STURXi;
1701 UnscaledOp = ARM64::STURWi;
1705 UnscaledOp = ARM64::STURBi;
1709 UnscaledOp = ARM64::STURHi;
1713 UnscaledOp = ARM64::STURSi;
1717 UnscaledOp = ARM64::STURDi;
1721 UnscaledOp = ARM64::STURQi;
1723 case ARM64::STRBBui:
1725 UnscaledOp = ARM64::STURBBi;
1727 case ARM64::STRHHui:
1729 UnscaledOp = ARM64::STURHHi;
1759 case ARM64::LDURHHi:
1760 case ARM64::LDURBBi:
1761 case ARM64::LDURSBXi:
1762 case ARM64::LDURSBWi:
1763 case ARM64::LDURSHXi:
1764 case ARM64::LDURSHWi:
1765 case ARM64::LDURSWi:
1773 case ARM64::STURBBi:
1774 case ARM64::STURHHi:
1779 Offset += MI.getOperand(ImmIdx).getImm() * Scale;
1781 bool useUnscaledOp = false;
1782 // If the offset doesn't match the scale, we rewrite the instruction to
1783 // use the unscaled instruction instead. Likewise, if we have a negative
1784 // offset (and have an unscaled op to use).
1785 if ((Offset & (Scale - 1)) != 0 || (Offset < 0 && UnscaledOp != 0))
1786 useUnscaledOp = true;
1788 // Use an unscaled addressing mode if the instruction has a negative offset
1789 // (or if the instruction is already using an unscaled addressing mode).
1792 // ldp/stp instructions.
1795 } else if (UnscaledOp == 0 || useUnscaledOp) {
1805 // Attempt to fold address computation.
1806 int MaxOff = (1 << (MaskBits - IsSigned)) - 1;
1807 int MinOff = (IsSigned ? (-MaxOff - 1) : 0);
1808 if (Offset >= MinOff && Offset <= MaxOff) {
1809 if (EmittableOffset)
1810 *EmittableOffset = Offset;
1813 int NewOff = Offset < 0 ? MinOff : MaxOff;
1814 if (EmittableOffset)
1815 *EmittableOffset = NewOff;
1816 Offset = (Offset - NewOff) * Scale;
1818 if (OutUseUnscaledOp)
1819 *OutUseUnscaledOp = useUnscaledOp;
1821 *OutUnscaledOp = UnscaledOp;
1822 return ARM64FrameOffsetCanUpdate |
1823 (Offset == 0 ? ARM64FrameOffsetIsLegal : 0);
1826 bool llvm::rewriteARM64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
1827 unsigned FrameReg, int &Offset,
1828 const ARM64InstrInfo *TII) {
1829 unsigned Opcode = MI.getOpcode();
1830 unsigned ImmIdx = FrameRegIdx + 1;
1832 if (Opcode == ARM64::ADDSXri || Opcode == ARM64::ADDXri) {
1833 Offset += MI.getOperand(ImmIdx).getImm();
1834 emitFrameOffset(*MI.getParent(), MI, MI.getDebugLoc(),
1835 MI.getOperand(0).getReg(), FrameReg, Offset, TII,
1836 MachineInstr::NoFlags, (Opcode == ARM64::ADDSXri));
1837 MI.eraseFromParent();
1843 unsigned UnscaledOp;
1845 int Status = isARM64FrameOffsetLegal(MI, Offset, &UseUnscaledOp, &UnscaledOp,
1847 if (Status & ARM64FrameOffsetCanUpdate) {
1848 if (Status & ARM64FrameOffsetIsLegal)
1849 // Replace the FrameIndex with FrameReg.
1850 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
1852 MI.setDesc(TII->get(UnscaledOp));
1854 MI.getOperand(ImmIdx).ChangeToImmediate(NewOffset);
1861 void ARM64InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
1862 NopInst.setOpcode(ARM64::HINT);
1863 NopInst.addOperand(MCOperand::CreateImm(0));