1 //===- ARM64InstrInfo.h - ARM64 Instruction Information ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM64 implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_ARM64INSTRINFO_H
15 #define LLVM_TARGET_ARM64INSTRINFO_H
18 #include "ARM64RegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "ARM64GenInstrInfo.inc"
27 class ARM64TargetMachine;
29 class ARM64InstrInfo : public ARM64GenInstrInfo {
30 // Reserve bits in the MachineMemOperand target hint flags, starting at 1.
31 // They will be shifted into MOTargetHintStart when accessed.
32 enum TargetMemOperandFlags {
36 const ARM64RegisterInfo RI;
37 const ARM64Subtarget &Subtarget;
40 explicit ARM64InstrInfo(const ARM64Subtarget &STI);
42 /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
43 /// such, whenever a client has an instance of instruction info, it should
44 /// always be able to get register info as well (through this method).
45 const ARM64RegisterInfo &getRegisterInfo() const { return RI; }
47 unsigned GetInstSizeInBytes(const MachineInstr *MI) const;
49 bool isCoalescableExtInstr(const MachineInstr &MI, unsigned &SrcReg,
50 unsigned &DstReg, unsigned &SubIdx) const override;
52 unsigned isLoadFromStackSlot(const MachineInstr *MI,
53 int &FrameIndex) const override;
54 unsigned isStoreToStackSlot(const MachineInstr *MI,
55 int &FrameIndex) const override;
57 /// \brief Does this instruction set its full destination register to zero?
58 bool isGPRZero(const MachineInstr *MI) const;
60 /// \brief Does this instruction rename a GPR without modifying bits?
61 bool isGPRCopy(const MachineInstr *MI) const;
63 /// \brief Does this instruction rename an FPR without modifying bits?
64 bool isFPRCopy(const MachineInstr *MI) const;
66 /// Return true if this is load/store scales or extends its register offset.
67 /// This refers to scaling a dynamic index as opposed to scaled immediates.
68 /// MI should be a memory op that allows scaled addressing.
69 bool isScaledAddr(const MachineInstr *MI) const;
71 /// Return true if pairing the given load or store is hinted to be
73 bool isLdStPairSuppressed(const MachineInstr *MI) const;
75 /// Hint that pairing the given load or store is unprofitable.
76 void suppressLdStPair(MachineInstr *MI) const;
78 bool getLdStBaseRegImmOfs(MachineInstr *LdSt, unsigned &BaseReg,
80 const TargetRegisterInfo *TRI) const override;
82 bool enableClusterLoads() const override { return true; }
84 bool shouldClusterLoads(MachineInstr *FirstLdSt, MachineInstr *SecondLdSt,
85 unsigned NumLoads) const override;
87 bool shouldScheduleAdjacent(MachineInstr *First,
88 MachineInstr *Second) const override;
90 MachineInstr *emitFrameIndexDebugValue(MachineFunction &MF, int FrameIx,
91 uint64_t Offset, const MDNode *MDPtr,
93 void copyPhysRegTuple(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
94 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
95 bool KillSrc, unsigned Opcode,
96 llvm::ArrayRef<unsigned> Indices) const;
97 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
98 DebugLoc DL, unsigned DestReg, unsigned SrcReg,
99 bool KillSrc) const override;
101 void storeRegToStackSlot(MachineBasicBlock &MBB,
102 MachineBasicBlock::iterator MBBI, unsigned SrcReg,
103 bool isKill, int FrameIndex,
104 const TargetRegisterClass *RC,
105 const TargetRegisterInfo *TRI) const override;
107 void loadRegFromStackSlot(MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator MBBI, unsigned DestReg,
109 int FrameIndex, const TargetRegisterClass *RC,
110 const TargetRegisterInfo *TRI) const override;
113 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
114 const SmallVectorImpl<unsigned> &Ops,
115 int FrameIndex) const override;
117 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
118 MachineBasicBlock *&FBB,
119 SmallVectorImpl<MachineOperand> &Cond,
120 bool AllowModify = false) const override;
121 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
122 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
123 MachineBasicBlock *FBB,
124 const SmallVectorImpl<MachineOperand> &Cond,
125 DebugLoc DL) const override;
127 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
128 bool canInsertSelect(const MachineBasicBlock &,
129 const SmallVectorImpl<MachineOperand> &Cond, unsigned,
130 unsigned, int &, int &, int &) const override;
131 void insertSelect(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
132 DebugLoc DL, unsigned DstReg,
133 const SmallVectorImpl<MachineOperand> &Cond,
134 unsigned TrueReg, unsigned FalseReg) const override;
135 void getNoopForMachoTarget(MCInst &NopInst) const override;
137 /// analyzeCompare - For a comparison instruction, return the source registers
138 /// in SrcReg and SrcReg2, and the value it compares against in CmpValue.
139 /// Return true if the comparison instruction can be analyzed.
140 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
141 unsigned &SrcReg2, int &CmpMask,
142 int &CmpValue) const override;
143 /// optimizeCompareInstr - Convert the instruction supplying the argument to
144 /// the comparison into one that sets the zero bit in the flags register.
145 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
146 unsigned SrcReg2, int CmpMask, int CmpValue,
147 const MachineRegisterInfo *MRI) const override;
150 void instantiateCondBranch(MachineBasicBlock &MBB, DebugLoc DL,
151 MachineBasicBlock *TBB,
152 const SmallVectorImpl<MachineOperand> &Cond) const;
155 /// emitFrameOffset - Emit instructions as needed to set DestReg to SrcReg
156 /// plus Offset. This is intended to be used from within the prolog/epilog
157 /// insertion (PEI) pass, where a virtual scratch register may be allocated
158 /// if necessary, to be replaced by the scavenger at the end of PEI.
159 void emitFrameOffset(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
160 DebugLoc DL, unsigned DestReg, unsigned SrcReg, int Offset,
161 const ARM64InstrInfo *TII,
162 MachineInstr::MIFlag = MachineInstr::NoFlags,
163 bool SetCPSR = false);
165 /// rewriteARM64FrameIndex - Rewrite MI to access 'Offset' bytes from the
166 /// FP. Return false if the offset could not be handled directly in MI, and
167 /// return the left-over portion by reference.
168 bool rewriteARM64FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
169 unsigned FrameReg, int &Offset,
170 const ARM64InstrInfo *TII);
172 /// \brief Use to report the frame offset status in isARM64FrameOffsetLegal.
173 enum ARM64FrameOffsetStatus {
174 ARM64FrameOffsetCannotUpdate = 0x0, ///< Offset cannot apply.
175 ARM64FrameOffsetIsLegal = 0x1, ///< Offset is legal.
176 ARM64FrameOffsetCanUpdate = 0x2 ///< Offset can apply, at least partly.
179 /// \brief Check if the @p Offset is a valid frame offset for @p MI.
180 /// The returned value reports the validity of the frame offset for @p MI.
181 /// It uses the values defined by ARM64FrameOffsetStatus for that.
182 /// If result == ARM64FrameOffsetCannotUpdate, @p MI cannot be updated to
184 /// If result & ARM64FrameOffsetIsLegal, @p Offset can completely be
185 /// rewriten in @p MI.
186 /// If result & ARM64FrameOffsetCanUpdate, @p Offset contains the
187 /// amount that is off the limit of the legal offset.
188 /// If set, @p OutUseUnscaledOp will contain the whether @p MI should be
189 /// turned into an unscaled operator, which opcode is in @p OutUnscaledOp.
190 /// If set, @p EmittableOffset contains the amount that can be set in @p MI
191 /// (possibly with @p OutUnscaledOp if OutUseUnscaledOp is true) and that
192 /// is a legal offset.
193 int isARM64FrameOffsetLegal(const MachineInstr &MI, int &Offset,
194 bool *OutUseUnscaledOp = NULL,
195 unsigned *OutUnscaledOp = NULL,
196 int *EmittableOffset = NULL);
198 static inline bool isUncondBranchOpcode(int Opc) { return Opc == ARM64::B; }
200 static inline bool isCondBranchOpcode(int Opc) {
215 static inline bool isIndirectBranchOpcode(int Opc) { return Opc == ARM64::BR; }
217 } // end namespace llvm