1 //===- ARM64InstrInfo.td - Describe the ARM64 Instructions -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // ARM64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM64-specific DAG Nodes.
18 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
19 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
22 SDTCisInt<0>, SDTCisVT<1, i32>]>;
24 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
25 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
31 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
32 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
39 def SDT_ARM64Brcond : SDTypeProfile<0, 3,
40 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
42 def SDT_ARM64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
43 def SDT_ARM64tbz : SDTypeProfile<0, 3, [SDTCisVT<0, i64>, SDTCisVT<1, i64>,
44 SDTCisVT<2, OtherVT>]>;
47 def SDT_ARM64CSel : SDTypeProfile<1, 4,
52 def SDT_ARM64FCmp : SDTypeProfile<0, 2,
55 def SDT_ARM64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
56 def SDT_ARM64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
57 def SDT_ARM64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
60 def SDT_ARM64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
61 def SDT_ARM64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
62 def SDT_ARM64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
63 SDTCisInt<2>, SDTCisInt<3>]>;
64 def SDT_ARM64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
65 def SDT_ARM64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
66 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
67 def SDT_ARM64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
69 def SDT_ARM64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
70 def SDT_ARM64fcmpz : SDTypeProfile<1, 1, []>;
71 def SDT_ARM64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
72 def SDT_ARM64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
74 def SDT_ARM64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
77 def SDT_ARM64TCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
78 def SDT_ARM64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
80 def SDT_ARM64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
82 def SDT_ARM64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
84 def SDT_ARM64WrapperLarge : SDTypeProfile<1, 4,
85 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
86 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
91 def ARM64adrp : SDNode<"ARM64ISD::ADRP", SDTIntUnaryOp, []>;
92 def ARM64addlow : SDNode<"ARM64ISD::ADDlow", SDTIntBinOp, []>;
93 def ARM64LOADgot : SDNode<"ARM64ISD::LOADgot", SDTIntUnaryOp>;
94 def ARM64callseq_start : SDNode<"ISD::CALLSEQ_START",
95 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
96 [SDNPHasChain, SDNPOutGlue]>;
97 def ARM64callseq_end : SDNode<"ISD::CALLSEQ_END",
98 SDCallSeqEnd<[ SDTCisVT<0, i32>,
100 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
101 def ARM64call : SDNode<"ARM64ISD::CALL",
102 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
103 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
105 def ARM64brcond : SDNode<"ARM64ISD::BRCOND", SDT_ARM64Brcond,
107 def ARM64cbz : SDNode<"ARM64ISD::CBZ", SDT_ARM64cbz,
109 def ARM64cbnz : SDNode<"ARM64ISD::CBNZ", SDT_ARM64cbz,
111 def ARM64tbz : SDNode<"ARM64ISD::TBZ", SDT_ARM64tbz,
113 def ARM64tbnz : SDNode<"ARM64ISD::TBNZ", SDT_ARM64tbz,
117 def ARM64csel : SDNode<"ARM64ISD::CSEL", SDT_ARM64CSel>;
118 def ARM64csinv : SDNode<"ARM64ISD::CSINV", SDT_ARM64CSel>;
119 def ARM64csneg : SDNode<"ARM64ISD::CSNEG", SDT_ARM64CSel>;
120 def ARM64csinc : SDNode<"ARM64ISD::CSINC", SDT_ARM64CSel>;
121 def ARM64retflag : SDNode<"ARM64ISD::RET_FLAG", SDTNone,
122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
123 def ARM64adc : SDNode<"ARM64ISD::ADC", SDTBinaryArithWithFlagsIn >;
124 def ARM64sbc : SDNode<"ARM64ISD::SBC", SDTBinaryArithWithFlagsIn>;
125 def ARM64add_flag : SDNode<"ARM64ISD::ADDS", SDTBinaryArithWithFlagsOut,
127 def ARM64sub_flag : SDNode<"ARM64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
128 def ARM64and_flag : SDNode<"ARM64ISD::ANDS", SDTBinaryArithWithFlagsOut>;
129 def ARM64adc_flag : SDNode<"ARM64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
130 def ARM64sbc_flag : SDNode<"ARM64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
132 def ARM64threadpointer : SDNode<"ARM64ISD::THREAD_POINTER", SDTPtrLeaf>;
134 def ARM64fcmp : SDNode<"ARM64ISD::FCMP", SDT_ARM64FCmp>;
136 def ARM64fmax : SDNode<"ARM64ISD::FMAX", SDTFPBinOp>;
137 def ARM64fmin : SDNode<"ARM64ISD::FMIN", SDTFPBinOp>;
139 def ARM64dup : SDNode<"ARM64ISD::DUP", SDT_ARM64Dup>;
140 def ARM64duplane8 : SDNode<"ARM64ISD::DUPLANE8", SDT_ARM64DupLane>;
141 def ARM64duplane16 : SDNode<"ARM64ISD::DUPLANE16", SDT_ARM64DupLane>;
142 def ARM64duplane32 : SDNode<"ARM64ISD::DUPLANE32", SDT_ARM64DupLane>;
143 def ARM64duplane64 : SDNode<"ARM64ISD::DUPLANE64", SDT_ARM64DupLane>;
145 def ARM64zip1 : SDNode<"ARM64ISD::ZIP1", SDT_ARM64Zip>;
146 def ARM64zip2 : SDNode<"ARM64ISD::ZIP2", SDT_ARM64Zip>;
147 def ARM64uzp1 : SDNode<"ARM64ISD::UZP1", SDT_ARM64Zip>;
148 def ARM64uzp2 : SDNode<"ARM64ISD::UZP2", SDT_ARM64Zip>;
149 def ARM64trn1 : SDNode<"ARM64ISD::TRN1", SDT_ARM64Zip>;
150 def ARM64trn2 : SDNode<"ARM64ISD::TRN2", SDT_ARM64Zip>;
152 def ARM64movi_edit : SDNode<"ARM64ISD::MOVIedit", SDT_ARM64MOVIedit>;
153 def ARM64movi_shift : SDNode<"ARM64ISD::MOVIshift", SDT_ARM64MOVIshift>;
154 def ARM64movi_msl : SDNode<"ARM64ISD::MOVImsl", SDT_ARM64MOVIshift>;
155 def ARM64mvni_shift : SDNode<"ARM64ISD::MVNIshift", SDT_ARM64MOVIshift>;
156 def ARM64mvni_msl : SDNode<"ARM64ISD::MVNImsl", SDT_ARM64MOVIshift>;
157 def ARM64movi : SDNode<"ARM64ISD::MOVI", SDT_ARM64MOVIedit>;
158 def ARM64fmov : SDNode<"ARM64ISD::FMOV", SDT_ARM64MOVIedit>;
160 def ARM64rev16 : SDNode<"ARM64ISD::REV16", SDT_ARM64UnaryVec>;
161 def ARM64rev32 : SDNode<"ARM64ISD::REV32", SDT_ARM64UnaryVec>;
162 def ARM64rev64 : SDNode<"ARM64ISD::REV64", SDT_ARM64UnaryVec>;
163 def ARM64ext : SDNode<"ARM64ISD::EXT", SDT_ARM64ExtVec>;
165 def ARM64vashr : SDNode<"ARM64ISD::VASHR", SDT_ARM64vshift>;
166 def ARM64vlshr : SDNode<"ARM64ISD::VLSHR", SDT_ARM64vshift>;
167 def ARM64vshl : SDNode<"ARM64ISD::VSHL", SDT_ARM64vshift>;
168 def ARM64sqshli : SDNode<"ARM64ISD::SQSHL_I", SDT_ARM64vshift>;
169 def ARM64uqshli : SDNode<"ARM64ISD::UQSHL_I", SDT_ARM64vshift>;
170 def ARM64sqshlui : SDNode<"ARM64ISD::SQSHLU_I", SDT_ARM64vshift>;
171 def ARM64srshri : SDNode<"ARM64ISD::SRSHR_I", SDT_ARM64vshift>;
172 def ARM64urshri : SDNode<"ARM64ISD::URSHR_I", SDT_ARM64vshift>;
174 def ARM64not: SDNode<"ARM64ISD::NOT", SDT_ARM64unvec>;
175 def ARM64bit: SDNode<"ARM64ISD::BIT", SDT_ARM64trivec>;
177 def ARM64cmeq: SDNode<"ARM64ISD::CMEQ", SDT_ARM64binvec>;
178 def ARM64cmge: SDNode<"ARM64ISD::CMGE", SDT_ARM64binvec>;
179 def ARM64cmgt: SDNode<"ARM64ISD::CMGT", SDT_ARM64binvec>;
180 def ARM64cmhi: SDNode<"ARM64ISD::CMHI", SDT_ARM64binvec>;
181 def ARM64cmhs: SDNode<"ARM64ISD::CMHS", SDT_ARM64binvec>;
183 def ARM64fcmeq: SDNode<"ARM64ISD::FCMEQ", SDT_ARM64fcmp>;
184 def ARM64fcmge: SDNode<"ARM64ISD::FCMGE", SDT_ARM64fcmp>;
185 def ARM64fcmgt: SDNode<"ARM64ISD::FCMGT", SDT_ARM64fcmp>;
187 def ARM64cmeqz: SDNode<"ARM64ISD::CMEQz", SDT_ARM64unvec>;
188 def ARM64cmgez: SDNode<"ARM64ISD::CMGEz", SDT_ARM64unvec>;
189 def ARM64cmgtz: SDNode<"ARM64ISD::CMGTz", SDT_ARM64unvec>;
190 def ARM64cmlez: SDNode<"ARM64ISD::CMLEz", SDT_ARM64unvec>;
191 def ARM64cmltz: SDNode<"ARM64ISD::CMLTz", SDT_ARM64unvec>;
192 def ARM64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
193 (ARM64not (ARM64cmeqz (and node:$LHS, node:$RHS)))>;
195 def ARM64fcmeqz: SDNode<"ARM64ISD::FCMEQz", SDT_ARM64fcmpz>;
196 def ARM64fcmgez: SDNode<"ARM64ISD::FCMGEz", SDT_ARM64fcmpz>;
197 def ARM64fcmgtz: SDNode<"ARM64ISD::FCMGTz", SDT_ARM64fcmpz>;
198 def ARM64fcmlez: SDNode<"ARM64ISD::FCMLEz", SDT_ARM64fcmpz>;
199 def ARM64fcmltz: SDNode<"ARM64ISD::FCMLTz", SDT_ARM64fcmpz>;
201 def ARM64bici: SDNode<"ARM64ISD::BICi", SDT_ARM64vecimm>;
202 def ARM64orri: SDNode<"ARM64ISD::ORRi", SDT_ARM64vecimm>;
204 def ARM64neg : SDNode<"ARM64ISD::NEG", SDT_ARM64unvec>;
206 def ARM64tcret: SDNode<"ARM64ISD::TC_RETURN", SDT_ARM64TCRET,
207 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
209 def ARM64Prefetch : SDNode<"ARM64ISD::PREFETCH", SDT_ARM64PREFETCH,
210 [SDNPHasChain, SDNPSideEffect]>;
212 def ARM64sitof: SDNode<"ARM64ISD::SITOF", SDT_ARM64ITOF>;
213 def ARM64uitof: SDNode<"ARM64ISD::UITOF", SDT_ARM64ITOF>;
215 def ARM64tlsdesc_call : SDNode<"ARM64ISD::TLSDESC_CALL", SDT_ARM64TLSDescCall,
216 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
219 def ARM64WrapperLarge : SDNode<"ARM64ISD::WrapperLarge", SDT_ARM64WrapperLarge>;
222 //===----------------------------------------------------------------------===//
224 //===----------------------------------------------------------------------===//
226 // ARM64 Instruction Predicate Definitions.
228 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
229 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
230 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
231 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
232 def ForCodeSize : Predicate<"ForCodeSize">;
233 def NotForCodeSize : Predicate<"!ForCodeSize">;
235 include "ARM64InstrFormats.td"
237 //===----------------------------------------------------------------------===//
239 //===----------------------------------------------------------------------===//
240 // Miscellaneous instructions.
241 //===----------------------------------------------------------------------===//
243 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
244 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
245 [(ARM64callseq_start timm:$amt)]>;
246 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
247 [(ARM64callseq_end timm:$amt1, timm:$amt2)]>;
248 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
250 let isReMaterializable = 1, isCodeGenOnly = 1 in {
251 // FIXME: The following pseudo instructions are only needed because remat
252 // cannot handle multiple instructions. When that changes, they can be
253 // removed, along with the ARM64Wrapper node.
255 let AddedComplexity = 10 in
256 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
257 [(set GPR64:$dst, (ARM64LOADgot tglobaladdr:$addr))]>,
260 // The MOVaddr instruction should match only when the add is not folded
261 // into a load or store address.
263 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
264 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaladdr:$hi),
265 tglobaladdr:$low))]>,
266 Sched<[WriteAdrAdr]>;
268 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
269 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tjumptable:$hi),
271 Sched<[WriteAdrAdr]>;
273 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
274 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tconstpool:$hi),
276 Sched<[WriteAdrAdr]>;
278 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
279 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tblockaddress:$hi),
280 tblockaddress:$low))]>,
281 Sched<[WriteAdrAdr]>;
283 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
284 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaltlsaddr:$hi),
285 tglobaltlsaddr:$low))]>,
286 Sched<[WriteAdrAdr]>;
288 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
289 [(set GPR64:$dst, (ARM64addlow (ARM64adrp texternalsym:$hi),
290 texternalsym:$low))]>,
291 Sched<[WriteAdrAdr]>;
293 } // isReMaterializable, isCodeGenOnly
295 def : Pat<(ARM64LOADgot tglobaltlsaddr:$addr),
296 (LOADgot tglobaltlsaddr:$addr)>;
298 def : Pat<(ARM64LOADgot texternalsym:$addr),
299 (LOADgot texternalsym:$addr)>;
301 def : Pat<(ARM64LOADgot tconstpool:$addr),
302 (LOADgot tconstpool:$addr)>;
304 //===----------------------------------------------------------------------===//
305 // System instructions.
306 //===----------------------------------------------------------------------===//
308 def HINT : HintI<"hint">;
309 def : InstAlias<"nop", (HINT 0b000)>;
310 def : InstAlias<"yield",(HINT 0b001)>;
311 def : InstAlias<"wfe", (HINT 0b010)>;
312 def : InstAlias<"wfi", (HINT 0b011)>;
313 def : InstAlias<"sev", (HINT 0b100)>;
314 def : InstAlias<"sevl", (HINT 0b101)>;
316 // As far as LLVM is concerned this writes to the system's exclusive monitors.
317 let mayLoad = 1, mayStore = 1 in
318 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
320 def DMB : CRmSystemI<barrier_op, 0b101, "dmb">;
321 def DSB : CRmSystemI<barrier_op, 0b100, "dsb">;
322 def ISB : CRmSystemI<barrier_op, 0b110, "isb">;
323 def : InstAlias<"clrex", (CLREX 0xf)>;
324 def : InstAlias<"isb", (ISB 0xf)>;
328 def MSRcpsr: MSRcpsrI;
330 // The thread pointer (on Linux, at least, where this has been implemented) is
332 def : Pat<(ARM64threadpointer), (MRS 0xde82)>;
334 // Generic system instructions
335 def SYSxt : SystemXtI<0, "sys">;
336 def SYSLxt : SystemLXtI<1, "sysl">;
338 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
339 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
340 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
342 //===----------------------------------------------------------------------===//
343 // Move immediate instructions.
344 //===----------------------------------------------------------------------===//
346 defm MOVK : InsertImmediate<0b11, "movk">;
347 defm MOVN : MoveImmediate<0b00, "movn">;
349 let PostEncoderMethod = "fixMOVZ" in
350 defm MOVZ : MoveImmediate<0b10, "movz">;
352 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
353 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
354 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
355 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
356 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
357 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
359 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
360 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
361 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
362 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
364 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
365 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
366 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
367 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
369 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g3:$sym, 48)>;
370 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g2:$sym, 32)>;
371 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
372 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
374 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
375 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
376 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
378 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g2:$sym, 32)>;
379 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
380 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
382 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
383 isAsCheapAsAMove = 1 in {
384 // FIXME: The following pseudo instructions are only needed because remat
385 // cannot handle multiple instructions. When that changes, we can select
386 // directly to the real instructions and get rid of these pseudos.
389 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
390 [(set GPR32:$dst, imm:$src)]>,
393 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
394 [(set GPR64:$dst, imm:$src)]>,
396 } // isReMaterializable, isCodeGenOnly
398 def : Pat<(ARM64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
399 tglobaladdr:$g1, tglobaladdr:$g0),
400 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
401 tglobaladdr:$g2, 32),
402 tglobaladdr:$g1, 16),
403 tglobaladdr:$g0, 0)>;
405 def : Pat<(ARM64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
406 tblockaddress:$g1, tblockaddress:$g0),
407 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
408 tblockaddress:$g2, 32),
409 tblockaddress:$g1, 16),
410 tblockaddress:$g0, 0)>;
412 def : Pat<(ARM64WrapperLarge tconstpool:$g3, tconstpool:$g2,
413 tconstpool:$g1, tconstpool:$g0),
414 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
420 //===----------------------------------------------------------------------===//
421 // Arithmetic instructions.
422 //===----------------------------------------------------------------------===//
424 // Add/subtract with carry.
425 defm ADC : AddSubCarry<0, "adc", "adcs", ARM64adc, ARM64adc_flag>;
426 defm SBC : AddSubCarry<1, "sbc", "sbcs", ARM64sbc, ARM64sbc_flag>;
428 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
429 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
430 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
431 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
434 defm ADD : AddSub<0, "add", add>;
435 defm SUB : AddSub<1, "sub">;
437 defm ADDS : AddSubS<0, "adds", ARM64add_flag>;
438 defm SUBS : AddSubS<1, "subs", ARM64sub_flag>;
440 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
441 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
442 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
443 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
444 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
445 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
446 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
447 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
448 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
449 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
450 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
451 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
452 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
453 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
454 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
455 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
456 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
458 // Because of the immediate format for add/sub-imm instructions, the
459 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
460 // These patterns capture that transformation.
461 let AddedComplexity = 1 in {
462 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
463 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
464 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
465 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
466 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
467 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
468 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
469 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
472 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
473 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
474 def : InstAlias<"neg $dst, $src, $shift",
475 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift:$shift)>;
476 def : InstAlias<"neg $dst, $src, $shift",
477 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift:$shift)>;
479 // Because of the immediate format for add/sub-imm instructions, the
480 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
481 // These patterns capture that transformation.
482 let AddedComplexity = 1 in {
483 def : Pat<(ARM64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
484 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
485 def : Pat<(ARM64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
486 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
487 def : Pat<(ARM64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
488 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
489 def : Pat<(ARM64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
490 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
493 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
494 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
495 def : InstAlias<"negs $dst, $src, $shift",
496 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift:$shift)>;
497 def : InstAlias<"negs $dst, $src, $shift",
498 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift:$shift)>;
500 // Unsigned/Signed divide
501 defm UDIV : Div<0, "udiv", udiv>;
502 defm SDIV : Div<1, "sdiv", sdiv>;
503 let isCodeGenOnly = 1 in {
504 defm UDIV_Int : Div<0, "udiv", int_arm64_udiv>;
505 defm SDIV_Int : Div<1, "sdiv", int_arm64_sdiv>;
509 defm ASRV : Shift<0b10, "asrv", sra>;
510 defm LSLV : Shift<0b00, "lslv", shl>;
511 defm LSRV : Shift<0b01, "lsrv", srl>;
512 defm RORV : Shift<0b11, "rorv", rotr>;
514 def : ShiftAlias<"asr", ASRVWr, GPR32>;
515 def : ShiftAlias<"asr", ASRVXr, GPR64>;
516 def : ShiftAlias<"lsl", LSLVWr, GPR32>;
517 def : ShiftAlias<"lsl", LSLVXr, GPR64>;
518 def : ShiftAlias<"lsr", LSRVWr, GPR32>;
519 def : ShiftAlias<"lsr", LSRVXr, GPR64>;
520 def : ShiftAlias<"ror", RORVWr, GPR32>;
521 def : ShiftAlias<"ror", RORVXr, GPR64>;
524 let AddedComplexity = 7 in {
525 defm MADD : MulAccum<0, "madd", add>;
526 defm MSUB : MulAccum<1, "msub", sub>;
528 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
529 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
530 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
531 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
533 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
534 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
535 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
536 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
537 } // AddedComplexity = 7
539 let AddedComplexity = 5 in {
540 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
541 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
542 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
543 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
545 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
546 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
547 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
548 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
550 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
551 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
552 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
553 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
554 } // AddedComplexity = 5
556 def : MulAccumWAlias<"mul", MADDWrrr>;
557 def : MulAccumXAlias<"mul", MADDXrrr>;
558 def : MulAccumWAlias<"mneg", MSUBWrrr>;
559 def : MulAccumXAlias<"mneg", MSUBXrrr>;
560 def : WideMulAccumAlias<"smull", SMADDLrrr>;
561 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
562 def : WideMulAccumAlias<"umull", UMADDLrrr>;
563 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
566 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
567 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
570 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_arm64_crc32b, "crc32b">;
571 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_arm64_crc32h, "crc32h">;
572 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_arm64_crc32w, "crc32w">;
573 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_arm64_crc32x, "crc32x">;
575 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_arm64_crc32cb, "crc32cb">;
576 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_arm64_crc32ch, "crc32ch">;
577 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_arm64_crc32cw, "crc32cw">;
578 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_arm64_crc32cx, "crc32cx">;
581 //===----------------------------------------------------------------------===//
582 // Logical instructions.
583 //===----------------------------------------------------------------------===//
586 defm ANDS : LogicalImmS<0b11, "ands", ARM64and_flag>;
587 defm AND : LogicalImm<0b00, "and", and>;
588 defm EOR : LogicalImm<0b10, "eor", xor>;
589 defm ORR : LogicalImm<0b01, "orr", or>;
591 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
592 logical_imm32:$imm)>;
593 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
594 logical_imm64:$imm)>;
598 defm ANDS : LogicalRegS<0b11, 0, "ands">;
599 defm BICS : LogicalRegS<0b11, 1, "bics">;
600 defm AND : LogicalReg<0b00, 0, "and", and>;
601 defm BIC : LogicalReg<0b00, 1, "bic",
602 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
603 defm EON : LogicalReg<0b10, 1, "eon",
604 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
605 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
606 defm ORN : LogicalReg<0b01, 1, "orn",
607 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
608 defm ORR : LogicalReg<0b01, 0, "orr", or>;
610 def : InstAlias<"tst $src1, $src2",
611 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
612 def : InstAlias<"tst $src1, $src2",
613 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>;
615 def : InstAlias<"tst $src1, $src2",
616 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>;
617 def : InstAlias<"tst $src1, $src2",
618 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>;
620 def : InstAlias<"tst $src1, $src2, $sh",
621 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift:$sh)>;
622 def : InstAlias<"tst $src1, $src2, $sh",
623 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift:$sh)>;
625 def : InstAlias<"mvn $Wd, $Wm",
626 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0)>;
627 def : InstAlias<"mvn $Xd, $Xm",
628 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>;
630 def : InstAlias<"mvn $Wd, $Wm, $sh",
631 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift:$sh)>;
632 def : InstAlias<"mvn $Xd, $Xm, $sh",
633 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift:$sh)>;
635 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
636 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
639 //===----------------------------------------------------------------------===//
640 // One operand data processing instructions.
641 //===----------------------------------------------------------------------===//
643 defm CLS : OneOperandData<0b101, "cls">;
644 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
645 defm RBIT : OneOperandData<0b000, "rbit">;
646 def REV16Wr : OneWRegData<0b001, "rev16",
647 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
648 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
650 def : Pat<(cttz GPR32:$Rn),
651 (CLZWr (RBITWr GPR32:$Rn))>;
652 def : Pat<(cttz GPR64:$Rn),
653 (CLZXr (RBITXr GPR64:$Rn))>;
654 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
657 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
661 // Unlike the other one operand instructions, the instructions with the "rev"
662 // mnemonic do *not* just different in the size bit, but actually use different
663 // opcode bits for the different sizes.
664 def REVWr : OneWRegData<0b010, "rev", bswap>;
665 def REVXr : OneXRegData<0b011, "rev", bswap>;
666 def REV32Xr : OneXRegData<0b010, "rev32",
667 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
669 //===----------------------------------------------------------------------===//
670 // Bitfield immediate extraction instruction.
671 //===----------------------------------------------------------------------===//
672 let neverHasSideEffects = 1 in
673 defm EXTR : ExtractImm<"extr">;
674 def : InstAlias<"ror $dst, $src, $shift",
675 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
676 def : InstAlias<"ror $dst, $src, $shift",
677 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
679 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
680 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
681 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
682 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
684 //===----------------------------------------------------------------------===//
685 // Other bitfield immediate instructions.
686 //===----------------------------------------------------------------------===//
687 let neverHasSideEffects = 1 in {
688 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
689 defm SBFM : BitfieldImm<0b00, "sbfm">;
690 defm UBFM : BitfieldImm<0b10, "ubfm">;
693 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
694 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
695 return CurDAG->getTargetConstant(enc, MVT::i64);
698 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
699 uint64_t enc = 31 - N->getZExtValue();
700 return CurDAG->getTargetConstant(enc, MVT::i64);
703 // min(7, 31 - shift_amt)
704 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
705 uint64_t enc = 31 - N->getZExtValue();
706 enc = enc > 7 ? 7 : enc;
707 return CurDAG->getTargetConstant(enc, MVT::i64);
710 // min(15, 31 - shift_amt)
711 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
712 uint64_t enc = 31 - N->getZExtValue();
713 enc = enc > 15 ? 15 : enc;
714 return CurDAG->getTargetConstant(enc, MVT::i64);
717 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
718 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
719 return CurDAG->getTargetConstant(enc, MVT::i64);
722 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
723 uint64_t enc = 63 - N->getZExtValue();
724 return CurDAG->getTargetConstant(enc, MVT::i64);
727 // min(7, 63 - shift_amt)
728 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
729 uint64_t enc = 63 - N->getZExtValue();
730 enc = enc > 7 ? 7 : enc;
731 return CurDAG->getTargetConstant(enc, MVT::i64);
734 // min(15, 63 - shift_amt)
735 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
736 uint64_t enc = 63 - N->getZExtValue();
737 enc = enc > 15 ? 15 : enc;
738 return CurDAG->getTargetConstant(enc, MVT::i64);
741 // min(31, 63 - shift_amt)
742 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
743 uint64_t enc = 63 - N->getZExtValue();
744 enc = enc > 31 ? 31 : enc;
745 return CurDAG->getTargetConstant(enc, MVT::i64);
748 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
749 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
750 (i64 (i32shift_b imm0_31:$imm)))>;
751 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
752 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
753 (i64 (i64shift_b imm0_63:$imm)))>;
755 let AddedComplexity = 10 in {
756 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
757 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
758 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
759 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
762 def : InstAlias<"asr $dst, $src, $shift",
763 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
764 def : InstAlias<"asr $dst, $src, $shift",
765 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
766 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
767 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
768 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
769 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
770 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
772 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
773 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
774 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
775 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
777 def : InstAlias<"lsr $dst, $src, $shift",
778 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
779 def : InstAlias<"lsr $dst, $src, $shift",
780 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
781 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
782 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
783 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
784 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
785 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
787 //===----------------------------------------------------------------------===//
788 // Conditionally set flags instructions.
789 //===----------------------------------------------------------------------===//
790 defm CCMN : CondSetFlagsImm<0, "ccmn">;
791 defm CCMP : CondSetFlagsImm<1, "ccmp">;
793 defm CCMN : CondSetFlagsReg<0, "ccmn">;
794 defm CCMP : CondSetFlagsReg<1, "ccmp">;
796 //===----------------------------------------------------------------------===//
797 // Conditional select instructions.
798 //===----------------------------------------------------------------------===//
799 defm CSEL : CondSelect<0, 0b00, "csel">;
801 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
802 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
803 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
804 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
806 def : Pat<(ARM64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
807 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
808 def : Pat<(ARM64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
809 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
810 def : Pat<(ARM64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
811 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
812 def : Pat<(ARM64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
813 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
814 def : Pat<(ARM64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
815 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
816 def : Pat<(ARM64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
817 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
819 def : Pat<(ARM64csel (i32 0), (i32 1), (i32 imm:$cc), CPSR),
820 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
821 def : Pat<(ARM64csel (i64 0), (i64 1), (i32 imm:$cc), CPSR),
822 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
823 def : Pat<(ARM64csel (i32 0), (i32 -1), (i32 imm:$cc), CPSR),
824 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
825 def : Pat<(ARM64csel (i64 0), (i64 -1), (i32 imm:$cc), CPSR),
826 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
828 // The inverse of the condition code from the alias instruction is what is used
829 // in the aliased instruction. The parser all ready inverts the condition code
830 // for these aliases.
831 // FIXME: Is this the correct way to handle these aliases?
832 def : InstAlias<"cset $dst, $cc", (CSINCWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
833 def : InstAlias<"cset $dst, $cc", (CSINCXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
835 def : InstAlias<"csetm $dst, $cc", (CSINVWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
836 def : InstAlias<"csetm $dst, $cc", (CSINVXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
838 def : InstAlias<"cinc $dst, $src, $cc",
839 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
840 def : InstAlias<"cinc $dst, $src, $cc",
841 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
843 def : InstAlias<"cinv $dst, $src, $cc",
844 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
845 def : InstAlias<"cinv $dst, $src, $cc",
846 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
848 def : InstAlias<"cneg $dst, $src, $cc",
849 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
850 def : InstAlias<"cneg $dst, $src, $cc",
851 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
853 //===----------------------------------------------------------------------===//
854 // PC-relative instructions.
855 //===----------------------------------------------------------------------===//
856 let isReMaterializable = 1 in {
857 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
858 def ADR : ADRI<0, "adr", adrlabel, []>;
859 } // neverHasSideEffects = 1
861 def ADRP : ADRI<1, "adrp", adrplabel,
862 [(set GPR64:$Xd, (ARM64adrp tglobaladdr:$label))]>;
863 } // isReMaterializable = 1
865 // page address of a constant pool entry, block address
866 def : Pat<(ARM64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
867 def : Pat<(ARM64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
869 //===----------------------------------------------------------------------===//
870 // Unconditional branch (register) instructions.
871 //===----------------------------------------------------------------------===//
873 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
874 def RET : BranchReg<0b0010, "ret", []>;
875 def DRPS : SpecialReturn<0b0101, "drps">;
876 def ERET : SpecialReturn<0b0100, "eret">;
877 } // isReturn = 1, isTerminator = 1, isBarrier = 1
879 // Default to the LR register.
880 def : InstAlias<"ret", (RET LR)>;
882 let isCall = 1, Defs = [LR], Uses = [SP] in {
883 def BLR : BranchReg<0b0001, "blr", [(ARM64call GPR64:$Rn)]>;
886 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
887 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
888 } // isBranch, isTerminator, isBarrier, isIndirectBranch
890 // Create a separate pseudo-instruction for codegen to use so that we don't
891 // flag lr as used in every function. It'll be restored before the RET by the
892 // epilogue if it's legitimately used.
893 def RET_ReallyLR : Pseudo<(outs), (ins), [(ARM64retflag)]> {
894 let isTerminator = 1;
899 // This is a directive-like pseudo-instruction. The purpose is to insert an
900 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
901 // (which in the usual case is a BLR).
902 let hasSideEffects = 1 in
903 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
904 let AsmString = ".tlsdesccall $sym";
907 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
908 // gets expanded to two MCInsts during lowering.
909 let isCall = 1, Defs = [LR] in
911 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
912 [(ARM64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
914 def : Pat<(ARM64tlsdesc_call GPR64:$dest, texternalsym:$sym),
915 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
916 //===----------------------------------------------------------------------===//
917 // Conditional branch (immediate) instruction.
918 //===----------------------------------------------------------------------===//
919 def Bcc : BranchCond;
921 //===----------------------------------------------------------------------===//
922 // Compare-and-branch instructions.
923 //===----------------------------------------------------------------------===//
924 defm CBZ : CmpBranch<0, "cbz", ARM64cbz>;
925 defm CBNZ : CmpBranch<1, "cbnz", ARM64cbnz>;
927 //===----------------------------------------------------------------------===//
928 // Test-bit-and-branch instructions.
929 //===----------------------------------------------------------------------===//
930 def TBZ : TestBranch<0, "tbz", ARM64tbz>;
931 def TBNZ : TestBranch<1, "tbnz", ARM64tbnz>;
933 //===----------------------------------------------------------------------===//
934 // Unconditional branch (immediate) instructions.
935 //===----------------------------------------------------------------------===//
936 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
937 def B : BranchImm<0, "b", [(br bb:$addr)]>;
938 } // isBranch, isTerminator, isBarrier
940 let isCall = 1, Defs = [LR], Uses = [SP] in {
941 def BL : CallImm<1, "bl", [(ARM64call tglobaladdr:$addr)]>;
943 def : Pat<(ARM64call texternalsym:$func), (BL texternalsym:$func)>;
945 //===----------------------------------------------------------------------===//
946 // Exception generation instructions.
947 //===----------------------------------------------------------------------===//
948 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
949 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
950 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
951 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
952 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
953 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
954 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
955 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
957 // DCPSn defaults to an immediate operand of zero if unspecified.
958 def : InstAlias<"dcps1", (DCPS1 0)>;
959 def : InstAlias<"dcps2", (DCPS2 0)>;
960 def : InstAlias<"dcps3", (DCPS3 0)>;
962 //===----------------------------------------------------------------------===//
963 // Load instructions.
964 //===----------------------------------------------------------------------===//
966 // Pair (indexed, offset)
967 def LDPWi : LoadPairOffset<0b00, 0, GPR32, am_indexed32simm7, "ldp">;
968 def LDPXi : LoadPairOffset<0b10, 0, GPR64, am_indexed64simm7, "ldp">;
969 def LDPSi : LoadPairOffset<0b00, 1, FPR32, am_indexed32simm7, "ldp">;
970 def LDPDi : LoadPairOffset<0b01, 1, FPR64, am_indexed64simm7, "ldp">;
971 def LDPQi : LoadPairOffset<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
973 def LDPSWi : LoadPairOffset<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
975 // Pair (pre-indexed)
976 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "ldp">;
977 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "ldp">;
978 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "ldp">;
979 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "ldp">;
980 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "ldp">;
982 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7_wb, "ldpsw">;
984 // Pair (post-indexed)
985 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
986 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
987 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
988 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
989 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
991 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
994 // Pair (no allocate)
995 def LDNPWi : LoadPairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "ldnp">;
996 def LDNPXi : LoadPairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "ldnp">;
997 def LDNPSi : LoadPairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "ldnp">;
998 def LDNPDi : LoadPairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "ldnp">;
999 def LDNPQi : LoadPairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "ldnp">;
1002 // (register offset)
1005 let AddedComplexity = 10 in {
1007 def LDRBBro : Load8RO<0b00, 0, 0b01, GPR32, "ldrb",
1008 [(set GPR32:$Rt, (zextloadi8 ro_indexed8:$addr))]>;
1009 def LDRHHro : Load16RO<0b01, 0, 0b01, GPR32, "ldrh",
1010 [(set GPR32:$Rt, (zextloadi16 ro_indexed16:$addr))]>;
1011 def LDRWro : Load32RO<0b10, 0, 0b01, GPR32, "ldr",
1012 [(set GPR32:$Rt, (load ro_indexed32:$addr))]>;
1013 def LDRXro : Load64RO<0b11, 0, 0b01, GPR64, "ldr",
1014 [(set GPR64:$Rt, (load ro_indexed64:$addr))]>;
1017 def LDRBro : Load8RO<0b00, 1, 0b01, FPR8, "ldr",
1018 [(set FPR8:$Rt, (load ro_indexed8:$addr))]>;
1019 def LDRHro : Load16RO<0b01, 1, 0b01, FPR16, "ldr",
1020 [(set FPR16:$Rt, (load ro_indexed16:$addr))]>;
1021 def LDRSro : Load32RO<0b10, 1, 0b01, FPR32, "ldr",
1022 [(set (f32 FPR32:$Rt), (load ro_indexed32:$addr))]>;
1023 def LDRDro : Load64RO<0b11, 1, 0b01, FPR64, "ldr",
1024 [(set (f64 FPR64:$Rt), (load ro_indexed64:$addr))]>;
1025 def LDRQro : Load128RO<0b00, 1, 0b11, FPR128, "ldr", []> {
1029 // For regular load, we do not have any alignment requirement.
1030 // Thus, it is safe to directly map the vector loads with interesting
1031 // addressing modes.
1032 // FIXME: We could do the same for bitconvert to floating point vectors.
1033 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1034 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1035 (LDRBro ro_indexed8:$addr), bsub)>;
1036 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1037 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1038 (LDRBro ro_indexed8:$addr), bsub)>;
1039 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1040 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1041 (LDRHro ro_indexed16:$addr), hsub)>;
1042 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1043 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1044 (LDRHro ro_indexed16:$addr), hsub)>;
1045 def : Pat <(v2i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1046 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1047 (LDRSro ro_indexed32:$addr), ssub)>;
1048 def : Pat <(v4i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1049 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1050 (LDRSro ro_indexed32:$addr), ssub)>;
1051 def : Pat <(v1i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1052 (LDRDro ro_indexed64:$addr)>;
1053 def : Pat <(v2i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1054 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1055 (LDRDro ro_indexed64:$addr), dsub)>;
1057 // Match all load 64 bits width whose type is compatible with FPR64
1058 def : Pat<(v2f32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1059 def : Pat<(v1f64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1060 def : Pat<(v8i8 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1061 def : Pat<(v4i16 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1062 def : Pat<(v2i32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1063 def : Pat<(v1i64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1065 // Match all load 128 bits width whose type is compatible with FPR128
1066 def : Pat<(v4f32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1067 def : Pat<(v2f64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1068 def : Pat<(v16i8 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1069 def : Pat<(v8i16 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1070 def : Pat<(v4i32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1071 def : Pat<(v2i64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1072 def : Pat<(f128 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1074 // Load sign-extended half-word
1075 def LDRSHWro : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh",
1076 [(set GPR32:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1077 def LDRSHXro : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh",
1078 [(set GPR64:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1080 // Load sign-extended byte
1081 def LDRSBWro : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb",
1082 [(set GPR32:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1083 def LDRSBXro : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb",
1084 [(set GPR64:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1086 // Load sign-extended word
1087 def LDRSWro : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw",
1088 [(set GPR64:$Rt, (sextloadi32 ro_indexed32:$addr))]>;
1091 def PRFMro : PrefetchRO<0b11, 0, 0b10, "prfm",
1092 [(ARM64Prefetch imm:$Rt, ro_indexed64:$addr)]>;
1095 def : Pat<(i64 (zextloadi8 ro_indexed8:$addr)),
1096 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1097 def : Pat<(i64 (zextloadi16 ro_indexed16:$addr)),
1098 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1100 // zextloadi1 -> zextloadi8
1101 def : Pat<(i32 (zextloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1102 def : Pat<(i64 (zextloadi1 ro_indexed8:$addr)),
1103 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1105 // extload -> zextload
1106 def : Pat<(i32 (extloadi16 ro_indexed16:$addr)), (LDRHHro ro_indexed16:$addr)>;
1107 def : Pat<(i32 (extloadi8 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1108 def : Pat<(i32 (extloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1109 def : Pat<(i64 (extloadi32 ro_indexed32:$addr)),
1110 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1111 def : Pat<(i64 (extloadi16 ro_indexed16:$addr)),
1112 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1113 def : Pat<(i64 (extloadi8 ro_indexed8:$addr)),
1114 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1115 def : Pat<(i64 (extloadi1 ro_indexed8:$addr)),
1116 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1118 } // AddedComplexity = 10
1121 // (unsigned immediate)
1123 def LDRXui : LoadUI<0b11, 0, 0b01, GPR64, am_indexed64, "ldr",
1124 [(set GPR64:$Rt, (load am_indexed64:$addr))]>;
1125 def LDRWui : LoadUI<0b10, 0, 0b01, GPR32, am_indexed32, "ldr",
1126 [(set GPR32:$Rt, (load am_indexed32:$addr))]>;
1127 def LDRBui : LoadUI<0b00, 1, 0b01, FPR8, am_indexed8, "ldr",
1128 [(set FPR8:$Rt, (load am_indexed8:$addr))]>;
1129 def LDRHui : LoadUI<0b01, 1, 0b01, FPR16, am_indexed16, "ldr",
1130 [(set FPR16:$Rt, (load am_indexed16:$addr))]>;
1131 def LDRSui : LoadUI<0b10, 1, 0b01, FPR32, am_indexed32, "ldr",
1132 [(set (f32 FPR32:$Rt), (load am_indexed32:$addr))]>;
1133 def LDRDui : LoadUI<0b11, 1, 0b01, FPR64, am_indexed64, "ldr",
1134 [(set (f64 FPR64:$Rt), (load am_indexed64:$addr))]>;
1135 def LDRQui : LoadUI<0b00, 1, 0b11, FPR128, am_indexed128, "ldr",
1136 [(set (f128 FPR128:$Rt), (load am_indexed128:$addr))]>;
1138 // For regular load, we do not have any alignment requirement.
1139 // Thus, it is safe to directly map the vector loads with interesting
1140 // addressing modes.
1141 // FIXME: We could do the same for bitconvert to floating point vectors.
1142 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1143 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1144 (LDRBui am_indexed8:$addr), bsub)>;
1145 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1146 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1147 (LDRBui am_indexed8:$addr), bsub)>;
1148 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1149 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1150 (LDRHui am_indexed16:$addr), hsub)>;
1151 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1152 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1153 (LDRHui am_indexed16:$addr), hsub)>;
1154 def : Pat <(v2i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1155 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1156 (LDRSui am_indexed32:$addr), ssub)>;
1157 def : Pat <(v4i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1158 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1159 (LDRSui am_indexed32:$addr), ssub)>;
1160 def : Pat <(v1i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1161 (LDRDui am_indexed64:$addr)>;
1162 def : Pat <(v2i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1163 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1164 (LDRDui am_indexed64:$addr), dsub)>;
1166 // Match all load 64 bits width whose type is compatible with FPR64
1167 def : Pat<(v2f32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1168 def : Pat<(v1f64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1169 def : Pat<(v8i8 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1170 def : Pat<(v4i16 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1171 def : Pat<(v2i32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1172 def : Pat<(v1i64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1174 // Match all load 128 bits width whose type is compatible with FPR128
1175 def : Pat<(v4f32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1176 def : Pat<(v2f64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1177 def : Pat<(v16i8 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1178 def : Pat<(v8i16 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1179 def : Pat<(v4i32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1180 def : Pat<(v2i64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1181 def : Pat<(f128 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1183 def LDRHHui : LoadUI<0b01, 0, 0b01, GPR32, am_indexed16, "ldrh",
1184 [(set GPR32:$Rt, (zextloadi16 am_indexed16:$addr))]>;
1185 def LDRBBui : LoadUI<0b00, 0, 0b01, GPR32, am_indexed8, "ldrb",
1186 [(set GPR32:$Rt, (zextloadi8 am_indexed8:$addr))]>;
1188 def : Pat<(i64 (zextloadi8 am_indexed8:$addr)),
1189 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1190 def : Pat<(i64 (zextloadi16 am_indexed16:$addr)),
1191 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1193 // zextloadi1 -> zextloadi8
1194 def : Pat<(i32 (zextloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1195 def : Pat<(i64 (zextloadi1 am_indexed8:$addr)),
1196 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1198 // extload -> zextload
1199 def : Pat<(i32 (extloadi16 am_indexed16:$addr)), (LDRHHui am_indexed16:$addr)>;
1200 def : Pat<(i32 (extloadi8 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1201 def : Pat<(i32 (extloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1202 def : Pat<(i64 (extloadi32 am_indexed32:$addr)),
1203 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1204 def : Pat<(i64 (extloadi16 am_indexed16:$addr)),
1205 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1206 def : Pat<(i64 (extloadi8 am_indexed8:$addr)),
1207 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1208 def : Pat<(i64 (extloadi1 am_indexed8:$addr)),
1209 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1211 // load sign-extended half-word
1212 def LDRSHWui : LoadUI<0b01, 0, 0b11, GPR32, am_indexed16, "ldrsh",
1213 [(set GPR32:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1214 def LDRSHXui : LoadUI<0b01, 0, 0b10, GPR64, am_indexed16, "ldrsh",
1215 [(set GPR64:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1217 // load sign-extended byte
1218 def LDRSBWui : LoadUI<0b00, 0, 0b11, GPR32, am_indexed8, "ldrsb",
1219 [(set GPR32:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1220 def LDRSBXui : LoadUI<0b00, 0, 0b10, GPR64, am_indexed8, "ldrsb",
1221 [(set GPR64:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1223 // load sign-extended word
1224 def LDRSWui : LoadUI<0b10, 0, 0b10, GPR64, am_indexed32, "ldrsw",
1225 [(set GPR64:$Rt, (sextloadi32 am_indexed32:$addr))]>;
1227 // load zero-extended word
1228 def : Pat<(i64 (zextloadi32 am_indexed32:$addr)),
1229 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1232 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1233 [(ARM64Prefetch imm:$Rt, am_indexed64:$addr)]>;
1237 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1238 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1239 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1240 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1241 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1243 // load sign-extended word
1244 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1247 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1248 // [(ARM64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1251 // (unscaled immediate)
1252 def LDURXi : LoadUnscaled<0b11, 0, 0b01, GPR64, am_unscaled64, "ldur",
1253 [(set GPR64:$Rt, (load am_unscaled64:$addr))]>;
1254 def LDURWi : LoadUnscaled<0b10, 0, 0b01, GPR32, am_unscaled32, "ldur",
1255 [(set GPR32:$Rt, (load am_unscaled32:$addr))]>;
1256 def LDURBi : LoadUnscaled<0b00, 1, 0b01, FPR8, am_unscaled8, "ldur",
1257 [(set FPR8:$Rt, (load am_unscaled8:$addr))]>;
1258 def LDURHi : LoadUnscaled<0b01, 1, 0b01, FPR16, am_unscaled16, "ldur",
1259 [(set FPR16:$Rt, (load am_unscaled16:$addr))]>;
1260 def LDURSi : LoadUnscaled<0b10, 1, 0b01, FPR32, am_unscaled32, "ldur",
1261 [(set (f32 FPR32:$Rt), (load am_unscaled32:$addr))]>;
1262 def LDURDi : LoadUnscaled<0b11, 1, 0b01, FPR64, am_unscaled64, "ldur",
1263 [(set (f64 FPR64:$Rt), (load am_unscaled64:$addr))]>;
1264 def LDURQi : LoadUnscaled<0b00, 1, 0b11, FPR128, am_unscaled128, "ldur",
1265 [(set (v2f64 FPR128:$Rt), (load am_unscaled128:$addr))]>;
1268 : LoadUnscaled<0b01, 0, 0b01, GPR32, am_unscaled16, "ldurh",
1269 [(set GPR32:$Rt, (zextloadi16 am_unscaled16:$addr))]>;
1271 : LoadUnscaled<0b00, 0, 0b01, GPR32, am_unscaled8, "ldurb",
1272 [(set GPR32:$Rt, (zextloadi8 am_unscaled8:$addr))]>;
1274 // Match all load 64 bits width whose type is compatible with FPR64
1275 def : Pat<(v2f32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1276 def : Pat<(v1f64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1277 def : Pat<(v8i8 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1278 def : Pat<(v4i16 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1279 def : Pat<(v2i32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1280 def : Pat<(v1i64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1282 // Match all load 128 bits width whose type is compatible with FPR128
1283 def : Pat<(v4f32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1284 def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1285 def : Pat<(v16i8 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1286 def : Pat<(v8i16 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1287 def : Pat<(v4i32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1288 def : Pat<(v2i64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1289 def : Pat<(f128 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1292 def : Pat<(i32 (extloadi16 am_unscaled16:$addr)), (LDURHHi am_unscaled16:$addr)>;
1293 def : Pat<(i32 (extloadi8 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1294 def : Pat<(i32 (extloadi1 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1295 def : Pat<(i64 (extloadi32 am_unscaled32:$addr)),
1296 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1297 def : Pat<(i64 (extloadi16 am_unscaled16:$addr)),
1298 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1299 def : Pat<(i64 (extloadi8 am_unscaled8:$addr)),
1300 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1301 def : Pat<(i64 (extloadi1 am_unscaled8:$addr)),
1302 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1304 def : Pat<(i32 (zextloadi16 am_unscaled16:$addr)),
1305 (LDURHHi am_unscaled16:$addr)>;
1306 def : Pat<(i32 (zextloadi8 am_unscaled8:$addr)),
1307 (LDURBBi am_unscaled8:$addr)>;
1308 def : Pat<(i32 (zextloadi1 am_unscaled8:$addr)),
1309 (LDURBBi am_unscaled8:$addr)>;
1310 def : Pat<(i64 (zextloadi32 am_unscaled32:$addr)),
1311 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1312 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1313 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1314 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1315 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1316 def : Pat<(i64 (zextloadi1 am_unscaled8:$addr)),
1317 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1321 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1323 // Define new assembler match classes as we want to only match these when
1324 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1325 // associate a DiagnosticType either, as we want the diagnostic for the
1326 // canonical form (the scaled operand) to take precedence.
1327 def MemoryUnscaledFB8Operand : AsmOperandClass {
1328 let Name = "MemoryUnscaledFB8";
1329 let RenderMethod = "addMemoryUnscaledOperands";
1331 def MemoryUnscaledFB16Operand : AsmOperandClass {
1332 let Name = "MemoryUnscaledFB16";
1333 let RenderMethod = "addMemoryUnscaledOperands";
1335 def MemoryUnscaledFB32Operand : AsmOperandClass {
1336 let Name = "MemoryUnscaledFB32";
1337 let RenderMethod = "addMemoryUnscaledOperands";
1339 def MemoryUnscaledFB64Operand : AsmOperandClass {
1340 let Name = "MemoryUnscaledFB64";
1341 let RenderMethod = "addMemoryUnscaledOperands";
1343 def MemoryUnscaledFB128Operand : AsmOperandClass {
1344 let Name = "MemoryUnscaledFB128";
1345 let RenderMethod = "addMemoryUnscaledOperands";
1347 def am_unscaled_fb8 : Operand<i64> {
1348 let ParserMatchClass = MemoryUnscaledFB8Operand;
1349 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1351 def am_unscaled_fb16 : Operand<i64> {
1352 let ParserMatchClass = MemoryUnscaledFB16Operand;
1353 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1355 def am_unscaled_fb32 : Operand<i64> {
1356 let ParserMatchClass = MemoryUnscaledFB32Operand;
1357 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1359 def am_unscaled_fb64 : Operand<i64> {
1360 let ParserMatchClass = MemoryUnscaledFB64Operand;
1361 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1363 def am_unscaled_fb128 : Operand<i64> {
1364 let ParserMatchClass = MemoryUnscaledFB128Operand;
1365 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1367 def : InstAlias<"ldr $Rt, $addr", (LDURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1368 def : InstAlias<"ldr $Rt, $addr", (LDURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1369 def : InstAlias<"ldr $Rt, $addr", (LDURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1370 def : InstAlias<"ldr $Rt, $addr", (LDURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1371 def : InstAlias<"ldr $Rt, $addr", (LDURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1372 def : InstAlias<"ldr $Rt, $addr", (LDURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1373 def : InstAlias<"ldr $Rt, $addr", (LDURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1376 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1377 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1378 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1379 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1381 // load sign-extended half-word
1383 : LoadUnscaled<0b01, 0, 0b11, GPR32, am_unscaled16, "ldursh",
1384 [(set GPR32:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1386 : LoadUnscaled<0b01, 0, 0b10, GPR64, am_unscaled16, "ldursh",
1387 [(set GPR64:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1389 // load sign-extended byte
1391 : LoadUnscaled<0b00, 0, 0b11, GPR32, am_unscaled8, "ldursb",
1392 [(set GPR32:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1394 : LoadUnscaled<0b00, 0, 0b10, GPR64, am_unscaled8, "ldursb",
1395 [(set GPR64:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1397 // load sign-extended word
1399 : LoadUnscaled<0b10, 0, 0b10, GPR64, am_unscaled32, "ldursw",
1400 [(set GPR64:$Rt, (sextloadi32 am_unscaled32:$addr))]>;
1402 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1403 def : InstAlias<"ldrb $Rt, $addr", (LDURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1404 def : InstAlias<"ldrh $Rt, $addr", (LDURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1405 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBWi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1406 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBXi GPR64:$Rt, am_unscaled_fb8:$addr)>;
1407 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHWi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1408 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHXi GPR64:$Rt, am_unscaled_fb16:$addr)>;
1409 def : InstAlias<"ldrsw $Rt, $addr", (LDURSWi GPR64:$Rt, am_unscaled_fb32:$addr)>;
1412 def PRFUMi : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1413 [(ARM64Prefetch imm:$Rt, am_unscaled64:$addr)]>;
1416 // (unscaled immediate, unprivileged)
1417 def LDTRXi : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1418 def LDTRWi : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1420 def LDTRHi : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1421 def LDTRBi : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1423 // load sign-extended half-word
1424 def LDTRSHWi : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1425 def LDTRSHXi : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1427 // load sign-extended byte
1428 def LDTRSBWi : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1429 def LDTRSBXi : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1431 // load sign-extended word
1432 def LDTRSWi : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1435 // (immediate pre-indexed)
1436 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1437 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1438 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1439 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1440 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1441 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1442 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1444 // load sign-extended half-word
1445 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1446 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1448 // load sign-extended byte
1449 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1450 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1452 // load zero-extended byte
1453 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1454 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1456 // load sign-extended word
1457 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1459 // ISel pseudos and patterns. See expanded comment on LoadPreIdxPseudo.
1460 def LDRDpre_isel : LoadPreIdxPseudo<FPR64>;
1461 def LDRSpre_isel : LoadPreIdxPseudo<FPR32>;
1462 def LDRXpre_isel : LoadPreIdxPseudo<GPR64>;
1463 def LDRWpre_isel : LoadPreIdxPseudo<GPR32>;
1464 def LDRHHpre_isel : LoadPreIdxPseudo<GPR32>;
1465 def LDRBBpre_isel : LoadPreIdxPseudo<GPR32>;
1467 def LDRSWpre_isel : LoadPreIdxPseudo<GPR64>;
1468 def LDRSHWpre_isel : LoadPreIdxPseudo<GPR32>;
1469 def LDRSHXpre_isel : LoadPreIdxPseudo<GPR64>;
1470 def LDRSBWpre_isel : LoadPreIdxPseudo<GPR32>;
1471 def LDRSBXpre_isel : LoadPreIdxPseudo<GPR64>;
1474 // (immediate post-indexed)
1475 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1476 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1477 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1478 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1479 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1480 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1481 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1483 // load sign-extended half-word
1484 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1485 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1487 // load sign-extended byte
1488 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1489 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1491 // load zero-extended byte
1492 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1493 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1495 // load sign-extended word
1496 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1498 // ISel pseudos and patterns. See expanded comment on LoadPostIdxPseudo.
1499 def LDRDpost_isel : LoadPostIdxPseudo<FPR64>;
1500 def LDRSpost_isel : LoadPostIdxPseudo<FPR32>;
1501 def LDRXpost_isel : LoadPostIdxPseudo<GPR64>;
1502 def LDRWpost_isel : LoadPostIdxPseudo<GPR32>;
1503 def LDRHHpost_isel : LoadPostIdxPseudo<GPR32>;
1504 def LDRBBpost_isel : LoadPostIdxPseudo<GPR32>;
1506 def LDRSWpost_isel : LoadPostIdxPseudo<GPR64>;
1507 def LDRSHWpost_isel : LoadPostIdxPseudo<GPR32>;
1508 def LDRSHXpost_isel : LoadPostIdxPseudo<GPR64>;
1509 def LDRSBWpost_isel : LoadPostIdxPseudo<GPR32>;
1510 def LDRSBXpost_isel : LoadPostIdxPseudo<GPR64>;
1512 //===----------------------------------------------------------------------===//
1513 // Store instructions.
1514 //===----------------------------------------------------------------------===//
1516 // Pair (indexed, offset)
1517 // FIXME: Use dedicated range-checked addressing mode operand here.
1518 def STPWi : StorePairOffset<0b00, 0, GPR32, am_indexed32simm7, "stp">;
1519 def STPXi : StorePairOffset<0b10, 0, GPR64, am_indexed64simm7, "stp">;
1520 def STPSi : StorePairOffset<0b00, 1, FPR32, am_indexed32simm7, "stp">;
1521 def STPDi : StorePairOffset<0b01, 1, FPR64, am_indexed64simm7, "stp">;
1522 def STPQi : StorePairOffset<0b10, 1, FPR128, am_indexed128simm7, "stp">;
1524 // Pair (pre-indexed)
1525 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "stp">;
1526 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "stp">;
1527 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "stp">;
1528 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "stp">;
1529 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "stp">;
1531 // Pair (pre-indexed)
1532 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1533 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1534 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1535 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1536 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1538 // Pair (no allocate)
1539 def STNPWi : StorePairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "stnp">;
1540 def STNPXi : StorePairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "stnp">;
1541 def STNPSi : StorePairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "stnp">;
1542 def STNPDi : StorePairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "stnp">;
1543 def STNPQi : StorePairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "stnp">;
1546 // (Register offset)
1548 let AddedComplexity = 10 in {
1551 def STRHHro : Store16RO<0b01, 0, 0b00, GPR32, "strh",
1552 [(truncstorei16 GPR32:$Rt, ro_indexed16:$addr)]>;
1553 def STRBBro : Store8RO<0b00, 0, 0b00, GPR32, "strb",
1554 [(truncstorei8 GPR32:$Rt, ro_indexed8:$addr)]>;
1555 def STRWro : Store32RO<0b10, 0, 0b00, GPR32, "str",
1556 [(store GPR32:$Rt, ro_indexed32:$addr)]>;
1557 def STRXro : Store64RO<0b11, 0, 0b00, GPR64, "str",
1558 [(store GPR64:$Rt, ro_indexed64:$addr)]>;
1561 def : Pat<(truncstorei8 GPR64:$Rt, ro_indexed8:$addr),
1562 (STRBBro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed8:$addr)>;
1563 def : Pat<(truncstorei16 GPR64:$Rt, ro_indexed16:$addr),
1564 (STRHHro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed16:$addr)>;
1565 def : Pat<(truncstorei32 GPR64:$Rt, ro_indexed32:$addr),
1566 (STRWro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed32:$addr)>;
1570 def STRBro : Store8RO<0b00, 1, 0b00, FPR8, "str",
1571 [(store FPR8:$Rt, ro_indexed8:$addr)]>;
1572 def STRHro : Store16RO<0b01, 1, 0b00, FPR16, "str",
1573 [(store FPR16:$Rt, ro_indexed16:$addr)]>;
1574 def STRSro : Store32RO<0b10, 1, 0b00, FPR32, "str",
1575 [(store (f32 FPR32:$Rt), ro_indexed32:$addr)]>;
1576 def STRDro : Store64RO<0b11, 1, 0b00, FPR64, "str",
1577 [(store (f64 FPR64:$Rt), ro_indexed64:$addr)]>;
1578 def STRQro : Store128RO<0b00, 1, 0b10, FPR128, "str", []> {
1582 // Match all store 64 bits width whose type is compatible with FPR64
1583 def : Pat<(store (v2f32 FPR64:$Rn), ro_indexed64:$addr),
1584 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1585 def : Pat<(store (v1f64 FPR64:$Rn), ro_indexed64:$addr),
1586 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1587 def : Pat<(store (v8i8 FPR64:$Rn), ro_indexed64:$addr),
1588 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1589 def : Pat<(store (v4i16 FPR64:$Rn), ro_indexed64:$addr),
1590 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1591 def : Pat<(store (v2i32 FPR64:$Rn), ro_indexed64:$addr),
1592 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1593 def : Pat<(store (v1i64 FPR64:$Rn), ro_indexed64:$addr),
1594 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1596 // Match all store 128 bits width whose type is compatible with FPR128
1597 def : Pat<(store (v4f32 FPR128:$Rn), ro_indexed128:$addr),
1598 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1599 def : Pat<(store (v2f64 FPR128:$Rn), ro_indexed128:$addr),
1600 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1601 def : Pat<(store (v16i8 FPR128:$Rn), ro_indexed128:$addr),
1602 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1603 def : Pat<(store (v8i16 FPR128:$Rn), ro_indexed128:$addr),
1604 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1605 def : Pat<(store (v4i32 FPR128:$Rn), ro_indexed128:$addr),
1606 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1607 def : Pat<(store (v2i64 FPR128:$Rn), ro_indexed128:$addr),
1608 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1609 def : Pat<(store (f128 FPR128:$Rn), ro_indexed128:$addr),
1610 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1613 // (unsigned immediate)
1614 def STRXui : StoreUI<0b11, 0, 0b00, GPR64, am_indexed64, "str",
1615 [(store GPR64:$Rt, am_indexed64:$addr)]>;
1616 def STRWui : StoreUI<0b10, 0, 0b00, GPR32, am_indexed32, "str",
1617 [(store GPR32:$Rt, am_indexed32:$addr)]>;
1618 def STRBui : StoreUI<0b00, 1, 0b00, FPR8, am_indexed8, "str",
1619 [(store FPR8:$Rt, am_indexed8:$addr)]>;
1620 def STRHui : StoreUI<0b01, 1, 0b00, FPR16, am_indexed16, "str",
1621 [(store FPR16:$Rt, am_indexed16:$addr)]>;
1622 def STRSui : StoreUI<0b10, 1, 0b00, FPR32, am_indexed32, "str",
1623 [(store (f32 FPR32:$Rt), am_indexed32:$addr)]>;
1624 def STRDui : StoreUI<0b11, 1, 0b00, FPR64, am_indexed64, "str",
1625 [(store (f64 FPR64:$Rt), am_indexed64:$addr)]>;
1626 def STRQui : StoreUI<0b00, 1, 0b10, FPR128, am_indexed128, "str", []> {
1630 // Match all store 64 bits width whose type is compatible with FPR64
1631 def : Pat<(store (v2f32 FPR64:$Rn), am_indexed64:$addr),
1632 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1633 def : Pat<(store (v1f64 FPR64:$Rn), am_indexed64:$addr),
1634 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1635 def : Pat<(store (v8i8 FPR64:$Rn), am_indexed64:$addr),
1636 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1637 def : Pat<(store (v4i16 FPR64:$Rn), am_indexed64:$addr),
1638 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1639 def : Pat<(store (v2i32 FPR64:$Rn), am_indexed64:$addr),
1640 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1641 def : Pat<(store (v1i64 FPR64:$Rn), am_indexed64:$addr),
1642 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1644 // Match all store 128 bits width whose type is compatible with FPR128
1645 def : Pat<(store (v4f32 FPR128:$Rn), am_indexed128:$addr),
1646 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1647 def : Pat<(store (v2f64 FPR128:$Rn), am_indexed128:$addr),
1648 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1649 def : Pat<(store (v16i8 FPR128:$Rn), am_indexed128:$addr),
1650 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1651 def : Pat<(store (v8i16 FPR128:$Rn), am_indexed128:$addr),
1652 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1653 def : Pat<(store (v4i32 FPR128:$Rn), am_indexed128:$addr),
1654 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1655 def : Pat<(store (v2i64 FPR128:$Rn), am_indexed128:$addr),
1656 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1657 def : Pat<(store (f128 FPR128:$Rn), am_indexed128:$addr),
1658 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1660 def STRHHui : StoreUI<0b01, 0, 0b00, GPR32, am_indexed16, "strh",
1661 [(truncstorei16 GPR32:$Rt, am_indexed16:$addr)]>;
1662 def STRBBui : StoreUI<0b00, 0, 0b00, GPR32, am_indexed8, "strb",
1663 [(truncstorei8 GPR32:$Rt, am_indexed8:$addr)]>;
1666 def : Pat<(truncstorei32 GPR64:$Rt, am_indexed32:$addr),
1667 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed32:$addr)>;
1668 def : Pat<(truncstorei16 GPR64:$Rt, am_indexed16:$addr),
1669 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed16:$addr)>;
1670 def : Pat<(truncstorei8 GPR64:$Rt, am_indexed8:$addr),
1671 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed8:$addr)>;
1673 } // AddedComplexity = 10
1676 // (unscaled immediate)
1677 def STURXi : StoreUnscaled<0b11, 0, 0b00, GPR64, am_unscaled64, "stur",
1678 [(store GPR64:$Rt, am_unscaled64:$addr)]>;
1679 def STURWi : StoreUnscaled<0b10, 0, 0b00, GPR32, am_unscaled32, "stur",
1680 [(store GPR32:$Rt, am_unscaled32:$addr)]>;
1681 def STURBi : StoreUnscaled<0b00, 1, 0b00, FPR8, am_unscaled8, "stur",
1682 [(store FPR8:$Rt, am_unscaled8:$addr)]>;
1683 def STURHi : StoreUnscaled<0b01, 1, 0b00, FPR16, am_unscaled16, "stur",
1684 [(store FPR16:$Rt, am_unscaled16:$addr)]>;
1685 def STURSi : StoreUnscaled<0b10, 1, 0b00, FPR32, am_unscaled32, "stur",
1686 [(store (f32 FPR32:$Rt), am_unscaled32:$addr)]>;
1687 def STURDi : StoreUnscaled<0b11, 1, 0b00, FPR64, am_unscaled64, "stur",
1688 [(store (f64 FPR64:$Rt), am_unscaled64:$addr)]>;
1689 def STURQi : StoreUnscaled<0b00, 1, 0b10, FPR128, am_unscaled128, "stur",
1690 [(store (v2f64 FPR128:$Rt), am_unscaled128:$addr)]>;
1691 def STURHHi : StoreUnscaled<0b01, 0, 0b00, GPR32, am_unscaled16, "sturh",
1692 [(truncstorei16 GPR32:$Rt, am_unscaled16:$addr)]>;
1693 def STURBBi : StoreUnscaled<0b00, 0, 0b00, GPR32, am_unscaled8, "sturb",
1694 [(truncstorei8 GPR32:$Rt, am_unscaled8:$addr)]>;
1696 // Match all store 64 bits width whose type is compatible with FPR64
1697 def : Pat<(store (v2f32 FPR64:$Rn), am_unscaled64:$addr),
1698 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1699 def : Pat<(store (v1f64 FPR64:$Rn), am_unscaled64:$addr),
1700 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1701 def : Pat<(store (v8i8 FPR64:$Rn), am_unscaled64:$addr),
1702 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1703 def : Pat<(store (v4i16 FPR64:$Rn), am_unscaled64:$addr),
1704 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1705 def : Pat<(store (v2i32 FPR64:$Rn), am_unscaled64:$addr),
1706 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1707 def : Pat<(store (v1i64 FPR64:$Rn), am_unscaled64:$addr),
1708 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1710 // Match all store 128 bits width whose type is compatible with FPR128
1711 def : Pat<(store (v4f32 FPR128:$Rn), am_unscaled128:$addr),
1712 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1713 def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
1714 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1715 def : Pat<(store (v16i8 FPR128:$Rn), am_unscaled128:$addr),
1716 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1717 def : Pat<(store (v8i16 FPR128:$Rn), am_unscaled128:$addr),
1718 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1719 def : Pat<(store (v4i32 FPR128:$Rn), am_unscaled128:$addr),
1720 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1721 def : Pat<(store (v2i64 FPR128:$Rn), am_unscaled128:$addr),
1722 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1723 def : Pat<(store (f128 FPR128:$Rn), am_unscaled128:$addr),
1724 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1726 // unscaled i64 truncating stores
1727 def : Pat<(truncstorei32 GPR64:$Rt, am_unscaled32:$addr),
1728 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled32:$addr)>;
1729 def : Pat<(truncstorei16 GPR64:$Rt, am_unscaled16:$addr),
1730 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled16:$addr)>;
1731 def : Pat<(truncstorei8 GPR64:$Rt, am_unscaled8:$addr),
1732 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled8:$addr)>;
1735 // STR mnemonics fall back to STUR for negative or unaligned offsets.
1736 def : InstAlias<"str $Rt, $addr", (STURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1737 def : InstAlias<"str $Rt, $addr", (STURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1738 def : InstAlias<"str $Rt, $addr", (STURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1739 def : InstAlias<"str $Rt, $addr", (STURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1740 def : InstAlias<"str $Rt, $addr", (STURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1741 def : InstAlias<"str $Rt, $addr", (STURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1742 def : InstAlias<"str $Rt, $addr", (STURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1744 def : InstAlias<"strb $Rt, $addr", (STURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1745 def : InstAlias<"strh $Rt, $addr", (STURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1748 // (unscaled immediate, unprivileged)
1749 def STTRWi : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
1750 def STTRXi : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
1752 def STTRHi : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
1753 def STTRBi : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
1756 // (immediate pre-indexed)
1757 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str">;
1758 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str">;
1759 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str">;
1760 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str">;
1761 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str">;
1762 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str">;
1763 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str">;
1765 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb">;
1766 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh">;
1768 // ISel pseudos and patterns. See expanded comment on StorePreIdxPseudo.
1769 defm STRDpre : StorePreIdxPseudo<FPR64, f64, pre_store>;
1770 defm STRSpre : StorePreIdxPseudo<FPR32, f32, pre_store>;
1771 defm STRXpre : StorePreIdxPseudo<GPR64, i64, pre_store>;
1772 defm STRWpre : StorePreIdxPseudo<GPR32, i32, pre_store>;
1773 defm STRHHpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti16>;
1774 defm STRBBpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti8>;
1776 def : Pat<(pre_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1777 (STRWpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1779 def : Pat<(pre_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1780 (STRHHpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1782 def : Pat<(pre_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1783 (STRBBpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1787 // (immediate post-indexed)
1788 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str">;
1789 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str">;
1790 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str">;
1791 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str">;
1792 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str">;
1793 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str">;
1794 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str">;
1796 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb">;
1797 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh">;
1799 // ISel pseudos and patterns. See expanded comment on StorePostIdxPseudo.
1800 defm STRDpost : StorePostIdxPseudo<FPR64, f64, post_store, STRDpost>;
1801 defm STRSpost : StorePostIdxPseudo<FPR32, f32, post_store, STRSpost>;
1802 defm STRXpost : StorePostIdxPseudo<GPR64, i64, post_store, STRXpost>;
1803 defm STRWpost : StorePostIdxPseudo<GPR32, i32, post_store, STRWpost>;
1804 defm STRHHpost : StorePostIdxPseudo<GPR32, i32, post_truncsti16, STRHHpost>;
1805 defm STRBBpost : StorePostIdxPseudo<GPR32, i32, post_truncsti8, STRBBpost>;
1807 def : Pat<(post_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1808 (STRWpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1810 def : Pat<(post_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1811 (STRHHpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1813 def : Pat<(post_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1814 (STRBBpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1818 //===----------------------------------------------------------------------===//
1819 // Load/store exclusive instructions.
1820 //===----------------------------------------------------------------------===//
1822 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
1823 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
1824 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
1825 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
1827 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
1828 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
1829 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
1830 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
1832 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
1833 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
1834 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
1835 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
1837 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
1838 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
1839 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
1840 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
1842 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
1843 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
1844 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
1845 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
1847 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
1848 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
1849 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
1850 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
1852 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
1853 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
1855 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
1856 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
1858 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
1859 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
1861 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
1862 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
1864 //===----------------------------------------------------------------------===//
1865 // Scaled floating point to integer conversion instructions.
1866 //===----------------------------------------------------------------------===//
1868 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
1869 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
1870 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
1871 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
1872 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
1873 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
1874 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
1875 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
1876 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
1877 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
1878 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
1879 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
1880 let isCodeGenOnly = 1 in {
1881 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
1882 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
1883 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
1884 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
1887 //===----------------------------------------------------------------------===//
1888 // Scaled integer to floating point conversion instructions.
1889 //===----------------------------------------------------------------------===//
1891 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
1892 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
1894 //===----------------------------------------------------------------------===//
1895 // Unscaled integer to floating point conversion instruction.
1896 //===----------------------------------------------------------------------===//
1898 defm FMOV : UnscaledConversion<"fmov">;
1900 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
1901 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
1903 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1904 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1905 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1906 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1907 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1908 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1909 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
1910 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1911 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
1912 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1913 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
1915 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
1916 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1917 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
1918 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1919 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
1920 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1921 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
1922 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1923 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
1924 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1925 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
1926 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1928 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
1929 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
1930 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
1931 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
1932 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
1933 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1934 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
1935 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
1937 //===----------------------------------------------------------------------===//
1938 // Floating point conversion instruction.
1939 //===----------------------------------------------------------------------===//
1941 defm FCVT : FPConversion<"fcvt">;
1943 def : Pat<(f32_to_f16 FPR32:$Rn),
1944 (i32 (COPY_TO_REGCLASS
1945 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
1948 def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
1949 [(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
1951 //===----------------------------------------------------------------------===//
1952 // Floating point single operand instructions.
1953 //===----------------------------------------------------------------------===//
1955 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
1956 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
1957 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
1958 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
1959 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
1960 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
1961 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_arm64_neon_frintn>;
1962 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
1964 def : Pat<(v1f64 (int_arm64_neon_frintn (v1f64 FPR64:$Rn))),
1965 (FRINTNDr FPR64:$Rn)>;
1967 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
1968 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
1969 // <rdar://problem/13715968>
1970 // TODO: We should really model the FPSR flags correctly. This is really ugly.
1971 let hasSideEffects = 1 in {
1972 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
1975 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
1977 let SchedRW = [WriteFDiv] in {
1978 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
1981 //===----------------------------------------------------------------------===//
1982 // Floating point two operand instructions.
1983 //===----------------------------------------------------------------------===//
1985 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
1986 let SchedRW = [WriteFDiv] in {
1987 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
1989 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_arm64_neon_fmaxnm>;
1990 defm FMAX : TwoOperandFPData<0b0100, "fmax", ARM64fmax>;
1991 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_arm64_neon_fminnm>;
1992 defm FMIN : TwoOperandFPData<0b0101, "fmin", ARM64fmin>;
1993 let SchedRW = [WriteFMul] in {
1994 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
1995 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
1997 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
1999 def : Pat<(v1f64 (ARM64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2000 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2001 def : Pat<(v1f64 (ARM64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2002 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2003 def : Pat<(v1f64 (int_arm64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2004 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2005 def : Pat<(v1f64 (int_arm64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2006 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2008 //===----------------------------------------------------------------------===//
2009 // Floating point three operand instructions.
2010 //===----------------------------------------------------------------------===//
2012 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2013 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2014 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2015 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2016 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2017 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2018 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2020 // The following def pats catch the case where the LHS of an FMA is negated.
2021 // The TriOpFrag above catches the case where the middle operand is negated.
2023 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2024 // the NEON variant.
2025 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2026 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2028 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2029 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2031 //===----------------------------------------------------------------------===//
2032 // Floating point comparison instructions.
2033 //===----------------------------------------------------------------------===//
2035 defm FCMPE : FPComparison<1, "fcmpe">;
2036 defm FCMP : FPComparison<0, "fcmp", ARM64fcmp>;
2038 //===----------------------------------------------------------------------===//
2039 // Floating point conditional comparison instructions.
2040 //===----------------------------------------------------------------------===//
2042 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2043 defm FCCMP : FPCondComparison<0, "fccmp">;
2045 //===----------------------------------------------------------------------===//
2046 // Floating point conditional select instruction.
2047 //===----------------------------------------------------------------------===//
2049 defm FCSEL : FPCondSelect<"fcsel">;
2051 // CSEL instructions providing f128 types need to be handled by a
2052 // pseudo-instruction since the eventual code will need to introduce basic
2053 // blocks and control flow.
2054 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2055 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2056 [(set (f128 FPR128:$Rd),
2057 (ARM64csel FPR128:$Rn, FPR128:$Rm,
2058 (i32 imm:$cond), CPSR))]> {
2060 let usesCustomInserter = 1;
2064 //===----------------------------------------------------------------------===//
2065 // Floating point immediate move.
2066 //===----------------------------------------------------------------------===//
2068 let isReMaterializable = 1 in {
2069 defm FMOV : FPMoveImmediate<"fmov">;
2072 //===----------------------------------------------------------------------===//
2073 // Advanced SIMD two vector instructions.
2074 //===----------------------------------------------------------------------===//
2076 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_arm64_neon_abs>;
2077 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_arm64_neon_cls>;
2078 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2079 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", ARM64cmeqz>;
2080 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", ARM64cmgez>;
2081 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", ARM64cmgtz>;
2082 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", ARM64cmlez>;
2083 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", ARM64cmltz>;
2084 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2085 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2087 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2088 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2089 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2090 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2091 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2092 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_arm64_neon_fcvtas>;
2093 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_arm64_neon_fcvtau>;
2094 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2095 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2096 (FCVTLv4i16 V64:$Rn)>;
2097 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2099 (FCVTLv8i16 V128:$Rn)>;
2100 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2101 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2103 (FCVTLv4i32 V128:$Rn)>;
2105 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_arm64_neon_fcvtms>;
2106 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_arm64_neon_fcvtmu>;
2107 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_arm64_neon_fcvtns>;
2108 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_arm64_neon_fcvtnu>;
2109 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2110 def : Pat<(v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2111 (FCVTNv4i16 V128:$Rn)>;
2112 def : Pat<(concat_vectors V64:$Rd,
2113 (v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2114 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2115 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2116 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2117 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2118 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_arm64_neon_fcvtps>;
2119 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_arm64_neon_fcvtpu>;
2120 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2121 int_arm64_neon_fcvtxn>;
2122 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2123 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2124 let isCodeGenOnly = 1 in {
2125 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2126 int_arm64_neon_fcvtzs>;
2127 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2128 int_arm64_neon_fcvtzu>;
2130 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2131 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_arm64_neon_frecpe>;
2132 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2133 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2134 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2135 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_arm64_neon_frintn>;
2136 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2137 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2138 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2139 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_arm64_neon_frsqrte>;
2140 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2141 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2142 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2143 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2144 // Aliases for MVN -> NOT.
2145 def : InstAlias<"mvn.8b $Vd, $Vn", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2146 def : InstAlias<"mvn.16b $Vd, $Vn", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2147 def : InstAlias<"mvn $Vd.8b, $Vn.8b", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2148 def : InstAlias<"mvn $Vd.16b, $Vn.16b", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2150 def : Pat<(ARM64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2151 def : Pat<(ARM64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2152 def : Pat<(ARM64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2153 def : Pat<(ARM64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2154 def : Pat<(ARM64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2155 def : Pat<(ARM64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2156 def : Pat<(ARM64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2158 def : Pat<(ARM64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2159 def : Pat<(ARM64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2160 def : Pat<(ARM64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2161 def : Pat<(ARM64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2162 def : Pat<(ARM64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2163 def : Pat<(ARM64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2164 def : Pat<(ARM64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2165 def : Pat<(ARM64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2167 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2168 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2169 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2170 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2171 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2173 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_arm64_neon_rbit>;
2174 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", ARM64rev16>;
2175 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", ARM64rev32>;
2176 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", ARM64rev64>;
2177 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2178 BinOpFrag<(add node:$LHS, (int_arm64_neon_saddlp node:$RHS))> >;
2179 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_arm64_neon_saddlp>;
2180 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2181 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2182 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2183 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2184 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_arm64_neon_sqxtn>;
2185 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_arm64_neon_sqxtun>;
2186 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_arm64_neon_suqadd>;
2187 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2188 BinOpFrag<(add node:$LHS, (int_arm64_neon_uaddlp node:$RHS))> >;
2189 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2190 int_arm64_neon_uaddlp>;
2191 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2192 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_arm64_neon_uqxtn>;
2193 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_arm64_neon_urecpe>;
2194 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_arm64_neon_ursqrte>;
2195 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_arm64_neon_usqadd>;
2196 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2198 def : Pat<(v2f32 (ARM64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2199 def : Pat<(v4f32 (ARM64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2201 // Patterns for vector long shift (by element width). These need to match all
2202 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2204 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2205 def : Pat<(ARM64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2206 (SHLLv8i8 V64:$Rn)>;
2207 def : Pat<(ARM64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2208 (SHLLv16i8 V128:$Rn)>;
2209 def : Pat<(ARM64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2210 (SHLLv4i16 V64:$Rn)>;
2211 def : Pat<(ARM64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2212 (SHLLv8i16 V128:$Rn)>;
2213 def : Pat<(ARM64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2214 (SHLLv2i32 V64:$Rn)>;
2215 def : Pat<(ARM64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2216 (SHLLv4i32 V128:$Rn)>;
2219 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2220 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2221 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2223 //===----------------------------------------------------------------------===//
2224 // Advanced SIMD three vector instructions.
2225 //===----------------------------------------------------------------------===//
2227 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2228 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_arm64_neon_addp>;
2229 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", ARM64cmeq>;
2230 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", ARM64cmge>;
2231 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", ARM64cmgt>;
2232 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", ARM64cmhi>;
2233 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", ARM64cmhs>;
2234 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", ARM64cmtst>;
2235 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_arm64_neon_fabd>;
2236 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_arm64_neon_facge>;
2237 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_arm64_neon_facgt>;
2238 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_arm64_neon_addp>;
2239 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2240 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2241 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2242 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2243 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2244 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_arm64_neon_fmaxnmp>;
2245 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_arm64_neon_fmaxnm>;
2246 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_arm64_neon_fmaxp>;
2247 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", ARM64fmax>;
2248 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_arm64_neon_fminnmp>;
2249 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_arm64_neon_fminnm>;
2250 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_arm64_neon_fminp>;
2251 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", ARM64fmin>;
2253 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2254 // instruction expects the addend first, while the fma intrinsic puts it last.
2255 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2256 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2257 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2258 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2260 // The following def pats catch the case where the LHS of an FMA is negated.
2261 // The TriOpFrag above catches the case where the middle operand is negated.
2262 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2263 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2265 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2266 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2268 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2269 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2271 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_arm64_neon_fmulx>;
2272 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2273 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_arm64_neon_frecps>;
2274 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_arm64_neon_frsqrts>;
2275 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2276 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2277 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2278 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2279 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2280 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2281 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_arm64_neon_pmul>;
2282 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2283 TriOpFrag<(add node:$LHS, (int_arm64_neon_sabd node:$MHS, node:$RHS))> >;
2284 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_arm64_neon_sabd>;
2285 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_arm64_neon_shadd>;
2286 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_arm64_neon_shsub>;
2287 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_arm64_neon_smaxp>;
2288 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_arm64_neon_smax>;
2289 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_arm64_neon_sminp>;
2290 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_arm64_neon_smin>;
2291 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_arm64_neon_sqadd>;
2292 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_arm64_neon_sqdmulh>;
2293 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_arm64_neon_sqrdmulh>;
2294 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_arm64_neon_sqrshl>;
2295 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_arm64_neon_sqshl>;
2296 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_arm64_neon_sqsub>;
2297 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_arm64_neon_srhadd>;
2298 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_arm64_neon_srshl>;
2299 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_arm64_neon_sshl>;
2300 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2301 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2302 TriOpFrag<(add node:$LHS, (int_arm64_neon_uabd node:$MHS, node:$RHS))> >;
2303 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_arm64_neon_uabd>;
2304 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_arm64_neon_uhadd>;
2305 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_arm64_neon_uhsub>;
2306 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_arm64_neon_umaxp>;
2307 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_arm64_neon_umax>;
2308 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_arm64_neon_uminp>;
2309 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_arm64_neon_umin>;
2310 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_arm64_neon_uqadd>;
2311 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_arm64_neon_uqrshl>;
2312 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_arm64_neon_uqshl>;
2313 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_arm64_neon_uqsub>;
2314 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_arm64_neon_urhadd>;
2315 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_arm64_neon_urshl>;
2316 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_arm64_neon_ushl>;
2318 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2319 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2320 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2321 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2322 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", ARM64bit>;
2323 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2324 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2325 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2326 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2327 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2328 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2330 // FIXME: the .16b and .8b variantes should be emitted by the
2331 // AsmWriter. TableGen's AsmWriter-generator doesn't deal with variant syntaxes
2332 // in aliases yet though.
2333 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2334 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2335 def : InstAlias<"{mov\t$dst.8h, $src.8h|mov.8h\t$dst, $src}",
2336 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2337 def : InstAlias<"{mov\t$dst.4s, $src.4s|mov.4s\t$dst, $src}",
2338 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2339 def : InstAlias<"{mov\t$dst.2d, $src.2d|mov.2d\t$dst, $src}",
2340 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2342 def : InstAlias<"{mov\t$dst.8b, $src.8b|mov.8b\t$dst, $src}",
2343 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2344 def : InstAlias<"{mov\t$dst.4h, $src.4h|mov.4h\t$dst, $src}",
2345 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2346 def : InstAlias<"{mov\t$dst.2s, $src.2s|mov.2s\t$dst, $src}",
2347 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2348 def : InstAlias<"{mov\t$dst.1d, $src.1d|mov.1d\t$dst, $src}",
2349 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2351 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2352 "|cmls.8b\t$dst, $src1, $src2}",
2353 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2354 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2355 "|cmls.16b\t$dst, $src1, $src2}",
2356 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2357 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2358 "|cmls.4h\t$dst, $src1, $src2}",
2359 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2360 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2361 "|cmls.8h\t$dst, $src1, $src2}",
2362 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2363 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2364 "|cmls.2s\t$dst, $src1, $src2}",
2365 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2366 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2367 "|cmls.4s\t$dst, $src1, $src2}",
2368 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2369 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2370 "|cmls.2d\t$dst, $src1, $src2}",
2371 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2373 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2374 "|cmlo.8b\t$dst, $src1, $src2}",
2375 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2376 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2377 "|cmlo.16b\t$dst, $src1, $src2}",
2378 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2379 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2380 "|cmlo.4h\t$dst, $src1, $src2}",
2381 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2382 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2383 "|cmlo.8h\t$dst, $src1, $src2}",
2384 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2385 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2386 "|cmlo.2s\t$dst, $src1, $src2}",
2387 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2388 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2389 "|cmlo.4s\t$dst, $src1, $src2}",
2390 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2391 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2392 "|cmlo.2d\t$dst, $src1, $src2}",
2393 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2395 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2396 "|cmle.8b\t$dst, $src1, $src2}",
2397 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2398 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2399 "|cmle.16b\t$dst, $src1, $src2}",
2400 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2401 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2402 "|cmle.4h\t$dst, $src1, $src2}",
2403 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2404 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2405 "|cmle.8h\t$dst, $src1, $src2}",
2406 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2407 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2408 "|cmle.2s\t$dst, $src1, $src2}",
2409 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2410 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2411 "|cmle.4s\t$dst, $src1, $src2}",
2412 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2413 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2414 "|cmle.2d\t$dst, $src1, $src2}",
2415 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2417 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2418 "|cmlt.8b\t$dst, $src1, $src2}",
2419 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2420 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2421 "|cmlt.16b\t$dst, $src1, $src2}",
2422 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2423 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2424 "|cmlt.4h\t$dst, $src1, $src2}",
2425 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2426 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2427 "|cmlt.8h\t$dst, $src1, $src2}",
2428 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2429 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2430 "|cmlt.2s\t$dst, $src1, $src2}",
2431 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2432 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2433 "|cmlt.4s\t$dst, $src1, $src2}",
2434 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2435 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2436 "|cmlt.2d\t$dst, $src1, $src2}",
2437 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2439 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2440 "|fcmle.2s\t$dst, $src1, $src2}",
2441 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2442 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2443 "|fcmle.4s\t$dst, $src1, $src2}",
2444 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2445 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2446 "|fcmle.2d\t$dst, $src1, $src2}",
2447 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2449 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2450 "|fcmlt.2s\t$dst, $src1, $src2}",
2451 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2452 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2453 "|fcmlt.4s\t$dst, $src1, $src2}",
2454 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2455 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2456 "|fcmlt.2d\t$dst, $src1, $src2}",
2457 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2459 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2460 "|facle.2s\t$dst, $src1, $src2}",
2461 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2462 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2463 "|facle.4s\t$dst, $src1, $src2}",
2464 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2465 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2466 "|facle.2d\t$dst, $src1, $src2}",
2467 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2469 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2470 "|faclt.2s\t$dst, $src1, $src2}",
2471 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2472 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2473 "|faclt.4s\t$dst, $src1, $src2}",
2474 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2475 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2476 "|faclt.2d\t$dst, $src1, $src2}",
2477 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2479 //===----------------------------------------------------------------------===//
2480 // Advanced SIMD three scalar instructions.
2481 //===----------------------------------------------------------------------===//
2483 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2484 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", ARM64cmeq>;
2485 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", ARM64cmge>;
2486 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", ARM64cmgt>;
2487 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", ARM64cmhi>;
2488 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", ARM64cmhs>;
2489 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", ARM64cmtst>;
2490 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_arm64_sisd_fabd>;
2491 def : Pat<(v1f64 (int_arm64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2492 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2493 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2494 int_arm64_neon_facge>;
2495 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2496 int_arm64_neon_facgt>;
2497 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2498 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2499 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2500 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_arm64_neon_fmulx>;
2501 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_arm64_neon_frecps>;
2502 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_arm64_neon_frsqrts>;
2503 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_arm64_neon_sqadd>;
2504 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_arm64_neon_sqdmulh>;
2505 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_arm64_neon_sqrdmulh>;
2506 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_arm64_neon_sqrshl>;
2507 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_arm64_neon_sqshl>;
2508 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_arm64_neon_sqsub>;
2509 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_arm64_neon_srshl>;
2510 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_arm64_neon_sshl>;
2511 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2512 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_arm64_neon_uqadd>;
2513 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_arm64_neon_uqrshl>;
2514 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_arm64_neon_uqshl>;
2515 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_arm64_neon_uqsub>;
2516 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_arm64_neon_urshl>;
2517 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_arm64_neon_ushl>;
2519 def : InstAlias<"cmls $dst, $src1, $src2",
2520 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2521 def : InstAlias<"cmle $dst, $src1, $src2",
2522 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2523 def : InstAlias<"cmlo $dst, $src1, $src2",
2524 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2525 def : InstAlias<"cmlt $dst, $src1, $src2",
2526 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2527 def : InstAlias<"fcmle $dst, $src1, $src2",
2528 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2529 def : InstAlias<"fcmle $dst, $src1, $src2",
2530 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2531 def : InstAlias<"fcmlt $dst, $src1, $src2",
2532 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2533 def : InstAlias<"fcmlt $dst, $src1, $src2",
2534 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2535 def : InstAlias<"facle $dst, $src1, $src2",
2536 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2537 def : InstAlias<"facle $dst, $src1, $src2",
2538 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2539 def : InstAlias<"faclt $dst, $src1, $src2",
2540 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2541 def : InstAlias<"faclt $dst, $src1, $src2",
2542 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2544 //===----------------------------------------------------------------------===//
2545 // Advanced SIMD three scalar instructions (mixed operands).
2546 //===----------------------------------------------------------------------===//
2547 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2548 int_arm64_neon_sqdmulls_scalar>;
2549 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2550 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2552 def : Pat<(i64 (int_arm64_neon_sqadd (i64 FPR64:$Rd),
2553 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2554 (i32 FPR32:$Rm))))),
2555 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2556 def : Pat<(i64 (int_arm64_neon_sqsub (i64 FPR64:$Rd),
2557 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2558 (i32 FPR32:$Rm))))),
2559 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2561 //===----------------------------------------------------------------------===//
2562 // Advanced SIMD two scalar instructions.
2563 //===----------------------------------------------------------------------===//
2565 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_arm64_neon_abs>;
2566 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", ARM64cmeqz>;
2567 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", ARM64cmgez>;
2568 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", ARM64cmgtz>;
2569 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", ARM64cmlez>;
2570 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", ARM64cmltz>;
2571 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2572 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2573 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2574 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2575 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2576 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2577 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2578 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2579 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2580 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2581 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2582 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2583 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2584 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2585 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2586 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2587 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2588 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2589 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2590 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
2591 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2592 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", ARM64sitof>;
2593 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2594 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2595 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_arm64_neon_scalar_sqxtn>;
2596 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_arm64_neon_scalar_sqxtun>;
2597 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2598 int_arm64_neon_suqadd>;
2599 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", ARM64uitof>;
2600 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_arm64_neon_scalar_uqxtn>;
2601 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2602 int_arm64_neon_usqadd>;
2604 def : Pat<(v1i64 (int_arm64_neon_fcvtas (v1f64 FPR64:$Rn))),
2605 (FCVTASv1i64 FPR64:$Rn)>;
2606 def : Pat<(v1i64 (int_arm64_neon_fcvtau (v1f64 FPR64:$Rn))),
2607 (FCVTAUv1i64 FPR64:$Rn)>;
2608 def : Pat<(v1i64 (int_arm64_neon_fcvtms (v1f64 FPR64:$Rn))),
2609 (FCVTMSv1i64 FPR64:$Rn)>;
2610 def : Pat<(v1i64 (int_arm64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2611 (FCVTMUv1i64 FPR64:$Rn)>;
2612 def : Pat<(v1i64 (int_arm64_neon_fcvtns (v1f64 FPR64:$Rn))),
2613 (FCVTNSv1i64 FPR64:$Rn)>;
2614 def : Pat<(v1i64 (int_arm64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2615 (FCVTNUv1i64 FPR64:$Rn)>;
2616 def : Pat<(v1i64 (int_arm64_neon_fcvtps (v1f64 FPR64:$Rn))),
2617 (FCVTPSv1i64 FPR64:$Rn)>;
2618 def : Pat<(v1i64 (int_arm64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2619 (FCVTPUv1i64 FPR64:$Rn)>;
2621 def : Pat<(f32 (int_arm64_neon_frecpe (f32 FPR32:$Rn))),
2622 (FRECPEv1i32 FPR32:$Rn)>;
2623 def : Pat<(f64 (int_arm64_neon_frecpe (f64 FPR64:$Rn))),
2624 (FRECPEv1i64 FPR64:$Rn)>;
2625 def : Pat<(v1f64 (int_arm64_neon_frecpe (v1f64 FPR64:$Rn))),
2626 (FRECPEv1i64 FPR64:$Rn)>;
2628 def : Pat<(f32 (int_arm64_neon_frecpx (f32 FPR32:$Rn))),
2629 (FRECPXv1i32 FPR32:$Rn)>;
2630 def : Pat<(f64 (int_arm64_neon_frecpx (f64 FPR64:$Rn))),
2631 (FRECPXv1i64 FPR64:$Rn)>;
2633 def : Pat<(f32 (int_arm64_neon_frsqrte (f32 FPR32:$Rn))),
2634 (FRSQRTEv1i32 FPR32:$Rn)>;
2635 def : Pat<(f64 (int_arm64_neon_frsqrte (f64 FPR64:$Rn))),
2636 (FRSQRTEv1i64 FPR64:$Rn)>;
2637 def : Pat<(v1f64 (int_arm64_neon_frsqrte (v1f64 FPR64:$Rn))),
2638 (FRSQRTEv1i64 FPR64:$Rn)>;
2640 // If an integer is about to be converted to a floating point value,
2641 // just load it on the floating point unit.
2642 // Here are the patterns for 8 and 16-bits to float.
2644 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2645 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2646 (LDRBro ro_indexed8:$addr), bsub))>;
2647 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2648 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2649 (LDRBui am_indexed8:$addr), bsub))>;
2650 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2651 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2652 (LDURBi am_unscaled8:$addr), bsub))>;
2653 // 16-bits -> float.
2654 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2655 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2656 (LDRHro ro_indexed16:$addr), hsub))>;
2657 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2658 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2659 (LDRHui am_indexed16:$addr), hsub))>;
2660 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2661 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2662 (LDURHi am_unscaled16:$addr), hsub))>;
2663 // 32-bits are handled in target specific dag combine:
2664 // performIntToFpCombine.
2665 // 64-bits integer to 32-bits floating point, not possible with
2666 // UCVTF on floating point registers (both source and destination
2667 // must have the same size).
2669 // Here are the patterns for 8, 16, 32, and 64-bits to double.
2670 // 8-bits -> double.
2671 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2672 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2673 (LDRBro ro_indexed8:$addr), bsub))>;
2674 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2675 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2676 (LDRBui am_indexed8:$addr), bsub))>;
2677 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2678 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2679 (LDURBi am_unscaled8:$addr), bsub))>;
2680 // 16-bits -> double.
2681 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2682 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2683 (LDRHro ro_indexed16:$addr), hsub))>;
2684 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2685 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2686 (LDRHui am_indexed16:$addr), hsub))>;
2687 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2688 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2689 (LDURHi am_unscaled16:$addr), hsub))>;
2690 // 32-bits -> double.
2691 def : Pat <(f64 (uint_to_fp (i32 (load ro_indexed32:$addr)))),
2692 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2693 (LDRSro ro_indexed32:$addr), ssub))>;
2694 def : Pat <(f64 (uint_to_fp (i32 (load am_indexed32:$addr)))),
2695 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2696 (LDRSui am_indexed32:$addr), ssub))>;
2697 def : Pat <(f64 (uint_to_fp (i32 (load am_unscaled32:$addr)))),
2698 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2699 (LDURSi am_unscaled32:$addr), ssub))>;
2700 // 64-bits -> double are handled in target specific dag combine:
2701 // performIntToFpCombine.
2703 //===----------------------------------------------------------------------===//
2704 // Advanced SIMD three different-sized vector instructions.
2705 //===----------------------------------------------------------------------===//
2707 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_arm64_neon_addhn>;
2708 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_arm64_neon_subhn>;
2709 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_arm64_neon_raddhn>;
2710 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_arm64_neon_rsubhn>;
2711 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_arm64_neon_pmull>;
2712 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
2713 int_arm64_neon_sabd>;
2714 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
2715 int_arm64_neon_sabd>;
2716 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
2717 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
2718 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
2719 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
2720 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
2721 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2722 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
2723 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2724 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_arm64_neon_smull>;
2725 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
2726 int_arm64_neon_sqadd>;
2727 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
2728 int_arm64_neon_sqsub>;
2729 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
2730 int_arm64_neon_sqdmull>;
2731 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
2732 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
2733 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
2734 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
2735 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
2736 int_arm64_neon_uabd>;
2737 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
2738 int_arm64_neon_uabd>;
2739 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
2740 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
2741 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
2742 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
2743 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
2744 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2745 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
2746 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2747 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_arm64_neon_umull>;
2748 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
2749 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
2750 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
2751 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
2753 // Patterns for 64-bit pmull
2754 def : Pat<(int_arm64_neon_pmull64 V64:$Rn, V64:$Rm),
2755 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
2756 def : Pat<(int_arm64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
2757 (vector_extract (v2i64 V128:$Rm), (i64 1))),
2758 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
2760 // CodeGen patterns for addhn and subhn instructions, which can actually be
2761 // written in LLVM IR without too much difficulty.
2764 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
2765 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2766 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2768 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2769 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2771 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2772 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2773 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2775 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2776 V128:$Rn, V128:$Rm)>;
2777 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2778 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2780 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2781 V128:$Rn, V128:$Rm)>;
2782 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2783 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2785 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2786 V128:$Rn, V128:$Rm)>;
2789 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
2790 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2791 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2793 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2794 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2796 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2797 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2798 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2800 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2801 V128:$Rn, V128:$Rm)>;
2802 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2803 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2805 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2806 V128:$Rn, V128:$Rm)>;
2807 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2808 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2810 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2811 V128:$Rn, V128:$Rm)>;
2813 //----------------------------------------------------------------------------
2814 // AdvSIMD bitwise extract from vector instruction.
2815 //----------------------------------------------------------------------------
2817 defm EXT : SIMDBitwiseExtract<"ext">;
2819 def : Pat<(v4i16 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2820 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2821 def : Pat<(v8i16 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2822 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2823 def : Pat<(v2i32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2824 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2825 def : Pat<(v2f32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2826 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2827 def : Pat<(v4i32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2828 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2829 def : Pat<(v4f32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2830 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2831 def : Pat<(v2i64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2832 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2833 def : Pat<(v2f64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2834 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2836 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
2838 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
2839 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2840 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
2841 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2842 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
2843 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2844 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
2845 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2846 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
2847 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2848 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
2849 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2852 //----------------------------------------------------------------------------
2853 // AdvSIMD zip vector
2854 //----------------------------------------------------------------------------
2856 defm TRN1 : SIMDZipVector<0b010, "trn1", ARM64trn1>;
2857 defm TRN2 : SIMDZipVector<0b110, "trn2", ARM64trn2>;
2858 defm UZP1 : SIMDZipVector<0b001, "uzp1", ARM64uzp1>;
2859 defm UZP2 : SIMDZipVector<0b101, "uzp2", ARM64uzp2>;
2860 defm ZIP1 : SIMDZipVector<0b011, "zip1", ARM64zip1>;
2861 defm ZIP2 : SIMDZipVector<0b111, "zip2", ARM64zip2>;
2863 //----------------------------------------------------------------------------
2864 // AdvSIMD TBL/TBX instructions
2865 //----------------------------------------------------------------------------
2867 defm TBL : SIMDTableLookup< 0, "tbl">;
2868 defm TBX : SIMDTableLookupTied<1, "tbx">;
2870 def : Pat<(v8i8 (int_arm64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
2871 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
2872 def : Pat<(v16i8 (int_arm64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
2873 (TBLv16i8One V128:$Ri, V128:$Rn)>;
2875 def : Pat<(v8i8 (int_arm64_neon_tbx1 (v8i8 V64:$Rd),
2876 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
2877 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
2878 def : Pat<(v16i8 (int_arm64_neon_tbx1 (v16i8 V128:$Rd),
2879 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
2880 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
2883 //----------------------------------------------------------------------------
2884 // AdvSIMD scalar CPY instruction
2885 //----------------------------------------------------------------------------
2887 defm CPY : SIMDScalarCPY<"cpy">;
2889 //----------------------------------------------------------------------------
2890 // AdvSIMD scalar pairwise instructions
2891 //----------------------------------------------------------------------------
2893 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
2894 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
2895 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
2896 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
2897 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
2898 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
2899 def : Pat<(i64 (int_arm64_neon_saddv (v2i64 V128:$Rn))),
2900 (ADDPv2i64p V128:$Rn)>;
2901 def : Pat<(i64 (int_arm64_neon_uaddv (v2i64 V128:$Rn))),
2902 (ADDPv2i64p V128:$Rn)>;
2903 def : Pat<(f32 (int_arm64_neon_faddv (v2f32 V64:$Rn))),
2904 (FADDPv2i32p V64:$Rn)>;
2905 def : Pat<(f32 (int_arm64_neon_faddv (v4f32 V128:$Rn))),
2906 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
2907 def : Pat<(f64 (int_arm64_neon_faddv (v2f64 V128:$Rn))),
2908 (FADDPv2i64p V128:$Rn)>;
2909 def : Pat<(f32 (int_arm64_neon_fmaxnmv (v2f32 V64:$Rn))),
2910 (FMAXNMPv2i32p V64:$Rn)>;
2911 def : Pat<(f64 (int_arm64_neon_fmaxnmv (v2f64 V128:$Rn))),
2912 (FMAXNMPv2i64p V128:$Rn)>;
2913 def : Pat<(f32 (int_arm64_neon_fmaxv (v2f32 V64:$Rn))),
2914 (FMAXPv2i32p V64:$Rn)>;
2915 def : Pat<(f64 (int_arm64_neon_fmaxv (v2f64 V128:$Rn))),
2916 (FMAXPv2i64p V128:$Rn)>;
2917 def : Pat<(f32 (int_arm64_neon_fminnmv (v2f32 V64:$Rn))),
2918 (FMINNMPv2i32p V64:$Rn)>;
2919 def : Pat<(f64 (int_arm64_neon_fminnmv (v2f64 V128:$Rn))),
2920 (FMINNMPv2i64p V128:$Rn)>;
2921 def : Pat<(f32 (int_arm64_neon_fminv (v2f32 V64:$Rn))),
2922 (FMINPv2i32p V64:$Rn)>;
2923 def : Pat<(f64 (int_arm64_neon_fminv (v2f64 V128:$Rn))),
2924 (FMINPv2i64p V128:$Rn)>;
2926 //----------------------------------------------------------------------------
2927 // AdvSIMD INS/DUP instructions
2928 //----------------------------------------------------------------------------
2930 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
2931 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
2932 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
2933 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
2934 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
2935 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
2936 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
2938 def DUPv2i64lane : SIMDDup64FromElement;
2939 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
2940 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
2941 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
2942 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
2943 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
2944 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
2946 def : Pat<(v2f32 (ARM64dup (f32 FPR32:$Rn))),
2947 (v2f32 (DUPv2i32lane
2948 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
2950 def : Pat<(v4f32 (ARM64dup (f32 FPR32:$Rn))),
2951 (v4f32 (DUPv4i32lane
2952 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
2954 def : Pat<(v2f64 (ARM64dup (f64 FPR64:$Rn))),
2955 (v2f64 (DUPv2i64lane
2956 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
2959 def : Pat<(v2f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
2960 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
2961 def : Pat<(v4f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
2962 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
2963 def : Pat<(v2f64 (ARM64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
2964 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
2969 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
2970 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
2971 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
2972 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
2973 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
2974 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
2975 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
2976 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
2977 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
2978 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
2979 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
2980 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
2982 // Extracting i8 or i16 elements will have the zero-extend transformed to
2983 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
2984 // for ARM64. Match these patterns here since UMOV already zeroes out the high
2985 // bits of the destination register.
2986 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
2988 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
2989 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
2991 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
2995 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
2996 (SUBREG_TO_REG (i32 0),
2997 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
2998 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
2999 (SUBREG_TO_REG (i32 0),
3000 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3002 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3003 (SUBREG_TO_REG (i32 0),
3004 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3005 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3006 (SUBREG_TO_REG (i32 0),
3007 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3009 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3010 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3011 (i32 FPR32:$Rn), ssub))>;
3012 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3013 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3014 (i32 FPR32:$Rn), ssub))>;
3015 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3016 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3017 (i64 FPR64:$Rn), dsub))>;
3019 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3020 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3021 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3022 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3023 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3024 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3026 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3027 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3030 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3032 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3035 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3036 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3038 V128:$Rn, VectorIndexS:$imm,
3039 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3041 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3042 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3044 V128:$Rn, VectorIndexD:$imm,
3045 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3048 // Copy an element at a constant index in one vector into a constant indexed
3049 // element of another.
3050 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3051 // index type and INS extension
3052 def : Pat<(v16i8 (int_arm64_neon_vcopy_lane
3053 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3054 VectorIndexB:$idx2)),
3056 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3058 def : Pat<(v8i16 (int_arm64_neon_vcopy_lane
3059 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3060 VectorIndexH:$idx2)),
3062 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3064 def : Pat<(v4i32 (int_arm64_neon_vcopy_lane
3065 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3066 VectorIndexS:$idx2)),
3068 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3070 def : Pat<(v2i64 (int_arm64_neon_vcopy_lane
3071 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3072 VectorIndexD:$idx2)),
3074 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3077 // Floating point vector extractions are codegen'd as either a sequence of
3078 // subregister extractions, possibly fed by an INS if the lane number is
3079 // anything other than zero.
3080 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3081 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3082 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3083 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3084 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3085 (f64 (EXTRACT_SUBREG
3086 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3087 V128:$Rn, VectorIndexD:$idx),
3089 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3090 (f32 (EXTRACT_SUBREG
3091 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3092 V128:$Rn, VectorIndexS:$idx),
3095 // All concat_vectors operations are canonicalised to act on i64 vectors for
3096 // ARM64. In the general case we need an instruction, which had just as well be
3098 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3099 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3100 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3101 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3103 def : ConcatPat<v2i64, v1i64>;
3104 def : ConcatPat<v2f64, v1f64>;
3105 def : ConcatPat<v4i32, v2i32>;
3106 def : ConcatPat<v4f32, v2f32>;
3107 def : ConcatPat<v8i16, v4i16>;
3108 def : ConcatPat<v16i8, v8i8>;
3110 // If the high lanes are undef, though, we can just ignore them:
3111 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3112 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3113 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3115 def : ConcatUndefPat<v2i64, v1i64>;
3116 def : ConcatUndefPat<v2f64, v1f64>;
3117 def : ConcatUndefPat<v4i32, v2i32>;
3118 def : ConcatUndefPat<v4f32, v2f32>;
3119 def : ConcatUndefPat<v8i16, v4i16>;
3120 def : ConcatUndefPat<v16i8, v8i8>;
3122 //----------------------------------------------------------------------------
3123 // AdvSIMD across lanes instructions
3124 //----------------------------------------------------------------------------
3126 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3127 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3128 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3129 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3130 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3131 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3132 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3133 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_arm64_neon_fmaxnmv>;
3134 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_arm64_neon_fmaxv>;
3135 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_arm64_neon_fminnmv>;
3136 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_arm64_neon_fminv>;
3138 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3139 // If there is a sign extension after this intrinsic, consume it as smov already
3141 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3143 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3144 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3146 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3148 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3149 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3151 // If there is a sign extension after this intrinsic, consume it as smov already
3153 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3155 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3156 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3158 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3160 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3161 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3163 // If there is a sign extension after this intrinsic, consume it as smov already
3165 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3167 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3168 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3170 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3172 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3173 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3175 // If there is a sign extension after this intrinsic, consume it as smov already
3177 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3179 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3180 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3182 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3184 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3185 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3188 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3189 (i32 (EXTRACT_SUBREG
3190 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3191 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3195 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3196 // If there is a masking operation keeping only what has been actually
3197 // generated, consume it.
3198 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3199 (i32 (EXTRACT_SUBREG
3200 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3201 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3203 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3204 (i32 (EXTRACT_SUBREG
3205 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3206 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3208 // If there is a masking operation keeping only what has been actually
3209 // generated, consume it.
3210 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3211 (i32 (EXTRACT_SUBREG
3212 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3213 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3215 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3216 (i32 (EXTRACT_SUBREG
3217 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3218 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3221 // If there is a masking operation keeping only what has been actually
3222 // generated, consume it.
3223 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3224 (i32 (EXTRACT_SUBREG
3225 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3226 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3228 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3229 (i32 (EXTRACT_SUBREG
3230 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3231 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3233 // If there is a masking operation keeping only what has been actually
3234 // generated, consume it.
3235 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3236 (i32 (EXTRACT_SUBREG
3237 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3238 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3240 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3241 (i32 (EXTRACT_SUBREG
3242 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3243 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3246 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3247 (i32 (EXTRACT_SUBREG
3248 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3249 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3254 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3255 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3257 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3258 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3260 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3262 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3263 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3266 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3267 (i32 (EXTRACT_SUBREG
3268 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3269 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3271 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3272 (i32 (EXTRACT_SUBREG
3273 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3274 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3277 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3278 (i64 (EXTRACT_SUBREG
3279 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3280 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3284 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3286 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3287 (i32 (EXTRACT_SUBREG
3288 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3289 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3291 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3292 (i32 (EXTRACT_SUBREG
3293 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3294 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3297 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3298 (i32 (EXTRACT_SUBREG
3299 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3300 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3302 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3303 (i32 (EXTRACT_SUBREG
3304 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3305 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3308 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3309 (i64 (EXTRACT_SUBREG
3310 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3311 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3315 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_arm64_neon_saddv>;
3316 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3317 def : Pat<(i32 (int_arm64_neon_saddv (v2i32 V64:$Rn))),
3318 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3320 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_arm64_neon_uaddv>;
3321 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3322 def : Pat<(i32 (int_arm64_neon_uaddv (v2i32 V64:$Rn))),
3323 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3325 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_arm64_neon_smaxv>;
3326 def : Pat<(i32 (int_arm64_neon_smaxv (v2i32 V64:$Rn))),
3327 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3329 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_arm64_neon_sminv>;
3330 def : Pat<(i32 (int_arm64_neon_sminv (v2i32 V64:$Rn))),
3331 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3333 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_arm64_neon_umaxv>;
3334 def : Pat<(i32 (int_arm64_neon_umaxv (v2i32 V64:$Rn))),
3335 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3337 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_arm64_neon_uminv>;
3338 def : Pat<(i32 (int_arm64_neon_uminv (v2i32 V64:$Rn))),
3339 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3341 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_arm64_neon_saddlv>;
3342 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_arm64_neon_uaddlv>;
3344 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3345 def : Pat<(i64 (int_arm64_neon_saddlv (v2i32 V64:$Rn))),
3346 (i64 (EXTRACT_SUBREG
3347 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3348 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3350 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3351 def : Pat<(i64 (int_arm64_neon_uaddlv (v2i32 V64:$Rn))),
3352 (i64 (EXTRACT_SUBREG
3353 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3354 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3357 //------------------------------------------------------------------------------
3358 // AdvSIMD modified immediate instructions
3359 //------------------------------------------------------------------------------
3362 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", ARM64bici>;
3364 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", ARM64orri>;
3368 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3370 [(set (v2f64 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3371 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3373 [(set (v2f32 V64:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3374 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3376 [(set (v4f32 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3380 // EDIT byte mask: scalar
3381 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3382 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3383 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3384 // The movi_edit node has the immediate value already encoded, so we use
3385 // a plain imm0_255 here.
3386 def : Pat<(f64 (ARM64movi_edit imm0_255:$shift)),
3387 (MOVID imm0_255:$shift)>;
3389 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3390 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3391 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3392 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3394 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3395 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3396 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3397 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3399 // EDIT byte mask: 2d
3401 // The movi_edit node has the immediate value already encoded, so we use
3402 // a plain imm0_255 in the pattern
3403 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3404 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3407 [(set (v2i64 V128:$Rd), (ARM64movi_edit imm0_255:$imm8))]>;
3410 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3411 // Complexity is added to break a tie with a plain MOVI.
3412 let AddedComplexity = 1 in {
3413 def : Pat<(f32 fpimm0),
3414 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3416 def : Pat<(f64 fpimm0),
3417 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3421 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3422 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3423 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3424 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3426 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3427 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3428 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3429 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3431 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3432 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3433 def : Pat<(v2i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3434 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
3435 def : Pat<(v4i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3436 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
3437 def : Pat<(v4i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3438 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
3439 def : Pat<(v8i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3440 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
3442 // EDIT per word: 2s & 4s with MSL shifter
3443 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
3444 [(set (v2i32 V64:$Rd),
3445 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3446 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
3447 [(set (v4i32 V128:$Rd),
3448 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3450 // Per byte: 8b & 16b
3451 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
3453 [(set (v8i8 V64:$Rd), (ARM64movi imm0_255:$imm8))]>;
3454 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
3456 [(set (v16i8 V128:$Rd), (ARM64movi imm0_255:$imm8))]>;
3460 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3461 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
3462 def : Pat<(v2i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3463 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
3464 def : Pat<(v4i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3465 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
3466 def : Pat<(v4i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3467 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
3468 def : Pat<(v8i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3469 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
3471 // EDIT per word: 2s & 4s with MSL shifter
3472 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
3473 [(set (v2i32 V64:$Rd),
3474 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3475 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
3476 [(set (v4i32 V128:$Rd),
3477 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3479 //----------------------------------------------------------------------------
3480 // AdvSIMD indexed element
3481 //----------------------------------------------------------------------------
3483 let neverHasSideEffects = 1 in {
3484 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
3485 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
3488 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
3489 // instruction expects the addend first, while the intrinsic expects it last.
3491 // On the other hand, there are quite a few valid combinatorial options due to
3492 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
3493 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3494 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
3495 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3496 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
3498 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3499 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
3500 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3501 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
3502 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3503 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
3504 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3505 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
3507 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
3508 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3510 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3511 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3512 VectorIndexS:$idx))),
3513 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3514 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3515 (v2f32 (ARM64duplane32
3516 (v4f32 (insert_subvector undef,
3517 (v2f32 (fneg V64:$Rm)),
3519 VectorIndexS:$idx)))),
3520 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3521 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3522 VectorIndexS:$idx)>;
3523 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3524 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3525 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3526 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3528 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3530 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3531 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3532 VectorIndexS:$idx))),
3533 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
3534 VectorIndexS:$idx)>;
3535 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3536 (v4f32 (ARM64duplane32
3537 (v4f32 (insert_subvector undef,
3538 (v2f32 (fneg V64:$Rm)),
3540 VectorIndexS:$idx)))),
3541 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3542 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3543 VectorIndexS:$idx)>;
3544 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3545 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3546 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3547 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3549 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
3550 // (DUPLANE from 64-bit would be trivial).
3551 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3552 (ARM64duplane64 (v2f64 (fneg V128:$Rm)),
3553 VectorIndexD:$idx))),
3555 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3556 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3557 (ARM64dup (f64 (fneg FPR64Op:$Rm))))),
3558 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
3559 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
3561 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
3562 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3563 (vector_extract (v4f32 (fneg V128:$Rm)),
3564 VectorIndexS:$idx))),
3565 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3566 V128:$Rm, VectorIndexS:$idx)>;
3567 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3568 (vector_extract (v2f32 (fneg V64:$Rm)),
3569 VectorIndexS:$idx))),
3570 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3571 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
3573 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
3574 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
3575 (vector_extract (v2f64 (fneg V128:$Rm)),
3576 VectorIndexS:$idx))),
3577 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
3578 V128:$Rm, VectorIndexS:$idx)>;
3581 defm : FMLSIndexedAfterNegPatterns<
3582 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
3583 defm : FMLSIndexedAfterNegPatterns<
3584 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
3586 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_arm64_neon_fmulx>;
3587 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
3589 def : Pat<(v2f32 (fmul V64:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3590 (FMULv2i32_indexed V64:$Rn,
3591 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3593 def : Pat<(v4f32 (fmul V128:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3594 (FMULv4i32_indexed V128:$Rn,
3595 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3597 def : Pat<(v2f64 (fmul V128:$Rn, (ARM64dup (f64 FPR64:$Rm)))),
3598 (FMULv2i64_indexed V128:$Rn,
3599 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
3602 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_arm64_neon_sqdmulh>;
3603 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_arm64_neon_sqrdmulh>;
3604 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
3605 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
3606 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
3607 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
3608 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
3609 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
3610 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3611 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
3612 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3613 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
3614 int_arm64_neon_smull>;
3615 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
3616 int_arm64_neon_sqadd>;
3617 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
3618 int_arm64_neon_sqsub>;
3619 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_arm64_neon_sqdmull>;
3620 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
3621 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3622 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
3623 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3624 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
3625 int_arm64_neon_umull>;
3627 // A scalar sqdmull with the second operand being a vector lane can be
3628 // handled directly with the indexed instruction encoding.
3629 def : Pat<(int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3630 (vector_extract (v4i32 V128:$Vm),
3631 VectorIndexS:$idx)),
3632 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
3634 //----------------------------------------------------------------------------
3635 // AdvSIMD scalar shift instructions
3636 //----------------------------------------------------------------------------
3637 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
3638 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
3639 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
3640 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
3641 // Codegen patterns for the above. We don't put these directly on the
3642 // instructions because TableGen's type inference can't handle the truth.
3643 // Having the same base pattern for fp <--> int totally freaks it out.
3644 def : Pat<(int_arm64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
3645 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
3646 def : Pat<(int_arm64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
3647 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
3648 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
3649 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3650 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
3651 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3652 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
3654 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3655 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
3657 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3658 def : Pat<(int_arm64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
3659 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3660 def : Pat<(int_arm64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
3661 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3662 def : Pat<(f64 (int_arm64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3663 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3664 def : Pat<(f64 (int_arm64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3665 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3666 def : Pat<(v1f64 (int_arm64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
3668 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3669 def : Pat<(v1f64 (int_arm64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
3671 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3673 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", ARM64vshl>;
3674 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
3675 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
3676 int_arm64_neon_sqrshrn>;
3677 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
3678 int_arm64_neon_sqrshrun>;
3679 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3680 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3681 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
3682 int_arm64_neon_sqshrn>;
3683 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
3684 int_arm64_neon_sqshrun>;
3685 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
3686 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", ARM64srshri>;
3687 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
3688 TriOpFrag<(add node:$LHS,
3689 (ARM64srshri node:$MHS, node:$RHS))>>;
3690 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", ARM64vashr>;
3691 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
3692 TriOpFrag<(add node:$LHS,
3693 (ARM64vashr node:$MHS, node:$RHS))>>;
3694 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
3695 int_arm64_neon_uqrshrn>;
3696 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3697 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
3698 int_arm64_neon_uqshrn>;
3699 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", ARM64urshri>;
3700 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
3701 TriOpFrag<(add node:$LHS,
3702 (ARM64urshri node:$MHS, node:$RHS))>>;
3703 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", ARM64vlshr>;
3704 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
3705 TriOpFrag<(add node:$LHS,
3706 (ARM64vlshr node:$MHS, node:$RHS))>>;
3708 //----------------------------------------------------------------------------
3709 // AdvSIMD vector shift instructions
3710 //----------------------------------------------------------------------------
3711 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_arm64_neon_vcvtfp2fxs>;
3712 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_arm64_neon_vcvtfp2fxu>;
3713 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
3714 int_arm64_neon_vcvtfxs2fp>;
3715 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
3716 int_arm64_neon_rshrn>;
3717 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", ARM64vshl>;
3718 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
3719 BinOpFrag<(trunc (ARM64vashr node:$LHS, node:$RHS))>>;
3720 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_arm64_neon_vsli>;
3721 def : Pat<(v1i64 (int_arm64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3722 (i32 vecshiftL64:$imm))),
3723 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
3724 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
3725 int_arm64_neon_sqrshrn>;
3726 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
3727 int_arm64_neon_sqrshrun>;
3728 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3729 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3730 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
3731 int_arm64_neon_sqshrn>;
3732 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
3733 int_arm64_neon_sqshrun>;
3734 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_arm64_neon_vsri>;
3735 def : Pat<(v1i64 (int_arm64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3736 (i32 vecshiftR64:$imm))),
3737 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
3738 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", ARM64srshri>;
3739 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
3740 TriOpFrag<(add node:$LHS,
3741 (ARM64srshri node:$MHS, node:$RHS))> >;
3742 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
3743 BinOpFrag<(ARM64vshl (sext node:$LHS), node:$RHS)>>;
3745 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", ARM64vashr>;
3746 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
3747 TriOpFrag<(add node:$LHS, (ARM64vashr node:$MHS, node:$RHS))>>;
3748 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
3749 int_arm64_neon_vcvtfxu2fp>;
3750 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
3751 int_arm64_neon_uqrshrn>;
3752 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3753 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
3754 int_arm64_neon_uqshrn>;
3755 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", ARM64urshri>;
3756 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
3757 TriOpFrag<(add node:$LHS,
3758 (ARM64urshri node:$MHS, node:$RHS))> >;
3759 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
3760 BinOpFrag<(ARM64vshl (zext node:$LHS), node:$RHS)>>;
3761 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", ARM64vlshr>;
3762 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
3763 TriOpFrag<(add node:$LHS, (ARM64vlshr node:$MHS, node:$RHS))> >;
3765 // SHRN patterns for when a logical right shift was used instead of arithmetic
3766 // (the immediate guarantees no sign bits actually end up in the result so it
3768 def : Pat<(v8i8 (trunc (ARM64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
3769 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
3770 def : Pat<(v4i16 (trunc (ARM64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
3771 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
3772 def : Pat<(v2i32 (trunc (ARM64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
3773 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
3775 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
3776 (trunc (ARM64vlshr (v8i16 V128:$Rn),
3777 vecshiftR16Narrow:$imm)))),
3778 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3779 V128:$Rn, vecshiftR16Narrow:$imm)>;
3780 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
3781 (trunc (ARM64vlshr (v4i32 V128:$Rn),
3782 vecshiftR32Narrow:$imm)))),
3783 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3784 V128:$Rn, vecshiftR32Narrow:$imm)>;
3785 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
3786 (trunc (ARM64vlshr (v2i64 V128:$Rn),
3787 vecshiftR64Narrow:$imm)))),
3788 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3789 V128:$Rn, vecshiftR32Narrow:$imm)>;
3791 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
3792 // Anyexts are implemented as zexts.
3793 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
3794 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
3795 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
3796 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
3797 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
3798 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
3799 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
3800 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
3801 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
3802 // Also match an extend from the upper half of a 128 bit source register.
3803 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3804 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
3805 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3806 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
3807 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3808 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
3809 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3810 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
3811 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3812 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
3813 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3814 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
3815 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3816 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
3817 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3818 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
3819 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3820 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
3822 // Vector shift sxtl aliases
3823 def : InstAlias<"sxtl.8h $dst, $src1",
3824 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3825 def : InstAlias<"sxtl $dst.8h, $src1.8b",
3826 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3827 def : InstAlias<"sxtl.4s $dst, $src1",
3828 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3829 def : InstAlias<"sxtl $dst.4s, $src1.4h",
3830 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3831 def : InstAlias<"sxtl.2d $dst, $src1",
3832 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3833 def : InstAlias<"sxtl $dst.2d, $src1.2s",
3834 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3836 // Vector shift sxtl2 aliases
3837 def : InstAlias<"sxtl2.8h $dst, $src1",
3838 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3839 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
3840 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3841 def : InstAlias<"sxtl2.4s $dst, $src1",
3842 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3843 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
3844 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3845 def : InstAlias<"sxtl2.2d $dst, $src1",
3846 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
3847 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
3848 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
3850 // Vector shift uxtl aliases
3851 def : InstAlias<"uxtl.8h $dst, $src1",
3852 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3853 def : InstAlias<"uxtl $dst.8h, $src1.8b",
3854 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3855 def : InstAlias<"uxtl.4s $dst, $src1",
3856 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3857 def : InstAlias<"uxtl $dst.4s, $src1.4h",
3858 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3859 def : InstAlias<"uxtl.2d $dst, $src1",
3860 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3861 def : InstAlias<"uxtl $dst.2d, $src1.2s",
3862 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3864 // Vector shift uxtl2 aliases
3865 def : InstAlias<"uxtl2.8h $dst, $src1",
3866 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3867 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
3868 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3869 def : InstAlias<"uxtl2.4s $dst, $src1",
3870 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3871 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
3872 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3873 def : InstAlias<"uxtl2.2d $dst, $src1",
3874 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
3875 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
3876 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
3878 // If an integer is about to be converted to a floating point value,
3879 // just load it on the floating point unit.
3880 // These patterns are more complex because floating point loads do not
3881 // support sign extension.
3882 // The sign extension has to be explicitly added and is only supported for
3883 // one step: byte-to-half, half-to-word, word-to-doubleword.
3884 // SCVTF GPR -> FPR is 9 cycles.
3885 // SCVTF FPR -> FPR is 4 cyclces.
3886 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
3887 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
3888 // and still being faster.
3889 // However, this is not good for code size.
3890 // 8-bits -> float. 2 sizes step-up.
3891 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 ro_indexed8:$addr)))),
3892 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3897 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3898 (LDRBro ro_indexed8:$addr),
3903 ssub)))>, Requires<[NotForCodeSize]>;
3904 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_indexed8:$addr)))),
3905 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3910 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3911 (LDRBui am_indexed8:$addr),
3916 ssub)))>, Requires<[NotForCodeSize]>;
3917 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_unscaled8:$addr)))),
3918 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3923 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3924 (LDURBi am_unscaled8:$addr),
3929 ssub)))>, Requires<[NotForCodeSize]>;
3930 // 16-bits -> float. 1 size step-up.
3931 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
3932 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3934 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3935 (LDRHro ro_indexed16:$addr),
3938 ssub)))>, Requires<[NotForCodeSize]>;
3939 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
3940 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3942 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3943 (LDRHui am_indexed16:$addr),
3946 ssub)))>, Requires<[NotForCodeSize]>;
3947 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
3948 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3950 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3951 (LDURHi am_unscaled16:$addr),
3954 ssub)))>, Requires<[NotForCodeSize]>;
3955 // 32-bits to 32-bits are handled in target specific dag combine:
3956 // performIntToFpCombine.
3957 // 64-bits integer to 32-bits floating point, not possible with
3958 // SCVTF on floating point registers (both source and destination
3959 // must have the same size).
3961 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3962 // 8-bits -> double. 3 size step-up: give up.
3963 // 16-bits -> double. 2 size step.
3964 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
3965 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
3970 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3971 (LDRHro ro_indexed16:$addr),
3976 dsub)))>, Requires<[NotForCodeSize]>;
3977 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
3978 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
3983 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3984 (LDRHui am_indexed16:$addr),
3989 dsub)))>, Requires<[NotForCodeSize]>;
3990 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
3991 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
3996 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3997 (LDURHi am_unscaled16:$addr),
4002 dsub)))>, Requires<[NotForCodeSize]>;
4003 // 32-bits -> double. 1 size step-up.
4004 def : Pat <(f64 (sint_to_fp (i32 (load ro_indexed32:$addr)))),
4005 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4007 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4008 (LDRSro ro_indexed32:$addr),
4011 dsub)))>, Requires<[NotForCodeSize]>;
4012 def : Pat <(f64 (sint_to_fp (i32 (load am_indexed32:$addr)))),
4013 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4015 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4016 (LDRSui am_indexed32:$addr),
4019 dsub)))>, Requires<[NotForCodeSize]>;
4020 def : Pat <(f64 (sint_to_fp (i32 (load am_unscaled32:$addr)))),
4021 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4023 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4024 (LDURSi am_unscaled32:$addr),
4027 dsub)))>, Requires<[NotForCodeSize]>;
4028 // 64-bits -> double are handled in target specific dag combine:
4029 // performIntToFpCombine.
4032 //----------------------------------------------------------------------------
4033 // AdvSIMD Load-Store Structure
4034 //----------------------------------------------------------------------------
4035 defm LD1 : SIMDLd1Multiple<"ld1">;
4036 defm LD2 : SIMDLd2Multiple<"ld2">;
4037 defm LD3 : SIMDLd3Multiple<"ld3">;
4038 defm LD4 : SIMDLd4Multiple<"ld4">;
4040 defm ST1 : SIMDSt1Multiple<"st1">;
4041 defm ST2 : SIMDSt2Multiple<"st2">;
4042 defm ST3 : SIMDSt3Multiple<"st3">;
4043 defm ST4 : SIMDSt4Multiple<"st4">;
4045 class Ld1Pat<ValueType ty, Instruction INST>
4046 : Pat<(ty (load am_simdnoindex:$vaddr)), (INST am_simdnoindex:$vaddr)>;
4048 def : Ld1Pat<v16i8, LD1Onev16b>;
4049 def : Ld1Pat<v8i16, LD1Onev8h>;
4050 def : Ld1Pat<v4i32, LD1Onev4s>;
4051 def : Ld1Pat<v2i64, LD1Onev2d>;
4052 def : Ld1Pat<v8i8, LD1Onev8b>;
4053 def : Ld1Pat<v4i16, LD1Onev4h>;
4054 def : Ld1Pat<v2i32, LD1Onev2s>;
4055 def : Ld1Pat<v1i64, LD1Onev1d>;
4057 class St1Pat<ValueType ty, Instruction INST>
4058 : Pat<(store ty:$Vt, am_simdnoindex:$vaddr),
4059 (INST ty:$Vt, am_simdnoindex:$vaddr)>;
4061 def : St1Pat<v16i8, ST1Onev16b>;
4062 def : St1Pat<v8i16, ST1Onev8h>;
4063 def : St1Pat<v4i32, ST1Onev4s>;
4064 def : St1Pat<v2i64, ST1Onev2d>;
4065 def : St1Pat<v8i8, ST1Onev8b>;
4066 def : St1Pat<v4i16, ST1Onev4h>;
4067 def : St1Pat<v2i32, ST1Onev2s>;
4068 def : St1Pat<v1i64, ST1Onev1d>;
4074 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4075 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4076 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4077 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4078 let mayLoad = 1, neverHasSideEffects = 1 in {
4079 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4080 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4081 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4082 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4083 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4084 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4085 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4086 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4087 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4088 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4089 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4090 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4091 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4092 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4093 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4094 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4097 def : Pat<(v8i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4098 (LD1Rv8b am_simdnoindex:$vaddr)>;
4099 def : Pat<(v16i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4100 (LD1Rv16b am_simdnoindex:$vaddr)>;
4101 def : Pat<(v4i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4102 (LD1Rv4h am_simdnoindex:$vaddr)>;
4103 def : Pat<(v8i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4104 (LD1Rv8h am_simdnoindex:$vaddr)>;
4105 def : Pat<(v2i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4106 (LD1Rv2s am_simdnoindex:$vaddr)>;
4107 def : Pat<(v4i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4108 (LD1Rv4s am_simdnoindex:$vaddr)>;
4109 def : Pat<(v2i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4110 (LD1Rv2d am_simdnoindex:$vaddr)>;
4111 def : Pat<(v1i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4112 (LD1Rv1d am_simdnoindex:$vaddr)>;
4113 // Grab the floating point version too
4114 def : Pat<(v2f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4115 (LD1Rv2s am_simdnoindex:$vaddr)>;
4116 def : Pat<(v4f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4117 (LD1Rv4s am_simdnoindex:$vaddr)>;
4118 def : Pat<(v2f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4119 (LD1Rv2d am_simdnoindex:$vaddr)>;
4120 def : Pat<(v1f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4121 (LD1Rv1d am_simdnoindex:$vaddr)>;
4123 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4124 ValueType VTy, ValueType STy, Instruction LD1>
4125 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4126 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4127 (LD1 VecListOne128:$Rd, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4129 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4130 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4131 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4132 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4133 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4134 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4136 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4137 ValueType VTy, ValueType STy, Instruction LD1>
4138 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4139 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4141 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4142 VecIndex:$idx, am_simdnoindex:$vaddr),
4145 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4146 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4147 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4148 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4151 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4152 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4153 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4154 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4157 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4158 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4159 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4160 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4162 let AddedComplexity = 8 in
4163 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4164 ValueType VTy, ValueType STy, Instruction ST1>
4166 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4167 am_simdnoindex:$vaddr),
4168 (ST1 VecListOne128:$Vt, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4170 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4171 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4172 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4173 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4174 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4175 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4177 let AddedComplexity = 8 in
4178 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4179 ValueType VTy, ValueType STy, Instruction ST1>
4181 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4182 am_simdnoindex:$vaddr),
4183 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4184 VecIndex:$idx, am_simdnoindex:$vaddr)>;
4186 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4187 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4188 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4189 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4191 let mayStore = 1, neverHasSideEffects = 1 in {
4192 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4193 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4194 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4195 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4196 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4197 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4198 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4199 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4200 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4201 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4202 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4203 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4206 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4207 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4208 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4209 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4211 //----------------------------------------------------------------------------
4212 // Crypto extensions
4213 //----------------------------------------------------------------------------
4215 def AESErr : AESTiedInst<0b0100, "aese", int_arm64_crypto_aese>;
4216 def AESDrr : AESTiedInst<0b0101, "aesd", int_arm64_crypto_aesd>;
4217 def AESMCrr : AESInst< 0b0110, "aesmc", int_arm64_crypto_aesmc>;
4218 def AESIMCrr : AESInst< 0b0111, "aesimc", int_arm64_crypto_aesimc>;
4220 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_arm64_crypto_sha1c>;
4221 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_arm64_crypto_sha1p>;
4222 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_arm64_crypto_sha1m>;
4223 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_arm64_crypto_sha1su0>;
4224 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_arm64_crypto_sha256h>;
4225 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_arm64_crypto_sha256h2>;
4226 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_arm64_crypto_sha256su1>;
4228 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_arm64_crypto_sha1h>;
4229 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_arm64_crypto_sha1su1>;
4230 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_arm64_crypto_sha256su0>;
4232 //----------------------------------------------------------------------------
4234 //----------------------------------------------------------------------------
4235 // FIXME: Like for X86, these should go in their own separate .td file.
4237 // Any instruction that defines a 32-bit result leaves the high half of the
4238 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4239 // be copying from a truncate. But any other 32-bit operation will zero-extend
4241 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4242 def def32 : PatLeaf<(i32 GPR32:$src), [{
4243 return N->getOpcode() != ISD::TRUNCATE &&
4244 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4245 N->getOpcode() != ISD::CopyFromReg;
4248 // In the case of a 32-bit def that is known to implicitly zero-extend,
4249 // we can use a SUBREG_TO_REG.
4250 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4252 // For an anyext, we don't care what the high bits are, so we can perform an
4253 // INSERT_SUBREF into an IMPLICIT_DEF.
4254 def : Pat<(i64 (anyext GPR32:$src)),
4255 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4257 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4258 // instruction (UBFM) on the enclosing super-reg.
4259 def : Pat<(i64 (zext GPR32:$src)),
4260 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4262 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4263 // containing super-reg.
4264 def : Pat<(i64 (sext GPR32:$src)),
4265 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4266 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4267 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4268 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4269 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4270 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4271 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4272 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4274 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4275 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4276 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4277 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4278 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4279 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4281 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4282 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4283 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4284 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4285 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4286 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4288 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4289 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4290 (i64 (i64shift_a imm0_63:$imm)),
4291 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4293 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4294 // AddedComplexity for the following patterns since we want to match sext + sra
4295 // patterns before we attempt to match a single sra node.
4296 let AddedComplexity = 20 in {
4297 // We support all sext + sra combinations which preserve at least one bit of the
4298 // original value which is to be sign extended. E.g. we support shifts up to
4300 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4301 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4302 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4303 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4305 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4306 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4307 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4308 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4310 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4311 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4312 (i64 imm0_31:$imm), 31)>;
4313 } // AddedComplexity = 20
4315 // To truncate, we can simply extract from a subregister.
4316 def : Pat<(i32 (trunc GPR64sp:$src)),
4317 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4319 // __builtin_trap() uses the BRK instruction on ARM64.
4320 def : Pat<(trap), (BRK 1)>;
4322 // Conversions within AdvSIMD types in the same register size are free.
4324 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
4325 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
4326 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
4327 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4328 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
4329 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4331 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
4332 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
4333 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
4334 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4335 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
4336 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4338 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
4339 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
4340 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
4341 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4342 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
4343 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4345 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
4346 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
4347 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
4348 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4349 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
4350 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4352 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
4353 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
4354 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
4355 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
4356 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
4357 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
4359 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
4360 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
4361 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
4362 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
4363 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
4364 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
4366 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4367 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
4368 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
4369 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
4370 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
4371 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4374 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
4375 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
4376 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
4377 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
4378 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
4380 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
4381 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
4382 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
4383 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
4384 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
4385 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
4387 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
4388 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
4389 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
4390 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
4391 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
4392 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
4394 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
4395 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
4396 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
4397 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
4398 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
4399 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
4401 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
4402 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
4403 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
4404 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
4405 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
4406 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
4408 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
4409 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
4410 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
4411 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
4412 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
4413 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
4415 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
4416 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
4417 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
4418 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
4419 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
4420 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
4422 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
4423 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4424 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
4425 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4426 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
4427 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4428 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
4429 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4431 // A 64-bit subvector insert to the first 128-bit vector position
4432 // is a subregister copy that needs no instruction.
4433 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
4434 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4435 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
4436 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4437 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
4438 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4439 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
4440 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4441 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
4442 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4443 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
4444 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4446 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
4448 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
4449 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
4450 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
4451 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
4452 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
4453 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
4454 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
4455 // so we match on v4f32 here, not v2f32. This will also catch adding
4456 // the low two lanes of a true v4f32 vector.
4457 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
4458 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
4459 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
4461 // Scalar 64-bit shifts in FPR64 registers.
4462 def : Pat<(i64 (int_arm64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4463 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4464 def : Pat<(i64 (int_arm64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4465 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4466 def : Pat<(i64 (int_arm64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4467 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4468 def : Pat<(i64 (int_arm64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4469 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4471 // Tail call return handling. These are all compiler pseudo-instructions,
4472 // so no encoding information or anything like that.
4473 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
4474 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst), []>;
4475 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst), []>;
4478 def : Pat<(ARM64tcret tcGPR64:$dst), (TCRETURNri tcGPR64:$dst)>;
4479 def : Pat<(ARM64tcret (i64 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4480 def : Pat<(ARM64tcret (i64 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4482 include "ARM64InstrAtomics.td"