1 //===- ARM64InstrInfo.td - Describe the ARM64 Instructions -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // ARM64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
26 //===----------------------------------------------------------------------===//
27 // ARM64-specific DAG Nodes.
30 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
31 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
34 SDTCisInt<0>, SDTCisVT<1, i32>]>;
36 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
37 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
43 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
44 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
51 def SDT_ARM64Brcond : SDTypeProfile<0, 3,
52 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
54 def SDT_ARM64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
55 def SDT_ARM64tbz : SDTypeProfile<0, 3, [SDTCisVT<0, i64>, SDTCisVT<1, i64>,
56 SDTCisVT<2, OtherVT>]>;
59 def SDT_ARM64CSel : SDTypeProfile<1, 4,
64 def SDT_ARM64FCmp : SDTypeProfile<0, 2,
67 def SDT_ARM64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
68 def SDT_ARM64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
69 def SDT_ARM64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
72 def SDT_ARM64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
73 def SDT_ARM64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
74 def SDT_ARM64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
75 SDTCisInt<2>, SDTCisInt<3>]>;
76 def SDT_ARM64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
77 def SDT_ARM64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
78 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
79 def SDT_ARM64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
81 def SDT_ARM64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
82 def SDT_ARM64fcmpz : SDTypeProfile<1, 1, []>;
83 def SDT_ARM64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
84 def SDT_ARM64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
86 def SDT_ARM64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
89 def SDT_ARM64TCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
90 def SDT_ARM64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
92 def SDT_ARM64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
94 def SDT_ARM64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
96 def SDT_ARM64WrapperLarge : SDTypeProfile<1, 4,
97 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
98 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
103 def ARM64adrp : SDNode<"ARM64ISD::ADRP", SDTIntUnaryOp, []>;
104 def ARM64addlow : SDNode<"ARM64ISD::ADDlow", SDTIntBinOp, []>;
105 def ARM64LOADgot : SDNode<"ARM64ISD::LOADgot", SDTIntUnaryOp>;
106 def ARM64callseq_start : SDNode<"ISD::CALLSEQ_START",
107 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
108 [SDNPHasChain, SDNPOutGlue]>;
109 def ARM64callseq_end : SDNode<"ISD::CALLSEQ_END",
110 SDCallSeqEnd<[ SDTCisVT<0, i32>,
112 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
113 def ARM64call : SDNode<"ARM64ISD::CALL",
114 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
115 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
117 def ARM64brcond : SDNode<"ARM64ISD::BRCOND", SDT_ARM64Brcond,
119 def ARM64cbz : SDNode<"ARM64ISD::CBZ", SDT_ARM64cbz,
121 def ARM64cbnz : SDNode<"ARM64ISD::CBNZ", SDT_ARM64cbz,
123 def ARM64tbz : SDNode<"ARM64ISD::TBZ", SDT_ARM64tbz,
125 def ARM64tbnz : SDNode<"ARM64ISD::TBNZ", SDT_ARM64tbz,
129 def ARM64csel : SDNode<"ARM64ISD::CSEL", SDT_ARM64CSel>;
130 def ARM64csinv : SDNode<"ARM64ISD::CSINV", SDT_ARM64CSel>;
131 def ARM64csneg : SDNode<"ARM64ISD::CSNEG", SDT_ARM64CSel>;
132 def ARM64csinc : SDNode<"ARM64ISD::CSINC", SDT_ARM64CSel>;
133 def ARM64retflag : SDNode<"ARM64ISD::RET_FLAG", SDTNone,
134 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
135 def ARM64adc : SDNode<"ARM64ISD::ADC", SDTBinaryArithWithFlagsIn >;
136 def ARM64sbc : SDNode<"ARM64ISD::SBC", SDTBinaryArithWithFlagsIn>;
137 def ARM64add_flag : SDNode<"ARM64ISD::ADDS", SDTBinaryArithWithFlagsOut,
139 def ARM64sub_flag : SDNode<"ARM64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
140 def ARM64and_flag : SDNode<"ARM64ISD::ANDS", SDTBinaryArithWithFlagsOut,
142 def ARM64adc_flag : SDNode<"ARM64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
143 def ARM64sbc_flag : SDNode<"ARM64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
145 def ARM64threadpointer : SDNode<"ARM64ISD::THREAD_POINTER", SDTPtrLeaf>;
147 def ARM64fcmp : SDNode<"ARM64ISD::FCMP", SDT_ARM64FCmp>;
149 def ARM64fmax : SDNode<"ARM64ISD::FMAX", SDTFPBinOp>;
150 def ARM64fmin : SDNode<"ARM64ISD::FMIN", SDTFPBinOp>;
152 def ARM64dup : SDNode<"ARM64ISD::DUP", SDT_ARM64Dup>;
153 def ARM64duplane8 : SDNode<"ARM64ISD::DUPLANE8", SDT_ARM64DupLane>;
154 def ARM64duplane16 : SDNode<"ARM64ISD::DUPLANE16", SDT_ARM64DupLane>;
155 def ARM64duplane32 : SDNode<"ARM64ISD::DUPLANE32", SDT_ARM64DupLane>;
156 def ARM64duplane64 : SDNode<"ARM64ISD::DUPLANE64", SDT_ARM64DupLane>;
158 def ARM64zip1 : SDNode<"ARM64ISD::ZIP1", SDT_ARM64Zip>;
159 def ARM64zip2 : SDNode<"ARM64ISD::ZIP2", SDT_ARM64Zip>;
160 def ARM64uzp1 : SDNode<"ARM64ISD::UZP1", SDT_ARM64Zip>;
161 def ARM64uzp2 : SDNode<"ARM64ISD::UZP2", SDT_ARM64Zip>;
162 def ARM64trn1 : SDNode<"ARM64ISD::TRN1", SDT_ARM64Zip>;
163 def ARM64trn2 : SDNode<"ARM64ISD::TRN2", SDT_ARM64Zip>;
165 def ARM64movi_edit : SDNode<"ARM64ISD::MOVIedit", SDT_ARM64MOVIedit>;
166 def ARM64movi_shift : SDNode<"ARM64ISD::MOVIshift", SDT_ARM64MOVIshift>;
167 def ARM64movi_msl : SDNode<"ARM64ISD::MOVImsl", SDT_ARM64MOVIshift>;
168 def ARM64mvni_shift : SDNode<"ARM64ISD::MVNIshift", SDT_ARM64MOVIshift>;
169 def ARM64mvni_msl : SDNode<"ARM64ISD::MVNImsl", SDT_ARM64MOVIshift>;
170 def ARM64movi : SDNode<"ARM64ISD::MOVI", SDT_ARM64MOVIedit>;
171 def ARM64fmov : SDNode<"ARM64ISD::FMOV", SDT_ARM64MOVIedit>;
173 def ARM64rev16 : SDNode<"ARM64ISD::REV16", SDT_ARM64UnaryVec>;
174 def ARM64rev32 : SDNode<"ARM64ISD::REV32", SDT_ARM64UnaryVec>;
175 def ARM64rev64 : SDNode<"ARM64ISD::REV64", SDT_ARM64UnaryVec>;
176 def ARM64ext : SDNode<"ARM64ISD::EXT", SDT_ARM64ExtVec>;
178 def ARM64vashr : SDNode<"ARM64ISD::VASHR", SDT_ARM64vshift>;
179 def ARM64vlshr : SDNode<"ARM64ISD::VLSHR", SDT_ARM64vshift>;
180 def ARM64vshl : SDNode<"ARM64ISD::VSHL", SDT_ARM64vshift>;
181 def ARM64sqshli : SDNode<"ARM64ISD::SQSHL_I", SDT_ARM64vshift>;
182 def ARM64uqshli : SDNode<"ARM64ISD::UQSHL_I", SDT_ARM64vshift>;
183 def ARM64sqshlui : SDNode<"ARM64ISD::SQSHLU_I", SDT_ARM64vshift>;
184 def ARM64srshri : SDNode<"ARM64ISD::SRSHR_I", SDT_ARM64vshift>;
185 def ARM64urshri : SDNode<"ARM64ISD::URSHR_I", SDT_ARM64vshift>;
187 def ARM64not: SDNode<"ARM64ISD::NOT", SDT_ARM64unvec>;
188 def ARM64bit: SDNode<"ARM64ISD::BIT", SDT_ARM64trivec>;
189 def ARM64bsl: SDNode<"ARM64ISD::BSL", SDT_ARM64trivec>;
191 def ARM64cmeq: SDNode<"ARM64ISD::CMEQ", SDT_ARM64binvec>;
192 def ARM64cmge: SDNode<"ARM64ISD::CMGE", SDT_ARM64binvec>;
193 def ARM64cmgt: SDNode<"ARM64ISD::CMGT", SDT_ARM64binvec>;
194 def ARM64cmhi: SDNode<"ARM64ISD::CMHI", SDT_ARM64binvec>;
195 def ARM64cmhs: SDNode<"ARM64ISD::CMHS", SDT_ARM64binvec>;
197 def ARM64fcmeq: SDNode<"ARM64ISD::FCMEQ", SDT_ARM64fcmp>;
198 def ARM64fcmge: SDNode<"ARM64ISD::FCMGE", SDT_ARM64fcmp>;
199 def ARM64fcmgt: SDNode<"ARM64ISD::FCMGT", SDT_ARM64fcmp>;
201 def ARM64cmeqz: SDNode<"ARM64ISD::CMEQz", SDT_ARM64unvec>;
202 def ARM64cmgez: SDNode<"ARM64ISD::CMGEz", SDT_ARM64unvec>;
203 def ARM64cmgtz: SDNode<"ARM64ISD::CMGTz", SDT_ARM64unvec>;
204 def ARM64cmlez: SDNode<"ARM64ISD::CMLEz", SDT_ARM64unvec>;
205 def ARM64cmltz: SDNode<"ARM64ISD::CMLTz", SDT_ARM64unvec>;
206 def ARM64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
207 (ARM64not (ARM64cmeqz (and node:$LHS, node:$RHS)))>;
209 def ARM64fcmeqz: SDNode<"ARM64ISD::FCMEQz", SDT_ARM64fcmpz>;
210 def ARM64fcmgez: SDNode<"ARM64ISD::FCMGEz", SDT_ARM64fcmpz>;
211 def ARM64fcmgtz: SDNode<"ARM64ISD::FCMGTz", SDT_ARM64fcmpz>;
212 def ARM64fcmlez: SDNode<"ARM64ISD::FCMLEz", SDT_ARM64fcmpz>;
213 def ARM64fcmltz: SDNode<"ARM64ISD::FCMLTz", SDT_ARM64fcmpz>;
215 def ARM64bici: SDNode<"ARM64ISD::BICi", SDT_ARM64vecimm>;
216 def ARM64orri: SDNode<"ARM64ISD::ORRi", SDT_ARM64vecimm>;
218 def ARM64neg : SDNode<"ARM64ISD::NEG", SDT_ARM64unvec>;
220 def ARM64tcret: SDNode<"ARM64ISD::TC_RETURN", SDT_ARM64TCRET,
221 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
223 def ARM64Prefetch : SDNode<"ARM64ISD::PREFETCH", SDT_ARM64PREFETCH,
224 [SDNPHasChain, SDNPSideEffect]>;
226 def ARM64sitof: SDNode<"ARM64ISD::SITOF", SDT_ARM64ITOF>;
227 def ARM64uitof: SDNode<"ARM64ISD::UITOF", SDT_ARM64ITOF>;
229 def ARM64tlsdesc_call : SDNode<"ARM64ISD::TLSDESC_CALL", SDT_ARM64TLSDescCall,
230 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
233 def ARM64WrapperLarge : SDNode<"ARM64ISD::WrapperLarge", SDT_ARM64WrapperLarge>;
236 //===----------------------------------------------------------------------===//
238 //===----------------------------------------------------------------------===//
240 // ARM64 Instruction Predicate Definitions.
242 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
243 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
244 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
245 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
246 def ForCodeSize : Predicate<"ForCodeSize">;
247 def NotForCodeSize : Predicate<"!ForCodeSize">;
249 include "ARM64InstrFormats.td"
251 //===----------------------------------------------------------------------===//
253 //===----------------------------------------------------------------------===//
254 // Miscellaneous instructions.
255 //===----------------------------------------------------------------------===//
257 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
258 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
259 [(ARM64callseq_start timm:$amt)]>;
260 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
261 [(ARM64callseq_end timm:$amt1, timm:$amt2)]>;
262 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
264 let isReMaterializable = 1, isCodeGenOnly = 1 in {
265 // FIXME: The following pseudo instructions are only needed because remat
266 // cannot handle multiple instructions. When that changes, they can be
267 // removed, along with the ARM64Wrapper node.
269 let AddedComplexity = 10 in
270 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
271 [(set GPR64:$dst, (ARM64LOADgot tglobaladdr:$addr))]>,
274 // The MOVaddr instruction should match only when the add is not folded
275 // into a load or store address.
277 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
278 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaladdr:$hi),
279 tglobaladdr:$low))]>,
280 Sched<[WriteAdrAdr]>;
282 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
283 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tjumptable:$hi),
285 Sched<[WriteAdrAdr]>;
287 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
288 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tconstpool:$hi),
290 Sched<[WriteAdrAdr]>;
292 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
293 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tblockaddress:$hi),
294 tblockaddress:$low))]>,
295 Sched<[WriteAdrAdr]>;
297 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
298 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaltlsaddr:$hi),
299 tglobaltlsaddr:$low))]>,
300 Sched<[WriteAdrAdr]>;
302 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
303 [(set GPR64:$dst, (ARM64addlow (ARM64adrp texternalsym:$hi),
304 texternalsym:$low))]>,
305 Sched<[WriteAdrAdr]>;
307 } // isReMaterializable, isCodeGenOnly
309 def : Pat<(ARM64LOADgot tglobaltlsaddr:$addr),
310 (LOADgot tglobaltlsaddr:$addr)>;
312 def : Pat<(ARM64LOADgot texternalsym:$addr),
313 (LOADgot texternalsym:$addr)>;
315 def : Pat<(ARM64LOADgot tconstpool:$addr),
316 (LOADgot tconstpool:$addr)>;
318 //===----------------------------------------------------------------------===//
319 // System instructions.
320 //===----------------------------------------------------------------------===//
322 def HINT : HintI<"hint">;
323 def : InstAlias<"nop", (HINT 0b000)>;
324 def : InstAlias<"yield",(HINT 0b001)>;
325 def : InstAlias<"wfe", (HINT 0b010)>;
326 def : InstAlias<"wfi", (HINT 0b011)>;
327 def : InstAlias<"sev", (HINT 0b100)>;
328 def : InstAlias<"sevl", (HINT 0b101)>;
330 // As far as LLVM is concerned this writes to the system's exclusive monitors.
331 let mayLoad = 1, mayStore = 1 in
332 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
334 def DMB : CRmSystemI<barrier_op, 0b101, "dmb">;
335 def DSB : CRmSystemI<barrier_op, 0b100, "dsb">;
336 def ISB : CRmSystemI<barrier_op, 0b110, "isb">;
337 def : InstAlias<"clrex", (CLREX 0xf)>;
338 def : InstAlias<"isb", (ISB 0xf)>;
342 def MSRpstate: MSRpstateI;
344 // The thread pointer (on Linux, at least, where this has been implemented) is
346 def : Pat<(ARM64threadpointer), (MRS 0xde82)>;
348 // Generic system instructions
349 def SYSxt : SystemXtI<0, "sys">;
350 def SYSLxt : SystemLXtI<1, "sysl">;
352 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
353 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
354 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
356 //===----------------------------------------------------------------------===//
357 // Move immediate instructions.
358 //===----------------------------------------------------------------------===//
360 defm MOVK : InsertImmediate<0b11, "movk">;
361 defm MOVN : MoveImmediate<0b00, "movn">;
363 let PostEncoderMethod = "fixMOVZ" in
364 defm MOVZ : MoveImmediate<0b10, "movz">;
366 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
367 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
368 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
369 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
370 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
371 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
373 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
374 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
375 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
376 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
378 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
379 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
380 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
381 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
383 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
384 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
385 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
386 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
388 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
389 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
391 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
392 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
394 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
395 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
397 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
398 isAsCheapAsAMove = 1 in {
399 // FIXME: The following pseudo instructions are only needed because remat
400 // cannot handle multiple instructions. When that changes, we can select
401 // directly to the real instructions and get rid of these pseudos.
404 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
405 [(set GPR32:$dst, imm:$src)]>,
408 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
409 [(set GPR64:$dst, imm:$src)]>,
411 } // isReMaterializable, isCodeGenOnly
413 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
414 // eventual expansion code fewer bits to worry about getting right. Marshalling
415 // the types is a little tricky though:
416 def i64imm_32bit : ImmLeaf<i64, [{
417 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
420 def trunc_imm : SDNodeXForm<imm, [{
421 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
424 def : Pat<(i64 i64imm_32bit:$src),
425 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
427 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
429 def : Pat<(ARM64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
430 tglobaladdr:$g1, tglobaladdr:$g0),
431 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
432 tglobaladdr:$g2, 32),
433 tglobaladdr:$g1, 16),
434 tglobaladdr:$g0, 0)>;
436 def : Pat<(ARM64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
437 tblockaddress:$g1, tblockaddress:$g0),
438 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
439 tblockaddress:$g2, 32),
440 tblockaddress:$g1, 16),
441 tblockaddress:$g0, 0)>;
443 def : Pat<(ARM64WrapperLarge tconstpool:$g3, tconstpool:$g2,
444 tconstpool:$g1, tconstpool:$g0),
445 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
450 def : Pat<(ARM64WrapperLarge tjumptable:$g3, tjumptable:$g2,
451 tjumptable:$g1, tjumptable:$g0),
452 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
458 //===----------------------------------------------------------------------===//
459 // Arithmetic instructions.
460 //===----------------------------------------------------------------------===//
462 // Add/subtract with carry.
463 defm ADC : AddSubCarry<0, "adc", "adcs", ARM64adc, ARM64adc_flag>;
464 defm SBC : AddSubCarry<1, "sbc", "sbcs", ARM64sbc, ARM64sbc_flag>;
466 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
467 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
468 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
469 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
472 defm ADD : AddSub<0, "add", add>;
473 defm SUB : AddSub<1, "sub">;
475 defm ADDS : AddSubS<0, "adds", ARM64add_flag>;
476 defm SUBS : AddSubS<1, "subs", ARM64sub_flag>;
478 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
479 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
480 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
481 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
482 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
483 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
484 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
485 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
486 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
487 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
488 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
489 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
490 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
491 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
492 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
493 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
494 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
496 // Because of the immediate format for add/sub-imm instructions, the
497 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
498 // These patterns capture that transformation.
499 let AddedComplexity = 1 in {
500 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
501 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
502 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
503 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
504 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
505 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
506 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
507 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
510 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
511 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
512 def : InstAlias<"neg $dst, $src, $shift",
513 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift:$shift)>;
514 def : InstAlias<"neg $dst, $src, $shift",
515 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift:$shift)>;
517 // Because of the immediate format for add/sub-imm instructions, the
518 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
519 // These patterns capture that transformation.
520 let AddedComplexity = 1 in {
521 def : Pat<(ARM64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
522 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
523 def : Pat<(ARM64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
524 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
525 def : Pat<(ARM64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
526 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
527 def : Pat<(ARM64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
528 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
531 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
532 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
533 def : InstAlias<"negs $dst, $src, $shift",
534 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift:$shift)>;
535 def : InstAlias<"negs $dst, $src, $shift",
536 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift:$shift)>;
538 // Unsigned/Signed divide
539 defm UDIV : Div<0, "udiv", udiv>;
540 defm SDIV : Div<1, "sdiv", sdiv>;
541 let isCodeGenOnly = 1 in {
542 defm UDIV_Int : Div<0, "udiv", int_arm64_udiv>;
543 defm SDIV_Int : Div<1, "sdiv", int_arm64_sdiv>;
547 defm ASRV : Shift<0b10, "asrv", sra>;
548 defm LSLV : Shift<0b00, "lslv", shl>;
549 defm LSRV : Shift<0b01, "lsrv", srl>;
550 defm RORV : Shift<0b11, "rorv", rotr>;
552 def : ShiftAlias<"asr", ASRVWr, GPR32>;
553 def : ShiftAlias<"asr", ASRVXr, GPR64>;
554 def : ShiftAlias<"lsl", LSLVWr, GPR32>;
555 def : ShiftAlias<"lsl", LSLVXr, GPR64>;
556 def : ShiftAlias<"lsr", LSRVWr, GPR32>;
557 def : ShiftAlias<"lsr", LSRVXr, GPR64>;
558 def : ShiftAlias<"ror", RORVWr, GPR32>;
559 def : ShiftAlias<"ror", RORVXr, GPR64>;
562 let AddedComplexity = 7 in {
563 defm MADD : MulAccum<0, "madd", add>;
564 defm MSUB : MulAccum<1, "msub", sub>;
566 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
567 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
568 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
569 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
571 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
572 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
573 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
574 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
575 } // AddedComplexity = 7
577 let AddedComplexity = 5 in {
578 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
579 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
580 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
581 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
583 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
584 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
585 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
586 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
588 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
589 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
590 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
591 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
592 } // AddedComplexity = 5
594 def : MulAccumWAlias<"mul", MADDWrrr>;
595 def : MulAccumXAlias<"mul", MADDXrrr>;
596 def : MulAccumWAlias<"mneg", MSUBWrrr>;
597 def : MulAccumXAlias<"mneg", MSUBXrrr>;
598 def : WideMulAccumAlias<"smull", SMADDLrrr>;
599 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
600 def : WideMulAccumAlias<"umull", UMADDLrrr>;
601 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
604 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
605 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
608 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_arm64_crc32b, "crc32b">;
609 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_arm64_crc32h, "crc32h">;
610 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_arm64_crc32w, "crc32w">;
611 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_arm64_crc32x, "crc32x">;
613 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_arm64_crc32cb, "crc32cb">;
614 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_arm64_crc32ch, "crc32ch">;
615 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_arm64_crc32cw, "crc32cw">;
616 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_arm64_crc32cx, "crc32cx">;
619 //===----------------------------------------------------------------------===//
620 // Logical instructions.
621 //===----------------------------------------------------------------------===//
624 defm ANDS : LogicalImmS<0b11, "ands", ARM64and_flag>;
625 defm AND : LogicalImm<0b00, "and", and>;
626 defm EOR : LogicalImm<0b10, "eor", xor>;
627 defm ORR : LogicalImm<0b01, "orr", or>;
629 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
630 logical_imm32:$imm)>;
631 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
632 logical_imm64:$imm)>;
636 defm ANDS : LogicalRegS<0b11, 0, "ands", ARM64and_flag>;
637 defm BICS : LogicalRegS<0b11, 1, "bics",
638 BinOpFrag<(ARM64and_flag node:$LHS, (not node:$RHS))>>;
639 defm AND : LogicalReg<0b00, 0, "and", and>;
640 defm BIC : LogicalReg<0b00, 1, "bic",
641 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
642 defm EON : LogicalReg<0b10, 1, "eon",
643 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
644 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
645 defm ORN : LogicalReg<0b01, 1, "orn",
646 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
647 defm ORR : LogicalReg<0b01, 0, "orr", or>;
649 def : InstAlias<"tst $src1, $src2",
650 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
651 def : InstAlias<"tst $src1, $src2",
652 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>;
654 def : InstAlias<"tst $src1, $src2",
655 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>;
656 def : InstAlias<"tst $src1, $src2",
657 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>;
659 def : InstAlias<"tst $src1, $src2, $sh",
660 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift:$sh)>;
661 def : InstAlias<"tst $src1, $src2, $sh",
662 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift:$sh)>;
664 def : InstAlias<"mvn $Wd, $Wm",
665 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0)>;
666 def : InstAlias<"mvn $Xd, $Xm",
667 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>;
669 def : InstAlias<"mvn $Wd, $Wm, $sh",
670 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift:$sh)>;
671 def : InstAlias<"mvn $Xd, $Xm, $sh",
672 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift:$sh)>;
674 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
675 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
678 //===----------------------------------------------------------------------===//
679 // One operand data processing instructions.
680 //===----------------------------------------------------------------------===//
682 defm CLS : OneOperandData<0b101, "cls">;
683 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
684 defm RBIT : OneOperandData<0b000, "rbit">;
685 def REV16Wr : OneWRegData<0b001, "rev16",
686 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
687 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
689 def : Pat<(cttz GPR32:$Rn),
690 (CLZWr (RBITWr GPR32:$Rn))>;
691 def : Pat<(cttz GPR64:$Rn),
692 (CLZXr (RBITXr GPR64:$Rn))>;
693 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
696 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
700 // Unlike the other one operand instructions, the instructions with the "rev"
701 // mnemonic do *not* just different in the size bit, but actually use different
702 // opcode bits for the different sizes.
703 def REVWr : OneWRegData<0b010, "rev", bswap>;
704 def REVXr : OneXRegData<0b011, "rev", bswap>;
705 def REV32Xr : OneXRegData<0b010, "rev32",
706 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
708 // The bswap commutes with the rotr so we want a pattern for both possible
710 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
711 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
713 //===----------------------------------------------------------------------===//
714 // Bitfield immediate extraction instruction.
715 //===----------------------------------------------------------------------===//
716 let neverHasSideEffects = 1 in
717 defm EXTR : ExtractImm<"extr">;
718 def : InstAlias<"ror $dst, $src, $shift",
719 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
720 def : InstAlias<"ror $dst, $src, $shift",
721 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
723 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
724 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
725 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
726 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
728 //===----------------------------------------------------------------------===//
729 // Other bitfield immediate instructions.
730 //===----------------------------------------------------------------------===//
731 let neverHasSideEffects = 1 in {
732 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
733 defm SBFM : BitfieldImm<0b00, "sbfm">;
734 defm UBFM : BitfieldImm<0b10, "ubfm">;
737 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
738 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
739 return CurDAG->getTargetConstant(enc, MVT::i64);
742 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
743 uint64_t enc = 31 - N->getZExtValue();
744 return CurDAG->getTargetConstant(enc, MVT::i64);
747 // min(7, 31 - shift_amt)
748 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
749 uint64_t enc = 31 - N->getZExtValue();
750 enc = enc > 7 ? 7 : enc;
751 return CurDAG->getTargetConstant(enc, MVT::i64);
754 // min(15, 31 - shift_amt)
755 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
756 uint64_t enc = 31 - N->getZExtValue();
757 enc = enc > 15 ? 15 : enc;
758 return CurDAG->getTargetConstant(enc, MVT::i64);
761 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
762 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
763 return CurDAG->getTargetConstant(enc, MVT::i64);
766 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
767 uint64_t enc = 63 - N->getZExtValue();
768 return CurDAG->getTargetConstant(enc, MVT::i64);
771 // min(7, 63 - shift_amt)
772 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
773 uint64_t enc = 63 - N->getZExtValue();
774 enc = enc > 7 ? 7 : enc;
775 return CurDAG->getTargetConstant(enc, MVT::i64);
778 // min(15, 63 - shift_amt)
779 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
780 uint64_t enc = 63 - N->getZExtValue();
781 enc = enc > 15 ? 15 : enc;
782 return CurDAG->getTargetConstant(enc, MVT::i64);
785 // min(31, 63 - shift_amt)
786 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
787 uint64_t enc = 63 - N->getZExtValue();
788 enc = enc > 31 ? 31 : enc;
789 return CurDAG->getTargetConstant(enc, MVT::i64);
792 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
793 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
794 (i64 (i32shift_b imm0_31:$imm)))>;
795 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
796 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
797 (i64 (i64shift_b imm0_63:$imm)))>;
799 let AddedComplexity = 10 in {
800 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
801 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
802 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
803 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
806 def : InstAlias<"asr $dst, $src, $shift",
807 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
808 def : InstAlias<"asr $dst, $src, $shift",
809 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
810 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
811 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
812 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
813 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
814 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
816 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
817 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
818 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
819 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
821 def : InstAlias<"lsr $dst, $src, $shift",
822 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
823 def : InstAlias<"lsr $dst, $src, $shift",
824 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
825 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
826 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
827 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
828 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
829 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
831 //===----------------------------------------------------------------------===//
832 // Conditionally set flags instructions.
833 //===----------------------------------------------------------------------===//
834 defm CCMN : CondSetFlagsImm<0, "ccmn">;
835 defm CCMP : CondSetFlagsImm<1, "ccmp">;
837 defm CCMN : CondSetFlagsReg<0, "ccmn">;
838 defm CCMP : CondSetFlagsReg<1, "ccmp">;
840 //===----------------------------------------------------------------------===//
841 // Conditional select instructions.
842 //===----------------------------------------------------------------------===//
843 defm CSEL : CondSelect<0, 0b00, "csel">;
845 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
846 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
847 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
848 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
850 def : Pat<(ARM64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
851 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
852 def : Pat<(ARM64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
853 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
854 def : Pat<(ARM64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
855 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
856 def : Pat<(ARM64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
857 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
858 def : Pat<(ARM64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
859 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
860 def : Pat<(ARM64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
861 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
863 def : Pat<(ARM64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
864 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
865 def : Pat<(ARM64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
866 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
867 def : Pat<(ARM64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
868 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
869 def : Pat<(ARM64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
870 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
872 // The inverse of the condition code from the alias instruction is what is used
873 // in the aliased instruction. The parser all ready inverts the condition code
874 // for these aliases.
875 // FIXME: Is this the correct way to handle these aliases?
876 def : InstAlias<"cset $dst, $cc", (CSINCWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
877 def : InstAlias<"cset $dst, $cc", (CSINCXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
879 def : InstAlias<"csetm $dst, $cc", (CSINVWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
880 def : InstAlias<"csetm $dst, $cc", (CSINVXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
882 def : InstAlias<"cinc $dst, $src, $cc",
883 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
884 def : InstAlias<"cinc $dst, $src, $cc",
885 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
887 def : InstAlias<"cinv $dst, $src, $cc",
888 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
889 def : InstAlias<"cinv $dst, $src, $cc",
890 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
892 def : InstAlias<"cneg $dst, $src, $cc",
893 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
894 def : InstAlias<"cneg $dst, $src, $cc",
895 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
897 //===----------------------------------------------------------------------===//
898 // PC-relative instructions.
899 //===----------------------------------------------------------------------===//
900 let isReMaterializable = 1 in {
901 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
902 def ADR : ADRI<0, "adr", adrlabel, []>;
903 } // neverHasSideEffects = 1
905 def ADRP : ADRI<1, "adrp", adrplabel,
906 [(set GPR64:$Xd, (ARM64adrp tglobaladdr:$label))]>;
907 } // isReMaterializable = 1
909 // page address of a constant pool entry, block address
910 def : Pat<(ARM64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
911 def : Pat<(ARM64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
913 //===----------------------------------------------------------------------===//
914 // Unconditional branch (register) instructions.
915 //===----------------------------------------------------------------------===//
917 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
918 def RET : BranchReg<0b0010, "ret", []>;
919 def DRPS : SpecialReturn<0b0101, "drps">;
920 def ERET : SpecialReturn<0b0100, "eret">;
921 } // isReturn = 1, isTerminator = 1, isBarrier = 1
923 // Default to the LR register.
924 def : InstAlias<"ret", (RET LR)>;
926 let isCall = 1, Defs = [LR], Uses = [SP] in {
927 def BLR : BranchReg<0b0001, "blr", [(ARM64call GPR64:$Rn)]>;
930 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
931 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
932 } // isBranch, isTerminator, isBarrier, isIndirectBranch
934 // Create a separate pseudo-instruction for codegen to use so that we don't
935 // flag lr as used in every function. It'll be restored before the RET by the
936 // epilogue if it's legitimately used.
937 def RET_ReallyLR : Pseudo<(outs), (ins), [(ARM64retflag)]> {
938 let isTerminator = 1;
943 // This is a directive-like pseudo-instruction. The purpose is to insert an
944 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
945 // (which in the usual case is a BLR).
946 let hasSideEffects = 1 in
947 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
948 let AsmString = ".tlsdesccall $sym";
951 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
952 // gets expanded to two MCInsts during lowering.
953 let isCall = 1, Defs = [LR] in
955 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
956 [(ARM64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
958 def : Pat<(ARM64tlsdesc_call GPR64:$dest, texternalsym:$sym),
959 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
960 //===----------------------------------------------------------------------===//
961 // Conditional branch (immediate) instruction.
962 //===----------------------------------------------------------------------===//
963 def Bcc : BranchCond;
965 //===----------------------------------------------------------------------===//
966 // Compare-and-branch instructions.
967 //===----------------------------------------------------------------------===//
968 defm CBZ : CmpBranch<0, "cbz", ARM64cbz>;
969 defm CBNZ : CmpBranch<1, "cbnz", ARM64cbnz>;
971 //===----------------------------------------------------------------------===//
972 // Test-bit-and-branch instructions.
973 //===----------------------------------------------------------------------===//
974 def TBZ : TestBranch<0, "tbz", ARM64tbz>;
975 def TBNZ : TestBranch<1, "tbnz", ARM64tbnz>;
977 //===----------------------------------------------------------------------===//
978 // Unconditional branch (immediate) instructions.
979 //===----------------------------------------------------------------------===//
980 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
981 def B : BranchImm<0, "b", [(br bb:$addr)]>;
982 } // isBranch, isTerminator, isBarrier
984 let isCall = 1, Defs = [LR], Uses = [SP] in {
985 def BL : CallImm<1, "bl", [(ARM64call tglobaladdr:$addr)]>;
987 def : Pat<(ARM64call texternalsym:$func), (BL texternalsym:$func)>;
989 //===----------------------------------------------------------------------===//
990 // Exception generation instructions.
991 //===----------------------------------------------------------------------===//
992 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
993 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
994 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
995 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
996 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
997 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
998 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
999 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1001 // DCPSn defaults to an immediate operand of zero if unspecified.
1002 def : InstAlias<"dcps1", (DCPS1 0)>;
1003 def : InstAlias<"dcps2", (DCPS2 0)>;
1004 def : InstAlias<"dcps3", (DCPS3 0)>;
1006 //===----------------------------------------------------------------------===//
1007 // Load instructions.
1008 //===----------------------------------------------------------------------===//
1010 // Pair (indexed, offset)
1011 def LDPWi : LoadPairOffset<0b00, 0, GPR32, am_indexed32simm7, "ldp">;
1012 def LDPXi : LoadPairOffset<0b10, 0, GPR64, am_indexed64simm7, "ldp">;
1013 def LDPSi : LoadPairOffset<0b00, 1, FPR32, am_indexed32simm7, "ldp">;
1014 def LDPDi : LoadPairOffset<0b01, 1, FPR64, am_indexed64simm7, "ldp">;
1015 def LDPQi : LoadPairOffset<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
1017 def LDPSWi : LoadPairOffset<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
1019 // Pair (pre-indexed)
1020 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "ldp">;
1021 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "ldp">;
1022 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "ldp">;
1023 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "ldp">;
1024 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "ldp">;
1026 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7_wb, "ldpsw">;
1028 // Pair (post-indexed)
1029 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1030 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1031 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1032 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1033 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1035 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1038 // Pair (no allocate)
1039 def LDNPWi : LoadPairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "ldnp">;
1040 def LDNPXi : LoadPairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "ldnp">;
1041 def LDNPSi : LoadPairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "ldnp">;
1042 def LDNPDi : LoadPairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "ldnp">;
1043 def LDNPQi : LoadPairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "ldnp">;
1046 // (register offset)
1049 let AddedComplexity = 10 in {
1051 def LDRBBro : Load8RO<0b00, 0, 0b01, GPR32, "ldrb",
1052 [(set GPR32:$Rt, (zextloadi8 ro_indexed8:$addr))]>;
1053 def LDRHHro : Load16RO<0b01, 0, 0b01, GPR32, "ldrh",
1054 [(set GPR32:$Rt, (zextloadi16 ro_indexed16:$addr))]>;
1055 def LDRWro : Load32RO<0b10, 0, 0b01, GPR32, "ldr",
1056 [(set GPR32:$Rt, (load ro_indexed32:$addr))]>;
1057 def LDRXro : Load64RO<0b11, 0, 0b01, GPR64, "ldr",
1058 [(set GPR64:$Rt, (load ro_indexed64:$addr))]>;
1061 def LDRBro : Load8RO<0b00, 1, 0b01, FPR8, "ldr",
1062 [(set FPR8:$Rt, (load ro_indexed8:$addr))]>;
1063 def LDRHro : Load16RO<0b01, 1, 0b01, FPR16, "ldr",
1064 [(set (f16 FPR16:$Rt), (load ro_indexed16:$addr))]>;
1065 def LDRSro : Load32RO<0b10, 1, 0b01, FPR32, "ldr",
1066 [(set (f32 FPR32:$Rt), (load ro_indexed32:$addr))]>;
1067 def LDRDro : Load64RO<0b11, 1, 0b01, FPR64, "ldr",
1068 [(set (f64 FPR64:$Rt), (load ro_indexed64:$addr))]>;
1069 def LDRQro : Load128RO<0b00, 1, 0b11, FPR128, "ldr", []> {
1073 // For regular load, we do not have any alignment requirement.
1074 // Thus, it is safe to directly map the vector loads with interesting
1075 // addressing modes.
1076 // FIXME: We could do the same for bitconvert to floating point vectors.
1077 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1078 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1079 (LDRBro ro_indexed8:$addr), bsub)>;
1080 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1081 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1082 (LDRBro ro_indexed8:$addr), bsub)>;
1083 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1084 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1085 (LDRHro ro_indexed16:$addr), hsub)>;
1086 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1087 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1088 (LDRHro ro_indexed16:$addr), hsub)>;
1089 def : Pat <(v2i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1090 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1091 (LDRSro ro_indexed32:$addr), ssub)>;
1092 def : Pat <(v4i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1093 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1094 (LDRSro ro_indexed32:$addr), ssub)>;
1095 def : Pat <(v1i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1096 (LDRDro ro_indexed64:$addr)>;
1097 def : Pat <(v2i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1098 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1099 (LDRDro ro_indexed64:$addr), dsub)>;
1101 // Match all load 64 bits width whose type is compatible with FPR64
1102 def : Pat<(v2f32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1103 def : Pat<(v1f64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1104 def : Pat<(v8i8 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1105 def : Pat<(v4i16 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1106 def : Pat<(v2i32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1107 def : Pat<(v1i64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1109 // Match all load 128 bits width whose type is compatible with FPR128
1110 def : Pat<(v4f32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1111 def : Pat<(v2f64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1112 def : Pat<(v16i8 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1113 def : Pat<(v8i16 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1114 def : Pat<(v4i32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1115 def : Pat<(v2i64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1116 def : Pat<(f128 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1118 // Load sign-extended half-word
1119 def LDRSHWro : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh",
1120 [(set GPR32:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1121 def LDRSHXro : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh",
1122 [(set GPR64:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1124 // Load sign-extended byte
1125 def LDRSBWro : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb",
1126 [(set GPR32:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1127 def LDRSBXro : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb",
1128 [(set GPR64:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1130 // Load sign-extended word
1131 def LDRSWro : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw",
1132 [(set GPR64:$Rt, (sextloadi32 ro_indexed32:$addr))]>;
1135 def PRFMro : PrefetchRO<0b11, 0, 0b10, "prfm",
1136 [(ARM64Prefetch imm:$Rt, ro_indexed64:$addr)]>;
1139 def : Pat<(i64 (zextloadi8 ro_indexed8:$addr)),
1140 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1141 def : Pat<(i64 (zextloadi16 ro_indexed16:$addr)),
1142 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1143 def : Pat<(i64 (zextloadi32 ro_indexed32:$addr)),
1144 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1146 // zextloadi1 -> zextloadi8
1147 def : Pat<(i32 (zextloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1148 def : Pat<(i64 (zextloadi1 ro_indexed8:$addr)),
1149 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1151 // extload -> zextload
1152 def : Pat<(i32 (extloadi16 ro_indexed16:$addr)), (LDRHHro ro_indexed16:$addr)>;
1153 def : Pat<(i32 (extloadi8 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1154 def : Pat<(i32 (extloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1155 def : Pat<(i64 (extloadi32 ro_indexed32:$addr)),
1156 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1157 def : Pat<(i64 (extloadi16 ro_indexed16:$addr)),
1158 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1159 def : Pat<(i64 (extloadi8 ro_indexed8:$addr)),
1160 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1161 def : Pat<(i64 (extloadi1 ro_indexed8:$addr)),
1162 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1164 } // AddedComplexity = 10
1167 // (unsigned immediate)
1169 def LDRXui : LoadUI<0b11, 0, 0b01, GPR64, am_indexed64, "ldr",
1170 [(set GPR64:$Rt, (load am_indexed64:$addr))]>;
1171 def LDRWui : LoadUI<0b10, 0, 0b01, GPR32, am_indexed32, "ldr",
1172 [(set GPR32:$Rt, (load am_indexed32:$addr))]>;
1173 def LDRBui : LoadUI<0b00, 1, 0b01, FPR8, am_indexed8, "ldr",
1174 [(set FPR8:$Rt, (load am_indexed8:$addr))]>;
1175 def LDRHui : LoadUI<0b01, 1, 0b01, FPR16, am_indexed16, "ldr",
1176 [(set (f16 FPR16:$Rt), (load am_indexed16:$addr))]>;
1177 def LDRSui : LoadUI<0b10, 1, 0b01, FPR32, am_indexed32, "ldr",
1178 [(set (f32 FPR32:$Rt), (load am_indexed32:$addr))]>;
1179 def LDRDui : LoadUI<0b11, 1, 0b01, FPR64, am_indexed64, "ldr",
1180 [(set (f64 FPR64:$Rt), (load am_indexed64:$addr))]>;
1181 def LDRQui : LoadUI<0b00, 1, 0b11, FPR128, am_indexed128, "ldr",
1182 [(set (f128 FPR128:$Rt), (load am_indexed128:$addr))]>;
1184 // For regular load, we do not have any alignment requirement.
1185 // Thus, it is safe to directly map the vector loads with interesting
1186 // addressing modes.
1187 // FIXME: We could do the same for bitconvert to floating point vectors.
1188 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1189 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1190 (LDRBui am_indexed8:$addr), bsub)>;
1191 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1192 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1193 (LDRBui am_indexed8:$addr), bsub)>;
1194 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1195 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1196 (LDRHui am_indexed16:$addr), hsub)>;
1197 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1198 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1199 (LDRHui am_indexed16:$addr), hsub)>;
1200 def : Pat <(v2i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1201 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1202 (LDRSui am_indexed32:$addr), ssub)>;
1203 def : Pat <(v4i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1204 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1205 (LDRSui am_indexed32:$addr), ssub)>;
1206 def : Pat <(v1i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1207 (LDRDui am_indexed64:$addr)>;
1208 def : Pat <(v2i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1209 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1210 (LDRDui am_indexed64:$addr), dsub)>;
1212 // Match all load 64 bits width whose type is compatible with FPR64
1213 def : Pat<(v2f32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1214 def : Pat<(v1f64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1215 def : Pat<(v8i8 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1216 def : Pat<(v4i16 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1217 def : Pat<(v2i32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1218 def : Pat<(v1i64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1220 // Match all load 128 bits width whose type is compatible with FPR128
1221 def : Pat<(v4f32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1222 def : Pat<(v2f64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1223 def : Pat<(v16i8 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1224 def : Pat<(v8i16 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1225 def : Pat<(v4i32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1226 def : Pat<(v2i64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1227 def : Pat<(f128 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1229 def LDRHHui : LoadUI<0b01, 0, 0b01, GPR32, am_indexed16, "ldrh",
1230 [(set GPR32:$Rt, (zextloadi16 am_indexed16:$addr))]>;
1231 def LDRBBui : LoadUI<0b00, 0, 0b01, GPR32, am_indexed8, "ldrb",
1232 [(set GPR32:$Rt, (zextloadi8 am_indexed8:$addr))]>;
1234 def : Pat<(i64 (zextloadi8 am_indexed8:$addr)),
1235 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1236 def : Pat<(i64 (zextloadi16 am_indexed16:$addr)),
1237 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1239 // zextloadi1 -> zextloadi8
1240 def : Pat<(i32 (zextloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1241 def : Pat<(i64 (zextloadi1 am_indexed8:$addr)),
1242 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1244 // extload -> zextload
1245 def : Pat<(i32 (extloadi16 am_indexed16:$addr)), (LDRHHui am_indexed16:$addr)>;
1246 def : Pat<(i32 (extloadi8 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1247 def : Pat<(i32 (extloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1248 def : Pat<(i64 (extloadi32 am_indexed32:$addr)),
1249 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1250 def : Pat<(i64 (extloadi16 am_indexed16:$addr)),
1251 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1252 def : Pat<(i64 (extloadi8 am_indexed8:$addr)),
1253 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1254 def : Pat<(i64 (extloadi1 am_indexed8:$addr)),
1255 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1257 // load sign-extended half-word
1258 def LDRSHWui : LoadUI<0b01, 0, 0b11, GPR32, am_indexed16, "ldrsh",
1259 [(set GPR32:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1260 def LDRSHXui : LoadUI<0b01, 0, 0b10, GPR64, am_indexed16, "ldrsh",
1261 [(set GPR64:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1263 // load sign-extended byte
1264 def LDRSBWui : LoadUI<0b00, 0, 0b11, GPR32, am_indexed8, "ldrsb",
1265 [(set GPR32:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1266 def LDRSBXui : LoadUI<0b00, 0, 0b10, GPR64, am_indexed8, "ldrsb",
1267 [(set GPR64:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1269 // load sign-extended word
1270 def LDRSWui : LoadUI<0b10, 0, 0b10, GPR64, am_indexed32, "ldrsw",
1271 [(set GPR64:$Rt, (sextloadi32 am_indexed32:$addr))]>;
1273 // load zero-extended word
1274 def : Pat<(i64 (zextloadi32 am_indexed32:$addr)),
1275 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1278 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1279 [(ARM64Prefetch imm:$Rt, am_indexed64:$addr)]>;
1283 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1284 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1285 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1286 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1287 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1289 // load sign-extended word
1290 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1293 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1294 // [(ARM64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1297 // (unscaled immediate)
1298 def LDURXi : LoadUnscaled<0b11, 0, 0b01, GPR64, am_unscaled64, "ldur",
1299 [(set GPR64:$Rt, (load am_unscaled64:$addr))]>;
1300 def LDURWi : LoadUnscaled<0b10, 0, 0b01, GPR32, am_unscaled32, "ldur",
1301 [(set GPR32:$Rt, (load am_unscaled32:$addr))]>;
1302 def LDURBi : LoadUnscaled<0b00, 1, 0b01, FPR8, am_unscaled8, "ldur",
1303 [(set FPR8:$Rt, (load am_unscaled8:$addr))]>;
1304 def LDURHi : LoadUnscaled<0b01, 1, 0b01, FPR16, am_unscaled16, "ldur",
1305 [(set (f16 FPR16:$Rt), (load am_unscaled16:$addr))]>;
1306 def LDURSi : LoadUnscaled<0b10, 1, 0b01, FPR32, am_unscaled32, "ldur",
1307 [(set (f32 FPR32:$Rt), (load am_unscaled32:$addr))]>;
1308 def LDURDi : LoadUnscaled<0b11, 1, 0b01, FPR64, am_unscaled64, "ldur",
1309 [(set (f64 FPR64:$Rt), (load am_unscaled64:$addr))]>;
1310 def LDURQi : LoadUnscaled<0b00, 1, 0b11, FPR128, am_unscaled128, "ldur",
1311 [(set (v2f64 FPR128:$Rt), (load am_unscaled128:$addr))]>;
1314 : LoadUnscaled<0b01, 0, 0b01, GPR32, am_unscaled16, "ldurh",
1315 [(set GPR32:$Rt, (zextloadi16 am_unscaled16:$addr))]>;
1317 : LoadUnscaled<0b00, 0, 0b01, GPR32, am_unscaled8, "ldurb",
1318 [(set GPR32:$Rt, (zextloadi8 am_unscaled8:$addr))]>;
1320 // Match all load 64 bits width whose type is compatible with FPR64
1321 def : Pat<(v2f32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1322 def : Pat<(v1f64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1323 def : Pat<(v8i8 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1324 def : Pat<(v4i16 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1325 def : Pat<(v2i32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1326 def : Pat<(v1i64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1328 // Match all load 128 bits width whose type is compatible with FPR128
1329 def : Pat<(v4f32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1330 def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1331 def : Pat<(v16i8 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1332 def : Pat<(v8i16 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1333 def : Pat<(v4i32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1334 def : Pat<(v2i64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1335 def : Pat<(f128 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1338 def : Pat<(i32 (extloadi16 am_unscaled16:$addr)), (LDURHHi am_unscaled16:$addr)>;
1339 def : Pat<(i32 (extloadi8 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1340 def : Pat<(i32 (extloadi1 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1341 def : Pat<(i64 (extloadi32 am_unscaled32:$addr)),
1342 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1343 def : Pat<(i64 (extloadi16 am_unscaled16:$addr)),
1344 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1345 def : Pat<(i64 (extloadi8 am_unscaled8:$addr)),
1346 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1347 def : Pat<(i64 (extloadi1 am_unscaled8:$addr)),
1348 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1350 def : Pat<(i32 (zextloadi16 am_unscaled16:$addr)),
1351 (LDURHHi am_unscaled16:$addr)>;
1352 def : Pat<(i32 (zextloadi8 am_unscaled8:$addr)),
1353 (LDURBBi am_unscaled8:$addr)>;
1354 def : Pat<(i32 (zextloadi1 am_unscaled8:$addr)),
1355 (LDURBBi am_unscaled8:$addr)>;
1356 def : Pat<(i64 (zextloadi32 am_unscaled32:$addr)),
1357 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1358 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1359 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1360 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1361 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1362 def : Pat<(i64 (zextloadi1 am_unscaled8:$addr)),
1363 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1367 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1369 // Define new assembler match classes as we want to only match these when
1370 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1371 // associate a DiagnosticType either, as we want the diagnostic for the
1372 // canonical form (the scaled operand) to take precedence.
1373 def MemoryUnscaledFB8Operand : AsmOperandClass {
1374 let Name = "MemoryUnscaledFB8";
1375 let RenderMethod = "addMemoryUnscaledOperands";
1377 def MemoryUnscaledFB16Operand : AsmOperandClass {
1378 let Name = "MemoryUnscaledFB16";
1379 let RenderMethod = "addMemoryUnscaledOperands";
1381 def MemoryUnscaledFB32Operand : AsmOperandClass {
1382 let Name = "MemoryUnscaledFB32";
1383 let RenderMethod = "addMemoryUnscaledOperands";
1385 def MemoryUnscaledFB64Operand : AsmOperandClass {
1386 let Name = "MemoryUnscaledFB64";
1387 let RenderMethod = "addMemoryUnscaledOperands";
1389 def MemoryUnscaledFB128Operand : AsmOperandClass {
1390 let Name = "MemoryUnscaledFB128";
1391 let RenderMethod = "addMemoryUnscaledOperands";
1393 def am_unscaled_fb8 : Operand<i64> {
1394 let ParserMatchClass = MemoryUnscaledFB8Operand;
1395 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1397 def am_unscaled_fb16 : Operand<i64> {
1398 let ParserMatchClass = MemoryUnscaledFB16Operand;
1399 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1401 def am_unscaled_fb32 : Operand<i64> {
1402 let ParserMatchClass = MemoryUnscaledFB32Operand;
1403 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1405 def am_unscaled_fb64 : Operand<i64> {
1406 let ParserMatchClass = MemoryUnscaledFB64Operand;
1407 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1409 def am_unscaled_fb128 : Operand<i64> {
1410 let ParserMatchClass = MemoryUnscaledFB128Operand;
1411 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1413 def : InstAlias<"ldr $Rt, $addr", (LDURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1414 def : InstAlias<"ldr $Rt, $addr", (LDURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1415 def : InstAlias<"ldr $Rt, $addr", (LDURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1416 def : InstAlias<"ldr $Rt, $addr", (LDURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1417 def : InstAlias<"ldr $Rt, $addr", (LDURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1418 def : InstAlias<"ldr $Rt, $addr", (LDURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1419 def : InstAlias<"ldr $Rt, $addr", (LDURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1422 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1423 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1424 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1425 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1427 // load sign-extended half-word
1429 : LoadUnscaled<0b01, 0, 0b11, GPR32, am_unscaled16, "ldursh",
1430 [(set GPR32:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1432 : LoadUnscaled<0b01, 0, 0b10, GPR64, am_unscaled16, "ldursh",
1433 [(set GPR64:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1435 // load sign-extended byte
1437 : LoadUnscaled<0b00, 0, 0b11, GPR32, am_unscaled8, "ldursb",
1438 [(set GPR32:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1440 : LoadUnscaled<0b00, 0, 0b10, GPR64, am_unscaled8, "ldursb",
1441 [(set GPR64:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1443 // load sign-extended word
1445 : LoadUnscaled<0b10, 0, 0b10, GPR64, am_unscaled32, "ldursw",
1446 [(set GPR64:$Rt, (sextloadi32 am_unscaled32:$addr))]>;
1448 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1449 def : InstAlias<"ldrb $Rt, $addr", (LDURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1450 def : InstAlias<"ldrh $Rt, $addr", (LDURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1451 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBWi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1452 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBXi GPR64:$Rt, am_unscaled_fb8:$addr)>;
1453 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHWi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1454 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHXi GPR64:$Rt, am_unscaled_fb16:$addr)>;
1455 def : InstAlias<"ldrsw $Rt, $addr", (LDURSWi GPR64:$Rt, am_unscaled_fb32:$addr)>;
1458 def PRFUMi : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1459 [(ARM64Prefetch imm:$Rt, am_unscaled64:$addr)]>;
1462 // (unscaled immediate, unprivileged)
1463 def LDTRXi : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1464 def LDTRWi : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1466 def LDTRHi : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1467 def LDTRBi : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1469 // load sign-extended half-word
1470 def LDTRSHWi : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1471 def LDTRSHXi : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1473 // load sign-extended byte
1474 def LDTRSBWi : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1475 def LDTRSBXi : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1477 // load sign-extended word
1478 def LDTRSWi : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1481 // (immediate pre-indexed)
1482 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1483 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1484 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1485 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1486 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1487 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1488 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1490 // load sign-extended half-word
1491 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1492 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1494 // load sign-extended byte
1495 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1496 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1498 // load zero-extended byte
1499 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1500 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1502 // load sign-extended word
1503 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1505 // ISel pseudos and patterns. See expanded comment on LoadPreIdxPseudo.
1506 def LDRDpre_isel : LoadPreIdxPseudo<FPR64>;
1507 def LDRSpre_isel : LoadPreIdxPseudo<FPR32>;
1508 def LDRXpre_isel : LoadPreIdxPseudo<GPR64>;
1509 def LDRWpre_isel : LoadPreIdxPseudo<GPR32>;
1510 def LDRHHpre_isel : LoadPreIdxPseudo<GPR32>;
1511 def LDRBBpre_isel : LoadPreIdxPseudo<GPR32>;
1513 def LDRSWpre_isel : LoadPreIdxPseudo<GPR64>;
1514 def LDRSHWpre_isel : LoadPreIdxPseudo<GPR32>;
1515 def LDRSHXpre_isel : LoadPreIdxPseudo<GPR64>;
1516 def LDRSBWpre_isel : LoadPreIdxPseudo<GPR32>;
1517 def LDRSBXpre_isel : LoadPreIdxPseudo<GPR64>;
1520 // (immediate post-indexed)
1521 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1522 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1523 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1524 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1525 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1526 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1527 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1529 // load sign-extended half-word
1530 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1531 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1533 // load sign-extended byte
1534 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1535 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1537 // load zero-extended byte
1538 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1539 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1541 // load sign-extended word
1542 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1544 // ISel pseudos and patterns. See expanded comment on LoadPostIdxPseudo.
1545 def LDRDpost_isel : LoadPostIdxPseudo<FPR64>;
1546 def LDRSpost_isel : LoadPostIdxPseudo<FPR32>;
1547 def LDRXpost_isel : LoadPostIdxPseudo<GPR64>;
1548 def LDRWpost_isel : LoadPostIdxPseudo<GPR32>;
1549 def LDRHHpost_isel : LoadPostIdxPseudo<GPR32>;
1550 def LDRBBpost_isel : LoadPostIdxPseudo<GPR32>;
1552 def LDRSWpost_isel : LoadPostIdxPseudo<GPR64>;
1553 def LDRSHWpost_isel : LoadPostIdxPseudo<GPR32>;
1554 def LDRSHXpost_isel : LoadPostIdxPseudo<GPR64>;
1555 def LDRSBWpost_isel : LoadPostIdxPseudo<GPR32>;
1556 def LDRSBXpost_isel : LoadPostIdxPseudo<GPR64>;
1558 //===----------------------------------------------------------------------===//
1559 // Store instructions.
1560 //===----------------------------------------------------------------------===//
1562 // Pair (indexed, offset)
1563 // FIXME: Use dedicated range-checked addressing mode operand here.
1564 def STPWi : StorePairOffset<0b00, 0, GPR32, am_indexed32simm7, "stp">;
1565 def STPXi : StorePairOffset<0b10, 0, GPR64, am_indexed64simm7, "stp">;
1566 def STPSi : StorePairOffset<0b00, 1, FPR32, am_indexed32simm7, "stp">;
1567 def STPDi : StorePairOffset<0b01, 1, FPR64, am_indexed64simm7, "stp">;
1568 def STPQi : StorePairOffset<0b10, 1, FPR128, am_indexed128simm7, "stp">;
1570 // Pair (pre-indexed)
1571 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "stp">;
1572 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "stp">;
1573 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "stp">;
1574 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "stp">;
1575 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "stp">;
1577 // Pair (pre-indexed)
1578 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1579 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1580 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1581 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1582 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1584 // Pair (no allocate)
1585 def STNPWi : StorePairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "stnp">;
1586 def STNPXi : StorePairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "stnp">;
1587 def STNPSi : StorePairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "stnp">;
1588 def STNPDi : StorePairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "stnp">;
1589 def STNPQi : StorePairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "stnp">;
1592 // (Register offset)
1594 let AddedComplexity = 10 in {
1597 def STRHHro : Store16RO<0b01, 0, 0b00, GPR32, "strh",
1598 [(truncstorei16 GPR32:$Rt, ro_indexed16:$addr)]>;
1599 def STRBBro : Store8RO<0b00, 0, 0b00, GPR32, "strb",
1600 [(truncstorei8 GPR32:$Rt, ro_indexed8:$addr)]>;
1601 def STRWro : Store32RO<0b10, 0, 0b00, GPR32, "str",
1602 [(store GPR32:$Rt, ro_indexed32:$addr)]>;
1603 def STRXro : Store64RO<0b11, 0, 0b00, GPR64, "str",
1604 [(store GPR64:$Rt, ro_indexed64:$addr)]>;
1607 def : Pat<(truncstorei8 GPR64:$Rt, ro_indexed8:$addr),
1608 (STRBBro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed8:$addr)>;
1609 def : Pat<(truncstorei16 GPR64:$Rt, ro_indexed16:$addr),
1610 (STRHHro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed16:$addr)>;
1611 def : Pat<(truncstorei32 GPR64:$Rt, ro_indexed32:$addr),
1612 (STRWro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed32:$addr)>;
1616 def STRBro : Store8RO<0b00, 1, 0b00, FPR8, "str",
1617 [(store FPR8:$Rt, ro_indexed8:$addr)]>;
1618 def STRHro : Store16RO<0b01, 1, 0b00, FPR16, "str",
1619 [(store (f16 FPR16:$Rt), ro_indexed16:$addr)]>;
1620 def STRSro : Store32RO<0b10, 1, 0b00, FPR32, "str",
1621 [(store (f32 FPR32:$Rt), ro_indexed32:$addr)]>;
1622 def STRDro : Store64RO<0b11, 1, 0b00, FPR64, "str",
1623 [(store (f64 FPR64:$Rt), ro_indexed64:$addr)]>;
1624 def STRQro : Store128RO<0b00, 1, 0b10, FPR128, "str", []> {
1628 // Match all store 64 bits width whose type is compatible with FPR64
1629 def : Pat<(store (v2f32 FPR64:$Rn), ro_indexed64:$addr),
1630 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1631 def : Pat<(store (v1f64 FPR64:$Rn), ro_indexed64:$addr),
1632 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1633 def : Pat<(store (v8i8 FPR64:$Rn), ro_indexed64:$addr),
1634 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1635 def : Pat<(store (v4i16 FPR64:$Rn), ro_indexed64:$addr),
1636 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1637 def : Pat<(store (v2i32 FPR64:$Rn), ro_indexed64:$addr),
1638 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1639 def : Pat<(store (v1i64 FPR64:$Rn), ro_indexed64:$addr),
1640 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1642 // Match all store 128 bits width whose type is compatible with FPR128
1643 def : Pat<(store (v4f32 FPR128:$Rn), ro_indexed128:$addr),
1644 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1645 def : Pat<(store (v2f64 FPR128:$Rn), ro_indexed128:$addr),
1646 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1647 def : Pat<(store (v16i8 FPR128:$Rn), ro_indexed128:$addr),
1648 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1649 def : Pat<(store (v8i16 FPR128:$Rn), ro_indexed128:$addr),
1650 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1651 def : Pat<(store (v4i32 FPR128:$Rn), ro_indexed128:$addr),
1652 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1653 def : Pat<(store (v2i64 FPR128:$Rn), ro_indexed128:$addr),
1654 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1655 def : Pat<(store (f128 FPR128:$Rn), ro_indexed128:$addr),
1656 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1659 // (unsigned immediate)
1660 def STRXui : StoreUI<0b11, 0, 0b00, GPR64, am_indexed64, "str",
1661 [(store GPR64:$Rt, am_indexed64:$addr)]>;
1662 def STRWui : StoreUI<0b10, 0, 0b00, GPR32, am_indexed32, "str",
1663 [(store GPR32:$Rt, am_indexed32:$addr)]>;
1664 def STRBui : StoreUI<0b00, 1, 0b00, FPR8, am_indexed8, "str",
1665 [(store FPR8:$Rt, am_indexed8:$addr)]>;
1666 def STRHui : StoreUI<0b01, 1, 0b00, FPR16, am_indexed16, "str",
1667 [(store (f16 FPR16:$Rt), am_indexed16:$addr)]>;
1668 def STRSui : StoreUI<0b10, 1, 0b00, FPR32, am_indexed32, "str",
1669 [(store (f32 FPR32:$Rt), am_indexed32:$addr)]>;
1670 def STRDui : StoreUI<0b11, 1, 0b00, FPR64, am_indexed64, "str",
1671 [(store (f64 FPR64:$Rt), am_indexed64:$addr)]>;
1672 def STRQui : StoreUI<0b00, 1, 0b10, FPR128, am_indexed128, "str", []> {
1676 // Match all store 64 bits width whose type is compatible with FPR64
1677 def : Pat<(store (v2f32 FPR64:$Rn), am_indexed64:$addr),
1678 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1679 def : Pat<(store (v1f64 FPR64:$Rn), am_indexed64:$addr),
1680 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1681 def : Pat<(store (v8i8 FPR64:$Rn), am_indexed64:$addr),
1682 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1683 def : Pat<(store (v4i16 FPR64:$Rn), am_indexed64:$addr),
1684 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1685 def : Pat<(store (v2i32 FPR64:$Rn), am_indexed64:$addr),
1686 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1687 def : Pat<(store (v1i64 FPR64:$Rn), am_indexed64:$addr),
1688 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1690 // Match all store 128 bits width whose type is compatible with FPR128
1691 def : Pat<(store (v4f32 FPR128:$Rn), am_indexed128:$addr),
1692 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1693 def : Pat<(store (v2f64 FPR128:$Rn), am_indexed128:$addr),
1694 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1695 def : Pat<(store (v16i8 FPR128:$Rn), am_indexed128:$addr),
1696 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1697 def : Pat<(store (v8i16 FPR128:$Rn), am_indexed128:$addr),
1698 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1699 def : Pat<(store (v4i32 FPR128:$Rn), am_indexed128:$addr),
1700 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1701 def : Pat<(store (v2i64 FPR128:$Rn), am_indexed128:$addr),
1702 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1703 def : Pat<(store (f128 FPR128:$Rn), am_indexed128:$addr),
1704 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1706 def STRHHui : StoreUI<0b01, 0, 0b00, GPR32, am_indexed16, "strh",
1707 [(truncstorei16 GPR32:$Rt, am_indexed16:$addr)]>;
1708 def STRBBui : StoreUI<0b00, 0, 0b00, GPR32, am_indexed8, "strb",
1709 [(truncstorei8 GPR32:$Rt, am_indexed8:$addr)]>;
1712 def : Pat<(truncstorei32 GPR64:$Rt, am_indexed32:$addr),
1713 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed32:$addr)>;
1714 def : Pat<(truncstorei16 GPR64:$Rt, am_indexed16:$addr),
1715 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed16:$addr)>;
1716 def : Pat<(truncstorei8 GPR64:$Rt, am_indexed8:$addr),
1717 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed8:$addr)>;
1719 } // AddedComplexity = 10
1722 // (unscaled immediate)
1723 def STURXi : StoreUnscaled<0b11, 0, 0b00, GPR64, am_unscaled64, "stur",
1724 [(store GPR64:$Rt, am_unscaled64:$addr)]>;
1725 def STURWi : StoreUnscaled<0b10, 0, 0b00, GPR32, am_unscaled32, "stur",
1726 [(store GPR32:$Rt, am_unscaled32:$addr)]>;
1727 def STURBi : StoreUnscaled<0b00, 1, 0b00, FPR8, am_unscaled8, "stur",
1728 [(store FPR8:$Rt, am_unscaled8:$addr)]>;
1729 def STURHi : StoreUnscaled<0b01, 1, 0b00, FPR16, am_unscaled16, "stur",
1730 [(store (f16 FPR16:$Rt), am_unscaled16:$addr)]>;
1731 def STURSi : StoreUnscaled<0b10, 1, 0b00, FPR32, am_unscaled32, "stur",
1732 [(store (f32 FPR32:$Rt), am_unscaled32:$addr)]>;
1733 def STURDi : StoreUnscaled<0b11, 1, 0b00, FPR64, am_unscaled64, "stur",
1734 [(store (f64 FPR64:$Rt), am_unscaled64:$addr)]>;
1735 def STURQi : StoreUnscaled<0b00, 1, 0b10, FPR128, am_unscaled128, "stur",
1736 [(store (v2f64 FPR128:$Rt), am_unscaled128:$addr)]>;
1737 def STURHHi : StoreUnscaled<0b01, 0, 0b00, GPR32, am_unscaled16, "sturh",
1738 [(truncstorei16 GPR32:$Rt, am_unscaled16:$addr)]>;
1739 def STURBBi : StoreUnscaled<0b00, 0, 0b00, GPR32, am_unscaled8, "sturb",
1740 [(truncstorei8 GPR32:$Rt, am_unscaled8:$addr)]>;
1742 // Match all store 64 bits width whose type is compatible with FPR64
1743 def : Pat<(store (v2f32 FPR64:$Rn), am_unscaled64:$addr),
1744 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1745 def : Pat<(store (v1f64 FPR64:$Rn), am_unscaled64:$addr),
1746 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1747 def : Pat<(store (v8i8 FPR64:$Rn), am_unscaled64:$addr),
1748 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1749 def : Pat<(store (v4i16 FPR64:$Rn), am_unscaled64:$addr),
1750 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1751 def : Pat<(store (v2i32 FPR64:$Rn), am_unscaled64:$addr),
1752 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1753 def : Pat<(store (v1i64 FPR64:$Rn), am_unscaled64:$addr),
1754 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1756 // Match all store 128 bits width whose type is compatible with FPR128
1757 def : Pat<(store (v4f32 FPR128:$Rn), am_unscaled128:$addr),
1758 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1759 def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
1760 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1761 def : Pat<(store (v16i8 FPR128:$Rn), am_unscaled128:$addr),
1762 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1763 def : Pat<(store (v8i16 FPR128:$Rn), am_unscaled128:$addr),
1764 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1765 def : Pat<(store (v4i32 FPR128:$Rn), am_unscaled128:$addr),
1766 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1767 def : Pat<(store (v2i64 FPR128:$Rn), am_unscaled128:$addr),
1768 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1769 def : Pat<(store (f128 FPR128:$Rn), am_unscaled128:$addr),
1770 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1772 // unscaled i64 truncating stores
1773 def : Pat<(truncstorei32 GPR64:$Rt, am_unscaled32:$addr),
1774 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled32:$addr)>;
1775 def : Pat<(truncstorei16 GPR64:$Rt, am_unscaled16:$addr),
1776 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled16:$addr)>;
1777 def : Pat<(truncstorei8 GPR64:$Rt, am_unscaled8:$addr),
1778 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled8:$addr)>;
1781 // STR mnemonics fall back to STUR for negative or unaligned offsets.
1782 def : InstAlias<"str $Rt, $addr", (STURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1783 def : InstAlias<"str $Rt, $addr", (STURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1784 def : InstAlias<"str $Rt, $addr", (STURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1785 def : InstAlias<"str $Rt, $addr", (STURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1786 def : InstAlias<"str $Rt, $addr", (STURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1787 def : InstAlias<"str $Rt, $addr", (STURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1788 def : InstAlias<"str $Rt, $addr", (STURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1790 def : InstAlias<"strb $Rt, $addr", (STURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1791 def : InstAlias<"strh $Rt, $addr", (STURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1794 // (unscaled immediate, unprivileged)
1795 def STTRWi : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
1796 def STTRXi : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
1798 def STTRHi : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
1799 def STTRBi : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
1802 // (immediate pre-indexed)
1803 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str">;
1804 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str">;
1805 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str">;
1806 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str">;
1807 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str">;
1808 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str">;
1809 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str">;
1811 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb">;
1812 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh">;
1814 // ISel pseudos and patterns. See expanded comment on StorePreIdxPseudo.
1815 defm STRDpre : StorePreIdxPseudo<FPR64, f64, pre_store>;
1816 defm STRSpre : StorePreIdxPseudo<FPR32, f32, pre_store>;
1817 defm STRXpre : StorePreIdxPseudo<GPR64, i64, pre_store>;
1818 defm STRWpre : StorePreIdxPseudo<GPR32, i32, pre_store>;
1819 defm STRHHpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti16>;
1820 defm STRBBpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti8>;
1822 def : Pat<(pre_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1823 (STRWpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1825 def : Pat<(pre_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1826 (STRHHpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1828 def : Pat<(pre_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1829 (STRBBpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1833 // (immediate post-indexed)
1834 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str">;
1835 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str">;
1836 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str">;
1837 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str">;
1838 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str">;
1839 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str">;
1840 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str">;
1842 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb">;
1843 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh">;
1845 // ISel pseudos and patterns. See expanded comment on StorePostIdxPseudo.
1846 defm STRDpost : StorePostIdxPseudo<FPR64, f64, post_store, STRDpost>;
1847 defm STRSpost : StorePostIdxPseudo<FPR32, f32, post_store, STRSpost>;
1848 defm STRXpost : StorePostIdxPseudo<GPR64, i64, post_store, STRXpost>;
1849 defm STRWpost : StorePostIdxPseudo<GPR32, i32, post_store, STRWpost>;
1850 defm STRHHpost : StorePostIdxPseudo<GPR32, i32, post_truncsti16, STRHHpost>;
1851 defm STRBBpost : StorePostIdxPseudo<GPR32, i32, post_truncsti8, STRBBpost>;
1853 def : Pat<(post_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1854 (STRWpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1856 def : Pat<(post_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1857 (STRHHpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1859 def : Pat<(post_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1860 (STRBBpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1864 //===----------------------------------------------------------------------===//
1865 // Load/store exclusive instructions.
1866 //===----------------------------------------------------------------------===//
1868 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
1869 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
1870 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
1871 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
1873 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
1874 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
1875 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
1876 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
1878 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
1879 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
1880 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
1881 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
1883 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
1884 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
1885 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
1886 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
1888 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
1889 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
1890 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
1891 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
1893 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
1894 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
1895 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
1896 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
1898 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
1899 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
1901 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
1902 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
1904 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
1905 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
1907 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
1908 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
1910 //===----------------------------------------------------------------------===//
1911 // Scaled floating point to integer conversion instructions.
1912 //===----------------------------------------------------------------------===//
1914 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
1915 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
1916 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
1917 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
1918 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
1919 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
1920 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
1921 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
1922 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
1923 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
1924 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
1925 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
1926 let isCodeGenOnly = 1 in {
1927 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
1928 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
1929 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
1930 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
1933 //===----------------------------------------------------------------------===//
1934 // Scaled integer to floating point conversion instructions.
1935 //===----------------------------------------------------------------------===//
1937 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
1938 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
1940 //===----------------------------------------------------------------------===//
1941 // Unscaled integer to floating point conversion instruction.
1942 //===----------------------------------------------------------------------===//
1944 defm FMOV : UnscaledConversion<"fmov">;
1946 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
1947 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
1949 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1950 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1951 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1952 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1953 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1954 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1955 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
1956 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1957 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
1958 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1959 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
1961 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
1962 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1963 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
1964 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1965 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
1966 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1967 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
1968 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1969 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
1970 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1971 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
1972 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1974 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
1975 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
1976 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
1977 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
1978 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
1979 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1980 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
1981 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
1983 //===----------------------------------------------------------------------===//
1984 // Floating point conversion instruction.
1985 //===----------------------------------------------------------------------===//
1987 defm FCVT : FPConversion<"fcvt">;
1989 def : Pat<(f32_to_f16 FPR32:$Rn),
1990 (i32 (COPY_TO_REGCLASS
1991 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
1994 def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
1995 [(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
1997 //===----------------------------------------------------------------------===//
1998 // Floating point single operand instructions.
1999 //===----------------------------------------------------------------------===//
2001 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2002 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2003 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2004 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2005 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2006 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2007 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_arm64_neon_frintn>;
2008 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2010 def : Pat<(v1f64 (int_arm64_neon_frintn (v1f64 FPR64:$Rn))),
2011 (FRINTNDr FPR64:$Rn)>;
2013 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2014 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2015 // <rdar://problem/13715968>
2016 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2017 let hasSideEffects = 1 in {
2018 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2021 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2023 let SchedRW = [WriteFDiv] in {
2024 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2027 //===----------------------------------------------------------------------===//
2028 // Floating point two operand instructions.
2029 //===----------------------------------------------------------------------===//
2031 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2032 let SchedRW = [WriteFDiv] in {
2033 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2035 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_arm64_neon_fmaxnm>;
2036 defm FMAX : TwoOperandFPData<0b0100, "fmax", ARM64fmax>;
2037 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_arm64_neon_fminnm>;
2038 defm FMIN : TwoOperandFPData<0b0101, "fmin", ARM64fmin>;
2039 let SchedRW = [WriteFMul] in {
2040 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2041 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2043 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2045 def : Pat<(v1f64 (ARM64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2046 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2047 def : Pat<(v1f64 (ARM64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2048 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2049 def : Pat<(v1f64 (int_arm64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2050 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2051 def : Pat<(v1f64 (int_arm64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2052 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2054 //===----------------------------------------------------------------------===//
2055 // Floating point three operand instructions.
2056 //===----------------------------------------------------------------------===//
2058 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2059 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2060 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2061 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2062 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2063 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2064 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2066 // The following def pats catch the case where the LHS of an FMA is negated.
2067 // The TriOpFrag above catches the case where the middle operand is negated.
2069 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2070 // the NEON variant.
2071 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2072 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2074 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2075 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2077 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2079 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2080 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2082 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2083 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2085 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2086 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2088 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2089 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2091 //===----------------------------------------------------------------------===//
2092 // Floating point comparison instructions.
2093 //===----------------------------------------------------------------------===//
2095 defm FCMPE : FPComparison<1, "fcmpe">;
2096 defm FCMP : FPComparison<0, "fcmp", ARM64fcmp>;
2098 //===----------------------------------------------------------------------===//
2099 // Floating point conditional comparison instructions.
2100 //===----------------------------------------------------------------------===//
2102 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2103 defm FCCMP : FPCondComparison<0, "fccmp">;
2105 //===----------------------------------------------------------------------===//
2106 // Floating point conditional select instruction.
2107 //===----------------------------------------------------------------------===//
2109 defm FCSEL : FPCondSelect<"fcsel">;
2111 // CSEL instructions providing f128 types need to be handled by a
2112 // pseudo-instruction since the eventual code will need to introduce basic
2113 // blocks and control flow.
2114 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2115 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2116 [(set (f128 FPR128:$Rd),
2117 (ARM64csel FPR128:$Rn, FPR128:$Rm,
2118 (i32 imm:$cond), NZCV))]> {
2120 let usesCustomInserter = 1;
2124 //===----------------------------------------------------------------------===//
2125 // Floating point immediate move.
2126 //===----------------------------------------------------------------------===//
2128 let isReMaterializable = 1 in {
2129 defm FMOV : FPMoveImmediate<"fmov">;
2132 //===----------------------------------------------------------------------===//
2133 // Advanced SIMD two vector instructions.
2134 //===----------------------------------------------------------------------===//
2136 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_arm64_neon_abs>;
2137 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_arm64_neon_cls>;
2138 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2139 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", ARM64cmeqz>;
2140 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", ARM64cmgez>;
2141 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", ARM64cmgtz>;
2142 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", ARM64cmlez>;
2143 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", ARM64cmltz>;
2144 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2145 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2147 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2148 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2149 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2150 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2151 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2152 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_arm64_neon_fcvtas>;
2153 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_arm64_neon_fcvtau>;
2154 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2155 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2156 (FCVTLv4i16 V64:$Rn)>;
2157 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2159 (FCVTLv8i16 V128:$Rn)>;
2160 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2161 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2163 (FCVTLv4i32 V128:$Rn)>;
2165 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_arm64_neon_fcvtms>;
2166 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_arm64_neon_fcvtmu>;
2167 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_arm64_neon_fcvtns>;
2168 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_arm64_neon_fcvtnu>;
2169 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2170 def : Pat<(v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2171 (FCVTNv4i16 V128:$Rn)>;
2172 def : Pat<(concat_vectors V64:$Rd,
2173 (v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2174 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2175 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2176 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2177 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2178 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_arm64_neon_fcvtps>;
2179 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_arm64_neon_fcvtpu>;
2180 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2181 int_arm64_neon_fcvtxn>;
2182 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2183 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2184 let isCodeGenOnly = 1 in {
2185 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2186 int_arm64_neon_fcvtzs>;
2187 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2188 int_arm64_neon_fcvtzu>;
2190 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2191 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_arm64_neon_frecpe>;
2192 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2193 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2194 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2195 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_arm64_neon_frintn>;
2196 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2197 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2198 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2199 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_arm64_neon_frsqrte>;
2200 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2201 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2202 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2203 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2204 // Aliases for MVN -> NOT.
2205 def : InstAlias<"mvn.8b $Vd, $Vn", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2206 def : InstAlias<"mvn.16b $Vd, $Vn", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2207 def : InstAlias<"mvn $Vd.8b, $Vn.8b", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2208 def : InstAlias<"mvn $Vd.16b, $Vn.16b", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2210 def : Pat<(ARM64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2211 def : Pat<(ARM64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2212 def : Pat<(ARM64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2213 def : Pat<(ARM64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2214 def : Pat<(ARM64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2215 def : Pat<(ARM64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2216 def : Pat<(ARM64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2218 def : Pat<(ARM64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2219 def : Pat<(ARM64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2220 def : Pat<(ARM64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2221 def : Pat<(ARM64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2222 def : Pat<(ARM64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2223 def : Pat<(ARM64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2224 def : Pat<(ARM64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2225 def : Pat<(ARM64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2227 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2228 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2229 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2230 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2231 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2233 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_arm64_neon_rbit>;
2234 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", ARM64rev16>;
2235 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", ARM64rev32>;
2236 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", ARM64rev64>;
2237 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2238 BinOpFrag<(add node:$LHS, (int_arm64_neon_saddlp node:$RHS))> >;
2239 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_arm64_neon_saddlp>;
2240 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2241 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2242 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2243 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2244 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_arm64_neon_sqxtn>;
2245 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_arm64_neon_sqxtun>;
2246 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_arm64_neon_suqadd>;
2247 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2248 BinOpFrag<(add node:$LHS, (int_arm64_neon_uaddlp node:$RHS))> >;
2249 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2250 int_arm64_neon_uaddlp>;
2251 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2252 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_arm64_neon_uqxtn>;
2253 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_arm64_neon_urecpe>;
2254 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_arm64_neon_ursqrte>;
2255 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_arm64_neon_usqadd>;
2256 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2258 def : Pat<(v2f32 (ARM64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2259 def : Pat<(v4f32 (ARM64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2261 // Patterns for vector long shift (by element width). These need to match all
2262 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2264 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2265 def : Pat<(ARM64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2266 (SHLLv8i8 V64:$Rn)>;
2267 def : Pat<(ARM64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2268 (SHLLv16i8 V128:$Rn)>;
2269 def : Pat<(ARM64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2270 (SHLLv4i16 V64:$Rn)>;
2271 def : Pat<(ARM64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2272 (SHLLv8i16 V128:$Rn)>;
2273 def : Pat<(ARM64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2274 (SHLLv2i32 V64:$Rn)>;
2275 def : Pat<(ARM64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2276 (SHLLv4i32 V128:$Rn)>;
2279 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2280 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2281 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2283 //===----------------------------------------------------------------------===//
2284 // Advanced SIMD three vector instructions.
2285 //===----------------------------------------------------------------------===//
2287 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2288 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_arm64_neon_addp>;
2289 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", ARM64cmeq>;
2290 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", ARM64cmge>;
2291 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", ARM64cmgt>;
2292 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", ARM64cmhi>;
2293 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", ARM64cmhs>;
2294 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", ARM64cmtst>;
2295 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_arm64_neon_fabd>;
2296 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_arm64_neon_facge>;
2297 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_arm64_neon_facgt>;
2298 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_arm64_neon_addp>;
2299 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2300 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2301 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2302 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2303 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2304 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_arm64_neon_fmaxnmp>;
2305 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_arm64_neon_fmaxnm>;
2306 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_arm64_neon_fmaxp>;
2307 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", ARM64fmax>;
2308 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_arm64_neon_fminnmp>;
2309 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_arm64_neon_fminnm>;
2310 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_arm64_neon_fminp>;
2311 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", ARM64fmin>;
2313 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2314 // instruction expects the addend first, while the fma intrinsic puts it last.
2315 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2316 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2317 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2318 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2320 // The following def pats catch the case where the LHS of an FMA is negated.
2321 // The TriOpFrag above catches the case where the middle operand is negated.
2322 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2323 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2325 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2326 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2328 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2329 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2331 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_arm64_neon_fmulx>;
2332 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2333 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_arm64_neon_frecps>;
2334 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_arm64_neon_frsqrts>;
2335 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2336 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2337 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2338 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2339 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2340 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2341 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_arm64_neon_pmul>;
2342 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2343 TriOpFrag<(add node:$LHS, (int_arm64_neon_sabd node:$MHS, node:$RHS))> >;
2344 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_arm64_neon_sabd>;
2345 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_arm64_neon_shadd>;
2346 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_arm64_neon_shsub>;
2347 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_arm64_neon_smaxp>;
2348 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_arm64_neon_smax>;
2349 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_arm64_neon_sminp>;
2350 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_arm64_neon_smin>;
2351 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_arm64_neon_sqadd>;
2352 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_arm64_neon_sqdmulh>;
2353 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_arm64_neon_sqrdmulh>;
2354 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_arm64_neon_sqrshl>;
2355 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_arm64_neon_sqshl>;
2356 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_arm64_neon_sqsub>;
2357 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_arm64_neon_srhadd>;
2358 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_arm64_neon_srshl>;
2359 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_arm64_neon_sshl>;
2360 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2361 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2362 TriOpFrag<(add node:$LHS, (int_arm64_neon_uabd node:$MHS, node:$RHS))> >;
2363 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_arm64_neon_uabd>;
2364 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_arm64_neon_uhadd>;
2365 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_arm64_neon_uhsub>;
2366 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_arm64_neon_umaxp>;
2367 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_arm64_neon_umax>;
2368 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_arm64_neon_uminp>;
2369 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_arm64_neon_umin>;
2370 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_arm64_neon_uqadd>;
2371 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_arm64_neon_uqrshl>;
2372 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_arm64_neon_uqshl>;
2373 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_arm64_neon_uqsub>;
2374 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_arm64_neon_urhadd>;
2375 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_arm64_neon_urshl>;
2376 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_arm64_neon_ushl>;
2378 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2379 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2380 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2381 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2382 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", ARM64bit>;
2383 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2384 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2385 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2386 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2387 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2388 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2390 def : Pat<(ARM64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2391 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2392 def : Pat<(ARM64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2393 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2394 def : Pat<(ARM64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2395 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2396 def : Pat<(ARM64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2397 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2399 def : Pat<(ARM64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2400 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2401 def : Pat<(ARM64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2402 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2403 def : Pat<(ARM64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2404 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2405 def : Pat<(ARM64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2406 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2408 // FIXME: the .16b and .8b variantes should be emitted by the
2409 // AsmWriter. TableGen's AsmWriter-generator doesn't deal with variant syntaxes
2410 // in aliases yet though.
2411 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2412 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2413 def : InstAlias<"{mov\t$dst.8h, $src.8h|mov.8h\t$dst, $src}",
2414 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2415 def : InstAlias<"{mov\t$dst.4s, $src.4s|mov.4s\t$dst, $src}",
2416 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2417 def : InstAlias<"{mov\t$dst.2d, $src.2d|mov.2d\t$dst, $src}",
2418 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2420 def : InstAlias<"{mov\t$dst.8b, $src.8b|mov.8b\t$dst, $src}",
2421 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2422 def : InstAlias<"{mov\t$dst.4h, $src.4h|mov.4h\t$dst, $src}",
2423 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2424 def : InstAlias<"{mov\t$dst.2s, $src.2s|mov.2s\t$dst, $src}",
2425 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2426 def : InstAlias<"{mov\t$dst.1d, $src.1d|mov.1d\t$dst, $src}",
2427 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2429 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2430 "|cmls.8b\t$dst, $src1, $src2}",
2431 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2432 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2433 "|cmls.16b\t$dst, $src1, $src2}",
2434 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2435 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2436 "|cmls.4h\t$dst, $src1, $src2}",
2437 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2438 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2439 "|cmls.8h\t$dst, $src1, $src2}",
2440 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2441 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2442 "|cmls.2s\t$dst, $src1, $src2}",
2443 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2444 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2445 "|cmls.4s\t$dst, $src1, $src2}",
2446 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2447 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2448 "|cmls.2d\t$dst, $src1, $src2}",
2449 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2451 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2452 "|cmlo.8b\t$dst, $src1, $src2}",
2453 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2454 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2455 "|cmlo.16b\t$dst, $src1, $src2}",
2456 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2457 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2458 "|cmlo.4h\t$dst, $src1, $src2}",
2459 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2460 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2461 "|cmlo.8h\t$dst, $src1, $src2}",
2462 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2463 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2464 "|cmlo.2s\t$dst, $src1, $src2}",
2465 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2466 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2467 "|cmlo.4s\t$dst, $src1, $src2}",
2468 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2469 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2470 "|cmlo.2d\t$dst, $src1, $src2}",
2471 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2473 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2474 "|cmle.8b\t$dst, $src1, $src2}",
2475 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2476 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2477 "|cmle.16b\t$dst, $src1, $src2}",
2478 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2479 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2480 "|cmle.4h\t$dst, $src1, $src2}",
2481 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2482 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2483 "|cmle.8h\t$dst, $src1, $src2}",
2484 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2485 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2486 "|cmle.2s\t$dst, $src1, $src2}",
2487 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2488 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2489 "|cmle.4s\t$dst, $src1, $src2}",
2490 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2491 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2492 "|cmle.2d\t$dst, $src1, $src2}",
2493 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2495 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2496 "|cmlt.8b\t$dst, $src1, $src2}",
2497 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2498 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2499 "|cmlt.16b\t$dst, $src1, $src2}",
2500 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2501 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2502 "|cmlt.4h\t$dst, $src1, $src2}",
2503 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2504 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2505 "|cmlt.8h\t$dst, $src1, $src2}",
2506 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2507 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2508 "|cmlt.2s\t$dst, $src1, $src2}",
2509 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2510 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2511 "|cmlt.4s\t$dst, $src1, $src2}",
2512 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2513 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2514 "|cmlt.2d\t$dst, $src1, $src2}",
2515 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2517 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2518 "|fcmle.2s\t$dst, $src1, $src2}",
2519 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2520 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2521 "|fcmle.4s\t$dst, $src1, $src2}",
2522 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2523 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2524 "|fcmle.2d\t$dst, $src1, $src2}",
2525 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2527 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2528 "|fcmlt.2s\t$dst, $src1, $src2}",
2529 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2530 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2531 "|fcmlt.4s\t$dst, $src1, $src2}",
2532 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2533 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2534 "|fcmlt.2d\t$dst, $src1, $src2}",
2535 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2537 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2538 "|facle.2s\t$dst, $src1, $src2}",
2539 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2540 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2541 "|facle.4s\t$dst, $src1, $src2}",
2542 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2543 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2544 "|facle.2d\t$dst, $src1, $src2}",
2545 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2547 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2548 "|faclt.2s\t$dst, $src1, $src2}",
2549 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2550 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2551 "|faclt.4s\t$dst, $src1, $src2}",
2552 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2553 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2554 "|faclt.2d\t$dst, $src1, $src2}",
2555 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2557 //===----------------------------------------------------------------------===//
2558 // Advanced SIMD three scalar instructions.
2559 //===----------------------------------------------------------------------===//
2561 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2562 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", ARM64cmeq>;
2563 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", ARM64cmge>;
2564 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", ARM64cmgt>;
2565 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", ARM64cmhi>;
2566 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", ARM64cmhs>;
2567 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", ARM64cmtst>;
2568 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_arm64_sisd_fabd>;
2569 def : Pat<(v1f64 (int_arm64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2570 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2571 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2572 int_arm64_neon_facge>;
2573 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2574 int_arm64_neon_facgt>;
2575 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2576 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2577 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2578 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_arm64_neon_fmulx>;
2579 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_arm64_neon_frecps>;
2580 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_arm64_neon_frsqrts>;
2581 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_arm64_neon_sqadd>;
2582 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_arm64_neon_sqdmulh>;
2583 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_arm64_neon_sqrdmulh>;
2584 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_arm64_neon_sqrshl>;
2585 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_arm64_neon_sqshl>;
2586 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_arm64_neon_sqsub>;
2587 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_arm64_neon_srshl>;
2588 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_arm64_neon_sshl>;
2589 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2590 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_arm64_neon_uqadd>;
2591 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_arm64_neon_uqrshl>;
2592 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_arm64_neon_uqshl>;
2593 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_arm64_neon_uqsub>;
2594 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_arm64_neon_urshl>;
2595 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_arm64_neon_ushl>;
2597 def : InstAlias<"cmls $dst, $src1, $src2",
2598 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2599 def : InstAlias<"cmle $dst, $src1, $src2",
2600 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2601 def : InstAlias<"cmlo $dst, $src1, $src2",
2602 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2603 def : InstAlias<"cmlt $dst, $src1, $src2",
2604 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2605 def : InstAlias<"fcmle $dst, $src1, $src2",
2606 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2607 def : InstAlias<"fcmle $dst, $src1, $src2",
2608 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2609 def : InstAlias<"fcmlt $dst, $src1, $src2",
2610 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2611 def : InstAlias<"fcmlt $dst, $src1, $src2",
2612 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2613 def : InstAlias<"facle $dst, $src1, $src2",
2614 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2615 def : InstAlias<"facle $dst, $src1, $src2",
2616 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2617 def : InstAlias<"faclt $dst, $src1, $src2",
2618 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2619 def : InstAlias<"faclt $dst, $src1, $src2",
2620 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2622 //===----------------------------------------------------------------------===//
2623 // Advanced SIMD three scalar instructions (mixed operands).
2624 //===----------------------------------------------------------------------===//
2625 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2626 int_arm64_neon_sqdmulls_scalar>;
2627 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2628 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2630 def : Pat<(i64 (int_arm64_neon_sqadd (i64 FPR64:$Rd),
2631 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2632 (i32 FPR32:$Rm))))),
2633 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2634 def : Pat<(i64 (int_arm64_neon_sqsub (i64 FPR64:$Rd),
2635 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2636 (i32 FPR32:$Rm))))),
2637 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2639 //===----------------------------------------------------------------------===//
2640 // Advanced SIMD two scalar instructions.
2641 //===----------------------------------------------------------------------===//
2643 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_arm64_neon_abs>;
2644 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", ARM64cmeqz>;
2645 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", ARM64cmgez>;
2646 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", ARM64cmgtz>;
2647 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", ARM64cmlez>;
2648 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", ARM64cmltz>;
2649 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2650 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2651 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2652 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2653 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2654 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2655 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2656 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2657 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2658 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2659 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2660 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2661 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2662 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2663 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2664 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2665 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2666 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2667 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2668 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
2669 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2670 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", ARM64sitof>;
2671 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2672 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2673 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_arm64_neon_scalar_sqxtn>;
2674 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_arm64_neon_scalar_sqxtun>;
2675 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2676 int_arm64_neon_suqadd>;
2677 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", ARM64uitof>;
2678 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_arm64_neon_scalar_uqxtn>;
2679 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2680 int_arm64_neon_usqadd>;
2682 def : Pat<(ARM64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
2684 def : Pat<(v1i64 (int_arm64_neon_fcvtas (v1f64 FPR64:$Rn))),
2685 (FCVTASv1i64 FPR64:$Rn)>;
2686 def : Pat<(v1i64 (int_arm64_neon_fcvtau (v1f64 FPR64:$Rn))),
2687 (FCVTAUv1i64 FPR64:$Rn)>;
2688 def : Pat<(v1i64 (int_arm64_neon_fcvtms (v1f64 FPR64:$Rn))),
2689 (FCVTMSv1i64 FPR64:$Rn)>;
2690 def : Pat<(v1i64 (int_arm64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2691 (FCVTMUv1i64 FPR64:$Rn)>;
2692 def : Pat<(v1i64 (int_arm64_neon_fcvtns (v1f64 FPR64:$Rn))),
2693 (FCVTNSv1i64 FPR64:$Rn)>;
2694 def : Pat<(v1i64 (int_arm64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2695 (FCVTNUv1i64 FPR64:$Rn)>;
2696 def : Pat<(v1i64 (int_arm64_neon_fcvtps (v1f64 FPR64:$Rn))),
2697 (FCVTPSv1i64 FPR64:$Rn)>;
2698 def : Pat<(v1i64 (int_arm64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2699 (FCVTPUv1i64 FPR64:$Rn)>;
2701 def : Pat<(f32 (int_arm64_neon_frecpe (f32 FPR32:$Rn))),
2702 (FRECPEv1i32 FPR32:$Rn)>;
2703 def : Pat<(f64 (int_arm64_neon_frecpe (f64 FPR64:$Rn))),
2704 (FRECPEv1i64 FPR64:$Rn)>;
2705 def : Pat<(v1f64 (int_arm64_neon_frecpe (v1f64 FPR64:$Rn))),
2706 (FRECPEv1i64 FPR64:$Rn)>;
2708 def : Pat<(f32 (int_arm64_neon_frecpx (f32 FPR32:$Rn))),
2709 (FRECPXv1i32 FPR32:$Rn)>;
2710 def : Pat<(f64 (int_arm64_neon_frecpx (f64 FPR64:$Rn))),
2711 (FRECPXv1i64 FPR64:$Rn)>;
2713 def : Pat<(f32 (int_arm64_neon_frsqrte (f32 FPR32:$Rn))),
2714 (FRSQRTEv1i32 FPR32:$Rn)>;
2715 def : Pat<(f64 (int_arm64_neon_frsqrte (f64 FPR64:$Rn))),
2716 (FRSQRTEv1i64 FPR64:$Rn)>;
2717 def : Pat<(v1f64 (int_arm64_neon_frsqrte (v1f64 FPR64:$Rn))),
2718 (FRSQRTEv1i64 FPR64:$Rn)>;
2720 // If an integer is about to be converted to a floating point value,
2721 // just load it on the floating point unit.
2722 // Here are the patterns for 8 and 16-bits to float.
2724 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2725 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2726 (LDRBro ro_indexed8:$addr), bsub))>;
2727 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2728 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2729 (LDRBui am_indexed8:$addr), bsub))>;
2730 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2731 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2732 (LDURBi am_unscaled8:$addr), bsub))>;
2733 // 16-bits -> float.
2734 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2735 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2736 (LDRHro ro_indexed16:$addr), hsub))>;
2737 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2738 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2739 (LDRHui am_indexed16:$addr), hsub))>;
2740 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2741 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2742 (LDURHi am_unscaled16:$addr), hsub))>;
2743 // 32-bits are handled in target specific dag combine:
2744 // performIntToFpCombine.
2745 // 64-bits integer to 32-bits floating point, not possible with
2746 // UCVTF on floating point registers (both source and destination
2747 // must have the same size).
2749 // Here are the patterns for 8, 16, 32, and 64-bits to double.
2750 // 8-bits -> double.
2751 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2752 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2753 (LDRBro ro_indexed8:$addr), bsub))>;
2754 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2755 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2756 (LDRBui am_indexed8:$addr), bsub))>;
2757 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2758 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2759 (LDURBi am_unscaled8:$addr), bsub))>;
2760 // 16-bits -> double.
2761 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2762 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2763 (LDRHro ro_indexed16:$addr), hsub))>;
2764 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2765 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2766 (LDRHui am_indexed16:$addr), hsub))>;
2767 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2768 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2769 (LDURHi am_unscaled16:$addr), hsub))>;
2770 // 32-bits -> double.
2771 def : Pat <(f64 (uint_to_fp (i32 (load ro_indexed32:$addr)))),
2772 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2773 (LDRSro ro_indexed32:$addr), ssub))>;
2774 def : Pat <(f64 (uint_to_fp (i32 (load am_indexed32:$addr)))),
2775 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2776 (LDRSui am_indexed32:$addr), ssub))>;
2777 def : Pat <(f64 (uint_to_fp (i32 (load am_unscaled32:$addr)))),
2778 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2779 (LDURSi am_unscaled32:$addr), ssub))>;
2780 // 64-bits -> double are handled in target specific dag combine:
2781 // performIntToFpCombine.
2783 //===----------------------------------------------------------------------===//
2784 // Advanced SIMD three different-sized vector instructions.
2785 //===----------------------------------------------------------------------===//
2787 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_arm64_neon_addhn>;
2788 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_arm64_neon_subhn>;
2789 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_arm64_neon_raddhn>;
2790 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_arm64_neon_rsubhn>;
2791 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_arm64_neon_pmull>;
2792 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
2793 int_arm64_neon_sabd>;
2794 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
2795 int_arm64_neon_sabd>;
2796 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
2797 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
2798 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
2799 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
2800 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
2801 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2802 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
2803 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2804 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_arm64_neon_smull>;
2805 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
2806 int_arm64_neon_sqadd>;
2807 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
2808 int_arm64_neon_sqsub>;
2809 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
2810 int_arm64_neon_sqdmull>;
2811 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
2812 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
2813 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
2814 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
2815 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
2816 int_arm64_neon_uabd>;
2817 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
2818 int_arm64_neon_uabd>;
2819 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
2820 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
2821 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
2822 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
2823 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
2824 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2825 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
2826 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2827 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_arm64_neon_umull>;
2828 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
2829 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
2830 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
2831 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
2833 // Patterns for 64-bit pmull
2834 def : Pat<(int_arm64_neon_pmull64 V64:$Rn, V64:$Rm),
2835 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
2836 def : Pat<(int_arm64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
2837 (vector_extract (v2i64 V128:$Rm), (i64 1))),
2838 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
2840 // CodeGen patterns for addhn and subhn instructions, which can actually be
2841 // written in LLVM IR without too much difficulty.
2844 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
2845 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2846 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2848 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2849 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2851 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2852 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2853 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2855 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2856 V128:$Rn, V128:$Rm)>;
2857 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2858 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2860 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2861 V128:$Rn, V128:$Rm)>;
2862 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2863 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2865 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2866 V128:$Rn, V128:$Rm)>;
2869 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
2870 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2871 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2873 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2874 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2876 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2877 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2878 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2880 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2881 V128:$Rn, V128:$Rm)>;
2882 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2883 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2885 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2886 V128:$Rn, V128:$Rm)>;
2887 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2888 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2890 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2891 V128:$Rn, V128:$Rm)>;
2893 //----------------------------------------------------------------------------
2894 // AdvSIMD bitwise extract from vector instruction.
2895 //----------------------------------------------------------------------------
2897 defm EXT : SIMDBitwiseExtract<"ext">;
2899 def : Pat<(v4i16 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2900 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2901 def : Pat<(v8i16 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2902 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2903 def : Pat<(v2i32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2904 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2905 def : Pat<(v2f32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2906 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2907 def : Pat<(v4i32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2908 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2909 def : Pat<(v4f32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2910 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2911 def : Pat<(v2i64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2912 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2913 def : Pat<(v2f64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2914 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2916 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
2918 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
2919 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2920 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
2921 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2922 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
2923 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2924 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
2925 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2926 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
2927 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2928 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
2929 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2932 //----------------------------------------------------------------------------
2933 // AdvSIMD zip vector
2934 //----------------------------------------------------------------------------
2936 defm TRN1 : SIMDZipVector<0b010, "trn1", ARM64trn1>;
2937 defm TRN2 : SIMDZipVector<0b110, "trn2", ARM64trn2>;
2938 defm UZP1 : SIMDZipVector<0b001, "uzp1", ARM64uzp1>;
2939 defm UZP2 : SIMDZipVector<0b101, "uzp2", ARM64uzp2>;
2940 defm ZIP1 : SIMDZipVector<0b011, "zip1", ARM64zip1>;
2941 defm ZIP2 : SIMDZipVector<0b111, "zip2", ARM64zip2>;
2943 //----------------------------------------------------------------------------
2944 // AdvSIMD TBL/TBX instructions
2945 //----------------------------------------------------------------------------
2947 defm TBL : SIMDTableLookup< 0, "tbl">;
2948 defm TBX : SIMDTableLookupTied<1, "tbx">;
2950 def : Pat<(v8i8 (int_arm64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
2951 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
2952 def : Pat<(v16i8 (int_arm64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
2953 (TBLv16i8One V128:$Ri, V128:$Rn)>;
2955 def : Pat<(v8i8 (int_arm64_neon_tbx1 (v8i8 V64:$Rd),
2956 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
2957 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
2958 def : Pat<(v16i8 (int_arm64_neon_tbx1 (v16i8 V128:$Rd),
2959 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
2960 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
2963 //----------------------------------------------------------------------------
2964 // AdvSIMD scalar CPY instruction
2965 //----------------------------------------------------------------------------
2967 defm CPY : SIMDScalarCPY<"cpy">;
2969 //----------------------------------------------------------------------------
2970 // AdvSIMD scalar pairwise instructions
2971 //----------------------------------------------------------------------------
2973 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
2974 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
2975 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
2976 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
2977 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
2978 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
2979 def : Pat<(i64 (int_arm64_neon_saddv (v2i64 V128:$Rn))),
2980 (ADDPv2i64p V128:$Rn)>;
2981 def : Pat<(i64 (int_arm64_neon_uaddv (v2i64 V128:$Rn))),
2982 (ADDPv2i64p V128:$Rn)>;
2983 def : Pat<(f32 (int_arm64_neon_faddv (v2f32 V64:$Rn))),
2984 (FADDPv2i32p V64:$Rn)>;
2985 def : Pat<(f32 (int_arm64_neon_faddv (v4f32 V128:$Rn))),
2986 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
2987 def : Pat<(f64 (int_arm64_neon_faddv (v2f64 V128:$Rn))),
2988 (FADDPv2i64p V128:$Rn)>;
2989 def : Pat<(f32 (int_arm64_neon_fmaxnmv (v2f32 V64:$Rn))),
2990 (FMAXNMPv2i32p V64:$Rn)>;
2991 def : Pat<(f64 (int_arm64_neon_fmaxnmv (v2f64 V128:$Rn))),
2992 (FMAXNMPv2i64p V128:$Rn)>;
2993 def : Pat<(f32 (int_arm64_neon_fmaxv (v2f32 V64:$Rn))),
2994 (FMAXPv2i32p V64:$Rn)>;
2995 def : Pat<(f64 (int_arm64_neon_fmaxv (v2f64 V128:$Rn))),
2996 (FMAXPv2i64p V128:$Rn)>;
2997 def : Pat<(f32 (int_arm64_neon_fminnmv (v2f32 V64:$Rn))),
2998 (FMINNMPv2i32p V64:$Rn)>;
2999 def : Pat<(f64 (int_arm64_neon_fminnmv (v2f64 V128:$Rn))),
3000 (FMINNMPv2i64p V128:$Rn)>;
3001 def : Pat<(f32 (int_arm64_neon_fminv (v2f32 V64:$Rn))),
3002 (FMINPv2i32p V64:$Rn)>;
3003 def : Pat<(f64 (int_arm64_neon_fminv (v2f64 V128:$Rn))),
3004 (FMINPv2i64p V128:$Rn)>;
3006 //----------------------------------------------------------------------------
3007 // AdvSIMD INS/DUP instructions
3008 //----------------------------------------------------------------------------
3010 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3011 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3012 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3013 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3014 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3015 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3016 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3018 def DUPv2i64lane : SIMDDup64FromElement;
3019 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3020 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3021 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3022 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3023 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3024 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3026 def : Pat<(v2f32 (ARM64dup (f32 FPR32:$Rn))),
3027 (v2f32 (DUPv2i32lane
3028 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3030 def : Pat<(v4f32 (ARM64dup (f32 FPR32:$Rn))),
3031 (v4f32 (DUPv4i32lane
3032 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3034 def : Pat<(v2f64 (ARM64dup (f64 FPR64:$Rn))),
3035 (v2f64 (DUPv2i64lane
3036 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3039 def : Pat<(v2f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3040 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3041 def : Pat<(v4f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3042 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3043 def : Pat<(v2f64 (ARM64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3044 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3046 // If there's an (ARM64dup (vector_extract ...) ...), we can use a duplane
3047 // instruction even if the types don't match: we just have to remap the lane
3048 // carefully. N.b. this trick only applies to truncations.
3049 def VecIndex_x2 : SDNodeXForm<imm, [{
3050 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3052 def VecIndex_x4 : SDNodeXForm<imm, [{
3053 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3055 def VecIndex_x8 : SDNodeXForm<imm, [{
3056 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3059 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3060 ValueType Src128VT, ValueType ScalVT,
3061 Instruction DUP, SDNodeXForm IdxXFORM> {
3062 def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3064 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3066 def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3068 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3071 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3072 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3073 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3075 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3076 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3077 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3079 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3080 SDNodeXForm IdxXFORM> {
3081 def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3083 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3085 def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3087 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3090 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3091 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3092 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3094 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3095 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3096 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3098 // SMOV and UMOV definitions, with some extra patterns for convenience
3102 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3103 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3104 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3105 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3106 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3107 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3108 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3109 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3110 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3111 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3112 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3113 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3115 // Extracting i8 or i16 elements will have the zero-extend transformed to
3116 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3117 // for ARM64. Match these patterns here since UMOV already zeroes out the high
3118 // bits of the destination register.
3119 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3121 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3122 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3124 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3128 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3129 (SUBREG_TO_REG (i32 0),
3130 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3131 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3132 (SUBREG_TO_REG (i32 0),
3133 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3135 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3136 (SUBREG_TO_REG (i32 0),
3137 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3138 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3139 (SUBREG_TO_REG (i32 0),
3140 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3142 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3143 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3144 (i32 FPR32:$Rn), ssub))>;
3145 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3146 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3147 (i32 FPR32:$Rn), ssub))>;
3148 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3149 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3150 (i64 FPR64:$Rn), dsub))>;
3152 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3153 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3154 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3155 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3156 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3157 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3159 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3160 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3163 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3165 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3168 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3169 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3171 V128:$Rn, VectorIndexS:$imm,
3172 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3174 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3175 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3177 V128:$Rn, VectorIndexD:$imm,
3178 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3181 // Copy an element at a constant index in one vector into a constant indexed
3182 // element of another.
3183 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3184 // index type and INS extension
3185 def : Pat<(v16i8 (int_arm64_neon_vcopy_lane
3186 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3187 VectorIndexB:$idx2)),
3189 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3191 def : Pat<(v8i16 (int_arm64_neon_vcopy_lane
3192 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3193 VectorIndexH:$idx2)),
3195 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3197 def : Pat<(v4i32 (int_arm64_neon_vcopy_lane
3198 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3199 VectorIndexS:$idx2)),
3201 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3203 def : Pat<(v2i64 (int_arm64_neon_vcopy_lane
3204 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3205 VectorIndexD:$idx2)),
3207 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3210 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3211 ValueType VTScal, Instruction INS> {
3212 def : Pat<(VT128 (vector_insert V128:$src,
3213 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3215 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3217 def : Pat<(VT128 (vector_insert V128:$src,
3218 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3220 (INS V128:$src, imm:$Immd,
3221 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3223 def : Pat<(VT64 (vector_insert V64:$src,
3224 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3226 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3227 imm:$Immd, V128:$Rn, imm:$Immn),
3230 def : Pat<(VT64 (vector_insert V64:$src,
3231 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3234 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3235 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3239 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3240 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3241 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3242 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3243 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3244 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3247 // Floating point vector extractions are codegen'd as either a sequence of
3248 // subregister extractions, possibly fed by an INS if the lane number is
3249 // anything other than zero.
3250 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3251 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3252 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3253 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3254 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3255 (f64 (EXTRACT_SUBREG
3256 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3257 V128:$Rn, VectorIndexD:$idx),
3259 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3260 (f32 (EXTRACT_SUBREG
3261 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3262 V128:$Rn, VectorIndexS:$idx),
3265 // All concat_vectors operations are canonicalised to act on i64 vectors for
3266 // ARM64. In the general case we need an instruction, which had just as well be
3268 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3269 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3270 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3271 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3273 def : ConcatPat<v2i64, v1i64>;
3274 def : ConcatPat<v2f64, v1f64>;
3275 def : ConcatPat<v4i32, v2i32>;
3276 def : ConcatPat<v4f32, v2f32>;
3277 def : ConcatPat<v8i16, v4i16>;
3278 def : ConcatPat<v16i8, v8i8>;
3280 // If the high lanes are undef, though, we can just ignore them:
3281 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3282 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3283 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3285 def : ConcatUndefPat<v2i64, v1i64>;
3286 def : ConcatUndefPat<v2f64, v1f64>;
3287 def : ConcatUndefPat<v4i32, v2i32>;
3288 def : ConcatUndefPat<v4f32, v2f32>;
3289 def : ConcatUndefPat<v8i16, v4i16>;
3290 def : ConcatUndefPat<v16i8, v8i8>;
3292 //----------------------------------------------------------------------------
3293 // AdvSIMD across lanes instructions
3294 //----------------------------------------------------------------------------
3296 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3297 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3298 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3299 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3300 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3301 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3302 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3303 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_arm64_neon_fmaxnmv>;
3304 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_arm64_neon_fmaxv>;
3305 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_arm64_neon_fminnmv>;
3306 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_arm64_neon_fminv>;
3308 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3309 // If there is a sign extension after this intrinsic, consume it as smov already
3311 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3313 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3314 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3316 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3318 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3319 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3321 // If there is a sign extension after this intrinsic, consume it as smov already
3323 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3325 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3326 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3328 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3330 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3331 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3333 // If there is a sign extension after this intrinsic, consume it as smov already
3335 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3337 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3338 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3340 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3342 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3343 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3345 // If there is a sign extension after this intrinsic, consume it as smov already
3347 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3349 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3350 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3352 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3354 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3355 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3358 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3359 (i32 (EXTRACT_SUBREG
3360 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3361 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3365 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3366 // If there is a masking operation keeping only what has been actually
3367 // generated, consume it.
3368 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3369 (i32 (EXTRACT_SUBREG
3370 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3371 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3373 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3374 (i32 (EXTRACT_SUBREG
3375 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3376 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3378 // If there is a masking operation keeping only what has been actually
3379 // generated, consume it.
3380 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3381 (i32 (EXTRACT_SUBREG
3382 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3383 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3385 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3386 (i32 (EXTRACT_SUBREG
3387 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3388 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3391 // If there is a masking operation keeping only what has been actually
3392 // generated, consume it.
3393 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3394 (i32 (EXTRACT_SUBREG
3395 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3396 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3398 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3399 (i32 (EXTRACT_SUBREG
3400 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3401 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3403 // If there is a masking operation keeping only what has been actually
3404 // generated, consume it.
3405 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3406 (i32 (EXTRACT_SUBREG
3407 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3408 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3410 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3411 (i32 (EXTRACT_SUBREG
3412 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3413 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3416 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3417 (i32 (EXTRACT_SUBREG
3418 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3419 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3424 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3425 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3427 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3428 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3430 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3432 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3433 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3436 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3437 (i32 (EXTRACT_SUBREG
3438 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3439 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3441 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3442 (i32 (EXTRACT_SUBREG
3443 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3444 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3447 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3448 (i64 (EXTRACT_SUBREG
3449 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3450 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3454 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3456 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3457 (i32 (EXTRACT_SUBREG
3458 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3459 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3461 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3462 (i32 (EXTRACT_SUBREG
3463 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3464 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3467 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3468 (i32 (EXTRACT_SUBREG
3469 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3470 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3472 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3473 (i32 (EXTRACT_SUBREG
3474 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3475 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3478 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3479 (i64 (EXTRACT_SUBREG
3480 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3481 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3485 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_arm64_neon_saddv>;
3486 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3487 def : Pat<(i32 (int_arm64_neon_saddv (v2i32 V64:$Rn))),
3488 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3490 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_arm64_neon_uaddv>;
3491 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3492 def : Pat<(i32 (int_arm64_neon_uaddv (v2i32 V64:$Rn))),
3493 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3495 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_arm64_neon_smaxv>;
3496 def : Pat<(i32 (int_arm64_neon_smaxv (v2i32 V64:$Rn))),
3497 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3499 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_arm64_neon_sminv>;
3500 def : Pat<(i32 (int_arm64_neon_sminv (v2i32 V64:$Rn))),
3501 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3503 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_arm64_neon_umaxv>;
3504 def : Pat<(i32 (int_arm64_neon_umaxv (v2i32 V64:$Rn))),
3505 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3507 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_arm64_neon_uminv>;
3508 def : Pat<(i32 (int_arm64_neon_uminv (v2i32 V64:$Rn))),
3509 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3511 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_arm64_neon_saddlv>;
3512 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_arm64_neon_uaddlv>;
3514 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3515 def : Pat<(i64 (int_arm64_neon_saddlv (v2i32 V64:$Rn))),
3516 (i64 (EXTRACT_SUBREG
3517 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3518 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3520 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3521 def : Pat<(i64 (int_arm64_neon_uaddlv (v2i32 V64:$Rn))),
3522 (i64 (EXTRACT_SUBREG
3523 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3524 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3527 //------------------------------------------------------------------------------
3528 // AdvSIMD modified immediate instructions
3529 //------------------------------------------------------------------------------
3532 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", ARM64bici>;
3534 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", ARM64orri>;
3538 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3540 [(set (v2f64 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3541 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3543 [(set (v2f32 V64:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3544 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3546 [(set (v4f32 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3550 // EDIT byte mask: scalar
3551 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3552 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3553 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3554 // The movi_edit node has the immediate value already encoded, so we use
3555 // a plain imm0_255 here.
3556 def : Pat<(f64 (ARM64movi_edit imm0_255:$shift)),
3557 (MOVID imm0_255:$shift)>;
3559 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3560 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3561 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3562 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3564 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3565 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3566 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3567 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3569 // EDIT byte mask: 2d
3571 // The movi_edit node has the immediate value already encoded, so we use
3572 // a plain imm0_255 in the pattern
3573 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3574 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3577 [(set (v2i64 V128:$Rd), (ARM64movi_edit imm0_255:$imm8))]>;
3580 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3581 // Complexity is added to break a tie with a plain MOVI.
3582 let AddedComplexity = 1 in {
3583 def : Pat<(f32 fpimm0),
3584 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3586 def : Pat<(f64 fpimm0),
3587 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3591 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3592 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3593 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3594 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3596 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3597 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3598 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3599 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3601 def : Pat<(v2f64 (ARM64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
3602 def : Pat<(v4f32 (ARM64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
3604 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3605 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3606 def : Pat<(v2i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3607 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
3608 def : Pat<(v4i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3609 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
3610 def : Pat<(v4i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3611 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
3612 def : Pat<(v8i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3613 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
3615 // EDIT per word: 2s & 4s with MSL shifter
3616 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
3617 [(set (v2i32 V64:$Rd),
3618 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3619 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
3620 [(set (v4i32 V128:$Rd),
3621 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3623 // Per byte: 8b & 16b
3624 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
3626 [(set (v8i8 V64:$Rd), (ARM64movi imm0_255:$imm8))]>;
3627 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
3629 [(set (v16i8 V128:$Rd), (ARM64movi imm0_255:$imm8))]>;
3633 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3634 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
3635 def : Pat<(v2i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3636 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
3637 def : Pat<(v4i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3638 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
3639 def : Pat<(v4i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3640 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
3641 def : Pat<(v8i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3642 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
3644 // EDIT per word: 2s & 4s with MSL shifter
3645 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
3646 [(set (v2i32 V64:$Rd),
3647 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3648 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
3649 [(set (v4i32 V128:$Rd),
3650 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3652 //----------------------------------------------------------------------------
3653 // AdvSIMD indexed element
3654 //----------------------------------------------------------------------------
3656 let neverHasSideEffects = 1 in {
3657 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
3658 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
3661 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
3662 // instruction expects the addend first, while the intrinsic expects it last.
3664 // On the other hand, there are quite a few valid combinatorial options due to
3665 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
3666 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3667 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
3668 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3669 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
3671 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3672 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
3673 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3674 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
3675 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3676 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
3677 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3678 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
3680 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
3681 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3683 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3684 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3685 VectorIndexS:$idx))),
3686 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3687 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3688 (v2f32 (ARM64duplane32
3689 (v4f32 (insert_subvector undef,
3690 (v2f32 (fneg V64:$Rm)),
3692 VectorIndexS:$idx)))),
3693 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3694 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3695 VectorIndexS:$idx)>;
3696 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3697 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3698 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3699 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3701 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3703 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3704 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3705 VectorIndexS:$idx))),
3706 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
3707 VectorIndexS:$idx)>;
3708 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3709 (v4f32 (ARM64duplane32
3710 (v4f32 (insert_subvector undef,
3711 (v2f32 (fneg V64:$Rm)),
3713 VectorIndexS:$idx)))),
3714 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3715 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3716 VectorIndexS:$idx)>;
3717 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3718 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3719 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3720 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3722 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
3723 // (DUPLANE from 64-bit would be trivial).
3724 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3725 (ARM64duplane64 (v2f64 (fneg V128:$Rm)),
3726 VectorIndexD:$idx))),
3728 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3729 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3730 (ARM64dup (f64 (fneg FPR64Op:$Rm))))),
3731 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
3732 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
3734 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
3735 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3736 (vector_extract (v4f32 (fneg V128:$Rm)),
3737 VectorIndexS:$idx))),
3738 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3739 V128:$Rm, VectorIndexS:$idx)>;
3740 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3741 (vector_extract (v2f32 (fneg V64:$Rm)),
3742 VectorIndexS:$idx))),
3743 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3744 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
3746 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
3747 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
3748 (vector_extract (v2f64 (fneg V128:$Rm)),
3749 VectorIndexS:$idx))),
3750 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
3751 V128:$Rm, VectorIndexS:$idx)>;
3754 defm : FMLSIndexedAfterNegPatterns<
3755 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
3756 defm : FMLSIndexedAfterNegPatterns<
3757 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
3759 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_arm64_neon_fmulx>;
3760 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
3762 def : Pat<(v2f32 (fmul V64:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3763 (FMULv2i32_indexed V64:$Rn,
3764 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3766 def : Pat<(v4f32 (fmul V128:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3767 (FMULv4i32_indexed V128:$Rn,
3768 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3770 def : Pat<(v2f64 (fmul V128:$Rn, (ARM64dup (f64 FPR64:$Rm)))),
3771 (FMULv2i64_indexed V128:$Rn,
3772 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
3775 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_arm64_neon_sqdmulh>;
3776 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_arm64_neon_sqrdmulh>;
3777 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
3778 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
3779 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
3780 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
3781 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
3782 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
3783 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3784 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
3785 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3786 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
3787 int_arm64_neon_smull>;
3788 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
3789 int_arm64_neon_sqadd>;
3790 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
3791 int_arm64_neon_sqsub>;
3792 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_arm64_neon_sqdmull>;
3793 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
3794 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3795 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
3796 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3797 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
3798 int_arm64_neon_umull>;
3800 // A scalar sqdmull with the second operand being a vector lane can be
3801 // handled directly with the indexed instruction encoding.
3802 def : Pat<(int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3803 (vector_extract (v4i32 V128:$Vm),
3804 VectorIndexS:$idx)),
3805 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
3807 //----------------------------------------------------------------------------
3808 // AdvSIMD scalar shift instructions
3809 //----------------------------------------------------------------------------
3810 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
3811 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
3812 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
3813 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
3814 // Codegen patterns for the above. We don't put these directly on the
3815 // instructions because TableGen's type inference can't handle the truth.
3816 // Having the same base pattern for fp <--> int totally freaks it out.
3817 def : Pat<(int_arm64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
3818 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
3819 def : Pat<(int_arm64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
3820 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
3821 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
3822 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3823 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
3824 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3825 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
3827 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3828 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
3830 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3831 def : Pat<(int_arm64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
3832 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3833 def : Pat<(int_arm64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
3834 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3835 def : Pat<(f64 (int_arm64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3836 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3837 def : Pat<(f64 (int_arm64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3838 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3839 def : Pat<(v1f64 (int_arm64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
3841 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3842 def : Pat<(v1f64 (int_arm64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
3844 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3846 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", ARM64vshl>;
3847 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
3848 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
3849 int_arm64_neon_sqrshrn>;
3850 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
3851 int_arm64_neon_sqrshrun>;
3852 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3853 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3854 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
3855 int_arm64_neon_sqshrn>;
3856 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
3857 int_arm64_neon_sqshrun>;
3858 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
3859 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", ARM64srshri>;
3860 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
3861 TriOpFrag<(add node:$LHS,
3862 (ARM64srshri node:$MHS, node:$RHS))>>;
3863 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", ARM64vashr>;
3864 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
3865 TriOpFrag<(add node:$LHS,
3866 (ARM64vashr node:$MHS, node:$RHS))>>;
3867 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
3868 int_arm64_neon_uqrshrn>;
3869 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3870 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
3871 int_arm64_neon_uqshrn>;
3872 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", ARM64urshri>;
3873 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
3874 TriOpFrag<(add node:$LHS,
3875 (ARM64urshri node:$MHS, node:$RHS))>>;
3876 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", ARM64vlshr>;
3877 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
3878 TriOpFrag<(add node:$LHS,
3879 (ARM64vlshr node:$MHS, node:$RHS))>>;
3881 //----------------------------------------------------------------------------
3882 // AdvSIMD vector shift instructions
3883 //----------------------------------------------------------------------------
3884 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_arm64_neon_vcvtfp2fxs>;
3885 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_arm64_neon_vcvtfp2fxu>;
3886 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
3887 int_arm64_neon_vcvtfxs2fp>;
3888 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
3889 int_arm64_neon_rshrn>;
3890 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", ARM64vshl>;
3891 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
3892 BinOpFrag<(trunc (ARM64vashr node:$LHS, node:$RHS))>>;
3893 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_arm64_neon_vsli>;
3894 def : Pat<(v1i64 (int_arm64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3895 (i32 vecshiftL64:$imm))),
3896 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
3897 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
3898 int_arm64_neon_sqrshrn>;
3899 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
3900 int_arm64_neon_sqrshrun>;
3901 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3902 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3903 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
3904 int_arm64_neon_sqshrn>;
3905 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
3906 int_arm64_neon_sqshrun>;
3907 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_arm64_neon_vsri>;
3908 def : Pat<(v1i64 (int_arm64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3909 (i32 vecshiftR64:$imm))),
3910 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
3911 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", ARM64srshri>;
3912 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
3913 TriOpFrag<(add node:$LHS,
3914 (ARM64srshri node:$MHS, node:$RHS))> >;
3915 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
3916 BinOpFrag<(ARM64vshl (sext node:$LHS), node:$RHS)>>;
3918 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", ARM64vashr>;
3919 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
3920 TriOpFrag<(add node:$LHS, (ARM64vashr node:$MHS, node:$RHS))>>;
3921 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
3922 int_arm64_neon_vcvtfxu2fp>;
3923 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
3924 int_arm64_neon_uqrshrn>;
3925 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3926 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
3927 int_arm64_neon_uqshrn>;
3928 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", ARM64urshri>;
3929 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
3930 TriOpFrag<(add node:$LHS,
3931 (ARM64urshri node:$MHS, node:$RHS))> >;
3932 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
3933 BinOpFrag<(ARM64vshl (zext node:$LHS), node:$RHS)>>;
3934 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", ARM64vlshr>;
3935 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
3936 TriOpFrag<(add node:$LHS, (ARM64vlshr node:$MHS, node:$RHS))> >;
3938 // SHRN patterns for when a logical right shift was used instead of arithmetic
3939 // (the immediate guarantees no sign bits actually end up in the result so it
3941 def : Pat<(v8i8 (trunc (ARM64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
3942 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
3943 def : Pat<(v4i16 (trunc (ARM64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
3944 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
3945 def : Pat<(v2i32 (trunc (ARM64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
3946 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
3948 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
3949 (trunc (ARM64vlshr (v8i16 V128:$Rn),
3950 vecshiftR16Narrow:$imm)))),
3951 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3952 V128:$Rn, vecshiftR16Narrow:$imm)>;
3953 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
3954 (trunc (ARM64vlshr (v4i32 V128:$Rn),
3955 vecshiftR32Narrow:$imm)))),
3956 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3957 V128:$Rn, vecshiftR32Narrow:$imm)>;
3958 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
3959 (trunc (ARM64vlshr (v2i64 V128:$Rn),
3960 vecshiftR64Narrow:$imm)))),
3961 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3962 V128:$Rn, vecshiftR32Narrow:$imm)>;
3964 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
3965 // Anyexts are implemented as zexts.
3966 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
3967 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
3968 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
3969 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
3970 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
3971 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
3972 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
3973 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
3974 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
3975 // Also match an extend from the upper half of a 128 bit source register.
3976 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3977 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
3978 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3979 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
3980 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3981 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
3982 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3983 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
3984 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3985 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
3986 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3987 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
3988 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3989 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
3990 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3991 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
3992 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3993 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
3995 // Vector shift sxtl aliases
3996 def : InstAlias<"sxtl.8h $dst, $src1",
3997 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3998 def : InstAlias<"sxtl $dst.8h, $src1.8b",
3999 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4000 def : InstAlias<"sxtl.4s $dst, $src1",
4001 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4002 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4003 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4004 def : InstAlias<"sxtl.2d $dst, $src1",
4005 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4006 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4007 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4009 // Vector shift sxtl2 aliases
4010 def : InstAlias<"sxtl2.8h $dst, $src1",
4011 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4012 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4013 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4014 def : InstAlias<"sxtl2.4s $dst, $src1",
4015 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4016 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4017 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4018 def : InstAlias<"sxtl2.2d $dst, $src1",
4019 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4020 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4021 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4023 // Vector shift uxtl aliases
4024 def : InstAlias<"uxtl.8h $dst, $src1",
4025 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4026 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4027 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4028 def : InstAlias<"uxtl.4s $dst, $src1",
4029 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4030 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4031 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4032 def : InstAlias<"uxtl.2d $dst, $src1",
4033 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4034 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4035 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4037 // Vector shift uxtl2 aliases
4038 def : InstAlias<"uxtl2.8h $dst, $src1",
4039 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4040 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4041 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4042 def : InstAlias<"uxtl2.4s $dst, $src1",
4043 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4044 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4045 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4046 def : InstAlias<"uxtl2.2d $dst, $src1",
4047 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4048 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4049 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4051 // If an integer is about to be converted to a floating point value,
4052 // just load it on the floating point unit.
4053 // These patterns are more complex because floating point loads do not
4054 // support sign extension.
4055 // The sign extension has to be explicitly added and is only supported for
4056 // one step: byte-to-half, half-to-word, word-to-doubleword.
4057 // SCVTF GPR -> FPR is 9 cycles.
4058 // SCVTF FPR -> FPR is 4 cyclces.
4059 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4060 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4061 // and still being faster.
4062 // However, this is not good for code size.
4063 // 8-bits -> float. 2 sizes step-up.
4064 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 ro_indexed8:$addr)))),
4065 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4070 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4071 (LDRBro ro_indexed8:$addr),
4076 ssub)))>, Requires<[NotForCodeSize]>;
4077 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_indexed8:$addr)))),
4078 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4083 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4084 (LDRBui am_indexed8:$addr),
4089 ssub)))>, Requires<[NotForCodeSize]>;
4090 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_unscaled8:$addr)))),
4091 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4096 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4097 (LDURBi am_unscaled8:$addr),
4102 ssub)))>, Requires<[NotForCodeSize]>;
4103 // 16-bits -> float. 1 size step-up.
4104 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
4105 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4107 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4108 (LDRHro ro_indexed16:$addr),
4111 ssub)))>, Requires<[NotForCodeSize]>;
4112 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
4113 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4115 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4116 (LDRHui am_indexed16:$addr),
4119 ssub)))>, Requires<[NotForCodeSize]>;
4120 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
4121 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4123 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4124 (LDURHi am_unscaled16:$addr),
4127 ssub)))>, Requires<[NotForCodeSize]>;
4128 // 32-bits to 32-bits are handled in target specific dag combine:
4129 // performIntToFpCombine.
4130 // 64-bits integer to 32-bits floating point, not possible with
4131 // SCVTF on floating point registers (both source and destination
4132 // must have the same size).
4134 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4135 // 8-bits -> double. 3 size step-up: give up.
4136 // 16-bits -> double. 2 size step.
4137 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
4138 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4143 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4144 (LDRHro ro_indexed16:$addr),
4149 dsub)))>, Requires<[NotForCodeSize]>;
4150 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
4151 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4156 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4157 (LDRHui am_indexed16:$addr),
4162 dsub)))>, Requires<[NotForCodeSize]>;
4163 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
4164 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4169 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4170 (LDURHi am_unscaled16:$addr),
4175 dsub)))>, Requires<[NotForCodeSize]>;
4176 // 32-bits -> double. 1 size step-up.
4177 def : Pat <(f64 (sint_to_fp (i32 (load ro_indexed32:$addr)))),
4178 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4180 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4181 (LDRSro ro_indexed32:$addr),
4184 dsub)))>, Requires<[NotForCodeSize]>;
4185 def : Pat <(f64 (sint_to_fp (i32 (load am_indexed32:$addr)))),
4186 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4188 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4189 (LDRSui am_indexed32:$addr),
4192 dsub)))>, Requires<[NotForCodeSize]>;
4193 def : Pat <(f64 (sint_to_fp (i32 (load am_unscaled32:$addr)))),
4194 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4196 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4197 (LDURSi am_unscaled32:$addr),
4200 dsub)))>, Requires<[NotForCodeSize]>;
4201 // 64-bits -> double are handled in target specific dag combine:
4202 // performIntToFpCombine.
4205 //----------------------------------------------------------------------------
4206 // AdvSIMD Load-Store Structure
4207 //----------------------------------------------------------------------------
4208 defm LD1 : SIMDLd1Multiple<"ld1">;
4209 defm LD2 : SIMDLd2Multiple<"ld2">;
4210 defm LD3 : SIMDLd3Multiple<"ld3">;
4211 defm LD4 : SIMDLd4Multiple<"ld4">;
4213 defm ST1 : SIMDSt1Multiple<"st1">;
4214 defm ST2 : SIMDSt2Multiple<"st2">;
4215 defm ST3 : SIMDSt3Multiple<"st3">;
4216 defm ST4 : SIMDSt4Multiple<"st4">;
4218 class Ld1Pat<ValueType ty, Instruction INST>
4219 : Pat<(ty (load am_simdnoindex:$vaddr)), (INST am_simdnoindex:$vaddr)>;
4221 def : Ld1Pat<v16i8, LD1Onev16b>;
4222 def : Ld1Pat<v8i16, LD1Onev8h>;
4223 def : Ld1Pat<v4i32, LD1Onev4s>;
4224 def : Ld1Pat<v2i64, LD1Onev2d>;
4225 def : Ld1Pat<v8i8, LD1Onev8b>;
4226 def : Ld1Pat<v4i16, LD1Onev4h>;
4227 def : Ld1Pat<v2i32, LD1Onev2s>;
4228 def : Ld1Pat<v1i64, LD1Onev1d>;
4230 class St1Pat<ValueType ty, Instruction INST>
4231 : Pat<(store ty:$Vt, am_simdnoindex:$vaddr),
4232 (INST ty:$Vt, am_simdnoindex:$vaddr)>;
4234 def : St1Pat<v16i8, ST1Onev16b>;
4235 def : St1Pat<v8i16, ST1Onev8h>;
4236 def : St1Pat<v4i32, ST1Onev4s>;
4237 def : St1Pat<v2i64, ST1Onev2d>;
4238 def : St1Pat<v8i8, ST1Onev8b>;
4239 def : St1Pat<v4i16, ST1Onev4h>;
4240 def : St1Pat<v2i32, ST1Onev2s>;
4241 def : St1Pat<v1i64, ST1Onev1d>;
4247 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4248 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4249 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4250 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4251 let mayLoad = 1, neverHasSideEffects = 1 in {
4252 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4253 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4254 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4255 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4256 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4257 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4258 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4259 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4260 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4261 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4262 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4263 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4264 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4265 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4266 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4267 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4270 def : Pat<(v8i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4271 (LD1Rv8b am_simdnoindex:$vaddr)>;
4272 def : Pat<(v16i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4273 (LD1Rv16b am_simdnoindex:$vaddr)>;
4274 def : Pat<(v4i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4275 (LD1Rv4h am_simdnoindex:$vaddr)>;
4276 def : Pat<(v8i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4277 (LD1Rv8h am_simdnoindex:$vaddr)>;
4278 def : Pat<(v2i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4279 (LD1Rv2s am_simdnoindex:$vaddr)>;
4280 def : Pat<(v4i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4281 (LD1Rv4s am_simdnoindex:$vaddr)>;
4282 def : Pat<(v2i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4283 (LD1Rv2d am_simdnoindex:$vaddr)>;
4284 def : Pat<(v1i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4285 (LD1Rv1d am_simdnoindex:$vaddr)>;
4286 // Grab the floating point version too
4287 def : Pat<(v2f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4288 (LD1Rv2s am_simdnoindex:$vaddr)>;
4289 def : Pat<(v4f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4290 (LD1Rv4s am_simdnoindex:$vaddr)>;
4291 def : Pat<(v2f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4292 (LD1Rv2d am_simdnoindex:$vaddr)>;
4293 def : Pat<(v1f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4294 (LD1Rv1d am_simdnoindex:$vaddr)>;
4296 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4297 ValueType VTy, ValueType STy, Instruction LD1>
4298 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4299 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4300 (LD1 VecListOne128:$Rd, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4302 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4303 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4304 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4305 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4306 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4307 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4309 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4310 ValueType VTy, ValueType STy, Instruction LD1>
4311 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4312 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4314 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4315 VecIndex:$idx, am_simdnoindex:$vaddr),
4318 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4319 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4320 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4321 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4324 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4325 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4326 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4327 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4330 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4331 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4332 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4333 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4335 let AddedComplexity = 8 in
4336 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4337 ValueType VTy, ValueType STy, Instruction ST1>
4339 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4340 am_simdnoindex:$vaddr),
4341 (ST1 VecListOne128:$Vt, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4343 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4344 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4345 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4346 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4347 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4348 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4350 let AddedComplexity = 8 in
4351 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4352 ValueType VTy, ValueType STy, Instruction ST1>
4354 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4355 am_simdnoindex:$vaddr),
4356 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4357 VecIndex:$idx, am_simdnoindex:$vaddr)>;
4359 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4360 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4361 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4362 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4364 let mayStore = 1, neverHasSideEffects = 1 in {
4365 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4366 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4367 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4368 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4369 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4370 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4371 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4372 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4373 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4374 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4375 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4376 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4379 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4380 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4381 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4382 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4384 //----------------------------------------------------------------------------
4385 // Crypto extensions
4386 //----------------------------------------------------------------------------
4388 def AESErr : AESTiedInst<0b0100, "aese", int_arm64_crypto_aese>;
4389 def AESDrr : AESTiedInst<0b0101, "aesd", int_arm64_crypto_aesd>;
4390 def AESMCrr : AESInst< 0b0110, "aesmc", int_arm64_crypto_aesmc>;
4391 def AESIMCrr : AESInst< 0b0111, "aesimc", int_arm64_crypto_aesimc>;
4393 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_arm64_crypto_sha1c>;
4394 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_arm64_crypto_sha1p>;
4395 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_arm64_crypto_sha1m>;
4396 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_arm64_crypto_sha1su0>;
4397 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_arm64_crypto_sha256h>;
4398 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_arm64_crypto_sha256h2>;
4399 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_arm64_crypto_sha256su1>;
4401 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_arm64_crypto_sha1h>;
4402 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_arm64_crypto_sha1su1>;
4403 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_arm64_crypto_sha256su0>;
4405 //----------------------------------------------------------------------------
4407 //----------------------------------------------------------------------------
4408 // FIXME: Like for X86, these should go in their own separate .td file.
4410 // Any instruction that defines a 32-bit result leaves the high half of the
4411 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4412 // be copying from a truncate. But any other 32-bit operation will zero-extend
4414 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4415 def def32 : PatLeaf<(i32 GPR32:$src), [{
4416 return N->getOpcode() != ISD::TRUNCATE &&
4417 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4418 N->getOpcode() != ISD::CopyFromReg;
4421 // In the case of a 32-bit def that is known to implicitly zero-extend,
4422 // we can use a SUBREG_TO_REG.
4423 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4425 // For an anyext, we don't care what the high bits are, so we can perform an
4426 // INSERT_SUBREF into an IMPLICIT_DEF.
4427 def : Pat<(i64 (anyext GPR32:$src)),
4428 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4430 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4431 // instruction (UBFM) on the enclosing super-reg.
4432 def : Pat<(i64 (zext GPR32:$src)),
4433 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4435 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4436 // containing super-reg.
4437 def : Pat<(i64 (sext GPR32:$src)),
4438 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4439 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4440 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4441 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4442 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4443 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4444 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4445 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4447 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4448 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4449 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4450 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4451 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4452 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4454 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4455 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4456 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4457 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4458 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4459 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4461 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4462 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4463 (i64 (i64shift_a imm0_63:$imm)),
4464 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4466 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4467 // AddedComplexity for the following patterns since we want to match sext + sra
4468 // patterns before we attempt to match a single sra node.
4469 let AddedComplexity = 20 in {
4470 // We support all sext + sra combinations which preserve at least one bit of the
4471 // original value which is to be sign extended. E.g. we support shifts up to
4473 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4474 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4475 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4476 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4478 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4479 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4480 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4481 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4483 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4484 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4485 (i64 imm0_31:$imm), 31)>;
4486 } // AddedComplexity = 20
4488 // To truncate, we can simply extract from a subregister.
4489 def : Pat<(i32 (trunc GPR64sp:$src)),
4490 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4492 // __builtin_trap() uses the BRK instruction on ARM64.
4493 def : Pat<(trap), (BRK 1)>;
4495 // Conversions within AdvSIMD types in the same register size are free.
4497 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
4498 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
4499 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
4500 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4501 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
4502 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4504 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
4505 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
4506 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
4507 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4508 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
4509 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4511 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
4512 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
4513 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
4514 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4515 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
4516 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4518 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
4519 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
4520 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
4521 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4522 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
4523 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4525 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
4526 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
4527 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
4528 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
4529 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
4530 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
4532 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
4533 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
4534 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
4535 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
4536 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
4537 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
4539 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4540 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
4541 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
4542 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
4543 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
4544 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4547 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
4548 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
4549 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
4550 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
4551 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
4553 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
4554 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
4555 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
4556 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
4557 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
4558 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
4560 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
4561 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
4562 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
4563 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
4564 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
4565 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
4567 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
4568 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
4569 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
4570 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
4571 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
4572 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
4574 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
4575 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
4576 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
4577 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
4578 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
4579 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
4581 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
4582 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
4583 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
4584 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
4585 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
4586 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
4588 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
4589 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
4590 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
4591 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
4592 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
4593 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
4595 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
4596 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4597 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
4598 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4599 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
4600 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4601 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
4602 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4604 // A 64-bit subvector insert to the first 128-bit vector position
4605 // is a subregister copy that needs no instruction.
4606 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
4607 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4608 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
4609 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4610 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
4611 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4612 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
4613 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4614 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
4615 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4616 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
4617 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4619 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
4621 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
4622 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
4623 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
4624 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
4625 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
4626 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
4627 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
4628 // so we match on v4f32 here, not v2f32. This will also catch adding
4629 // the low two lanes of a true v4f32 vector.
4630 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
4631 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
4632 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
4634 // Scalar 64-bit shifts in FPR64 registers.
4635 def : Pat<(i64 (int_arm64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4636 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4637 def : Pat<(i64 (int_arm64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4638 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4639 def : Pat<(i64 (int_arm64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4640 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4641 def : Pat<(i64 (int_arm64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4642 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4644 // Tail call return handling. These are all compiler pseudo-instructions,
4645 // so no encoding information or anything like that.
4646 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
4647 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst), []>;
4648 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst), []>;
4651 def : Pat<(ARM64tcret tcGPR64:$dst), (TCRETURNri tcGPR64:$dst)>;
4652 def : Pat<(ARM64tcret (i64 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4653 def : Pat<(ARM64tcret (i64 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4655 include "ARM64InstrAtomics.td"