1 //===- ARM64InstrInfo.td - Describe the ARM64 Instructions -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // ARM64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
24 //===----------------------------------------------------------------------===//
25 // ARM64-specific DAG Nodes.
28 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
29 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
32 SDTCisInt<0>, SDTCisVT<1, i32>]>;
34 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
35 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
41 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
42 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
49 def SDT_ARM64Brcond : SDTypeProfile<0, 3,
50 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
52 def SDT_ARM64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
53 def SDT_ARM64tbz : SDTypeProfile<0, 3, [SDTCisVT<0, i64>, SDTCisVT<1, i64>,
54 SDTCisVT<2, OtherVT>]>;
57 def SDT_ARM64CSel : SDTypeProfile<1, 4,
62 def SDT_ARM64FCmp : SDTypeProfile<0, 2,
65 def SDT_ARM64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
66 def SDT_ARM64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
67 def SDT_ARM64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
70 def SDT_ARM64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
71 def SDT_ARM64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
72 def SDT_ARM64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
73 SDTCisInt<2>, SDTCisInt<3>]>;
74 def SDT_ARM64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
75 def SDT_ARM64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
76 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
77 def SDT_ARM64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
79 def SDT_ARM64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
80 def SDT_ARM64fcmpz : SDTypeProfile<1, 1, []>;
81 def SDT_ARM64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
82 def SDT_ARM64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
84 def SDT_ARM64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
87 def SDT_ARM64TCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
88 def SDT_ARM64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
90 def SDT_ARM64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
92 def SDT_ARM64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
94 def SDT_ARM64WrapperLarge : SDTypeProfile<1, 4,
95 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
96 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
101 def ARM64adrp : SDNode<"ARM64ISD::ADRP", SDTIntUnaryOp, []>;
102 def ARM64addlow : SDNode<"ARM64ISD::ADDlow", SDTIntBinOp, []>;
103 def ARM64LOADgot : SDNode<"ARM64ISD::LOADgot", SDTIntUnaryOp>;
104 def ARM64callseq_start : SDNode<"ISD::CALLSEQ_START",
105 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
106 [SDNPHasChain, SDNPOutGlue]>;
107 def ARM64callseq_end : SDNode<"ISD::CALLSEQ_END",
108 SDCallSeqEnd<[ SDTCisVT<0, i32>,
110 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
111 def ARM64call : SDNode<"ARM64ISD::CALL",
112 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
113 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
115 def ARM64brcond : SDNode<"ARM64ISD::BRCOND", SDT_ARM64Brcond,
117 def ARM64cbz : SDNode<"ARM64ISD::CBZ", SDT_ARM64cbz,
119 def ARM64cbnz : SDNode<"ARM64ISD::CBNZ", SDT_ARM64cbz,
121 def ARM64tbz : SDNode<"ARM64ISD::TBZ", SDT_ARM64tbz,
123 def ARM64tbnz : SDNode<"ARM64ISD::TBNZ", SDT_ARM64tbz,
127 def ARM64csel : SDNode<"ARM64ISD::CSEL", SDT_ARM64CSel>;
128 def ARM64csinv : SDNode<"ARM64ISD::CSINV", SDT_ARM64CSel>;
129 def ARM64csneg : SDNode<"ARM64ISD::CSNEG", SDT_ARM64CSel>;
130 def ARM64csinc : SDNode<"ARM64ISD::CSINC", SDT_ARM64CSel>;
131 def ARM64retflag : SDNode<"ARM64ISD::RET_FLAG", SDTNone,
132 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
133 def ARM64adc : SDNode<"ARM64ISD::ADC", SDTBinaryArithWithFlagsIn >;
134 def ARM64sbc : SDNode<"ARM64ISD::SBC", SDTBinaryArithWithFlagsIn>;
135 def ARM64add_flag : SDNode<"ARM64ISD::ADDS", SDTBinaryArithWithFlagsOut,
137 def ARM64sub_flag : SDNode<"ARM64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
138 def ARM64and_flag : SDNode<"ARM64ISD::ANDS", SDTBinaryArithWithFlagsOut,
140 def ARM64adc_flag : SDNode<"ARM64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
141 def ARM64sbc_flag : SDNode<"ARM64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
143 def ARM64threadpointer : SDNode<"ARM64ISD::THREAD_POINTER", SDTPtrLeaf>;
145 def ARM64fcmp : SDNode<"ARM64ISD::FCMP", SDT_ARM64FCmp>;
147 def ARM64fmax : SDNode<"ARM64ISD::FMAX", SDTFPBinOp>;
148 def ARM64fmin : SDNode<"ARM64ISD::FMIN", SDTFPBinOp>;
150 def ARM64dup : SDNode<"ARM64ISD::DUP", SDT_ARM64Dup>;
151 def ARM64duplane8 : SDNode<"ARM64ISD::DUPLANE8", SDT_ARM64DupLane>;
152 def ARM64duplane16 : SDNode<"ARM64ISD::DUPLANE16", SDT_ARM64DupLane>;
153 def ARM64duplane32 : SDNode<"ARM64ISD::DUPLANE32", SDT_ARM64DupLane>;
154 def ARM64duplane64 : SDNode<"ARM64ISD::DUPLANE64", SDT_ARM64DupLane>;
156 def ARM64zip1 : SDNode<"ARM64ISD::ZIP1", SDT_ARM64Zip>;
157 def ARM64zip2 : SDNode<"ARM64ISD::ZIP2", SDT_ARM64Zip>;
158 def ARM64uzp1 : SDNode<"ARM64ISD::UZP1", SDT_ARM64Zip>;
159 def ARM64uzp2 : SDNode<"ARM64ISD::UZP2", SDT_ARM64Zip>;
160 def ARM64trn1 : SDNode<"ARM64ISD::TRN1", SDT_ARM64Zip>;
161 def ARM64trn2 : SDNode<"ARM64ISD::TRN2", SDT_ARM64Zip>;
163 def ARM64movi_edit : SDNode<"ARM64ISD::MOVIedit", SDT_ARM64MOVIedit>;
164 def ARM64movi_shift : SDNode<"ARM64ISD::MOVIshift", SDT_ARM64MOVIshift>;
165 def ARM64movi_msl : SDNode<"ARM64ISD::MOVImsl", SDT_ARM64MOVIshift>;
166 def ARM64mvni_shift : SDNode<"ARM64ISD::MVNIshift", SDT_ARM64MOVIshift>;
167 def ARM64mvni_msl : SDNode<"ARM64ISD::MVNImsl", SDT_ARM64MOVIshift>;
168 def ARM64movi : SDNode<"ARM64ISD::MOVI", SDT_ARM64MOVIedit>;
169 def ARM64fmov : SDNode<"ARM64ISD::FMOV", SDT_ARM64MOVIedit>;
171 def ARM64rev16 : SDNode<"ARM64ISD::REV16", SDT_ARM64UnaryVec>;
172 def ARM64rev32 : SDNode<"ARM64ISD::REV32", SDT_ARM64UnaryVec>;
173 def ARM64rev64 : SDNode<"ARM64ISD::REV64", SDT_ARM64UnaryVec>;
174 def ARM64ext : SDNode<"ARM64ISD::EXT", SDT_ARM64ExtVec>;
176 def ARM64vashr : SDNode<"ARM64ISD::VASHR", SDT_ARM64vshift>;
177 def ARM64vlshr : SDNode<"ARM64ISD::VLSHR", SDT_ARM64vshift>;
178 def ARM64vshl : SDNode<"ARM64ISD::VSHL", SDT_ARM64vshift>;
179 def ARM64sqshli : SDNode<"ARM64ISD::SQSHL_I", SDT_ARM64vshift>;
180 def ARM64uqshli : SDNode<"ARM64ISD::UQSHL_I", SDT_ARM64vshift>;
181 def ARM64sqshlui : SDNode<"ARM64ISD::SQSHLU_I", SDT_ARM64vshift>;
182 def ARM64srshri : SDNode<"ARM64ISD::SRSHR_I", SDT_ARM64vshift>;
183 def ARM64urshri : SDNode<"ARM64ISD::URSHR_I", SDT_ARM64vshift>;
185 def ARM64not: SDNode<"ARM64ISD::NOT", SDT_ARM64unvec>;
186 def ARM64bit: SDNode<"ARM64ISD::BIT", SDT_ARM64trivec>;
187 def ARM64bsl: SDNode<"ARM64ISD::BSL", SDT_ARM64trivec>;
189 def ARM64cmeq: SDNode<"ARM64ISD::CMEQ", SDT_ARM64binvec>;
190 def ARM64cmge: SDNode<"ARM64ISD::CMGE", SDT_ARM64binvec>;
191 def ARM64cmgt: SDNode<"ARM64ISD::CMGT", SDT_ARM64binvec>;
192 def ARM64cmhi: SDNode<"ARM64ISD::CMHI", SDT_ARM64binvec>;
193 def ARM64cmhs: SDNode<"ARM64ISD::CMHS", SDT_ARM64binvec>;
195 def ARM64fcmeq: SDNode<"ARM64ISD::FCMEQ", SDT_ARM64fcmp>;
196 def ARM64fcmge: SDNode<"ARM64ISD::FCMGE", SDT_ARM64fcmp>;
197 def ARM64fcmgt: SDNode<"ARM64ISD::FCMGT", SDT_ARM64fcmp>;
199 def ARM64cmeqz: SDNode<"ARM64ISD::CMEQz", SDT_ARM64unvec>;
200 def ARM64cmgez: SDNode<"ARM64ISD::CMGEz", SDT_ARM64unvec>;
201 def ARM64cmgtz: SDNode<"ARM64ISD::CMGTz", SDT_ARM64unvec>;
202 def ARM64cmlez: SDNode<"ARM64ISD::CMLEz", SDT_ARM64unvec>;
203 def ARM64cmltz: SDNode<"ARM64ISD::CMLTz", SDT_ARM64unvec>;
204 def ARM64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
205 (ARM64not (ARM64cmeqz (and node:$LHS, node:$RHS)))>;
207 def ARM64fcmeqz: SDNode<"ARM64ISD::FCMEQz", SDT_ARM64fcmpz>;
208 def ARM64fcmgez: SDNode<"ARM64ISD::FCMGEz", SDT_ARM64fcmpz>;
209 def ARM64fcmgtz: SDNode<"ARM64ISD::FCMGTz", SDT_ARM64fcmpz>;
210 def ARM64fcmlez: SDNode<"ARM64ISD::FCMLEz", SDT_ARM64fcmpz>;
211 def ARM64fcmltz: SDNode<"ARM64ISD::FCMLTz", SDT_ARM64fcmpz>;
213 def ARM64bici: SDNode<"ARM64ISD::BICi", SDT_ARM64vecimm>;
214 def ARM64orri: SDNode<"ARM64ISD::ORRi", SDT_ARM64vecimm>;
216 def ARM64neg : SDNode<"ARM64ISD::NEG", SDT_ARM64unvec>;
218 def ARM64tcret: SDNode<"ARM64ISD::TC_RETURN", SDT_ARM64TCRET,
219 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
221 def ARM64Prefetch : SDNode<"ARM64ISD::PREFETCH", SDT_ARM64PREFETCH,
222 [SDNPHasChain, SDNPSideEffect]>;
224 def ARM64sitof: SDNode<"ARM64ISD::SITOF", SDT_ARM64ITOF>;
225 def ARM64uitof: SDNode<"ARM64ISD::UITOF", SDT_ARM64ITOF>;
227 def ARM64tlsdesc_call : SDNode<"ARM64ISD::TLSDESC_CALL", SDT_ARM64TLSDescCall,
228 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
231 def ARM64WrapperLarge : SDNode<"ARM64ISD::WrapperLarge", SDT_ARM64WrapperLarge>;
234 //===----------------------------------------------------------------------===//
236 //===----------------------------------------------------------------------===//
238 // ARM64 Instruction Predicate Definitions.
240 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
241 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
242 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
243 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
244 def ForCodeSize : Predicate<"ForCodeSize">;
245 def NotForCodeSize : Predicate<"!ForCodeSize">;
247 include "ARM64InstrFormats.td"
249 //===----------------------------------------------------------------------===//
251 //===----------------------------------------------------------------------===//
252 // Miscellaneous instructions.
253 //===----------------------------------------------------------------------===//
255 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
256 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
257 [(ARM64callseq_start timm:$amt)]>;
258 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
259 [(ARM64callseq_end timm:$amt1, timm:$amt2)]>;
260 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
262 let isReMaterializable = 1, isCodeGenOnly = 1 in {
263 // FIXME: The following pseudo instructions are only needed because remat
264 // cannot handle multiple instructions. When that changes, they can be
265 // removed, along with the ARM64Wrapper node.
267 let AddedComplexity = 10 in
268 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
269 [(set GPR64:$dst, (ARM64LOADgot tglobaladdr:$addr))]>,
272 // The MOVaddr instruction should match only when the add is not folded
273 // into a load or store address.
275 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
276 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaladdr:$hi),
277 tglobaladdr:$low))]>,
278 Sched<[WriteAdrAdr]>;
280 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
281 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tjumptable:$hi),
283 Sched<[WriteAdrAdr]>;
285 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
286 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tconstpool:$hi),
288 Sched<[WriteAdrAdr]>;
290 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
291 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tblockaddress:$hi),
292 tblockaddress:$low))]>,
293 Sched<[WriteAdrAdr]>;
295 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
296 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaltlsaddr:$hi),
297 tglobaltlsaddr:$low))]>,
298 Sched<[WriteAdrAdr]>;
300 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
301 [(set GPR64:$dst, (ARM64addlow (ARM64adrp texternalsym:$hi),
302 texternalsym:$low))]>,
303 Sched<[WriteAdrAdr]>;
305 } // isReMaterializable, isCodeGenOnly
307 def : Pat<(ARM64LOADgot tglobaltlsaddr:$addr),
308 (LOADgot tglobaltlsaddr:$addr)>;
310 def : Pat<(ARM64LOADgot texternalsym:$addr),
311 (LOADgot texternalsym:$addr)>;
313 def : Pat<(ARM64LOADgot tconstpool:$addr),
314 (LOADgot tconstpool:$addr)>;
316 //===----------------------------------------------------------------------===//
317 // System instructions.
318 //===----------------------------------------------------------------------===//
320 def HINT : HintI<"hint">;
321 def : InstAlias<"nop", (HINT 0b000)>;
322 def : InstAlias<"yield",(HINT 0b001)>;
323 def : InstAlias<"wfe", (HINT 0b010)>;
324 def : InstAlias<"wfi", (HINT 0b011)>;
325 def : InstAlias<"sev", (HINT 0b100)>;
326 def : InstAlias<"sevl", (HINT 0b101)>;
328 // As far as LLVM is concerned this writes to the system's exclusive monitors.
329 let mayLoad = 1, mayStore = 1 in
330 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
332 def DMB : CRmSystemI<barrier_op, 0b101, "dmb">;
333 def DSB : CRmSystemI<barrier_op, 0b100, "dsb">;
334 def ISB : CRmSystemI<barrier_op, 0b110, "isb">;
335 def : InstAlias<"clrex", (CLREX 0xf)>;
336 def : InstAlias<"isb", (ISB 0xf)>;
340 def MSRcpsr: MSRcpsrI;
342 // The thread pointer (on Linux, at least, where this has been implemented) is
344 def : Pat<(ARM64threadpointer), (MRS 0xde82)>;
346 // Generic system instructions
347 def SYSxt : SystemXtI<0, "sys">;
348 def SYSLxt : SystemLXtI<1, "sysl">;
350 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
351 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
352 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
354 //===----------------------------------------------------------------------===//
355 // Move immediate instructions.
356 //===----------------------------------------------------------------------===//
358 defm MOVK : InsertImmediate<0b11, "movk">;
359 defm MOVN : MoveImmediate<0b00, "movn">;
361 let PostEncoderMethod = "fixMOVZ" in
362 defm MOVZ : MoveImmediate<0b10, "movz">;
364 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
365 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
366 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
367 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
368 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
369 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
371 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
372 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
373 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
374 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
376 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
377 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
378 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
379 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
381 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g3:$sym, 48)>;
382 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g2:$sym, 32)>;
383 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
384 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
386 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
387 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
388 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
389 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
391 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g2:$sym, 32)>;
392 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
393 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
395 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
396 isAsCheapAsAMove = 1 in {
397 // FIXME: The following pseudo instructions are only needed because remat
398 // cannot handle multiple instructions. When that changes, we can select
399 // directly to the real instructions and get rid of these pseudos.
402 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
403 [(set GPR32:$dst, imm:$src)]>,
406 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
407 [(set GPR64:$dst, imm:$src)]>,
409 } // isReMaterializable, isCodeGenOnly
411 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
412 // eventual expansion code fewer bits to worry about getting right. Marshalling
413 // the types is a little tricky though:
414 def i64imm_32bit : ImmLeaf<i64, [{
415 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
418 def trunc_imm : SDNodeXForm<imm, [{
419 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
422 def : Pat<(i64 i64imm_32bit:$src),
423 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
425 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
427 def : Pat<(ARM64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
428 tglobaladdr:$g1, tglobaladdr:$g0),
429 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
430 tglobaladdr:$g2, 32),
431 tglobaladdr:$g1, 16),
432 tglobaladdr:$g0, 0)>;
434 def : Pat<(ARM64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
435 tblockaddress:$g1, tblockaddress:$g0),
436 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
437 tblockaddress:$g2, 32),
438 tblockaddress:$g1, 16),
439 tblockaddress:$g0, 0)>;
441 def : Pat<(ARM64WrapperLarge tconstpool:$g3, tconstpool:$g2,
442 tconstpool:$g1, tconstpool:$g0),
443 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
448 def : Pat<(ARM64WrapperLarge tjumptable:$g3, tjumptable:$g2,
449 tjumptable:$g1, tjumptable:$g0),
450 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
456 //===----------------------------------------------------------------------===//
457 // Arithmetic instructions.
458 //===----------------------------------------------------------------------===//
460 // Add/subtract with carry.
461 defm ADC : AddSubCarry<0, "adc", "adcs", ARM64adc, ARM64adc_flag>;
462 defm SBC : AddSubCarry<1, "sbc", "sbcs", ARM64sbc, ARM64sbc_flag>;
464 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
465 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
466 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
467 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
470 defm ADD : AddSub<0, "add", add>;
471 defm SUB : AddSub<1, "sub">;
473 defm ADDS : AddSubS<0, "adds", ARM64add_flag>;
474 defm SUBS : AddSubS<1, "subs", ARM64sub_flag>;
476 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
477 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
478 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
479 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
480 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
481 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
482 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
483 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
484 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
485 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
486 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
487 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
488 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
489 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
490 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
491 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
492 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
494 // Because of the immediate format for add/sub-imm instructions, the
495 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
496 // These patterns capture that transformation.
497 let AddedComplexity = 1 in {
498 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
499 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
500 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
501 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
502 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
503 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
504 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
505 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
508 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
509 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
510 def : InstAlias<"neg $dst, $src, $shift",
511 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift:$shift)>;
512 def : InstAlias<"neg $dst, $src, $shift",
513 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift:$shift)>;
515 // Because of the immediate format for add/sub-imm instructions, the
516 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
517 // These patterns capture that transformation.
518 let AddedComplexity = 1 in {
519 def : Pat<(ARM64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
520 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
521 def : Pat<(ARM64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
522 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
523 def : Pat<(ARM64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
524 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
525 def : Pat<(ARM64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
526 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
529 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
530 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
531 def : InstAlias<"negs $dst, $src, $shift",
532 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift:$shift)>;
533 def : InstAlias<"negs $dst, $src, $shift",
534 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift:$shift)>;
536 // Unsigned/Signed divide
537 defm UDIV : Div<0, "udiv", udiv>;
538 defm SDIV : Div<1, "sdiv", sdiv>;
539 let isCodeGenOnly = 1 in {
540 defm UDIV_Int : Div<0, "udiv", int_arm64_udiv>;
541 defm SDIV_Int : Div<1, "sdiv", int_arm64_sdiv>;
545 defm ASRV : Shift<0b10, "asrv", sra>;
546 defm LSLV : Shift<0b00, "lslv", shl>;
547 defm LSRV : Shift<0b01, "lsrv", srl>;
548 defm RORV : Shift<0b11, "rorv", rotr>;
550 def : ShiftAlias<"asr", ASRVWr, GPR32>;
551 def : ShiftAlias<"asr", ASRVXr, GPR64>;
552 def : ShiftAlias<"lsl", LSLVWr, GPR32>;
553 def : ShiftAlias<"lsl", LSLVXr, GPR64>;
554 def : ShiftAlias<"lsr", LSRVWr, GPR32>;
555 def : ShiftAlias<"lsr", LSRVXr, GPR64>;
556 def : ShiftAlias<"ror", RORVWr, GPR32>;
557 def : ShiftAlias<"ror", RORVXr, GPR64>;
560 let AddedComplexity = 7 in {
561 defm MADD : MulAccum<0, "madd", add>;
562 defm MSUB : MulAccum<1, "msub", sub>;
564 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
565 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
566 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
567 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
569 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
570 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
571 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
572 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
573 } // AddedComplexity = 7
575 let AddedComplexity = 5 in {
576 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
577 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
578 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
579 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
581 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
582 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
583 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
584 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
586 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
587 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
588 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
589 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
590 } // AddedComplexity = 5
592 def : MulAccumWAlias<"mul", MADDWrrr>;
593 def : MulAccumXAlias<"mul", MADDXrrr>;
594 def : MulAccumWAlias<"mneg", MSUBWrrr>;
595 def : MulAccumXAlias<"mneg", MSUBXrrr>;
596 def : WideMulAccumAlias<"smull", SMADDLrrr>;
597 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
598 def : WideMulAccumAlias<"umull", UMADDLrrr>;
599 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
602 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
603 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
606 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_arm64_crc32b, "crc32b">;
607 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_arm64_crc32h, "crc32h">;
608 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_arm64_crc32w, "crc32w">;
609 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_arm64_crc32x, "crc32x">;
611 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_arm64_crc32cb, "crc32cb">;
612 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_arm64_crc32ch, "crc32ch">;
613 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_arm64_crc32cw, "crc32cw">;
614 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_arm64_crc32cx, "crc32cx">;
617 //===----------------------------------------------------------------------===//
618 // Logical instructions.
619 //===----------------------------------------------------------------------===//
622 defm ANDS : LogicalImmS<0b11, "ands", ARM64and_flag>;
623 defm AND : LogicalImm<0b00, "and", and>;
624 defm EOR : LogicalImm<0b10, "eor", xor>;
625 defm ORR : LogicalImm<0b01, "orr", or>;
627 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
628 logical_imm32:$imm)>;
629 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
630 logical_imm64:$imm)>;
634 defm ANDS : LogicalRegS<0b11, 0, "ands", ARM64and_flag>;
635 defm BICS : LogicalRegS<0b11, 1, "bics",
636 BinOpFrag<(ARM64and_flag node:$LHS, (not node:$RHS))>>;
637 defm AND : LogicalReg<0b00, 0, "and", and>;
638 defm BIC : LogicalReg<0b00, 1, "bic",
639 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
640 defm EON : LogicalReg<0b10, 1, "eon",
641 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
642 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
643 defm ORN : LogicalReg<0b01, 1, "orn",
644 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
645 defm ORR : LogicalReg<0b01, 0, "orr", or>;
647 def : InstAlias<"tst $src1, $src2",
648 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
649 def : InstAlias<"tst $src1, $src2",
650 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>;
652 def : InstAlias<"tst $src1, $src2",
653 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>;
654 def : InstAlias<"tst $src1, $src2",
655 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>;
657 def : InstAlias<"tst $src1, $src2, $sh",
658 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift:$sh)>;
659 def : InstAlias<"tst $src1, $src2, $sh",
660 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift:$sh)>;
662 def : InstAlias<"mvn $Wd, $Wm",
663 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0)>;
664 def : InstAlias<"mvn $Xd, $Xm",
665 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>;
667 def : InstAlias<"mvn $Wd, $Wm, $sh",
668 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift:$sh)>;
669 def : InstAlias<"mvn $Xd, $Xm, $sh",
670 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift:$sh)>;
672 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
673 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
676 //===----------------------------------------------------------------------===//
677 // One operand data processing instructions.
678 //===----------------------------------------------------------------------===//
680 defm CLS : OneOperandData<0b101, "cls">;
681 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
682 defm RBIT : OneOperandData<0b000, "rbit">;
683 def REV16Wr : OneWRegData<0b001, "rev16",
684 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
685 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
687 def : Pat<(cttz GPR32:$Rn),
688 (CLZWr (RBITWr GPR32:$Rn))>;
689 def : Pat<(cttz GPR64:$Rn),
690 (CLZXr (RBITXr GPR64:$Rn))>;
691 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
694 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
698 // Unlike the other one operand instructions, the instructions with the "rev"
699 // mnemonic do *not* just different in the size bit, but actually use different
700 // opcode bits for the different sizes.
701 def REVWr : OneWRegData<0b010, "rev", bswap>;
702 def REVXr : OneXRegData<0b011, "rev", bswap>;
703 def REV32Xr : OneXRegData<0b010, "rev32",
704 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
706 // The bswap commutes with the rotr so we want a pattern for both possible
708 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
709 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
711 //===----------------------------------------------------------------------===//
712 // Bitfield immediate extraction instruction.
713 //===----------------------------------------------------------------------===//
714 let neverHasSideEffects = 1 in
715 defm EXTR : ExtractImm<"extr">;
716 def : InstAlias<"ror $dst, $src, $shift",
717 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
718 def : InstAlias<"ror $dst, $src, $shift",
719 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
721 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
722 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
723 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
724 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
726 //===----------------------------------------------------------------------===//
727 // Other bitfield immediate instructions.
728 //===----------------------------------------------------------------------===//
729 let neverHasSideEffects = 1 in {
730 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
731 defm SBFM : BitfieldImm<0b00, "sbfm">;
732 defm UBFM : BitfieldImm<0b10, "ubfm">;
735 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
736 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
737 return CurDAG->getTargetConstant(enc, MVT::i64);
740 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
741 uint64_t enc = 31 - N->getZExtValue();
742 return CurDAG->getTargetConstant(enc, MVT::i64);
745 // min(7, 31 - shift_amt)
746 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
747 uint64_t enc = 31 - N->getZExtValue();
748 enc = enc > 7 ? 7 : enc;
749 return CurDAG->getTargetConstant(enc, MVT::i64);
752 // min(15, 31 - shift_amt)
753 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
754 uint64_t enc = 31 - N->getZExtValue();
755 enc = enc > 15 ? 15 : enc;
756 return CurDAG->getTargetConstant(enc, MVT::i64);
759 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
760 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
761 return CurDAG->getTargetConstant(enc, MVT::i64);
764 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
765 uint64_t enc = 63 - N->getZExtValue();
766 return CurDAG->getTargetConstant(enc, MVT::i64);
769 // min(7, 63 - shift_amt)
770 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
771 uint64_t enc = 63 - N->getZExtValue();
772 enc = enc > 7 ? 7 : enc;
773 return CurDAG->getTargetConstant(enc, MVT::i64);
776 // min(15, 63 - shift_amt)
777 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
778 uint64_t enc = 63 - N->getZExtValue();
779 enc = enc > 15 ? 15 : enc;
780 return CurDAG->getTargetConstant(enc, MVT::i64);
783 // min(31, 63 - shift_amt)
784 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
785 uint64_t enc = 63 - N->getZExtValue();
786 enc = enc > 31 ? 31 : enc;
787 return CurDAG->getTargetConstant(enc, MVT::i64);
790 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
791 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
792 (i64 (i32shift_b imm0_31:$imm)))>;
793 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
794 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
795 (i64 (i64shift_b imm0_63:$imm)))>;
797 let AddedComplexity = 10 in {
798 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
799 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
800 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
801 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
804 def : InstAlias<"asr $dst, $src, $shift",
805 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
806 def : InstAlias<"asr $dst, $src, $shift",
807 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
808 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
809 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
810 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
811 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
812 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
814 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
815 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
816 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
817 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
819 def : InstAlias<"lsr $dst, $src, $shift",
820 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
821 def : InstAlias<"lsr $dst, $src, $shift",
822 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
823 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
824 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
825 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
826 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
827 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
829 //===----------------------------------------------------------------------===//
830 // Conditionally set flags instructions.
831 //===----------------------------------------------------------------------===//
832 defm CCMN : CondSetFlagsImm<0, "ccmn">;
833 defm CCMP : CondSetFlagsImm<1, "ccmp">;
835 defm CCMN : CondSetFlagsReg<0, "ccmn">;
836 defm CCMP : CondSetFlagsReg<1, "ccmp">;
838 //===----------------------------------------------------------------------===//
839 // Conditional select instructions.
840 //===----------------------------------------------------------------------===//
841 defm CSEL : CondSelect<0, 0b00, "csel">;
843 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
844 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
845 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
846 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
848 def : Pat<(ARM64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
849 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
850 def : Pat<(ARM64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
851 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
852 def : Pat<(ARM64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
853 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
854 def : Pat<(ARM64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
855 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
856 def : Pat<(ARM64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
857 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
858 def : Pat<(ARM64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
859 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
861 def : Pat<(ARM64csel (i32 0), (i32 1), (i32 imm:$cc), CPSR),
862 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
863 def : Pat<(ARM64csel (i64 0), (i64 1), (i32 imm:$cc), CPSR),
864 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
865 def : Pat<(ARM64csel (i32 0), (i32 -1), (i32 imm:$cc), CPSR),
866 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
867 def : Pat<(ARM64csel (i64 0), (i64 -1), (i32 imm:$cc), CPSR),
868 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
870 // The inverse of the condition code from the alias instruction is what is used
871 // in the aliased instruction. The parser all ready inverts the condition code
872 // for these aliases.
873 // FIXME: Is this the correct way to handle these aliases?
874 def : InstAlias<"cset $dst, $cc", (CSINCWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
875 def : InstAlias<"cset $dst, $cc", (CSINCXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
877 def : InstAlias<"csetm $dst, $cc", (CSINVWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
878 def : InstAlias<"csetm $dst, $cc", (CSINVXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
880 def : InstAlias<"cinc $dst, $src, $cc",
881 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
882 def : InstAlias<"cinc $dst, $src, $cc",
883 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
885 def : InstAlias<"cinv $dst, $src, $cc",
886 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
887 def : InstAlias<"cinv $dst, $src, $cc",
888 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
890 def : InstAlias<"cneg $dst, $src, $cc",
891 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
892 def : InstAlias<"cneg $dst, $src, $cc",
893 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
895 //===----------------------------------------------------------------------===//
896 // PC-relative instructions.
897 //===----------------------------------------------------------------------===//
898 let isReMaterializable = 1 in {
899 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
900 def ADR : ADRI<0, "adr", adrlabel, []>;
901 } // neverHasSideEffects = 1
903 def ADRP : ADRI<1, "adrp", adrplabel,
904 [(set GPR64:$Xd, (ARM64adrp tglobaladdr:$label))]>;
905 } // isReMaterializable = 1
907 // page address of a constant pool entry, block address
908 def : Pat<(ARM64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
909 def : Pat<(ARM64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
911 //===----------------------------------------------------------------------===//
912 // Unconditional branch (register) instructions.
913 //===----------------------------------------------------------------------===//
915 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
916 def RET : BranchReg<0b0010, "ret", []>;
917 def DRPS : SpecialReturn<0b0101, "drps">;
918 def ERET : SpecialReturn<0b0100, "eret">;
919 } // isReturn = 1, isTerminator = 1, isBarrier = 1
921 // Default to the LR register.
922 def : InstAlias<"ret", (RET LR)>;
924 let isCall = 1, Defs = [LR], Uses = [SP] in {
925 def BLR : BranchReg<0b0001, "blr", [(ARM64call GPR64:$Rn)]>;
928 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
929 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
930 } // isBranch, isTerminator, isBarrier, isIndirectBranch
932 // Create a separate pseudo-instruction for codegen to use so that we don't
933 // flag lr as used in every function. It'll be restored before the RET by the
934 // epilogue if it's legitimately used.
935 def RET_ReallyLR : Pseudo<(outs), (ins), [(ARM64retflag)]> {
936 let isTerminator = 1;
941 // This is a directive-like pseudo-instruction. The purpose is to insert an
942 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
943 // (which in the usual case is a BLR).
944 let hasSideEffects = 1 in
945 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
946 let AsmString = ".tlsdesccall $sym";
949 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
950 // gets expanded to two MCInsts during lowering.
951 let isCall = 1, Defs = [LR] in
953 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
954 [(ARM64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
956 def : Pat<(ARM64tlsdesc_call GPR64:$dest, texternalsym:$sym),
957 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
958 //===----------------------------------------------------------------------===//
959 // Conditional branch (immediate) instruction.
960 //===----------------------------------------------------------------------===//
961 def Bcc : BranchCond;
963 //===----------------------------------------------------------------------===//
964 // Compare-and-branch instructions.
965 //===----------------------------------------------------------------------===//
966 defm CBZ : CmpBranch<0, "cbz", ARM64cbz>;
967 defm CBNZ : CmpBranch<1, "cbnz", ARM64cbnz>;
969 //===----------------------------------------------------------------------===//
970 // Test-bit-and-branch instructions.
971 //===----------------------------------------------------------------------===//
972 def TBZ : TestBranch<0, "tbz", ARM64tbz>;
973 def TBNZ : TestBranch<1, "tbnz", ARM64tbnz>;
975 //===----------------------------------------------------------------------===//
976 // Unconditional branch (immediate) instructions.
977 //===----------------------------------------------------------------------===//
978 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
979 def B : BranchImm<0, "b", [(br bb:$addr)]>;
980 } // isBranch, isTerminator, isBarrier
982 let isCall = 1, Defs = [LR], Uses = [SP] in {
983 def BL : CallImm<1, "bl", [(ARM64call tglobaladdr:$addr)]>;
985 def : Pat<(ARM64call texternalsym:$func), (BL texternalsym:$func)>;
987 //===----------------------------------------------------------------------===//
988 // Exception generation instructions.
989 //===----------------------------------------------------------------------===//
990 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
991 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
992 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
993 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
994 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
995 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
996 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
997 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
999 // DCPSn defaults to an immediate operand of zero if unspecified.
1000 def : InstAlias<"dcps1", (DCPS1 0)>;
1001 def : InstAlias<"dcps2", (DCPS2 0)>;
1002 def : InstAlias<"dcps3", (DCPS3 0)>;
1004 //===----------------------------------------------------------------------===//
1005 // Load instructions.
1006 //===----------------------------------------------------------------------===//
1008 // Pair (indexed, offset)
1009 def LDPWi : LoadPairOffset<0b00, 0, GPR32, am_indexed32simm7, "ldp">;
1010 def LDPXi : LoadPairOffset<0b10, 0, GPR64, am_indexed64simm7, "ldp">;
1011 def LDPSi : LoadPairOffset<0b00, 1, FPR32, am_indexed32simm7, "ldp">;
1012 def LDPDi : LoadPairOffset<0b01, 1, FPR64, am_indexed64simm7, "ldp">;
1013 def LDPQi : LoadPairOffset<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
1015 def LDPSWi : LoadPairOffset<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
1017 // Pair (pre-indexed)
1018 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "ldp">;
1019 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "ldp">;
1020 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "ldp">;
1021 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "ldp">;
1022 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "ldp">;
1024 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7_wb, "ldpsw">;
1026 // Pair (post-indexed)
1027 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1028 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1029 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1030 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1031 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1033 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1036 // Pair (no allocate)
1037 def LDNPWi : LoadPairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "ldnp">;
1038 def LDNPXi : LoadPairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "ldnp">;
1039 def LDNPSi : LoadPairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "ldnp">;
1040 def LDNPDi : LoadPairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "ldnp">;
1041 def LDNPQi : LoadPairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "ldnp">;
1044 // (register offset)
1047 let AddedComplexity = 10 in {
1049 def LDRBBro : Load8RO<0b00, 0, 0b01, GPR32, "ldrb",
1050 [(set GPR32:$Rt, (zextloadi8 ro_indexed8:$addr))]>;
1051 def LDRHHro : Load16RO<0b01, 0, 0b01, GPR32, "ldrh",
1052 [(set GPR32:$Rt, (zextloadi16 ro_indexed16:$addr))]>;
1053 def LDRWro : Load32RO<0b10, 0, 0b01, GPR32, "ldr",
1054 [(set GPR32:$Rt, (load ro_indexed32:$addr))]>;
1055 def LDRXro : Load64RO<0b11, 0, 0b01, GPR64, "ldr",
1056 [(set GPR64:$Rt, (load ro_indexed64:$addr))]>;
1059 def LDRBro : Load8RO<0b00, 1, 0b01, FPR8, "ldr",
1060 [(set FPR8:$Rt, (load ro_indexed8:$addr))]>;
1061 def LDRHro : Load16RO<0b01, 1, 0b01, FPR16, "ldr",
1062 [(set (f16 FPR16:$Rt), (load ro_indexed16:$addr))]>;
1063 def LDRSro : Load32RO<0b10, 1, 0b01, FPR32, "ldr",
1064 [(set (f32 FPR32:$Rt), (load ro_indexed32:$addr))]>;
1065 def LDRDro : Load64RO<0b11, 1, 0b01, FPR64, "ldr",
1066 [(set (f64 FPR64:$Rt), (load ro_indexed64:$addr))]>;
1067 def LDRQro : Load128RO<0b00, 1, 0b11, FPR128, "ldr", []> {
1071 // For regular load, we do not have any alignment requirement.
1072 // Thus, it is safe to directly map the vector loads with interesting
1073 // addressing modes.
1074 // FIXME: We could do the same for bitconvert to floating point vectors.
1075 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1076 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1077 (LDRBro ro_indexed8:$addr), bsub)>;
1078 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1079 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1080 (LDRBro ro_indexed8:$addr), bsub)>;
1081 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1082 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1083 (LDRHro ro_indexed16:$addr), hsub)>;
1084 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1085 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1086 (LDRHro ro_indexed16:$addr), hsub)>;
1087 def : Pat <(v2i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1088 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1089 (LDRSro ro_indexed32:$addr), ssub)>;
1090 def : Pat <(v4i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1091 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1092 (LDRSro ro_indexed32:$addr), ssub)>;
1093 def : Pat <(v1i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1094 (LDRDro ro_indexed64:$addr)>;
1095 def : Pat <(v2i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1096 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1097 (LDRDro ro_indexed64:$addr), dsub)>;
1099 // Match all load 64 bits width whose type is compatible with FPR64
1100 def : Pat<(v2f32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1101 def : Pat<(v1f64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1102 def : Pat<(v8i8 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1103 def : Pat<(v4i16 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1104 def : Pat<(v2i32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1105 def : Pat<(v1i64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1107 // Match all load 128 bits width whose type is compatible with FPR128
1108 def : Pat<(v4f32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1109 def : Pat<(v2f64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1110 def : Pat<(v16i8 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1111 def : Pat<(v8i16 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1112 def : Pat<(v4i32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1113 def : Pat<(v2i64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1114 def : Pat<(f128 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1116 // Load sign-extended half-word
1117 def LDRSHWro : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh",
1118 [(set GPR32:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1119 def LDRSHXro : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh",
1120 [(set GPR64:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1122 // Load sign-extended byte
1123 def LDRSBWro : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb",
1124 [(set GPR32:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1125 def LDRSBXro : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb",
1126 [(set GPR64:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1128 // Load sign-extended word
1129 def LDRSWro : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw",
1130 [(set GPR64:$Rt, (sextloadi32 ro_indexed32:$addr))]>;
1133 def PRFMro : PrefetchRO<0b11, 0, 0b10, "prfm",
1134 [(ARM64Prefetch imm:$Rt, ro_indexed64:$addr)]>;
1137 def : Pat<(i64 (zextloadi8 ro_indexed8:$addr)),
1138 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1139 def : Pat<(i64 (zextloadi16 ro_indexed16:$addr)),
1140 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1141 def : Pat<(i64 (zextloadi32 ro_indexed32:$addr)),
1142 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1144 // zextloadi1 -> zextloadi8
1145 def : Pat<(i32 (zextloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1146 def : Pat<(i64 (zextloadi1 ro_indexed8:$addr)),
1147 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1149 // extload -> zextload
1150 def : Pat<(i32 (extloadi16 ro_indexed16:$addr)), (LDRHHro ro_indexed16:$addr)>;
1151 def : Pat<(i32 (extloadi8 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1152 def : Pat<(i32 (extloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1153 def : Pat<(i64 (extloadi32 ro_indexed32:$addr)),
1154 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1155 def : Pat<(i64 (extloadi16 ro_indexed16:$addr)),
1156 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1157 def : Pat<(i64 (extloadi8 ro_indexed8:$addr)),
1158 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1159 def : Pat<(i64 (extloadi1 ro_indexed8:$addr)),
1160 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1162 } // AddedComplexity = 10
1165 // (unsigned immediate)
1167 def LDRXui : LoadUI<0b11, 0, 0b01, GPR64, am_indexed64, "ldr",
1168 [(set GPR64:$Rt, (load am_indexed64:$addr))]>;
1169 def LDRWui : LoadUI<0b10, 0, 0b01, GPR32, am_indexed32, "ldr",
1170 [(set GPR32:$Rt, (load am_indexed32:$addr))]>;
1171 def LDRBui : LoadUI<0b00, 1, 0b01, FPR8, am_indexed8, "ldr",
1172 [(set FPR8:$Rt, (load am_indexed8:$addr))]>;
1173 def LDRHui : LoadUI<0b01, 1, 0b01, FPR16, am_indexed16, "ldr",
1174 [(set (f16 FPR16:$Rt), (load am_indexed16:$addr))]>;
1175 def LDRSui : LoadUI<0b10, 1, 0b01, FPR32, am_indexed32, "ldr",
1176 [(set (f32 FPR32:$Rt), (load am_indexed32:$addr))]>;
1177 def LDRDui : LoadUI<0b11, 1, 0b01, FPR64, am_indexed64, "ldr",
1178 [(set (f64 FPR64:$Rt), (load am_indexed64:$addr))]>;
1179 def LDRQui : LoadUI<0b00, 1, 0b11, FPR128, am_indexed128, "ldr",
1180 [(set (f128 FPR128:$Rt), (load am_indexed128:$addr))]>;
1182 // For regular load, we do not have any alignment requirement.
1183 // Thus, it is safe to directly map the vector loads with interesting
1184 // addressing modes.
1185 // FIXME: We could do the same for bitconvert to floating point vectors.
1186 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1187 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1188 (LDRBui am_indexed8:$addr), bsub)>;
1189 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1190 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1191 (LDRBui am_indexed8:$addr), bsub)>;
1192 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1193 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1194 (LDRHui am_indexed16:$addr), hsub)>;
1195 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1196 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1197 (LDRHui am_indexed16:$addr), hsub)>;
1198 def : Pat <(v2i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1199 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1200 (LDRSui am_indexed32:$addr), ssub)>;
1201 def : Pat <(v4i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1202 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1203 (LDRSui am_indexed32:$addr), ssub)>;
1204 def : Pat <(v1i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1205 (LDRDui am_indexed64:$addr)>;
1206 def : Pat <(v2i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1207 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1208 (LDRDui am_indexed64:$addr), dsub)>;
1210 // Match all load 64 bits width whose type is compatible with FPR64
1211 def : Pat<(v2f32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1212 def : Pat<(v1f64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1213 def : Pat<(v8i8 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1214 def : Pat<(v4i16 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1215 def : Pat<(v2i32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1216 def : Pat<(v1i64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1218 // Match all load 128 bits width whose type is compatible with FPR128
1219 def : Pat<(v4f32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1220 def : Pat<(v2f64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1221 def : Pat<(v16i8 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1222 def : Pat<(v8i16 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1223 def : Pat<(v4i32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1224 def : Pat<(v2i64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1225 def : Pat<(f128 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1227 def LDRHHui : LoadUI<0b01, 0, 0b01, GPR32, am_indexed16, "ldrh",
1228 [(set GPR32:$Rt, (zextloadi16 am_indexed16:$addr))]>;
1229 def LDRBBui : LoadUI<0b00, 0, 0b01, GPR32, am_indexed8, "ldrb",
1230 [(set GPR32:$Rt, (zextloadi8 am_indexed8:$addr))]>;
1232 def : Pat<(i64 (zextloadi8 am_indexed8:$addr)),
1233 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1234 def : Pat<(i64 (zextloadi16 am_indexed16:$addr)),
1235 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1237 // zextloadi1 -> zextloadi8
1238 def : Pat<(i32 (zextloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1239 def : Pat<(i64 (zextloadi1 am_indexed8:$addr)),
1240 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1242 // extload -> zextload
1243 def : Pat<(i32 (extloadi16 am_indexed16:$addr)), (LDRHHui am_indexed16:$addr)>;
1244 def : Pat<(i32 (extloadi8 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1245 def : Pat<(i32 (extloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1246 def : Pat<(i64 (extloadi32 am_indexed32:$addr)),
1247 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1248 def : Pat<(i64 (extloadi16 am_indexed16:$addr)),
1249 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1250 def : Pat<(i64 (extloadi8 am_indexed8:$addr)),
1251 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1252 def : Pat<(i64 (extloadi1 am_indexed8:$addr)),
1253 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1255 // load sign-extended half-word
1256 def LDRSHWui : LoadUI<0b01, 0, 0b11, GPR32, am_indexed16, "ldrsh",
1257 [(set GPR32:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1258 def LDRSHXui : LoadUI<0b01, 0, 0b10, GPR64, am_indexed16, "ldrsh",
1259 [(set GPR64:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1261 // load sign-extended byte
1262 def LDRSBWui : LoadUI<0b00, 0, 0b11, GPR32, am_indexed8, "ldrsb",
1263 [(set GPR32:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1264 def LDRSBXui : LoadUI<0b00, 0, 0b10, GPR64, am_indexed8, "ldrsb",
1265 [(set GPR64:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1267 // load sign-extended word
1268 def LDRSWui : LoadUI<0b10, 0, 0b10, GPR64, am_indexed32, "ldrsw",
1269 [(set GPR64:$Rt, (sextloadi32 am_indexed32:$addr))]>;
1271 // load zero-extended word
1272 def : Pat<(i64 (zextloadi32 am_indexed32:$addr)),
1273 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1276 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1277 [(ARM64Prefetch imm:$Rt, am_indexed64:$addr)]>;
1281 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1282 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1283 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1284 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1285 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1287 // load sign-extended word
1288 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1291 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1292 // [(ARM64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1295 // (unscaled immediate)
1296 def LDURXi : LoadUnscaled<0b11, 0, 0b01, GPR64, am_unscaled64, "ldur",
1297 [(set GPR64:$Rt, (load am_unscaled64:$addr))]>;
1298 def LDURWi : LoadUnscaled<0b10, 0, 0b01, GPR32, am_unscaled32, "ldur",
1299 [(set GPR32:$Rt, (load am_unscaled32:$addr))]>;
1300 def LDURBi : LoadUnscaled<0b00, 1, 0b01, FPR8, am_unscaled8, "ldur",
1301 [(set FPR8:$Rt, (load am_unscaled8:$addr))]>;
1302 def LDURHi : LoadUnscaled<0b01, 1, 0b01, FPR16, am_unscaled16, "ldur",
1303 [(set (f16 FPR16:$Rt), (load am_unscaled16:$addr))]>;
1304 def LDURSi : LoadUnscaled<0b10, 1, 0b01, FPR32, am_unscaled32, "ldur",
1305 [(set (f32 FPR32:$Rt), (load am_unscaled32:$addr))]>;
1306 def LDURDi : LoadUnscaled<0b11, 1, 0b01, FPR64, am_unscaled64, "ldur",
1307 [(set (f64 FPR64:$Rt), (load am_unscaled64:$addr))]>;
1308 def LDURQi : LoadUnscaled<0b00, 1, 0b11, FPR128, am_unscaled128, "ldur",
1309 [(set (v2f64 FPR128:$Rt), (load am_unscaled128:$addr))]>;
1312 : LoadUnscaled<0b01, 0, 0b01, GPR32, am_unscaled16, "ldurh",
1313 [(set GPR32:$Rt, (zextloadi16 am_unscaled16:$addr))]>;
1315 : LoadUnscaled<0b00, 0, 0b01, GPR32, am_unscaled8, "ldurb",
1316 [(set GPR32:$Rt, (zextloadi8 am_unscaled8:$addr))]>;
1318 // Match all load 64 bits width whose type is compatible with FPR64
1319 def : Pat<(v2f32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1320 def : Pat<(v1f64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1321 def : Pat<(v8i8 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1322 def : Pat<(v4i16 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1323 def : Pat<(v2i32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1324 def : Pat<(v1i64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1326 // Match all load 128 bits width whose type is compatible with FPR128
1327 def : Pat<(v4f32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1328 def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1329 def : Pat<(v16i8 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1330 def : Pat<(v8i16 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1331 def : Pat<(v4i32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1332 def : Pat<(v2i64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1333 def : Pat<(f128 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1336 def : Pat<(i32 (extloadi16 am_unscaled16:$addr)), (LDURHHi am_unscaled16:$addr)>;
1337 def : Pat<(i32 (extloadi8 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1338 def : Pat<(i32 (extloadi1 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1339 def : Pat<(i64 (extloadi32 am_unscaled32:$addr)),
1340 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1341 def : Pat<(i64 (extloadi16 am_unscaled16:$addr)),
1342 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1343 def : Pat<(i64 (extloadi8 am_unscaled8:$addr)),
1344 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1345 def : Pat<(i64 (extloadi1 am_unscaled8:$addr)),
1346 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1348 def : Pat<(i32 (zextloadi16 am_unscaled16:$addr)),
1349 (LDURHHi am_unscaled16:$addr)>;
1350 def : Pat<(i32 (zextloadi8 am_unscaled8:$addr)),
1351 (LDURBBi am_unscaled8:$addr)>;
1352 def : Pat<(i32 (zextloadi1 am_unscaled8:$addr)),
1353 (LDURBBi am_unscaled8:$addr)>;
1354 def : Pat<(i64 (zextloadi32 am_unscaled32:$addr)),
1355 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1356 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1357 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1358 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1359 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1360 def : Pat<(i64 (zextloadi1 am_unscaled8:$addr)),
1361 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1365 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1367 // Define new assembler match classes as we want to only match these when
1368 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1369 // associate a DiagnosticType either, as we want the diagnostic for the
1370 // canonical form (the scaled operand) to take precedence.
1371 def MemoryUnscaledFB8Operand : AsmOperandClass {
1372 let Name = "MemoryUnscaledFB8";
1373 let RenderMethod = "addMemoryUnscaledOperands";
1375 def MemoryUnscaledFB16Operand : AsmOperandClass {
1376 let Name = "MemoryUnscaledFB16";
1377 let RenderMethod = "addMemoryUnscaledOperands";
1379 def MemoryUnscaledFB32Operand : AsmOperandClass {
1380 let Name = "MemoryUnscaledFB32";
1381 let RenderMethod = "addMemoryUnscaledOperands";
1383 def MemoryUnscaledFB64Operand : AsmOperandClass {
1384 let Name = "MemoryUnscaledFB64";
1385 let RenderMethod = "addMemoryUnscaledOperands";
1387 def MemoryUnscaledFB128Operand : AsmOperandClass {
1388 let Name = "MemoryUnscaledFB128";
1389 let RenderMethod = "addMemoryUnscaledOperands";
1391 def am_unscaled_fb8 : Operand<i64> {
1392 let ParserMatchClass = MemoryUnscaledFB8Operand;
1393 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1395 def am_unscaled_fb16 : Operand<i64> {
1396 let ParserMatchClass = MemoryUnscaledFB16Operand;
1397 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1399 def am_unscaled_fb32 : Operand<i64> {
1400 let ParserMatchClass = MemoryUnscaledFB32Operand;
1401 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1403 def am_unscaled_fb64 : Operand<i64> {
1404 let ParserMatchClass = MemoryUnscaledFB64Operand;
1405 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1407 def am_unscaled_fb128 : Operand<i64> {
1408 let ParserMatchClass = MemoryUnscaledFB128Operand;
1409 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1411 def : InstAlias<"ldr $Rt, $addr", (LDURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1412 def : InstAlias<"ldr $Rt, $addr", (LDURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1413 def : InstAlias<"ldr $Rt, $addr", (LDURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1414 def : InstAlias<"ldr $Rt, $addr", (LDURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1415 def : InstAlias<"ldr $Rt, $addr", (LDURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1416 def : InstAlias<"ldr $Rt, $addr", (LDURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1417 def : InstAlias<"ldr $Rt, $addr", (LDURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1420 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1421 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1422 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1423 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1425 // load sign-extended half-word
1427 : LoadUnscaled<0b01, 0, 0b11, GPR32, am_unscaled16, "ldursh",
1428 [(set GPR32:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1430 : LoadUnscaled<0b01, 0, 0b10, GPR64, am_unscaled16, "ldursh",
1431 [(set GPR64:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1433 // load sign-extended byte
1435 : LoadUnscaled<0b00, 0, 0b11, GPR32, am_unscaled8, "ldursb",
1436 [(set GPR32:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1438 : LoadUnscaled<0b00, 0, 0b10, GPR64, am_unscaled8, "ldursb",
1439 [(set GPR64:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1441 // load sign-extended word
1443 : LoadUnscaled<0b10, 0, 0b10, GPR64, am_unscaled32, "ldursw",
1444 [(set GPR64:$Rt, (sextloadi32 am_unscaled32:$addr))]>;
1446 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1447 def : InstAlias<"ldrb $Rt, $addr", (LDURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1448 def : InstAlias<"ldrh $Rt, $addr", (LDURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1449 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBWi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1450 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBXi GPR64:$Rt, am_unscaled_fb8:$addr)>;
1451 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHWi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1452 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHXi GPR64:$Rt, am_unscaled_fb16:$addr)>;
1453 def : InstAlias<"ldrsw $Rt, $addr", (LDURSWi GPR64:$Rt, am_unscaled_fb32:$addr)>;
1456 def PRFUMi : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1457 [(ARM64Prefetch imm:$Rt, am_unscaled64:$addr)]>;
1460 // (unscaled immediate, unprivileged)
1461 def LDTRXi : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1462 def LDTRWi : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1464 def LDTRHi : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1465 def LDTRBi : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1467 // load sign-extended half-word
1468 def LDTRSHWi : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1469 def LDTRSHXi : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1471 // load sign-extended byte
1472 def LDTRSBWi : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1473 def LDTRSBXi : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1475 // load sign-extended word
1476 def LDTRSWi : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1479 // (immediate pre-indexed)
1480 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1481 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1482 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1483 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1484 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1485 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1486 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1488 // load sign-extended half-word
1489 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1490 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1492 // load sign-extended byte
1493 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1494 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1496 // load zero-extended byte
1497 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1498 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1500 // load sign-extended word
1501 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1503 // ISel pseudos and patterns. See expanded comment on LoadPreIdxPseudo.
1504 def LDRDpre_isel : LoadPreIdxPseudo<FPR64>;
1505 def LDRSpre_isel : LoadPreIdxPseudo<FPR32>;
1506 def LDRXpre_isel : LoadPreIdxPseudo<GPR64>;
1507 def LDRWpre_isel : LoadPreIdxPseudo<GPR32>;
1508 def LDRHHpre_isel : LoadPreIdxPseudo<GPR32>;
1509 def LDRBBpre_isel : LoadPreIdxPseudo<GPR32>;
1511 def LDRSWpre_isel : LoadPreIdxPseudo<GPR64>;
1512 def LDRSHWpre_isel : LoadPreIdxPseudo<GPR32>;
1513 def LDRSHXpre_isel : LoadPreIdxPseudo<GPR64>;
1514 def LDRSBWpre_isel : LoadPreIdxPseudo<GPR32>;
1515 def LDRSBXpre_isel : LoadPreIdxPseudo<GPR64>;
1518 // (immediate post-indexed)
1519 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1520 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1521 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1522 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1523 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1524 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1525 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1527 // load sign-extended half-word
1528 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1529 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1531 // load sign-extended byte
1532 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1533 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1535 // load zero-extended byte
1536 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1537 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1539 // load sign-extended word
1540 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1542 // ISel pseudos and patterns. See expanded comment on LoadPostIdxPseudo.
1543 def LDRDpost_isel : LoadPostIdxPseudo<FPR64>;
1544 def LDRSpost_isel : LoadPostIdxPseudo<FPR32>;
1545 def LDRXpost_isel : LoadPostIdxPseudo<GPR64>;
1546 def LDRWpost_isel : LoadPostIdxPseudo<GPR32>;
1547 def LDRHHpost_isel : LoadPostIdxPseudo<GPR32>;
1548 def LDRBBpost_isel : LoadPostIdxPseudo<GPR32>;
1550 def LDRSWpost_isel : LoadPostIdxPseudo<GPR64>;
1551 def LDRSHWpost_isel : LoadPostIdxPseudo<GPR32>;
1552 def LDRSHXpost_isel : LoadPostIdxPseudo<GPR64>;
1553 def LDRSBWpost_isel : LoadPostIdxPseudo<GPR32>;
1554 def LDRSBXpost_isel : LoadPostIdxPseudo<GPR64>;
1556 //===----------------------------------------------------------------------===//
1557 // Store instructions.
1558 //===----------------------------------------------------------------------===//
1560 // Pair (indexed, offset)
1561 // FIXME: Use dedicated range-checked addressing mode operand here.
1562 def STPWi : StorePairOffset<0b00, 0, GPR32, am_indexed32simm7, "stp">;
1563 def STPXi : StorePairOffset<0b10, 0, GPR64, am_indexed64simm7, "stp">;
1564 def STPSi : StorePairOffset<0b00, 1, FPR32, am_indexed32simm7, "stp">;
1565 def STPDi : StorePairOffset<0b01, 1, FPR64, am_indexed64simm7, "stp">;
1566 def STPQi : StorePairOffset<0b10, 1, FPR128, am_indexed128simm7, "stp">;
1568 // Pair (pre-indexed)
1569 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "stp">;
1570 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "stp">;
1571 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "stp">;
1572 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "stp">;
1573 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "stp">;
1575 // Pair (pre-indexed)
1576 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1577 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1578 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1579 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1580 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1582 // Pair (no allocate)
1583 def STNPWi : StorePairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "stnp">;
1584 def STNPXi : StorePairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "stnp">;
1585 def STNPSi : StorePairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "stnp">;
1586 def STNPDi : StorePairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "stnp">;
1587 def STNPQi : StorePairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "stnp">;
1590 // (Register offset)
1592 let AddedComplexity = 10 in {
1595 def STRHHro : Store16RO<0b01, 0, 0b00, GPR32, "strh",
1596 [(truncstorei16 GPR32:$Rt, ro_indexed16:$addr)]>;
1597 def STRBBro : Store8RO<0b00, 0, 0b00, GPR32, "strb",
1598 [(truncstorei8 GPR32:$Rt, ro_indexed8:$addr)]>;
1599 def STRWro : Store32RO<0b10, 0, 0b00, GPR32, "str",
1600 [(store GPR32:$Rt, ro_indexed32:$addr)]>;
1601 def STRXro : Store64RO<0b11, 0, 0b00, GPR64, "str",
1602 [(store GPR64:$Rt, ro_indexed64:$addr)]>;
1605 def : Pat<(truncstorei8 GPR64:$Rt, ro_indexed8:$addr),
1606 (STRBBro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed8:$addr)>;
1607 def : Pat<(truncstorei16 GPR64:$Rt, ro_indexed16:$addr),
1608 (STRHHro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed16:$addr)>;
1609 def : Pat<(truncstorei32 GPR64:$Rt, ro_indexed32:$addr),
1610 (STRWro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed32:$addr)>;
1614 def STRBro : Store8RO<0b00, 1, 0b00, FPR8, "str",
1615 [(store FPR8:$Rt, ro_indexed8:$addr)]>;
1616 def STRHro : Store16RO<0b01, 1, 0b00, FPR16, "str",
1617 [(store (f16 FPR16:$Rt), ro_indexed16:$addr)]>;
1618 def STRSro : Store32RO<0b10, 1, 0b00, FPR32, "str",
1619 [(store (f32 FPR32:$Rt), ro_indexed32:$addr)]>;
1620 def STRDro : Store64RO<0b11, 1, 0b00, FPR64, "str",
1621 [(store (f64 FPR64:$Rt), ro_indexed64:$addr)]>;
1622 def STRQro : Store128RO<0b00, 1, 0b10, FPR128, "str", []> {
1626 // Match all store 64 bits width whose type is compatible with FPR64
1627 def : Pat<(store (v2f32 FPR64:$Rn), ro_indexed64:$addr),
1628 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1629 def : Pat<(store (v1f64 FPR64:$Rn), ro_indexed64:$addr),
1630 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1631 def : Pat<(store (v8i8 FPR64:$Rn), ro_indexed64:$addr),
1632 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1633 def : Pat<(store (v4i16 FPR64:$Rn), ro_indexed64:$addr),
1634 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1635 def : Pat<(store (v2i32 FPR64:$Rn), ro_indexed64:$addr),
1636 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1637 def : Pat<(store (v1i64 FPR64:$Rn), ro_indexed64:$addr),
1638 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1640 // Match all store 128 bits width whose type is compatible with FPR128
1641 def : Pat<(store (v4f32 FPR128:$Rn), ro_indexed128:$addr),
1642 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1643 def : Pat<(store (v2f64 FPR128:$Rn), ro_indexed128:$addr),
1644 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1645 def : Pat<(store (v16i8 FPR128:$Rn), ro_indexed128:$addr),
1646 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1647 def : Pat<(store (v8i16 FPR128:$Rn), ro_indexed128:$addr),
1648 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1649 def : Pat<(store (v4i32 FPR128:$Rn), ro_indexed128:$addr),
1650 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1651 def : Pat<(store (v2i64 FPR128:$Rn), ro_indexed128:$addr),
1652 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1653 def : Pat<(store (f128 FPR128:$Rn), ro_indexed128:$addr),
1654 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1657 // (unsigned immediate)
1658 def STRXui : StoreUI<0b11, 0, 0b00, GPR64, am_indexed64, "str",
1659 [(store GPR64:$Rt, am_indexed64:$addr)]>;
1660 def STRWui : StoreUI<0b10, 0, 0b00, GPR32, am_indexed32, "str",
1661 [(store GPR32:$Rt, am_indexed32:$addr)]>;
1662 def STRBui : StoreUI<0b00, 1, 0b00, FPR8, am_indexed8, "str",
1663 [(store FPR8:$Rt, am_indexed8:$addr)]>;
1664 def STRHui : StoreUI<0b01, 1, 0b00, FPR16, am_indexed16, "str",
1665 [(store (f16 FPR16:$Rt), am_indexed16:$addr)]>;
1666 def STRSui : StoreUI<0b10, 1, 0b00, FPR32, am_indexed32, "str",
1667 [(store (f32 FPR32:$Rt), am_indexed32:$addr)]>;
1668 def STRDui : StoreUI<0b11, 1, 0b00, FPR64, am_indexed64, "str",
1669 [(store (f64 FPR64:$Rt), am_indexed64:$addr)]>;
1670 def STRQui : StoreUI<0b00, 1, 0b10, FPR128, am_indexed128, "str", []> {
1674 // Match all store 64 bits width whose type is compatible with FPR64
1675 def : Pat<(store (v2f32 FPR64:$Rn), am_indexed64:$addr),
1676 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1677 def : Pat<(store (v1f64 FPR64:$Rn), am_indexed64:$addr),
1678 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1679 def : Pat<(store (v8i8 FPR64:$Rn), am_indexed64:$addr),
1680 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1681 def : Pat<(store (v4i16 FPR64:$Rn), am_indexed64:$addr),
1682 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1683 def : Pat<(store (v2i32 FPR64:$Rn), am_indexed64:$addr),
1684 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1685 def : Pat<(store (v1i64 FPR64:$Rn), am_indexed64:$addr),
1686 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1688 // Match all store 128 bits width whose type is compatible with FPR128
1689 def : Pat<(store (v4f32 FPR128:$Rn), am_indexed128:$addr),
1690 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1691 def : Pat<(store (v2f64 FPR128:$Rn), am_indexed128:$addr),
1692 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1693 def : Pat<(store (v16i8 FPR128:$Rn), am_indexed128:$addr),
1694 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1695 def : Pat<(store (v8i16 FPR128:$Rn), am_indexed128:$addr),
1696 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1697 def : Pat<(store (v4i32 FPR128:$Rn), am_indexed128:$addr),
1698 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1699 def : Pat<(store (v2i64 FPR128:$Rn), am_indexed128:$addr),
1700 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1701 def : Pat<(store (f128 FPR128:$Rn), am_indexed128:$addr),
1702 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1704 def STRHHui : StoreUI<0b01, 0, 0b00, GPR32, am_indexed16, "strh",
1705 [(truncstorei16 GPR32:$Rt, am_indexed16:$addr)]>;
1706 def STRBBui : StoreUI<0b00, 0, 0b00, GPR32, am_indexed8, "strb",
1707 [(truncstorei8 GPR32:$Rt, am_indexed8:$addr)]>;
1710 def : Pat<(truncstorei32 GPR64:$Rt, am_indexed32:$addr),
1711 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed32:$addr)>;
1712 def : Pat<(truncstorei16 GPR64:$Rt, am_indexed16:$addr),
1713 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed16:$addr)>;
1714 def : Pat<(truncstorei8 GPR64:$Rt, am_indexed8:$addr),
1715 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed8:$addr)>;
1717 } // AddedComplexity = 10
1720 // (unscaled immediate)
1721 def STURXi : StoreUnscaled<0b11, 0, 0b00, GPR64, am_unscaled64, "stur",
1722 [(store GPR64:$Rt, am_unscaled64:$addr)]>;
1723 def STURWi : StoreUnscaled<0b10, 0, 0b00, GPR32, am_unscaled32, "stur",
1724 [(store GPR32:$Rt, am_unscaled32:$addr)]>;
1725 def STURBi : StoreUnscaled<0b00, 1, 0b00, FPR8, am_unscaled8, "stur",
1726 [(store FPR8:$Rt, am_unscaled8:$addr)]>;
1727 def STURHi : StoreUnscaled<0b01, 1, 0b00, FPR16, am_unscaled16, "stur",
1728 [(store (f16 FPR16:$Rt), am_unscaled16:$addr)]>;
1729 def STURSi : StoreUnscaled<0b10, 1, 0b00, FPR32, am_unscaled32, "stur",
1730 [(store (f32 FPR32:$Rt), am_unscaled32:$addr)]>;
1731 def STURDi : StoreUnscaled<0b11, 1, 0b00, FPR64, am_unscaled64, "stur",
1732 [(store (f64 FPR64:$Rt), am_unscaled64:$addr)]>;
1733 def STURQi : StoreUnscaled<0b00, 1, 0b10, FPR128, am_unscaled128, "stur",
1734 [(store (v2f64 FPR128:$Rt), am_unscaled128:$addr)]>;
1735 def STURHHi : StoreUnscaled<0b01, 0, 0b00, GPR32, am_unscaled16, "sturh",
1736 [(truncstorei16 GPR32:$Rt, am_unscaled16:$addr)]>;
1737 def STURBBi : StoreUnscaled<0b00, 0, 0b00, GPR32, am_unscaled8, "sturb",
1738 [(truncstorei8 GPR32:$Rt, am_unscaled8:$addr)]>;
1740 // Match all store 64 bits width whose type is compatible with FPR64
1741 def : Pat<(store (v2f32 FPR64:$Rn), am_unscaled64:$addr),
1742 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1743 def : Pat<(store (v1f64 FPR64:$Rn), am_unscaled64:$addr),
1744 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1745 def : Pat<(store (v8i8 FPR64:$Rn), am_unscaled64:$addr),
1746 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1747 def : Pat<(store (v4i16 FPR64:$Rn), am_unscaled64:$addr),
1748 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1749 def : Pat<(store (v2i32 FPR64:$Rn), am_unscaled64:$addr),
1750 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1751 def : Pat<(store (v1i64 FPR64:$Rn), am_unscaled64:$addr),
1752 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1754 // Match all store 128 bits width whose type is compatible with FPR128
1755 def : Pat<(store (v4f32 FPR128:$Rn), am_unscaled128:$addr),
1756 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1757 def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
1758 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1759 def : Pat<(store (v16i8 FPR128:$Rn), am_unscaled128:$addr),
1760 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1761 def : Pat<(store (v8i16 FPR128:$Rn), am_unscaled128:$addr),
1762 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1763 def : Pat<(store (v4i32 FPR128:$Rn), am_unscaled128:$addr),
1764 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1765 def : Pat<(store (v2i64 FPR128:$Rn), am_unscaled128:$addr),
1766 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1767 def : Pat<(store (f128 FPR128:$Rn), am_unscaled128:$addr),
1768 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1770 // unscaled i64 truncating stores
1771 def : Pat<(truncstorei32 GPR64:$Rt, am_unscaled32:$addr),
1772 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled32:$addr)>;
1773 def : Pat<(truncstorei16 GPR64:$Rt, am_unscaled16:$addr),
1774 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled16:$addr)>;
1775 def : Pat<(truncstorei8 GPR64:$Rt, am_unscaled8:$addr),
1776 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled8:$addr)>;
1779 // STR mnemonics fall back to STUR for negative or unaligned offsets.
1780 def : InstAlias<"str $Rt, $addr", (STURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1781 def : InstAlias<"str $Rt, $addr", (STURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1782 def : InstAlias<"str $Rt, $addr", (STURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1783 def : InstAlias<"str $Rt, $addr", (STURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1784 def : InstAlias<"str $Rt, $addr", (STURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1785 def : InstAlias<"str $Rt, $addr", (STURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1786 def : InstAlias<"str $Rt, $addr", (STURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1788 def : InstAlias<"strb $Rt, $addr", (STURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1789 def : InstAlias<"strh $Rt, $addr", (STURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1792 // (unscaled immediate, unprivileged)
1793 def STTRWi : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
1794 def STTRXi : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
1796 def STTRHi : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
1797 def STTRBi : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
1800 // (immediate pre-indexed)
1801 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str">;
1802 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str">;
1803 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str">;
1804 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str">;
1805 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str">;
1806 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str">;
1807 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str">;
1809 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb">;
1810 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh">;
1812 // ISel pseudos and patterns. See expanded comment on StorePreIdxPseudo.
1813 defm STRDpre : StorePreIdxPseudo<FPR64, f64, pre_store>;
1814 defm STRSpre : StorePreIdxPseudo<FPR32, f32, pre_store>;
1815 defm STRXpre : StorePreIdxPseudo<GPR64, i64, pre_store>;
1816 defm STRWpre : StorePreIdxPseudo<GPR32, i32, pre_store>;
1817 defm STRHHpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti16>;
1818 defm STRBBpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti8>;
1820 def : Pat<(pre_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1821 (STRWpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1823 def : Pat<(pre_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1824 (STRHHpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1826 def : Pat<(pre_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1827 (STRBBpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1831 // (immediate post-indexed)
1832 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str">;
1833 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str">;
1834 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str">;
1835 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str">;
1836 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str">;
1837 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str">;
1838 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str">;
1840 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb">;
1841 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh">;
1843 // ISel pseudos and patterns. See expanded comment on StorePostIdxPseudo.
1844 defm STRDpost : StorePostIdxPseudo<FPR64, f64, post_store, STRDpost>;
1845 defm STRSpost : StorePostIdxPseudo<FPR32, f32, post_store, STRSpost>;
1846 defm STRXpost : StorePostIdxPseudo<GPR64, i64, post_store, STRXpost>;
1847 defm STRWpost : StorePostIdxPseudo<GPR32, i32, post_store, STRWpost>;
1848 defm STRHHpost : StorePostIdxPseudo<GPR32, i32, post_truncsti16, STRHHpost>;
1849 defm STRBBpost : StorePostIdxPseudo<GPR32, i32, post_truncsti8, STRBBpost>;
1851 def : Pat<(post_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1852 (STRWpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1854 def : Pat<(post_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1855 (STRHHpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1857 def : Pat<(post_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1858 (STRBBpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1862 //===----------------------------------------------------------------------===//
1863 // Load/store exclusive instructions.
1864 //===----------------------------------------------------------------------===//
1866 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
1867 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
1868 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
1869 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
1871 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
1872 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
1873 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
1874 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
1876 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
1877 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
1878 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
1879 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
1881 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
1882 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
1883 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
1884 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
1886 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
1887 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
1888 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
1889 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
1891 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
1892 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
1893 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
1894 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
1896 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
1897 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
1899 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
1900 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
1902 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
1903 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
1905 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
1906 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
1908 //===----------------------------------------------------------------------===//
1909 // Scaled floating point to integer conversion instructions.
1910 //===----------------------------------------------------------------------===//
1912 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
1913 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
1914 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
1915 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
1916 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
1917 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
1918 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
1919 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
1920 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
1921 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
1922 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
1923 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
1924 let isCodeGenOnly = 1 in {
1925 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
1926 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
1927 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
1928 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
1931 //===----------------------------------------------------------------------===//
1932 // Scaled integer to floating point conversion instructions.
1933 //===----------------------------------------------------------------------===//
1935 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
1936 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
1938 //===----------------------------------------------------------------------===//
1939 // Unscaled integer to floating point conversion instruction.
1940 //===----------------------------------------------------------------------===//
1942 defm FMOV : UnscaledConversion<"fmov">;
1944 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
1945 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
1947 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1948 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1949 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1950 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1951 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1952 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1953 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
1954 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1955 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
1956 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1957 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
1959 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
1960 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1961 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
1962 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1963 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
1964 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1965 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
1966 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1967 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
1968 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1969 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
1970 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1972 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
1973 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
1974 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
1975 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
1976 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
1977 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1978 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
1979 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
1981 //===----------------------------------------------------------------------===//
1982 // Floating point conversion instruction.
1983 //===----------------------------------------------------------------------===//
1985 defm FCVT : FPConversion<"fcvt">;
1987 def : Pat<(f32_to_f16 FPR32:$Rn),
1988 (i32 (COPY_TO_REGCLASS
1989 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
1992 def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
1993 [(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
1995 //===----------------------------------------------------------------------===//
1996 // Floating point single operand instructions.
1997 //===----------------------------------------------------------------------===//
1999 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2000 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2001 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2002 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2003 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2004 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2005 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_arm64_neon_frintn>;
2006 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2008 def : Pat<(v1f64 (int_arm64_neon_frintn (v1f64 FPR64:$Rn))),
2009 (FRINTNDr FPR64:$Rn)>;
2011 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2012 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2013 // <rdar://problem/13715968>
2014 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2015 let hasSideEffects = 1 in {
2016 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2019 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2021 let SchedRW = [WriteFDiv] in {
2022 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2025 //===----------------------------------------------------------------------===//
2026 // Floating point two operand instructions.
2027 //===----------------------------------------------------------------------===//
2029 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2030 let SchedRW = [WriteFDiv] in {
2031 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2033 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_arm64_neon_fmaxnm>;
2034 defm FMAX : TwoOperandFPData<0b0100, "fmax", ARM64fmax>;
2035 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_arm64_neon_fminnm>;
2036 defm FMIN : TwoOperandFPData<0b0101, "fmin", ARM64fmin>;
2037 let SchedRW = [WriteFMul] in {
2038 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2039 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2041 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2043 def : Pat<(v1f64 (ARM64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2044 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2045 def : Pat<(v1f64 (ARM64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2046 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2047 def : Pat<(v1f64 (int_arm64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2048 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2049 def : Pat<(v1f64 (int_arm64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2050 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2052 //===----------------------------------------------------------------------===//
2053 // Floating point three operand instructions.
2054 //===----------------------------------------------------------------------===//
2056 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2057 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2058 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2059 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2060 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2061 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2062 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2064 // The following def pats catch the case where the LHS of an FMA is negated.
2065 // The TriOpFrag above catches the case where the middle operand is negated.
2067 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2068 // the NEON variant.
2069 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2070 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2072 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2073 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2075 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2077 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2078 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2080 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2081 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2083 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2084 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2086 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2087 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2089 //===----------------------------------------------------------------------===//
2090 // Floating point comparison instructions.
2091 //===----------------------------------------------------------------------===//
2093 defm FCMPE : FPComparison<1, "fcmpe">;
2094 defm FCMP : FPComparison<0, "fcmp", ARM64fcmp>;
2096 //===----------------------------------------------------------------------===//
2097 // Floating point conditional comparison instructions.
2098 //===----------------------------------------------------------------------===//
2100 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2101 defm FCCMP : FPCondComparison<0, "fccmp">;
2103 //===----------------------------------------------------------------------===//
2104 // Floating point conditional select instruction.
2105 //===----------------------------------------------------------------------===//
2107 defm FCSEL : FPCondSelect<"fcsel">;
2109 // CSEL instructions providing f128 types need to be handled by a
2110 // pseudo-instruction since the eventual code will need to introduce basic
2111 // blocks and control flow.
2112 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2113 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2114 [(set (f128 FPR128:$Rd),
2115 (ARM64csel FPR128:$Rn, FPR128:$Rm,
2116 (i32 imm:$cond), CPSR))]> {
2118 let usesCustomInserter = 1;
2122 //===----------------------------------------------------------------------===//
2123 // Floating point immediate move.
2124 //===----------------------------------------------------------------------===//
2126 let isReMaterializable = 1 in {
2127 defm FMOV : FPMoveImmediate<"fmov">;
2130 //===----------------------------------------------------------------------===//
2131 // Advanced SIMD two vector instructions.
2132 //===----------------------------------------------------------------------===//
2134 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_arm64_neon_abs>;
2135 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_arm64_neon_cls>;
2136 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2137 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", ARM64cmeqz>;
2138 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", ARM64cmgez>;
2139 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", ARM64cmgtz>;
2140 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", ARM64cmlez>;
2141 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", ARM64cmltz>;
2142 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2143 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2145 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2146 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2147 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2148 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2149 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2150 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_arm64_neon_fcvtas>;
2151 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_arm64_neon_fcvtau>;
2152 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2153 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2154 (FCVTLv4i16 V64:$Rn)>;
2155 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2157 (FCVTLv8i16 V128:$Rn)>;
2158 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2159 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2161 (FCVTLv4i32 V128:$Rn)>;
2163 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_arm64_neon_fcvtms>;
2164 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_arm64_neon_fcvtmu>;
2165 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_arm64_neon_fcvtns>;
2166 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_arm64_neon_fcvtnu>;
2167 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2168 def : Pat<(v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2169 (FCVTNv4i16 V128:$Rn)>;
2170 def : Pat<(concat_vectors V64:$Rd,
2171 (v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2172 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2173 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2174 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2175 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2176 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_arm64_neon_fcvtps>;
2177 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_arm64_neon_fcvtpu>;
2178 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2179 int_arm64_neon_fcvtxn>;
2180 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2181 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2182 let isCodeGenOnly = 1 in {
2183 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2184 int_arm64_neon_fcvtzs>;
2185 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2186 int_arm64_neon_fcvtzu>;
2188 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2189 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_arm64_neon_frecpe>;
2190 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2191 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2192 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2193 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_arm64_neon_frintn>;
2194 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2195 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2196 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2197 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_arm64_neon_frsqrte>;
2198 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2199 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2200 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2201 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2202 // Aliases for MVN -> NOT.
2203 def : InstAlias<"mvn.8b $Vd, $Vn", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2204 def : InstAlias<"mvn.16b $Vd, $Vn", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2205 def : InstAlias<"mvn $Vd.8b, $Vn.8b", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2206 def : InstAlias<"mvn $Vd.16b, $Vn.16b", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2208 def : Pat<(ARM64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2209 def : Pat<(ARM64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2210 def : Pat<(ARM64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2211 def : Pat<(ARM64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2212 def : Pat<(ARM64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2213 def : Pat<(ARM64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2214 def : Pat<(ARM64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2216 def : Pat<(ARM64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2217 def : Pat<(ARM64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2218 def : Pat<(ARM64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2219 def : Pat<(ARM64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2220 def : Pat<(ARM64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2221 def : Pat<(ARM64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2222 def : Pat<(ARM64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2223 def : Pat<(ARM64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2225 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2226 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2227 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2228 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2229 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2231 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_arm64_neon_rbit>;
2232 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", ARM64rev16>;
2233 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", ARM64rev32>;
2234 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", ARM64rev64>;
2235 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2236 BinOpFrag<(add node:$LHS, (int_arm64_neon_saddlp node:$RHS))> >;
2237 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_arm64_neon_saddlp>;
2238 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2239 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2240 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2241 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2242 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_arm64_neon_sqxtn>;
2243 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_arm64_neon_sqxtun>;
2244 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_arm64_neon_suqadd>;
2245 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2246 BinOpFrag<(add node:$LHS, (int_arm64_neon_uaddlp node:$RHS))> >;
2247 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2248 int_arm64_neon_uaddlp>;
2249 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2250 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_arm64_neon_uqxtn>;
2251 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_arm64_neon_urecpe>;
2252 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_arm64_neon_ursqrte>;
2253 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_arm64_neon_usqadd>;
2254 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2256 def : Pat<(v2f32 (ARM64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2257 def : Pat<(v4f32 (ARM64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2259 // Patterns for vector long shift (by element width). These need to match all
2260 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2262 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2263 def : Pat<(ARM64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2264 (SHLLv8i8 V64:$Rn)>;
2265 def : Pat<(ARM64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2266 (SHLLv16i8 V128:$Rn)>;
2267 def : Pat<(ARM64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2268 (SHLLv4i16 V64:$Rn)>;
2269 def : Pat<(ARM64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2270 (SHLLv8i16 V128:$Rn)>;
2271 def : Pat<(ARM64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2272 (SHLLv2i32 V64:$Rn)>;
2273 def : Pat<(ARM64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2274 (SHLLv4i32 V128:$Rn)>;
2277 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2278 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2279 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2281 //===----------------------------------------------------------------------===//
2282 // Advanced SIMD three vector instructions.
2283 //===----------------------------------------------------------------------===//
2285 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2286 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_arm64_neon_addp>;
2287 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", ARM64cmeq>;
2288 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", ARM64cmge>;
2289 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", ARM64cmgt>;
2290 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", ARM64cmhi>;
2291 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", ARM64cmhs>;
2292 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", ARM64cmtst>;
2293 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_arm64_neon_fabd>;
2294 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_arm64_neon_facge>;
2295 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_arm64_neon_facgt>;
2296 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_arm64_neon_addp>;
2297 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2298 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2299 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2300 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2301 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2302 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_arm64_neon_fmaxnmp>;
2303 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_arm64_neon_fmaxnm>;
2304 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_arm64_neon_fmaxp>;
2305 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", ARM64fmax>;
2306 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_arm64_neon_fminnmp>;
2307 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_arm64_neon_fminnm>;
2308 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_arm64_neon_fminp>;
2309 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", ARM64fmin>;
2311 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2312 // instruction expects the addend first, while the fma intrinsic puts it last.
2313 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2314 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2315 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2316 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2318 // The following def pats catch the case where the LHS of an FMA is negated.
2319 // The TriOpFrag above catches the case where the middle operand is negated.
2320 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2321 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2323 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2324 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2326 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2327 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2329 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_arm64_neon_fmulx>;
2330 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2331 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_arm64_neon_frecps>;
2332 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_arm64_neon_frsqrts>;
2333 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2334 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2335 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2336 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2337 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2338 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2339 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_arm64_neon_pmul>;
2340 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2341 TriOpFrag<(add node:$LHS, (int_arm64_neon_sabd node:$MHS, node:$RHS))> >;
2342 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_arm64_neon_sabd>;
2343 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_arm64_neon_shadd>;
2344 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_arm64_neon_shsub>;
2345 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_arm64_neon_smaxp>;
2346 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_arm64_neon_smax>;
2347 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_arm64_neon_sminp>;
2348 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_arm64_neon_smin>;
2349 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_arm64_neon_sqadd>;
2350 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_arm64_neon_sqdmulh>;
2351 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_arm64_neon_sqrdmulh>;
2352 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_arm64_neon_sqrshl>;
2353 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_arm64_neon_sqshl>;
2354 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_arm64_neon_sqsub>;
2355 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_arm64_neon_srhadd>;
2356 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_arm64_neon_srshl>;
2357 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_arm64_neon_sshl>;
2358 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2359 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2360 TriOpFrag<(add node:$LHS, (int_arm64_neon_uabd node:$MHS, node:$RHS))> >;
2361 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_arm64_neon_uabd>;
2362 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_arm64_neon_uhadd>;
2363 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_arm64_neon_uhsub>;
2364 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_arm64_neon_umaxp>;
2365 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_arm64_neon_umax>;
2366 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_arm64_neon_uminp>;
2367 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_arm64_neon_umin>;
2368 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_arm64_neon_uqadd>;
2369 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_arm64_neon_uqrshl>;
2370 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_arm64_neon_uqshl>;
2371 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_arm64_neon_uqsub>;
2372 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_arm64_neon_urhadd>;
2373 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_arm64_neon_urshl>;
2374 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_arm64_neon_ushl>;
2376 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2377 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2378 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2379 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2380 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", ARM64bit>;
2381 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2382 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2383 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2384 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2385 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2386 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2388 def : Pat<(ARM64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2389 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2390 def : Pat<(ARM64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2391 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2392 def : Pat<(ARM64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2393 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2394 def : Pat<(ARM64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2395 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2397 def : Pat<(ARM64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2398 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2399 def : Pat<(ARM64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2400 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2401 def : Pat<(ARM64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2402 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2403 def : Pat<(ARM64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2404 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2406 // FIXME: the .16b and .8b variantes should be emitted by the
2407 // AsmWriter. TableGen's AsmWriter-generator doesn't deal with variant syntaxes
2408 // in aliases yet though.
2409 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2410 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2411 def : InstAlias<"{mov\t$dst.8h, $src.8h|mov.8h\t$dst, $src}",
2412 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2413 def : InstAlias<"{mov\t$dst.4s, $src.4s|mov.4s\t$dst, $src}",
2414 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2415 def : InstAlias<"{mov\t$dst.2d, $src.2d|mov.2d\t$dst, $src}",
2416 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2418 def : InstAlias<"{mov\t$dst.8b, $src.8b|mov.8b\t$dst, $src}",
2419 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2420 def : InstAlias<"{mov\t$dst.4h, $src.4h|mov.4h\t$dst, $src}",
2421 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2422 def : InstAlias<"{mov\t$dst.2s, $src.2s|mov.2s\t$dst, $src}",
2423 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2424 def : InstAlias<"{mov\t$dst.1d, $src.1d|mov.1d\t$dst, $src}",
2425 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2427 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2428 "|cmls.8b\t$dst, $src1, $src2}",
2429 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2430 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2431 "|cmls.16b\t$dst, $src1, $src2}",
2432 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2433 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2434 "|cmls.4h\t$dst, $src1, $src2}",
2435 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2436 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2437 "|cmls.8h\t$dst, $src1, $src2}",
2438 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2439 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2440 "|cmls.2s\t$dst, $src1, $src2}",
2441 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2442 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2443 "|cmls.4s\t$dst, $src1, $src2}",
2444 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2445 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2446 "|cmls.2d\t$dst, $src1, $src2}",
2447 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2449 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2450 "|cmlo.8b\t$dst, $src1, $src2}",
2451 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2452 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2453 "|cmlo.16b\t$dst, $src1, $src2}",
2454 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2455 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2456 "|cmlo.4h\t$dst, $src1, $src2}",
2457 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2458 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2459 "|cmlo.8h\t$dst, $src1, $src2}",
2460 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2461 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2462 "|cmlo.2s\t$dst, $src1, $src2}",
2463 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2464 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2465 "|cmlo.4s\t$dst, $src1, $src2}",
2466 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2467 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2468 "|cmlo.2d\t$dst, $src1, $src2}",
2469 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2471 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2472 "|cmle.8b\t$dst, $src1, $src2}",
2473 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2474 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2475 "|cmle.16b\t$dst, $src1, $src2}",
2476 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2477 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2478 "|cmle.4h\t$dst, $src1, $src2}",
2479 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2480 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2481 "|cmle.8h\t$dst, $src1, $src2}",
2482 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2483 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2484 "|cmle.2s\t$dst, $src1, $src2}",
2485 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2486 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2487 "|cmle.4s\t$dst, $src1, $src2}",
2488 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2489 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2490 "|cmle.2d\t$dst, $src1, $src2}",
2491 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2493 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2494 "|cmlt.8b\t$dst, $src1, $src2}",
2495 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2496 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2497 "|cmlt.16b\t$dst, $src1, $src2}",
2498 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2499 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2500 "|cmlt.4h\t$dst, $src1, $src2}",
2501 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2502 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2503 "|cmlt.8h\t$dst, $src1, $src2}",
2504 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2505 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2506 "|cmlt.2s\t$dst, $src1, $src2}",
2507 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2508 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2509 "|cmlt.4s\t$dst, $src1, $src2}",
2510 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2511 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2512 "|cmlt.2d\t$dst, $src1, $src2}",
2513 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2515 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2516 "|fcmle.2s\t$dst, $src1, $src2}",
2517 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2518 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2519 "|fcmle.4s\t$dst, $src1, $src2}",
2520 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2521 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2522 "|fcmle.2d\t$dst, $src1, $src2}",
2523 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2525 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2526 "|fcmlt.2s\t$dst, $src1, $src2}",
2527 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2528 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2529 "|fcmlt.4s\t$dst, $src1, $src2}",
2530 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2531 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2532 "|fcmlt.2d\t$dst, $src1, $src2}",
2533 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2535 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2536 "|facle.2s\t$dst, $src1, $src2}",
2537 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2538 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2539 "|facle.4s\t$dst, $src1, $src2}",
2540 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2541 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2542 "|facle.2d\t$dst, $src1, $src2}",
2543 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2545 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2546 "|faclt.2s\t$dst, $src1, $src2}",
2547 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2548 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2549 "|faclt.4s\t$dst, $src1, $src2}",
2550 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2551 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2552 "|faclt.2d\t$dst, $src1, $src2}",
2553 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2555 //===----------------------------------------------------------------------===//
2556 // Advanced SIMD three scalar instructions.
2557 //===----------------------------------------------------------------------===//
2559 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2560 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", ARM64cmeq>;
2561 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", ARM64cmge>;
2562 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", ARM64cmgt>;
2563 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", ARM64cmhi>;
2564 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", ARM64cmhs>;
2565 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", ARM64cmtst>;
2566 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_arm64_sisd_fabd>;
2567 def : Pat<(v1f64 (int_arm64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2568 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2569 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2570 int_arm64_neon_facge>;
2571 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2572 int_arm64_neon_facgt>;
2573 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2574 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2575 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2576 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_arm64_neon_fmulx>;
2577 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_arm64_neon_frecps>;
2578 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_arm64_neon_frsqrts>;
2579 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_arm64_neon_sqadd>;
2580 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_arm64_neon_sqdmulh>;
2581 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_arm64_neon_sqrdmulh>;
2582 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_arm64_neon_sqrshl>;
2583 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_arm64_neon_sqshl>;
2584 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_arm64_neon_sqsub>;
2585 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_arm64_neon_srshl>;
2586 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_arm64_neon_sshl>;
2587 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2588 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_arm64_neon_uqadd>;
2589 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_arm64_neon_uqrshl>;
2590 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_arm64_neon_uqshl>;
2591 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_arm64_neon_uqsub>;
2592 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_arm64_neon_urshl>;
2593 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_arm64_neon_ushl>;
2595 def : InstAlias<"cmls $dst, $src1, $src2",
2596 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2597 def : InstAlias<"cmle $dst, $src1, $src2",
2598 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2599 def : InstAlias<"cmlo $dst, $src1, $src2",
2600 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2601 def : InstAlias<"cmlt $dst, $src1, $src2",
2602 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2603 def : InstAlias<"fcmle $dst, $src1, $src2",
2604 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2605 def : InstAlias<"fcmle $dst, $src1, $src2",
2606 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2607 def : InstAlias<"fcmlt $dst, $src1, $src2",
2608 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2609 def : InstAlias<"fcmlt $dst, $src1, $src2",
2610 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2611 def : InstAlias<"facle $dst, $src1, $src2",
2612 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2613 def : InstAlias<"facle $dst, $src1, $src2",
2614 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2615 def : InstAlias<"faclt $dst, $src1, $src2",
2616 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2617 def : InstAlias<"faclt $dst, $src1, $src2",
2618 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2620 //===----------------------------------------------------------------------===//
2621 // Advanced SIMD three scalar instructions (mixed operands).
2622 //===----------------------------------------------------------------------===//
2623 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2624 int_arm64_neon_sqdmulls_scalar>;
2625 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2626 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2628 def : Pat<(i64 (int_arm64_neon_sqadd (i64 FPR64:$Rd),
2629 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2630 (i32 FPR32:$Rm))))),
2631 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2632 def : Pat<(i64 (int_arm64_neon_sqsub (i64 FPR64:$Rd),
2633 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2634 (i32 FPR32:$Rm))))),
2635 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2637 //===----------------------------------------------------------------------===//
2638 // Advanced SIMD two scalar instructions.
2639 //===----------------------------------------------------------------------===//
2641 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_arm64_neon_abs>;
2642 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", ARM64cmeqz>;
2643 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", ARM64cmgez>;
2644 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", ARM64cmgtz>;
2645 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", ARM64cmlez>;
2646 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", ARM64cmltz>;
2647 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2648 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2649 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2650 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2651 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2652 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2653 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2654 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2655 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2656 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2657 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2658 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2659 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2660 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2661 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2662 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2663 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2664 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2665 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2666 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
2667 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2668 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", ARM64sitof>;
2669 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2670 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2671 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_arm64_neon_scalar_sqxtn>;
2672 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_arm64_neon_scalar_sqxtun>;
2673 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2674 int_arm64_neon_suqadd>;
2675 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", ARM64uitof>;
2676 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_arm64_neon_scalar_uqxtn>;
2677 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2678 int_arm64_neon_usqadd>;
2680 def : Pat<(ARM64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
2682 def : Pat<(v1i64 (int_arm64_neon_fcvtas (v1f64 FPR64:$Rn))),
2683 (FCVTASv1i64 FPR64:$Rn)>;
2684 def : Pat<(v1i64 (int_arm64_neon_fcvtau (v1f64 FPR64:$Rn))),
2685 (FCVTAUv1i64 FPR64:$Rn)>;
2686 def : Pat<(v1i64 (int_arm64_neon_fcvtms (v1f64 FPR64:$Rn))),
2687 (FCVTMSv1i64 FPR64:$Rn)>;
2688 def : Pat<(v1i64 (int_arm64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2689 (FCVTMUv1i64 FPR64:$Rn)>;
2690 def : Pat<(v1i64 (int_arm64_neon_fcvtns (v1f64 FPR64:$Rn))),
2691 (FCVTNSv1i64 FPR64:$Rn)>;
2692 def : Pat<(v1i64 (int_arm64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2693 (FCVTNUv1i64 FPR64:$Rn)>;
2694 def : Pat<(v1i64 (int_arm64_neon_fcvtps (v1f64 FPR64:$Rn))),
2695 (FCVTPSv1i64 FPR64:$Rn)>;
2696 def : Pat<(v1i64 (int_arm64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2697 (FCVTPUv1i64 FPR64:$Rn)>;
2699 def : Pat<(f32 (int_arm64_neon_frecpe (f32 FPR32:$Rn))),
2700 (FRECPEv1i32 FPR32:$Rn)>;
2701 def : Pat<(f64 (int_arm64_neon_frecpe (f64 FPR64:$Rn))),
2702 (FRECPEv1i64 FPR64:$Rn)>;
2703 def : Pat<(v1f64 (int_arm64_neon_frecpe (v1f64 FPR64:$Rn))),
2704 (FRECPEv1i64 FPR64:$Rn)>;
2706 def : Pat<(f32 (int_arm64_neon_frecpx (f32 FPR32:$Rn))),
2707 (FRECPXv1i32 FPR32:$Rn)>;
2708 def : Pat<(f64 (int_arm64_neon_frecpx (f64 FPR64:$Rn))),
2709 (FRECPXv1i64 FPR64:$Rn)>;
2711 def : Pat<(f32 (int_arm64_neon_frsqrte (f32 FPR32:$Rn))),
2712 (FRSQRTEv1i32 FPR32:$Rn)>;
2713 def : Pat<(f64 (int_arm64_neon_frsqrte (f64 FPR64:$Rn))),
2714 (FRSQRTEv1i64 FPR64:$Rn)>;
2715 def : Pat<(v1f64 (int_arm64_neon_frsqrte (v1f64 FPR64:$Rn))),
2716 (FRSQRTEv1i64 FPR64:$Rn)>;
2718 // If an integer is about to be converted to a floating point value,
2719 // just load it on the floating point unit.
2720 // Here are the patterns for 8 and 16-bits to float.
2722 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2723 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2724 (LDRBro ro_indexed8:$addr), bsub))>;
2725 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2726 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2727 (LDRBui am_indexed8:$addr), bsub))>;
2728 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2729 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2730 (LDURBi am_unscaled8:$addr), bsub))>;
2731 // 16-bits -> float.
2732 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2733 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2734 (LDRHro ro_indexed16:$addr), hsub))>;
2735 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2736 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2737 (LDRHui am_indexed16:$addr), hsub))>;
2738 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2739 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2740 (LDURHi am_unscaled16:$addr), hsub))>;
2741 // 32-bits are handled in target specific dag combine:
2742 // performIntToFpCombine.
2743 // 64-bits integer to 32-bits floating point, not possible with
2744 // UCVTF on floating point registers (both source and destination
2745 // must have the same size).
2747 // Here are the patterns for 8, 16, 32, and 64-bits to double.
2748 // 8-bits -> double.
2749 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2750 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2751 (LDRBro ro_indexed8:$addr), bsub))>;
2752 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2753 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2754 (LDRBui am_indexed8:$addr), bsub))>;
2755 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2756 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2757 (LDURBi am_unscaled8:$addr), bsub))>;
2758 // 16-bits -> double.
2759 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2760 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2761 (LDRHro ro_indexed16:$addr), hsub))>;
2762 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2763 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2764 (LDRHui am_indexed16:$addr), hsub))>;
2765 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2766 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2767 (LDURHi am_unscaled16:$addr), hsub))>;
2768 // 32-bits -> double.
2769 def : Pat <(f64 (uint_to_fp (i32 (load ro_indexed32:$addr)))),
2770 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2771 (LDRSro ro_indexed32:$addr), ssub))>;
2772 def : Pat <(f64 (uint_to_fp (i32 (load am_indexed32:$addr)))),
2773 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2774 (LDRSui am_indexed32:$addr), ssub))>;
2775 def : Pat <(f64 (uint_to_fp (i32 (load am_unscaled32:$addr)))),
2776 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2777 (LDURSi am_unscaled32:$addr), ssub))>;
2778 // 64-bits -> double are handled in target specific dag combine:
2779 // performIntToFpCombine.
2781 //===----------------------------------------------------------------------===//
2782 // Advanced SIMD three different-sized vector instructions.
2783 //===----------------------------------------------------------------------===//
2785 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_arm64_neon_addhn>;
2786 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_arm64_neon_subhn>;
2787 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_arm64_neon_raddhn>;
2788 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_arm64_neon_rsubhn>;
2789 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_arm64_neon_pmull>;
2790 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
2791 int_arm64_neon_sabd>;
2792 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
2793 int_arm64_neon_sabd>;
2794 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
2795 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
2796 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
2797 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
2798 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
2799 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2800 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
2801 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2802 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_arm64_neon_smull>;
2803 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
2804 int_arm64_neon_sqadd>;
2805 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
2806 int_arm64_neon_sqsub>;
2807 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
2808 int_arm64_neon_sqdmull>;
2809 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
2810 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
2811 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
2812 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
2813 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
2814 int_arm64_neon_uabd>;
2815 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
2816 int_arm64_neon_uabd>;
2817 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
2818 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
2819 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
2820 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
2821 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
2822 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2823 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
2824 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2825 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_arm64_neon_umull>;
2826 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
2827 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
2828 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
2829 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
2831 // Patterns for 64-bit pmull
2832 def : Pat<(int_arm64_neon_pmull64 V64:$Rn, V64:$Rm),
2833 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
2834 def : Pat<(int_arm64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
2835 (vector_extract (v2i64 V128:$Rm), (i64 1))),
2836 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
2838 // CodeGen patterns for addhn and subhn instructions, which can actually be
2839 // written in LLVM IR without too much difficulty.
2842 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
2843 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2844 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2846 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2847 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2849 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2850 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2851 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2853 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2854 V128:$Rn, V128:$Rm)>;
2855 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2856 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2858 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2859 V128:$Rn, V128:$Rm)>;
2860 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2861 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2863 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2864 V128:$Rn, V128:$Rm)>;
2867 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
2868 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2869 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2871 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2872 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2874 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2875 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2876 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2878 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2879 V128:$Rn, V128:$Rm)>;
2880 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2881 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2883 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2884 V128:$Rn, V128:$Rm)>;
2885 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2886 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2888 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2889 V128:$Rn, V128:$Rm)>;
2891 //----------------------------------------------------------------------------
2892 // AdvSIMD bitwise extract from vector instruction.
2893 //----------------------------------------------------------------------------
2895 defm EXT : SIMDBitwiseExtract<"ext">;
2897 def : Pat<(v4i16 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2898 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2899 def : Pat<(v8i16 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2900 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2901 def : Pat<(v2i32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2902 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2903 def : Pat<(v2f32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2904 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2905 def : Pat<(v4i32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2906 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2907 def : Pat<(v4f32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2908 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2909 def : Pat<(v2i64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2910 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2911 def : Pat<(v2f64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2912 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2914 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
2916 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
2917 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2918 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
2919 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2920 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
2921 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2922 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
2923 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2924 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
2925 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2926 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
2927 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2930 //----------------------------------------------------------------------------
2931 // AdvSIMD zip vector
2932 //----------------------------------------------------------------------------
2934 defm TRN1 : SIMDZipVector<0b010, "trn1", ARM64trn1>;
2935 defm TRN2 : SIMDZipVector<0b110, "trn2", ARM64trn2>;
2936 defm UZP1 : SIMDZipVector<0b001, "uzp1", ARM64uzp1>;
2937 defm UZP2 : SIMDZipVector<0b101, "uzp2", ARM64uzp2>;
2938 defm ZIP1 : SIMDZipVector<0b011, "zip1", ARM64zip1>;
2939 defm ZIP2 : SIMDZipVector<0b111, "zip2", ARM64zip2>;
2941 //----------------------------------------------------------------------------
2942 // AdvSIMD TBL/TBX instructions
2943 //----------------------------------------------------------------------------
2945 defm TBL : SIMDTableLookup< 0, "tbl">;
2946 defm TBX : SIMDTableLookupTied<1, "tbx">;
2948 def : Pat<(v8i8 (int_arm64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
2949 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
2950 def : Pat<(v16i8 (int_arm64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
2951 (TBLv16i8One V128:$Ri, V128:$Rn)>;
2953 def : Pat<(v8i8 (int_arm64_neon_tbx1 (v8i8 V64:$Rd),
2954 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
2955 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
2956 def : Pat<(v16i8 (int_arm64_neon_tbx1 (v16i8 V128:$Rd),
2957 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
2958 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
2961 //----------------------------------------------------------------------------
2962 // AdvSIMD scalar CPY instruction
2963 //----------------------------------------------------------------------------
2965 defm CPY : SIMDScalarCPY<"cpy">;
2967 //----------------------------------------------------------------------------
2968 // AdvSIMD scalar pairwise instructions
2969 //----------------------------------------------------------------------------
2971 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
2972 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
2973 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
2974 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
2975 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
2976 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
2977 def : Pat<(i64 (int_arm64_neon_saddv (v2i64 V128:$Rn))),
2978 (ADDPv2i64p V128:$Rn)>;
2979 def : Pat<(i64 (int_arm64_neon_uaddv (v2i64 V128:$Rn))),
2980 (ADDPv2i64p V128:$Rn)>;
2981 def : Pat<(f32 (int_arm64_neon_faddv (v2f32 V64:$Rn))),
2982 (FADDPv2i32p V64:$Rn)>;
2983 def : Pat<(f32 (int_arm64_neon_faddv (v4f32 V128:$Rn))),
2984 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
2985 def : Pat<(f64 (int_arm64_neon_faddv (v2f64 V128:$Rn))),
2986 (FADDPv2i64p V128:$Rn)>;
2987 def : Pat<(f32 (int_arm64_neon_fmaxnmv (v2f32 V64:$Rn))),
2988 (FMAXNMPv2i32p V64:$Rn)>;
2989 def : Pat<(f64 (int_arm64_neon_fmaxnmv (v2f64 V128:$Rn))),
2990 (FMAXNMPv2i64p V128:$Rn)>;
2991 def : Pat<(f32 (int_arm64_neon_fmaxv (v2f32 V64:$Rn))),
2992 (FMAXPv2i32p V64:$Rn)>;
2993 def : Pat<(f64 (int_arm64_neon_fmaxv (v2f64 V128:$Rn))),
2994 (FMAXPv2i64p V128:$Rn)>;
2995 def : Pat<(f32 (int_arm64_neon_fminnmv (v2f32 V64:$Rn))),
2996 (FMINNMPv2i32p V64:$Rn)>;
2997 def : Pat<(f64 (int_arm64_neon_fminnmv (v2f64 V128:$Rn))),
2998 (FMINNMPv2i64p V128:$Rn)>;
2999 def : Pat<(f32 (int_arm64_neon_fminv (v2f32 V64:$Rn))),
3000 (FMINPv2i32p V64:$Rn)>;
3001 def : Pat<(f64 (int_arm64_neon_fminv (v2f64 V128:$Rn))),
3002 (FMINPv2i64p V128:$Rn)>;
3004 //----------------------------------------------------------------------------
3005 // AdvSIMD INS/DUP instructions
3006 //----------------------------------------------------------------------------
3008 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3009 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3010 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3011 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3012 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3013 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3014 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3016 def DUPv2i64lane : SIMDDup64FromElement;
3017 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3018 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3019 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3020 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3021 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3022 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3024 def : Pat<(v2f32 (ARM64dup (f32 FPR32:$Rn))),
3025 (v2f32 (DUPv2i32lane
3026 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3028 def : Pat<(v4f32 (ARM64dup (f32 FPR32:$Rn))),
3029 (v4f32 (DUPv4i32lane
3030 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3032 def : Pat<(v2f64 (ARM64dup (f64 FPR64:$Rn))),
3033 (v2f64 (DUPv2i64lane
3034 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3037 def : Pat<(v2f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3038 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3039 def : Pat<(v4f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3040 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3041 def : Pat<(v2f64 (ARM64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3042 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3044 // If there's an (ARM64dup (vector_extract ...) ...), we can use a duplane
3045 // instruction even if the types don't match: we just have to remap the lane
3046 // carefully. N.b. this trick only applies to truncations.
3047 def VecIndex_x2 : SDNodeXForm<imm, [{
3048 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3050 def VecIndex_x4 : SDNodeXForm<imm, [{
3051 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3053 def VecIndex_x8 : SDNodeXForm<imm, [{
3054 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3057 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3058 ValueType Src128VT, ValueType ScalVT,
3059 Instruction DUP, SDNodeXForm IdxXFORM> {
3060 def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3062 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3064 def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3066 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3069 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3070 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3071 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3073 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3074 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3075 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3077 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3078 SDNodeXForm IdxXFORM> {
3079 def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3081 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3083 def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3085 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3088 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3089 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3090 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3092 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3093 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3094 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3096 // SMOV and UMOV definitions, with some extra patterns for convenience
3100 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3101 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3102 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3103 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3104 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3105 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3106 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3107 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3108 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3109 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3110 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3111 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3113 // Extracting i8 or i16 elements will have the zero-extend transformed to
3114 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3115 // for ARM64. Match these patterns here since UMOV already zeroes out the high
3116 // bits of the destination register.
3117 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3119 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3120 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3122 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3126 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3127 (SUBREG_TO_REG (i32 0),
3128 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3129 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3130 (SUBREG_TO_REG (i32 0),
3131 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3133 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3134 (SUBREG_TO_REG (i32 0),
3135 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3136 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3137 (SUBREG_TO_REG (i32 0),
3138 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3140 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3141 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3142 (i32 FPR32:$Rn), ssub))>;
3143 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3144 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3145 (i32 FPR32:$Rn), ssub))>;
3146 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3147 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3148 (i64 FPR64:$Rn), dsub))>;
3150 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3151 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3152 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3153 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3154 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3155 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3157 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3158 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3161 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3163 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3166 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3167 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3169 V128:$Rn, VectorIndexS:$imm,
3170 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3172 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3173 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3175 V128:$Rn, VectorIndexD:$imm,
3176 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3179 // Copy an element at a constant index in one vector into a constant indexed
3180 // element of another.
3181 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3182 // index type and INS extension
3183 def : Pat<(v16i8 (int_arm64_neon_vcopy_lane
3184 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3185 VectorIndexB:$idx2)),
3187 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3189 def : Pat<(v8i16 (int_arm64_neon_vcopy_lane
3190 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3191 VectorIndexH:$idx2)),
3193 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3195 def : Pat<(v4i32 (int_arm64_neon_vcopy_lane
3196 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3197 VectorIndexS:$idx2)),
3199 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3201 def : Pat<(v2i64 (int_arm64_neon_vcopy_lane
3202 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3203 VectorIndexD:$idx2)),
3205 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3208 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3209 ValueType VTScal, Instruction INS> {
3210 def : Pat<(VT128 (vector_insert V128:$src,
3211 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3213 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3215 def : Pat<(VT128 (vector_insert V128:$src,
3216 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3218 (INS V128:$src, imm:$Immd,
3219 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3221 def : Pat<(VT64 (vector_insert V64:$src,
3222 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3224 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3225 imm:$Immd, V128:$Rn, imm:$Immn),
3228 def : Pat<(VT64 (vector_insert V64:$src,
3229 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3232 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3233 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3237 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3238 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3239 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3240 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3241 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3242 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3245 // Floating point vector extractions are codegen'd as either a sequence of
3246 // subregister extractions, possibly fed by an INS if the lane number is
3247 // anything other than zero.
3248 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3249 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3250 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3251 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3252 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3253 (f64 (EXTRACT_SUBREG
3254 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3255 V128:$Rn, VectorIndexD:$idx),
3257 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3258 (f32 (EXTRACT_SUBREG
3259 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3260 V128:$Rn, VectorIndexS:$idx),
3263 // All concat_vectors operations are canonicalised to act on i64 vectors for
3264 // ARM64. In the general case we need an instruction, which had just as well be
3266 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3267 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3268 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3269 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3271 def : ConcatPat<v2i64, v1i64>;
3272 def : ConcatPat<v2f64, v1f64>;
3273 def : ConcatPat<v4i32, v2i32>;
3274 def : ConcatPat<v4f32, v2f32>;
3275 def : ConcatPat<v8i16, v4i16>;
3276 def : ConcatPat<v16i8, v8i8>;
3278 // If the high lanes are undef, though, we can just ignore them:
3279 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3280 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3281 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3283 def : ConcatUndefPat<v2i64, v1i64>;
3284 def : ConcatUndefPat<v2f64, v1f64>;
3285 def : ConcatUndefPat<v4i32, v2i32>;
3286 def : ConcatUndefPat<v4f32, v2f32>;
3287 def : ConcatUndefPat<v8i16, v4i16>;
3288 def : ConcatUndefPat<v16i8, v8i8>;
3290 //----------------------------------------------------------------------------
3291 // AdvSIMD across lanes instructions
3292 //----------------------------------------------------------------------------
3294 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3295 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3296 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3297 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3298 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3299 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3300 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3301 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_arm64_neon_fmaxnmv>;
3302 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_arm64_neon_fmaxv>;
3303 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_arm64_neon_fminnmv>;
3304 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_arm64_neon_fminv>;
3306 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3307 // If there is a sign extension after this intrinsic, consume it as smov already
3309 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3311 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3312 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3314 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3316 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3317 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3319 // If there is a sign extension after this intrinsic, consume it as smov already
3321 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3323 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3324 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3326 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3328 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3329 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3331 // If there is a sign extension after this intrinsic, consume it as smov already
3333 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3335 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3336 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3338 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3340 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3341 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3343 // If there is a sign extension after this intrinsic, consume it as smov already
3345 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3347 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3348 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3350 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3352 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3353 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3356 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3357 (i32 (EXTRACT_SUBREG
3358 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3359 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3363 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3364 // If there is a masking operation keeping only what has been actually
3365 // generated, consume it.
3366 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3367 (i32 (EXTRACT_SUBREG
3368 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3369 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3371 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3372 (i32 (EXTRACT_SUBREG
3373 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3374 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3376 // If there is a masking operation keeping only what has been actually
3377 // generated, consume it.
3378 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3379 (i32 (EXTRACT_SUBREG
3380 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3381 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3383 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3384 (i32 (EXTRACT_SUBREG
3385 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3386 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3389 // If there is a masking operation keeping only what has been actually
3390 // generated, consume it.
3391 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3392 (i32 (EXTRACT_SUBREG
3393 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3394 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3396 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3397 (i32 (EXTRACT_SUBREG
3398 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3399 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3401 // If there is a masking operation keeping only what has been actually
3402 // generated, consume it.
3403 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3404 (i32 (EXTRACT_SUBREG
3405 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3406 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3408 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3409 (i32 (EXTRACT_SUBREG
3410 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3411 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3414 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3415 (i32 (EXTRACT_SUBREG
3416 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3417 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3422 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3423 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3425 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3426 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3428 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3430 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3431 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3434 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3435 (i32 (EXTRACT_SUBREG
3436 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3437 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3439 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3440 (i32 (EXTRACT_SUBREG
3441 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3442 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3445 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3446 (i64 (EXTRACT_SUBREG
3447 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3448 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3452 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3454 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3455 (i32 (EXTRACT_SUBREG
3456 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3457 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3459 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3460 (i32 (EXTRACT_SUBREG
3461 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3462 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3465 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3466 (i32 (EXTRACT_SUBREG
3467 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3468 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3470 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3471 (i32 (EXTRACT_SUBREG
3472 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3473 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3476 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3477 (i64 (EXTRACT_SUBREG
3478 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3479 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3483 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_arm64_neon_saddv>;
3484 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3485 def : Pat<(i32 (int_arm64_neon_saddv (v2i32 V64:$Rn))),
3486 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3488 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_arm64_neon_uaddv>;
3489 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3490 def : Pat<(i32 (int_arm64_neon_uaddv (v2i32 V64:$Rn))),
3491 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3493 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_arm64_neon_smaxv>;
3494 def : Pat<(i32 (int_arm64_neon_smaxv (v2i32 V64:$Rn))),
3495 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3497 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_arm64_neon_sminv>;
3498 def : Pat<(i32 (int_arm64_neon_sminv (v2i32 V64:$Rn))),
3499 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3501 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_arm64_neon_umaxv>;
3502 def : Pat<(i32 (int_arm64_neon_umaxv (v2i32 V64:$Rn))),
3503 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3505 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_arm64_neon_uminv>;
3506 def : Pat<(i32 (int_arm64_neon_uminv (v2i32 V64:$Rn))),
3507 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3509 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_arm64_neon_saddlv>;
3510 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_arm64_neon_uaddlv>;
3512 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3513 def : Pat<(i64 (int_arm64_neon_saddlv (v2i32 V64:$Rn))),
3514 (i64 (EXTRACT_SUBREG
3515 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3516 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3518 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3519 def : Pat<(i64 (int_arm64_neon_uaddlv (v2i32 V64:$Rn))),
3520 (i64 (EXTRACT_SUBREG
3521 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3522 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3525 //------------------------------------------------------------------------------
3526 // AdvSIMD modified immediate instructions
3527 //------------------------------------------------------------------------------
3530 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", ARM64bici>;
3532 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", ARM64orri>;
3536 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3538 [(set (v2f64 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3539 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3541 [(set (v2f32 V64:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3542 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3544 [(set (v4f32 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3548 // EDIT byte mask: scalar
3549 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3550 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3551 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3552 // The movi_edit node has the immediate value already encoded, so we use
3553 // a plain imm0_255 here.
3554 def : Pat<(f64 (ARM64movi_edit imm0_255:$shift)),
3555 (MOVID imm0_255:$shift)>;
3557 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3558 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3559 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3560 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3562 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3563 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3564 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3565 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3567 // EDIT byte mask: 2d
3569 // The movi_edit node has the immediate value already encoded, so we use
3570 // a plain imm0_255 in the pattern
3571 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3572 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3575 [(set (v2i64 V128:$Rd), (ARM64movi_edit imm0_255:$imm8))]>;
3578 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3579 // Complexity is added to break a tie with a plain MOVI.
3580 let AddedComplexity = 1 in {
3581 def : Pat<(f32 fpimm0),
3582 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3584 def : Pat<(f64 fpimm0),
3585 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3589 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3590 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3591 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3592 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3594 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3595 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3596 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3597 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3599 def : Pat<(v2f64 (ARM64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
3600 def : Pat<(v4f32 (ARM64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
3602 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3603 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3604 def : Pat<(v2i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3605 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
3606 def : Pat<(v4i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3607 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
3608 def : Pat<(v4i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3609 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
3610 def : Pat<(v8i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3611 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
3613 // EDIT per word: 2s & 4s with MSL shifter
3614 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
3615 [(set (v2i32 V64:$Rd),
3616 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3617 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
3618 [(set (v4i32 V128:$Rd),
3619 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3621 // Per byte: 8b & 16b
3622 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
3624 [(set (v8i8 V64:$Rd), (ARM64movi imm0_255:$imm8))]>;
3625 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
3627 [(set (v16i8 V128:$Rd), (ARM64movi imm0_255:$imm8))]>;
3631 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3632 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
3633 def : Pat<(v2i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3634 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
3635 def : Pat<(v4i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3636 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
3637 def : Pat<(v4i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3638 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
3639 def : Pat<(v8i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3640 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
3642 // EDIT per word: 2s & 4s with MSL shifter
3643 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
3644 [(set (v2i32 V64:$Rd),
3645 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3646 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
3647 [(set (v4i32 V128:$Rd),
3648 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3650 //----------------------------------------------------------------------------
3651 // AdvSIMD indexed element
3652 //----------------------------------------------------------------------------
3654 let neverHasSideEffects = 1 in {
3655 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
3656 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
3659 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
3660 // instruction expects the addend first, while the intrinsic expects it last.
3662 // On the other hand, there are quite a few valid combinatorial options due to
3663 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
3664 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3665 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
3666 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3667 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
3669 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3670 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
3671 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3672 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
3673 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3674 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
3675 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3676 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
3678 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
3679 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3681 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3682 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3683 VectorIndexS:$idx))),
3684 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3685 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3686 (v2f32 (ARM64duplane32
3687 (v4f32 (insert_subvector undef,
3688 (v2f32 (fneg V64:$Rm)),
3690 VectorIndexS:$idx)))),
3691 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3692 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3693 VectorIndexS:$idx)>;
3694 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3695 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3696 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3697 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3699 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3701 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3702 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3703 VectorIndexS:$idx))),
3704 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
3705 VectorIndexS:$idx)>;
3706 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3707 (v4f32 (ARM64duplane32
3708 (v4f32 (insert_subvector undef,
3709 (v2f32 (fneg V64:$Rm)),
3711 VectorIndexS:$idx)))),
3712 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3713 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3714 VectorIndexS:$idx)>;
3715 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3716 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3717 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3718 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3720 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
3721 // (DUPLANE from 64-bit would be trivial).
3722 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3723 (ARM64duplane64 (v2f64 (fneg V128:$Rm)),
3724 VectorIndexD:$idx))),
3726 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3727 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3728 (ARM64dup (f64 (fneg FPR64Op:$Rm))))),
3729 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
3730 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
3732 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
3733 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3734 (vector_extract (v4f32 (fneg V128:$Rm)),
3735 VectorIndexS:$idx))),
3736 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3737 V128:$Rm, VectorIndexS:$idx)>;
3738 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3739 (vector_extract (v2f32 (fneg V64:$Rm)),
3740 VectorIndexS:$idx))),
3741 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3742 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
3744 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
3745 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
3746 (vector_extract (v2f64 (fneg V128:$Rm)),
3747 VectorIndexS:$idx))),
3748 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
3749 V128:$Rm, VectorIndexS:$idx)>;
3752 defm : FMLSIndexedAfterNegPatterns<
3753 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
3754 defm : FMLSIndexedAfterNegPatterns<
3755 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
3757 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_arm64_neon_fmulx>;
3758 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
3760 def : Pat<(v2f32 (fmul V64:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3761 (FMULv2i32_indexed V64:$Rn,
3762 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3764 def : Pat<(v4f32 (fmul V128:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3765 (FMULv4i32_indexed V128:$Rn,
3766 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3768 def : Pat<(v2f64 (fmul V128:$Rn, (ARM64dup (f64 FPR64:$Rm)))),
3769 (FMULv2i64_indexed V128:$Rn,
3770 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
3773 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_arm64_neon_sqdmulh>;
3774 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_arm64_neon_sqrdmulh>;
3775 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
3776 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
3777 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
3778 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
3779 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
3780 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
3781 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3782 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
3783 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3784 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
3785 int_arm64_neon_smull>;
3786 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
3787 int_arm64_neon_sqadd>;
3788 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
3789 int_arm64_neon_sqsub>;
3790 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_arm64_neon_sqdmull>;
3791 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
3792 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3793 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
3794 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3795 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
3796 int_arm64_neon_umull>;
3798 // A scalar sqdmull with the second operand being a vector lane can be
3799 // handled directly with the indexed instruction encoding.
3800 def : Pat<(int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3801 (vector_extract (v4i32 V128:$Vm),
3802 VectorIndexS:$idx)),
3803 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
3805 //----------------------------------------------------------------------------
3806 // AdvSIMD scalar shift instructions
3807 //----------------------------------------------------------------------------
3808 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
3809 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
3810 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
3811 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
3812 // Codegen patterns for the above. We don't put these directly on the
3813 // instructions because TableGen's type inference can't handle the truth.
3814 // Having the same base pattern for fp <--> int totally freaks it out.
3815 def : Pat<(int_arm64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
3816 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
3817 def : Pat<(int_arm64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
3818 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
3819 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
3820 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3821 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
3822 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3823 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
3825 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3826 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
3828 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3829 def : Pat<(int_arm64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
3830 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3831 def : Pat<(int_arm64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
3832 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3833 def : Pat<(f64 (int_arm64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3834 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3835 def : Pat<(f64 (int_arm64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3836 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3837 def : Pat<(v1f64 (int_arm64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
3839 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3840 def : Pat<(v1f64 (int_arm64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
3842 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3844 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", ARM64vshl>;
3845 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
3846 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
3847 int_arm64_neon_sqrshrn>;
3848 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
3849 int_arm64_neon_sqrshrun>;
3850 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3851 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3852 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
3853 int_arm64_neon_sqshrn>;
3854 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
3855 int_arm64_neon_sqshrun>;
3856 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
3857 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", ARM64srshri>;
3858 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
3859 TriOpFrag<(add node:$LHS,
3860 (ARM64srshri node:$MHS, node:$RHS))>>;
3861 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", ARM64vashr>;
3862 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
3863 TriOpFrag<(add node:$LHS,
3864 (ARM64vashr node:$MHS, node:$RHS))>>;
3865 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
3866 int_arm64_neon_uqrshrn>;
3867 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3868 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
3869 int_arm64_neon_uqshrn>;
3870 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", ARM64urshri>;
3871 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
3872 TriOpFrag<(add node:$LHS,
3873 (ARM64urshri node:$MHS, node:$RHS))>>;
3874 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", ARM64vlshr>;
3875 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
3876 TriOpFrag<(add node:$LHS,
3877 (ARM64vlshr node:$MHS, node:$RHS))>>;
3879 //----------------------------------------------------------------------------
3880 // AdvSIMD vector shift instructions
3881 //----------------------------------------------------------------------------
3882 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_arm64_neon_vcvtfp2fxs>;
3883 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_arm64_neon_vcvtfp2fxu>;
3884 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
3885 int_arm64_neon_vcvtfxs2fp>;
3886 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
3887 int_arm64_neon_rshrn>;
3888 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", ARM64vshl>;
3889 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
3890 BinOpFrag<(trunc (ARM64vashr node:$LHS, node:$RHS))>>;
3891 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_arm64_neon_vsli>;
3892 def : Pat<(v1i64 (int_arm64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3893 (i32 vecshiftL64:$imm))),
3894 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
3895 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
3896 int_arm64_neon_sqrshrn>;
3897 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
3898 int_arm64_neon_sqrshrun>;
3899 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3900 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3901 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
3902 int_arm64_neon_sqshrn>;
3903 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
3904 int_arm64_neon_sqshrun>;
3905 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_arm64_neon_vsri>;
3906 def : Pat<(v1i64 (int_arm64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3907 (i32 vecshiftR64:$imm))),
3908 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
3909 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", ARM64srshri>;
3910 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
3911 TriOpFrag<(add node:$LHS,
3912 (ARM64srshri node:$MHS, node:$RHS))> >;
3913 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
3914 BinOpFrag<(ARM64vshl (sext node:$LHS), node:$RHS)>>;
3916 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", ARM64vashr>;
3917 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
3918 TriOpFrag<(add node:$LHS, (ARM64vashr node:$MHS, node:$RHS))>>;
3919 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
3920 int_arm64_neon_vcvtfxu2fp>;
3921 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
3922 int_arm64_neon_uqrshrn>;
3923 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3924 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
3925 int_arm64_neon_uqshrn>;
3926 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", ARM64urshri>;
3927 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
3928 TriOpFrag<(add node:$LHS,
3929 (ARM64urshri node:$MHS, node:$RHS))> >;
3930 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
3931 BinOpFrag<(ARM64vshl (zext node:$LHS), node:$RHS)>>;
3932 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", ARM64vlshr>;
3933 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
3934 TriOpFrag<(add node:$LHS, (ARM64vlshr node:$MHS, node:$RHS))> >;
3936 // SHRN patterns for when a logical right shift was used instead of arithmetic
3937 // (the immediate guarantees no sign bits actually end up in the result so it
3939 def : Pat<(v8i8 (trunc (ARM64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
3940 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
3941 def : Pat<(v4i16 (trunc (ARM64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
3942 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
3943 def : Pat<(v2i32 (trunc (ARM64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
3944 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
3946 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
3947 (trunc (ARM64vlshr (v8i16 V128:$Rn),
3948 vecshiftR16Narrow:$imm)))),
3949 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3950 V128:$Rn, vecshiftR16Narrow:$imm)>;
3951 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
3952 (trunc (ARM64vlshr (v4i32 V128:$Rn),
3953 vecshiftR32Narrow:$imm)))),
3954 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3955 V128:$Rn, vecshiftR32Narrow:$imm)>;
3956 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
3957 (trunc (ARM64vlshr (v2i64 V128:$Rn),
3958 vecshiftR64Narrow:$imm)))),
3959 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3960 V128:$Rn, vecshiftR32Narrow:$imm)>;
3962 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
3963 // Anyexts are implemented as zexts.
3964 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
3965 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
3966 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
3967 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
3968 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
3969 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
3970 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
3971 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
3972 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
3973 // Also match an extend from the upper half of a 128 bit source register.
3974 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3975 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
3976 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3977 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
3978 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3979 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
3980 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3981 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
3982 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3983 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
3984 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3985 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
3986 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3987 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
3988 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3989 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
3990 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3991 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
3993 // Vector shift sxtl aliases
3994 def : InstAlias<"sxtl.8h $dst, $src1",
3995 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3996 def : InstAlias<"sxtl $dst.8h, $src1.8b",
3997 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3998 def : InstAlias<"sxtl.4s $dst, $src1",
3999 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4000 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4001 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4002 def : InstAlias<"sxtl.2d $dst, $src1",
4003 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4004 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4005 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4007 // Vector shift sxtl2 aliases
4008 def : InstAlias<"sxtl2.8h $dst, $src1",
4009 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4010 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4011 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4012 def : InstAlias<"sxtl2.4s $dst, $src1",
4013 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4014 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4015 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4016 def : InstAlias<"sxtl2.2d $dst, $src1",
4017 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4018 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4019 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4021 // Vector shift uxtl aliases
4022 def : InstAlias<"uxtl.8h $dst, $src1",
4023 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4024 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4025 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4026 def : InstAlias<"uxtl.4s $dst, $src1",
4027 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4028 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4029 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4030 def : InstAlias<"uxtl.2d $dst, $src1",
4031 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4032 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4033 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4035 // Vector shift uxtl2 aliases
4036 def : InstAlias<"uxtl2.8h $dst, $src1",
4037 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4038 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4039 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4040 def : InstAlias<"uxtl2.4s $dst, $src1",
4041 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4042 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4043 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4044 def : InstAlias<"uxtl2.2d $dst, $src1",
4045 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4046 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4047 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4049 // If an integer is about to be converted to a floating point value,
4050 // just load it on the floating point unit.
4051 // These patterns are more complex because floating point loads do not
4052 // support sign extension.
4053 // The sign extension has to be explicitly added and is only supported for
4054 // one step: byte-to-half, half-to-word, word-to-doubleword.
4055 // SCVTF GPR -> FPR is 9 cycles.
4056 // SCVTF FPR -> FPR is 4 cyclces.
4057 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4058 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4059 // and still being faster.
4060 // However, this is not good for code size.
4061 // 8-bits -> float. 2 sizes step-up.
4062 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 ro_indexed8:$addr)))),
4063 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4068 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4069 (LDRBro ro_indexed8:$addr),
4074 ssub)))>, Requires<[NotForCodeSize]>;
4075 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_indexed8:$addr)))),
4076 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4081 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4082 (LDRBui am_indexed8:$addr),
4087 ssub)))>, Requires<[NotForCodeSize]>;
4088 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_unscaled8:$addr)))),
4089 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4094 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4095 (LDURBi am_unscaled8:$addr),
4100 ssub)))>, Requires<[NotForCodeSize]>;
4101 // 16-bits -> float. 1 size step-up.
4102 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
4103 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4105 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4106 (LDRHro ro_indexed16:$addr),
4109 ssub)))>, Requires<[NotForCodeSize]>;
4110 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
4111 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4113 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4114 (LDRHui am_indexed16:$addr),
4117 ssub)))>, Requires<[NotForCodeSize]>;
4118 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
4119 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4121 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4122 (LDURHi am_unscaled16:$addr),
4125 ssub)))>, Requires<[NotForCodeSize]>;
4126 // 32-bits to 32-bits are handled in target specific dag combine:
4127 // performIntToFpCombine.
4128 // 64-bits integer to 32-bits floating point, not possible with
4129 // SCVTF on floating point registers (both source and destination
4130 // must have the same size).
4132 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4133 // 8-bits -> double. 3 size step-up: give up.
4134 // 16-bits -> double. 2 size step.
4135 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
4136 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4141 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4142 (LDRHro ro_indexed16:$addr),
4147 dsub)))>, Requires<[NotForCodeSize]>;
4148 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
4149 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4154 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4155 (LDRHui am_indexed16:$addr),
4160 dsub)))>, Requires<[NotForCodeSize]>;
4161 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
4162 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4167 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4168 (LDURHi am_unscaled16:$addr),
4173 dsub)))>, Requires<[NotForCodeSize]>;
4174 // 32-bits -> double. 1 size step-up.
4175 def : Pat <(f64 (sint_to_fp (i32 (load ro_indexed32:$addr)))),
4176 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4178 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4179 (LDRSro ro_indexed32:$addr),
4182 dsub)))>, Requires<[NotForCodeSize]>;
4183 def : Pat <(f64 (sint_to_fp (i32 (load am_indexed32:$addr)))),
4184 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4186 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4187 (LDRSui am_indexed32:$addr),
4190 dsub)))>, Requires<[NotForCodeSize]>;
4191 def : Pat <(f64 (sint_to_fp (i32 (load am_unscaled32:$addr)))),
4192 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4194 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4195 (LDURSi am_unscaled32:$addr),
4198 dsub)))>, Requires<[NotForCodeSize]>;
4199 // 64-bits -> double are handled in target specific dag combine:
4200 // performIntToFpCombine.
4203 //----------------------------------------------------------------------------
4204 // AdvSIMD Load-Store Structure
4205 //----------------------------------------------------------------------------
4206 defm LD1 : SIMDLd1Multiple<"ld1">;
4207 defm LD2 : SIMDLd2Multiple<"ld2">;
4208 defm LD3 : SIMDLd3Multiple<"ld3">;
4209 defm LD4 : SIMDLd4Multiple<"ld4">;
4211 defm ST1 : SIMDSt1Multiple<"st1">;
4212 defm ST2 : SIMDSt2Multiple<"st2">;
4213 defm ST3 : SIMDSt3Multiple<"st3">;
4214 defm ST4 : SIMDSt4Multiple<"st4">;
4216 class Ld1Pat<ValueType ty, Instruction INST>
4217 : Pat<(ty (load am_simdnoindex:$vaddr)), (INST am_simdnoindex:$vaddr)>;
4219 def : Ld1Pat<v16i8, LD1Onev16b>;
4220 def : Ld1Pat<v8i16, LD1Onev8h>;
4221 def : Ld1Pat<v4i32, LD1Onev4s>;
4222 def : Ld1Pat<v2i64, LD1Onev2d>;
4223 def : Ld1Pat<v8i8, LD1Onev8b>;
4224 def : Ld1Pat<v4i16, LD1Onev4h>;
4225 def : Ld1Pat<v2i32, LD1Onev2s>;
4226 def : Ld1Pat<v1i64, LD1Onev1d>;
4228 class St1Pat<ValueType ty, Instruction INST>
4229 : Pat<(store ty:$Vt, am_simdnoindex:$vaddr),
4230 (INST ty:$Vt, am_simdnoindex:$vaddr)>;
4232 def : St1Pat<v16i8, ST1Onev16b>;
4233 def : St1Pat<v8i16, ST1Onev8h>;
4234 def : St1Pat<v4i32, ST1Onev4s>;
4235 def : St1Pat<v2i64, ST1Onev2d>;
4236 def : St1Pat<v8i8, ST1Onev8b>;
4237 def : St1Pat<v4i16, ST1Onev4h>;
4238 def : St1Pat<v2i32, ST1Onev2s>;
4239 def : St1Pat<v1i64, ST1Onev1d>;
4245 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4246 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4247 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4248 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4249 let mayLoad = 1, neverHasSideEffects = 1 in {
4250 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4251 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4252 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4253 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4254 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4255 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4256 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4257 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4258 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4259 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4260 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4261 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4262 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4263 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4264 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4265 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4268 def : Pat<(v8i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4269 (LD1Rv8b am_simdnoindex:$vaddr)>;
4270 def : Pat<(v16i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4271 (LD1Rv16b am_simdnoindex:$vaddr)>;
4272 def : Pat<(v4i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4273 (LD1Rv4h am_simdnoindex:$vaddr)>;
4274 def : Pat<(v8i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4275 (LD1Rv8h am_simdnoindex:$vaddr)>;
4276 def : Pat<(v2i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4277 (LD1Rv2s am_simdnoindex:$vaddr)>;
4278 def : Pat<(v4i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4279 (LD1Rv4s am_simdnoindex:$vaddr)>;
4280 def : Pat<(v2i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4281 (LD1Rv2d am_simdnoindex:$vaddr)>;
4282 def : Pat<(v1i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4283 (LD1Rv1d am_simdnoindex:$vaddr)>;
4284 // Grab the floating point version too
4285 def : Pat<(v2f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4286 (LD1Rv2s am_simdnoindex:$vaddr)>;
4287 def : Pat<(v4f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4288 (LD1Rv4s am_simdnoindex:$vaddr)>;
4289 def : Pat<(v2f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4290 (LD1Rv2d am_simdnoindex:$vaddr)>;
4291 def : Pat<(v1f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4292 (LD1Rv1d am_simdnoindex:$vaddr)>;
4294 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4295 ValueType VTy, ValueType STy, Instruction LD1>
4296 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4297 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4298 (LD1 VecListOne128:$Rd, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4300 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4301 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4302 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4303 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4304 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4305 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4307 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4308 ValueType VTy, ValueType STy, Instruction LD1>
4309 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4310 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4312 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4313 VecIndex:$idx, am_simdnoindex:$vaddr),
4316 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4317 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4318 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4319 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4322 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4323 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4324 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4325 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4328 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4329 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4330 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4331 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4333 let AddedComplexity = 8 in
4334 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4335 ValueType VTy, ValueType STy, Instruction ST1>
4337 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4338 am_simdnoindex:$vaddr),
4339 (ST1 VecListOne128:$Vt, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4341 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4342 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4343 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4344 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4345 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4346 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4348 let AddedComplexity = 8 in
4349 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4350 ValueType VTy, ValueType STy, Instruction ST1>
4352 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4353 am_simdnoindex:$vaddr),
4354 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4355 VecIndex:$idx, am_simdnoindex:$vaddr)>;
4357 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4358 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4359 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4360 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4362 let mayStore = 1, neverHasSideEffects = 1 in {
4363 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4364 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4365 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4366 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4367 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4368 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4369 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4370 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4371 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4372 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4373 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4374 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4377 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4378 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4379 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4380 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4382 //----------------------------------------------------------------------------
4383 // Crypto extensions
4384 //----------------------------------------------------------------------------
4386 def AESErr : AESTiedInst<0b0100, "aese", int_arm64_crypto_aese>;
4387 def AESDrr : AESTiedInst<0b0101, "aesd", int_arm64_crypto_aesd>;
4388 def AESMCrr : AESInst< 0b0110, "aesmc", int_arm64_crypto_aesmc>;
4389 def AESIMCrr : AESInst< 0b0111, "aesimc", int_arm64_crypto_aesimc>;
4391 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_arm64_crypto_sha1c>;
4392 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_arm64_crypto_sha1p>;
4393 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_arm64_crypto_sha1m>;
4394 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_arm64_crypto_sha1su0>;
4395 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_arm64_crypto_sha256h>;
4396 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_arm64_crypto_sha256h2>;
4397 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_arm64_crypto_sha256su1>;
4399 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_arm64_crypto_sha1h>;
4400 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_arm64_crypto_sha1su1>;
4401 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_arm64_crypto_sha256su0>;
4403 //----------------------------------------------------------------------------
4405 //----------------------------------------------------------------------------
4406 // FIXME: Like for X86, these should go in their own separate .td file.
4408 // Any instruction that defines a 32-bit result leaves the high half of the
4409 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4410 // be copying from a truncate. But any other 32-bit operation will zero-extend
4412 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4413 def def32 : PatLeaf<(i32 GPR32:$src), [{
4414 return N->getOpcode() != ISD::TRUNCATE &&
4415 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4416 N->getOpcode() != ISD::CopyFromReg;
4419 // In the case of a 32-bit def that is known to implicitly zero-extend,
4420 // we can use a SUBREG_TO_REG.
4421 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4423 // For an anyext, we don't care what the high bits are, so we can perform an
4424 // INSERT_SUBREF into an IMPLICIT_DEF.
4425 def : Pat<(i64 (anyext GPR32:$src)),
4426 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4428 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4429 // instruction (UBFM) on the enclosing super-reg.
4430 def : Pat<(i64 (zext GPR32:$src)),
4431 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4433 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4434 // containing super-reg.
4435 def : Pat<(i64 (sext GPR32:$src)),
4436 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4437 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4438 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4439 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4440 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4441 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4442 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4443 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4445 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4446 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4447 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4448 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4449 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4450 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4452 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4453 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4454 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4455 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4456 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4457 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4459 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4460 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4461 (i64 (i64shift_a imm0_63:$imm)),
4462 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4464 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4465 // AddedComplexity for the following patterns since we want to match sext + sra
4466 // patterns before we attempt to match a single sra node.
4467 let AddedComplexity = 20 in {
4468 // We support all sext + sra combinations which preserve at least one bit of the
4469 // original value which is to be sign extended. E.g. we support shifts up to
4471 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4472 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4473 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4474 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4476 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4477 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4478 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4479 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4481 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4482 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4483 (i64 imm0_31:$imm), 31)>;
4484 } // AddedComplexity = 20
4486 // To truncate, we can simply extract from a subregister.
4487 def : Pat<(i32 (trunc GPR64sp:$src)),
4488 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4490 // __builtin_trap() uses the BRK instruction on ARM64.
4491 def : Pat<(trap), (BRK 1)>;
4493 // Conversions within AdvSIMD types in the same register size are free.
4495 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
4496 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
4497 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
4498 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4499 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
4500 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4502 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
4503 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
4504 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
4505 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4506 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
4507 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4509 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
4510 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
4511 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
4512 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4513 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
4514 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4516 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
4517 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
4518 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
4519 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4520 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
4521 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4523 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
4524 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
4525 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
4526 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
4527 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
4528 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
4530 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
4531 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
4532 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
4533 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
4534 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
4535 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
4537 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4538 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
4539 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
4540 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
4541 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
4542 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4545 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
4546 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
4547 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
4548 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
4549 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
4551 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
4552 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
4553 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
4554 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
4555 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
4556 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
4558 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
4559 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
4560 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
4561 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
4562 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
4563 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
4565 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
4566 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
4567 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
4568 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
4569 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
4570 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
4572 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
4573 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
4574 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
4575 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
4576 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
4577 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
4579 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
4580 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
4581 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
4582 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
4583 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
4584 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
4586 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
4587 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
4588 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
4589 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
4590 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
4591 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
4593 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
4594 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4595 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
4596 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4597 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
4598 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4599 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
4600 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4602 // A 64-bit subvector insert to the first 128-bit vector position
4603 // is a subregister copy that needs no instruction.
4604 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
4605 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4606 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
4607 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4608 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
4609 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4610 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
4611 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4612 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
4613 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4614 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
4615 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4617 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
4619 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
4620 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
4621 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
4622 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
4623 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
4624 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
4625 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
4626 // so we match on v4f32 here, not v2f32. This will also catch adding
4627 // the low two lanes of a true v4f32 vector.
4628 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
4629 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
4630 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
4632 // Scalar 64-bit shifts in FPR64 registers.
4633 def : Pat<(i64 (int_arm64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4634 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4635 def : Pat<(i64 (int_arm64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4636 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4637 def : Pat<(i64 (int_arm64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4638 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4639 def : Pat<(i64 (int_arm64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4640 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4642 // Tail call return handling. These are all compiler pseudo-instructions,
4643 // so no encoding information or anything like that.
4644 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
4645 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst), []>;
4646 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst), []>;
4649 def : Pat<(ARM64tcret tcGPR64:$dst), (TCRETURNri tcGPR64:$dst)>;
4650 def : Pat<(ARM64tcret (i64 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4651 def : Pat<(ARM64tcret (i64 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4653 include "ARM64InstrAtomics.td"