1 //===- ARM64InstrInfo.td - Describe the ARM64 Instructions -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // ARM64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM Instruction Predicate Definitions.
17 def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">,
18 AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">;
19 def HasNEON : Predicate<"Subtarget->hasNEON()">,
20 AssemblerPredicate<"FeatureNEON", "neon">;
21 def HasCrypto : Predicate<"Subtarget->hasCrypto()">,
22 AssemblerPredicate<"FeatureCrypto", "crypto">;
23 def HasCRC : Predicate<"Subtarget->hasCRC()">,
24 AssemblerPredicate<"FeatureCRC", "crc">;
25 def IsLE : Predicate<"Subtarget->isLittleEndian()">;
26 def IsBE : Predicate<"!Subtarget->isLittleEndian()">;
28 //===----------------------------------------------------------------------===//
29 // ARM64-specific DAG Nodes.
32 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
33 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
36 SDTCisInt<0>, SDTCisVT<1, i32>]>;
38 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
39 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
45 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
46 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
53 def SDT_ARM64Brcond : SDTypeProfile<0, 3,
54 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
56 def SDT_ARM64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
57 def SDT_ARM64tbz : SDTypeProfile<0, 3, [SDTCisVT<0, i64>, SDTCisVT<1, i64>,
58 SDTCisVT<2, OtherVT>]>;
61 def SDT_ARM64CSel : SDTypeProfile<1, 4,
66 def SDT_ARM64FCmp : SDTypeProfile<0, 2,
69 def SDT_ARM64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
70 def SDT_ARM64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
71 def SDT_ARM64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
74 def SDT_ARM64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
75 def SDT_ARM64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
76 def SDT_ARM64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
77 SDTCisInt<2>, SDTCisInt<3>]>;
78 def SDT_ARM64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
79 def SDT_ARM64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
80 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
81 def SDT_ARM64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
83 def SDT_ARM64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
84 def SDT_ARM64fcmpz : SDTypeProfile<1, 1, []>;
85 def SDT_ARM64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
86 def SDT_ARM64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
88 def SDT_ARM64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
91 def SDT_ARM64TCRET : SDTypeProfile<0, 2, [SDTCisPtrTy<0>]>;
92 def SDT_ARM64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
94 def SDT_ARM64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
96 def SDT_ARM64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
98 def SDT_ARM64WrapperLarge : SDTypeProfile<1, 4,
99 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
100 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
101 SDTCisSameAs<1, 4>]>;
105 def ARM64adrp : SDNode<"ARM64ISD::ADRP", SDTIntUnaryOp, []>;
106 def ARM64addlow : SDNode<"ARM64ISD::ADDlow", SDTIntBinOp, []>;
107 def ARM64LOADgot : SDNode<"ARM64ISD::LOADgot", SDTIntUnaryOp>;
108 def ARM64callseq_start : SDNode<"ISD::CALLSEQ_START",
109 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
110 [SDNPHasChain, SDNPOutGlue]>;
111 def ARM64callseq_end : SDNode<"ISD::CALLSEQ_END",
112 SDCallSeqEnd<[ SDTCisVT<0, i32>,
114 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
115 def ARM64call : SDNode<"ARM64ISD::CALL",
116 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
117 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
119 def ARM64brcond : SDNode<"ARM64ISD::BRCOND", SDT_ARM64Brcond,
121 def ARM64cbz : SDNode<"ARM64ISD::CBZ", SDT_ARM64cbz,
123 def ARM64cbnz : SDNode<"ARM64ISD::CBNZ", SDT_ARM64cbz,
125 def ARM64tbz : SDNode<"ARM64ISD::TBZ", SDT_ARM64tbz,
127 def ARM64tbnz : SDNode<"ARM64ISD::TBNZ", SDT_ARM64tbz,
131 def ARM64csel : SDNode<"ARM64ISD::CSEL", SDT_ARM64CSel>;
132 def ARM64csinv : SDNode<"ARM64ISD::CSINV", SDT_ARM64CSel>;
133 def ARM64csneg : SDNode<"ARM64ISD::CSNEG", SDT_ARM64CSel>;
134 def ARM64csinc : SDNode<"ARM64ISD::CSINC", SDT_ARM64CSel>;
135 def ARM64retflag : SDNode<"ARM64ISD::RET_FLAG", SDTNone,
136 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
137 def ARM64adc : SDNode<"ARM64ISD::ADC", SDTBinaryArithWithFlagsIn >;
138 def ARM64sbc : SDNode<"ARM64ISD::SBC", SDTBinaryArithWithFlagsIn>;
139 def ARM64add_flag : SDNode<"ARM64ISD::ADDS", SDTBinaryArithWithFlagsOut,
141 def ARM64sub_flag : SDNode<"ARM64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
142 def ARM64and_flag : SDNode<"ARM64ISD::ANDS", SDTBinaryArithWithFlagsOut,
144 def ARM64adc_flag : SDNode<"ARM64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
145 def ARM64sbc_flag : SDNode<"ARM64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
147 def ARM64threadpointer : SDNode<"ARM64ISD::THREAD_POINTER", SDTPtrLeaf>;
149 def ARM64fcmp : SDNode<"ARM64ISD::FCMP", SDT_ARM64FCmp>;
151 def ARM64fmax : SDNode<"ARM64ISD::FMAX", SDTFPBinOp>;
152 def ARM64fmin : SDNode<"ARM64ISD::FMIN", SDTFPBinOp>;
154 def ARM64dup : SDNode<"ARM64ISD::DUP", SDT_ARM64Dup>;
155 def ARM64duplane8 : SDNode<"ARM64ISD::DUPLANE8", SDT_ARM64DupLane>;
156 def ARM64duplane16 : SDNode<"ARM64ISD::DUPLANE16", SDT_ARM64DupLane>;
157 def ARM64duplane32 : SDNode<"ARM64ISD::DUPLANE32", SDT_ARM64DupLane>;
158 def ARM64duplane64 : SDNode<"ARM64ISD::DUPLANE64", SDT_ARM64DupLane>;
160 def ARM64zip1 : SDNode<"ARM64ISD::ZIP1", SDT_ARM64Zip>;
161 def ARM64zip2 : SDNode<"ARM64ISD::ZIP2", SDT_ARM64Zip>;
162 def ARM64uzp1 : SDNode<"ARM64ISD::UZP1", SDT_ARM64Zip>;
163 def ARM64uzp2 : SDNode<"ARM64ISD::UZP2", SDT_ARM64Zip>;
164 def ARM64trn1 : SDNode<"ARM64ISD::TRN1", SDT_ARM64Zip>;
165 def ARM64trn2 : SDNode<"ARM64ISD::TRN2", SDT_ARM64Zip>;
167 def ARM64movi_edit : SDNode<"ARM64ISD::MOVIedit", SDT_ARM64MOVIedit>;
168 def ARM64movi_shift : SDNode<"ARM64ISD::MOVIshift", SDT_ARM64MOVIshift>;
169 def ARM64movi_msl : SDNode<"ARM64ISD::MOVImsl", SDT_ARM64MOVIshift>;
170 def ARM64mvni_shift : SDNode<"ARM64ISD::MVNIshift", SDT_ARM64MOVIshift>;
171 def ARM64mvni_msl : SDNode<"ARM64ISD::MVNImsl", SDT_ARM64MOVIshift>;
172 def ARM64movi : SDNode<"ARM64ISD::MOVI", SDT_ARM64MOVIedit>;
173 def ARM64fmov : SDNode<"ARM64ISD::FMOV", SDT_ARM64MOVIedit>;
175 def ARM64rev16 : SDNode<"ARM64ISD::REV16", SDT_ARM64UnaryVec>;
176 def ARM64rev32 : SDNode<"ARM64ISD::REV32", SDT_ARM64UnaryVec>;
177 def ARM64rev64 : SDNode<"ARM64ISD::REV64", SDT_ARM64UnaryVec>;
178 def ARM64ext : SDNode<"ARM64ISD::EXT", SDT_ARM64ExtVec>;
180 def ARM64vashr : SDNode<"ARM64ISD::VASHR", SDT_ARM64vshift>;
181 def ARM64vlshr : SDNode<"ARM64ISD::VLSHR", SDT_ARM64vshift>;
182 def ARM64vshl : SDNode<"ARM64ISD::VSHL", SDT_ARM64vshift>;
183 def ARM64sqshli : SDNode<"ARM64ISD::SQSHL_I", SDT_ARM64vshift>;
184 def ARM64uqshli : SDNode<"ARM64ISD::UQSHL_I", SDT_ARM64vshift>;
185 def ARM64sqshlui : SDNode<"ARM64ISD::SQSHLU_I", SDT_ARM64vshift>;
186 def ARM64srshri : SDNode<"ARM64ISD::SRSHR_I", SDT_ARM64vshift>;
187 def ARM64urshri : SDNode<"ARM64ISD::URSHR_I", SDT_ARM64vshift>;
189 def ARM64not: SDNode<"ARM64ISD::NOT", SDT_ARM64unvec>;
190 def ARM64bit: SDNode<"ARM64ISD::BIT", SDT_ARM64trivec>;
191 def ARM64bsl: SDNode<"ARM64ISD::BSL", SDT_ARM64trivec>;
193 def ARM64cmeq: SDNode<"ARM64ISD::CMEQ", SDT_ARM64binvec>;
194 def ARM64cmge: SDNode<"ARM64ISD::CMGE", SDT_ARM64binvec>;
195 def ARM64cmgt: SDNode<"ARM64ISD::CMGT", SDT_ARM64binvec>;
196 def ARM64cmhi: SDNode<"ARM64ISD::CMHI", SDT_ARM64binvec>;
197 def ARM64cmhs: SDNode<"ARM64ISD::CMHS", SDT_ARM64binvec>;
199 def ARM64fcmeq: SDNode<"ARM64ISD::FCMEQ", SDT_ARM64fcmp>;
200 def ARM64fcmge: SDNode<"ARM64ISD::FCMGE", SDT_ARM64fcmp>;
201 def ARM64fcmgt: SDNode<"ARM64ISD::FCMGT", SDT_ARM64fcmp>;
203 def ARM64cmeqz: SDNode<"ARM64ISD::CMEQz", SDT_ARM64unvec>;
204 def ARM64cmgez: SDNode<"ARM64ISD::CMGEz", SDT_ARM64unvec>;
205 def ARM64cmgtz: SDNode<"ARM64ISD::CMGTz", SDT_ARM64unvec>;
206 def ARM64cmlez: SDNode<"ARM64ISD::CMLEz", SDT_ARM64unvec>;
207 def ARM64cmltz: SDNode<"ARM64ISD::CMLTz", SDT_ARM64unvec>;
208 def ARM64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
209 (ARM64not (ARM64cmeqz (and node:$LHS, node:$RHS)))>;
211 def ARM64fcmeqz: SDNode<"ARM64ISD::FCMEQz", SDT_ARM64fcmpz>;
212 def ARM64fcmgez: SDNode<"ARM64ISD::FCMGEz", SDT_ARM64fcmpz>;
213 def ARM64fcmgtz: SDNode<"ARM64ISD::FCMGTz", SDT_ARM64fcmpz>;
214 def ARM64fcmlez: SDNode<"ARM64ISD::FCMLEz", SDT_ARM64fcmpz>;
215 def ARM64fcmltz: SDNode<"ARM64ISD::FCMLTz", SDT_ARM64fcmpz>;
217 def ARM64bici: SDNode<"ARM64ISD::BICi", SDT_ARM64vecimm>;
218 def ARM64orri: SDNode<"ARM64ISD::ORRi", SDT_ARM64vecimm>;
220 def ARM64neg : SDNode<"ARM64ISD::NEG", SDT_ARM64unvec>;
222 def ARM64tcret: SDNode<"ARM64ISD::TC_RETURN", SDT_ARM64TCRET,
223 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
225 def ARM64Prefetch : SDNode<"ARM64ISD::PREFETCH", SDT_ARM64PREFETCH,
226 [SDNPHasChain, SDNPSideEffect]>;
228 def ARM64sitof: SDNode<"ARM64ISD::SITOF", SDT_ARM64ITOF>;
229 def ARM64uitof: SDNode<"ARM64ISD::UITOF", SDT_ARM64ITOF>;
231 def ARM64tlsdesc_call : SDNode<"ARM64ISD::TLSDESC_CALL", SDT_ARM64TLSDescCall,
232 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
235 def ARM64WrapperLarge : SDNode<"ARM64ISD::WrapperLarge", SDT_ARM64WrapperLarge>;
238 //===----------------------------------------------------------------------===//
240 //===----------------------------------------------------------------------===//
242 // ARM64 Instruction Predicate Definitions.
244 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
245 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
246 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
247 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
248 def ForCodeSize : Predicate<"ForCodeSize">;
249 def NotForCodeSize : Predicate<"!ForCodeSize">;
251 include "ARM64InstrFormats.td"
253 //===----------------------------------------------------------------------===//
255 //===----------------------------------------------------------------------===//
256 // Miscellaneous instructions.
257 //===----------------------------------------------------------------------===//
259 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
260 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
261 [(ARM64callseq_start timm:$amt)]>;
262 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
263 [(ARM64callseq_end timm:$amt1, timm:$amt2)]>;
264 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
266 let isReMaterializable = 1, isCodeGenOnly = 1 in {
267 // FIXME: The following pseudo instructions are only needed because remat
268 // cannot handle multiple instructions. When that changes, they can be
269 // removed, along with the ARM64Wrapper node.
271 let AddedComplexity = 10 in
272 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
273 [(set GPR64:$dst, (ARM64LOADgot tglobaladdr:$addr))]>,
276 // The MOVaddr instruction should match only when the add is not folded
277 // into a load or store address.
279 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
280 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaladdr:$hi),
281 tglobaladdr:$low))]>,
282 Sched<[WriteAdrAdr]>;
284 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
285 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tjumptable:$hi),
287 Sched<[WriteAdrAdr]>;
289 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
290 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tconstpool:$hi),
292 Sched<[WriteAdrAdr]>;
294 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
295 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tblockaddress:$hi),
296 tblockaddress:$low))]>,
297 Sched<[WriteAdrAdr]>;
299 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
300 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaltlsaddr:$hi),
301 tglobaltlsaddr:$low))]>,
302 Sched<[WriteAdrAdr]>;
304 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
305 [(set GPR64:$dst, (ARM64addlow (ARM64adrp texternalsym:$hi),
306 texternalsym:$low))]>,
307 Sched<[WriteAdrAdr]>;
309 } // isReMaterializable, isCodeGenOnly
311 def : Pat<(ARM64LOADgot tglobaltlsaddr:$addr),
312 (LOADgot tglobaltlsaddr:$addr)>;
314 def : Pat<(ARM64LOADgot texternalsym:$addr),
315 (LOADgot texternalsym:$addr)>;
317 def : Pat<(ARM64LOADgot tconstpool:$addr),
318 (LOADgot tconstpool:$addr)>;
320 //===----------------------------------------------------------------------===//
321 // System instructions.
322 //===----------------------------------------------------------------------===//
324 def HINT : HintI<"hint">;
325 def : InstAlias<"nop", (HINT 0b000)>;
326 def : InstAlias<"yield",(HINT 0b001)>;
327 def : InstAlias<"wfe", (HINT 0b010)>;
328 def : InstAlias<"wfi", (HINT 0b011)>;
329 def : InstAlias<"sev", (HINT 0b100)>;
330 def : InstAlias<"sevl", (HINT 0b101)>;
332 // As far as LLVM is concerned this writes to the system's exclusive monitors.
333 let mayLoad = 1, mayStore = 1 in
334 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
336 def DMB : CRmSystemI<barrier_op, 0b101, "dmb">;
337 def DSB : CRmSystemI<barrier_op, 0b100, "dsb">;
338 def ISB : CRmSystemI<barrier_op, 0b110, "isb">;
339 def : InstAlias<"clrex", (CLREX 0xf)>;
340 def : InstAlias<"isb", (ISB 0xf)>;
344 def MSRpstate: MSRpstateI;
346 // The thread pointer (on Linux, at least, where this has been implemented) is
348 def : Pat<(ARM64threadpointer), (MRS 0xde82)>;
350 // Generic system instructions
351 def SYSxt : SystemXtI<0, "sys">;
352 def SYSLxt : SystemLXtI<1, "sysl">;
354 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
355 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
356 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
358 //===----------------------------------------------------------------------===//
359 // Move immediate instructions.
360 //===----------------------------------------------------------------------===//
362 defm MOVK : InsertImmediate<0b11, "movk">;
363 defm MOVN : MoveImmediate<0b00, "movn">;
365 let PostEncoderMethod = "fixMOVZ" in
366 defm MOVZ : MoveImmediate<0b10, "movz">;
368 // First group of aliases covers an implicit "lsl #0".
369 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
370 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
371 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
372 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
373 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
374 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
376 // Next, we have various ELF relocations with the ":XYZ_g0:sym" syntax.
377 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
378 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
379 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
380 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
382 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
383 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
384 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
385 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
387 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g3:$sym, 48)>;
388 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
389 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
390 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
392 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
393 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
395 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
396 def : InstAlias<"movn $Rd, $sym", (MOVNWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
398 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
399 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
401 // Final group of aliases covers true "mov $Rd, $imm" cases.
402 multiclass movw_mov_alias<string basename,Instruction INST, RegisterClass GPR,
403 int width, int shift> {
404 def _asmoperand : AsmOperandClass {
405 let Name = basename # width # "_lsl" # shift # "MovAlias";
406 let PredicateMethod = "is" # basename # "MovAlias<" # width # ", "
408 let RenderMethod = "add" # basename # "MovAliasOperands<" # shift # ">";
411 def _movimm : Operand<i32> {
412 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_asmoperand");
415 def : InstAlias<"mov $Rd, $imm",
416 (INST GPR:$Rd, !cast<Operand>(NAME # "_movimm"):$imm, shift)>;
419 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 0>;
420 defm : movw_mov_alias<"MOVZ", MOVZWi, GPR32, 32, 16>;
422 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 0>;
423 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 16>;
424 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 32>;
425 defm : movw_mov_alias<"MOVZ", MOVZXi, GPR64, 64, 48>;
427 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 0>;
428 defm : movw_mov_alias<"MOVN", MOVNWi, GPR32, 32, 16>;
430 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 0>;
431 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 16>;
432 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 32>;
433 defm : movw_mov_alias<"MOVN", MOVNXi, GPR64, 64, 48>;
435 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
436 isAsCheapAsAMove = 1 in {
437 // FIXME: The following pseudo instructions are only needed because remat
438 // cannot handle multiple instructions. When that changes, we can select
439 // directly to the real instructions and get rid of these pseudos.
442 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
443 [(set GPR32:$dst, imm:$src)]>,
446 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
447 [(set GPR64:$dst, imm:$src)]>,
449 } // isReMaterializable, isCodeGenOnly
451 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
452 // eventual expansion code fewer bits to worry about getting right. Marshalling
453 // the types is a little tricky though:
454 def i64imm_32bit : ImmLeaf<i64, [{
455 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
458 def trunc_imm : SDNodeXForm<imm, [{
459 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
462 def : Pat<(i64 i64imm_32bit:$src),
463 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
465 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
467 def : Pat<(ARM64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
468 tglobaladdr:$g1, tglobaladdr:$g0),
469 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
470 tglobaladdr:$g2, 32),
471 tglobaladdr:$g1, 16),
472 tglobaladdr:$g0, 0)>;
474 def : Pat<(ARM64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
475 tblockaddress:$g1, tblockaddress:$g0),
476 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
477 tblockaddress:$g2, 32),
478 tblockaddress:$g1, 16),
479 tblockaddress:$g0, 0)>;
481 def : Pat<(ARM64WrapperLarge tconstpool:$g3, tconstpool:$g2,
482 tconstpool:$g1, tconstpool:$g0),
483 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
488 def : Pat<(ARM64WrapperLarge tjumptable:$g3, tjumptable:$g2,
489 tjumptable:$g1, tjumptable:$g0),
490 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
496 //===----------------------------------------------------------------------===//
497 // Arithmetic instructions.
498 //===----------------------------------------------------------------------===//
500 // Add/subtract with carry.
501 defm ADC : AddSubCarry<0, "adc", "adcs", ARM64adc, ARM64adc_flag>;
502 defm SBC : AddSubCarry<1, "sbc", "sbcs", ARM64sbc, ARM64sbc_flag>;
504 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
505 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
506 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
507 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
510 defm ADD : AddSub<0, "add", add>;
511 defm SUB : AddSub<1, "sub">;
513 def : InstAlias<"mov $dst, $src",
514 (ADDWri GPR32sponly:$dst, GPR32sp:$src, 0, 0)>;
515 def : InstAlias<"mov $dst, $src",
516 (ADDWri GPR32sp:$dst, GPR32sponly:$src, 0, 0)>;
517 def : InstAlias<"mov $dst, $src",
518 (ADDXri GPR64sponly:$dst, GPR64sp:$src, 0, 0)>;
519 def : InstAlias<"mov $dst, $src",
520 (ADDXri GPR64sp:$dst, GPR64sponly:$src, 0, 0)>;
522 defm ADDS : AddSubS<0, "adds", ARM64add_flag, "cmn">;
523 defm SUBS : AddSubS<1, "subs", ARM64sub_flag, "cmp">;
525 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
526 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
527 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
528 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
529 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
530 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
531 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
532 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
533 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
534 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
535 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
536 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
537 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
538 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
539 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
540 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
541 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
543 // Because of the immediate format for add/sub-imm instructions, the
544 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
545 // These patterns capture that transformation.
546 let AddedComplexity = 1 in {
547 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
548 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
549 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
550 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
551 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
552 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
553 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
554 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
557 // FIXME: TableGen can very nearly handle printing all of these, we should make
559 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
560 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
561 def : InstAlias<"neg $dst, $src, $shift",
562 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift)>;
563 def : InstAlias<"neg $dst, $src, $shift",
564 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift)>;
566 // Because of the immediate format for add/sub-imm instructions, the
567 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
568 // These patterns capture that transformation.
569 let AddedComplexity = 1 in {
570 def : Pat<(ARM64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
571 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
572 def : Pat<(ARM64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
573 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
574 def : Pat<(ARM64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
575 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
576 def : Pat<(ARM64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
577 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
580 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
581 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
582 def : InstAlias<"negs $dst, $src, $shift",
583 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift32:$shift)>;
584 def : InstAlias<"negs $dst, $src, $shift",
585 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift64:$shift)>;
587 // Unsigned/Signed divide
588 defm UDIV : Div<0, "udiv", udiv>;
589 defm SDIV : Div<1, "sdiv", sdiv>;
590 let isCodeGenOnly = 1 in {
591 defm UDIV_Int : Div<0, "udiv", int_arm64_udiv>;
592 defm SDIV_Int : Div<1, "sdiv", int_arm64_sdiv>;
596 defm ASRV : Shift<0b10, "asr", sra>;
597 defm LSLV : Shift<0b00, "lsl", shl>;
598 defm LSRV : Shift<0b01, "lsr", srl>;
599 defm RORV : Shift<0b11, "ror", rotr>;
601 def : ShiftAlias<"asrv", ASRVWr, GPR32>;
602 def : ShiftAlias<"asrv", ASRVXr, GPR64>;
603 def : ShiftAlias<"lslv", LSLVWr, GPR32>;
604 def : ShiftAlias<"lslv", LSLVXr, GPR64>;
605 def : ShiftAlias<"lsrv", LSRVWr, GPR32>;
606 def : ShiftAlias<"lsrv", LSRVXr, GPR64>;
607 def : ShiftAlias<"rorv", RORVWr, GPR32>;
608 def : ShiftAlias<"rorv", RORVXr, GPR64>;
611 let AddedComplexity = 7 in {
612 defm MADD : MulAccum<0, "madd", add>;
613 defm MSUB : MulAccum<1, "msub", sub>;
615 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
616 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
617 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
618 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
620 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
621 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
622 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
623 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
624 } // AddedComplexity = 7
626 let AddedComplexity = 5 in {
627 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
628 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
629 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
630 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
632 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
633 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
634 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
635 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
637 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
638 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
639 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
640 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
641 } // AddedComplexity = 5
643 def : MulAccumWAlias<"mul", MADDWrrr>;
644 def : MulAccumXAlias<"mul", MADDXrrr>;
645 def : MulAccumWAlias<"mneg", MSUBWrrr>;
646 def : MulAccumXAlias<"mneg", MSUBXrrr>;
647 def : WideMulAccumAlias<"smull", SMADDLrrr>;
648 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
649 def : WideMulAccumAlias<"umull", UMADDLrrr>;
650 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
653 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
654 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
657 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_arm64_crc32b, "crc32b">;
658 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_arm64_crc32h, "crc32h">;
659 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_arm64_crc32w, "crc32w">;
660 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_arm64_crc32x, "crc32x">;
662 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_arm64_crc32cb, "crc32cb">;
663 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_arm64_crc32ch, "crc32ch">;
664 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_arm64_crc32cw, "crc32cw">;
665 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_arm64_crc32cx, "crc32cx">;
668 //===----------------------------------------------------------------------===//
669 // Logical instructions.
670 //===----------------------------------------------------------------------===//
673 defm ANDS : LogicalImmS<0b11, "ands", ARM64and_flag>;
674 defm AND : LogicalImm<0b00, "and", and>;
675 defm EOR : LogicalImm<0b10, "eor", xor>;
676 defm ORR : LogicalImm<0b01, "orr", or>;
678 // FIXME: these aliases *are* canonical sometimes (when movz can't be
679 // used). Actually, it seems to be working right now, but putting logical_immXX
680 // here is a bit dodgy on the AsmParser side too.
681 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
682 logical_imm32:$imm), 0>;
683 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
684 logical_imm64:$imm), 0>;
688 defm ANDS : LogicalRegS<0b11, 0, "ands", ARM64and_flag>;
689 defm BICS : LogicalRegS<0b11, 1, "bics",
690 BinOpFrag<(ARM64and_flag node:$LHS, (not node:$RHS))>>;
691 defm AND : LogicalReg<0b00, 0, "and", and>;
692 defm BIC : LogicalReg<0b00, 1, "bic",
693 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
694 defm EON : LogicalReg<0b10, 1, "eon",
695 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
696 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
697 defm ORN : LogicalReg<0b01, 1, "orn",
698 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
699 defm ORR : LogicalReg<0b01, 0, "orr", or>;
701 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
702 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
704 def : InstAlias<"tst $src1, $src2",
705 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
706 def : InstAlias<"tst $src1, $src2",
707 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>;
709 def : InstAlias<"tst $src1, $src2",
710 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>;
711 def : InstAlias<"tst $src1, $src2",
712 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>;
714 def : InstAlias<"tst $src1, $src2, $sh",
715 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift32:$sh)>;
716 def : InstAlias<"tst $src1, $src2, $sh",
717 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift64:$sh)>;
719 def : InstAlias<"mvn $Wd, $Wm",
720 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0)>;
721 def : InstAlias<"mvn $Xd, $Xm",
722 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>;
724 def : InstAlias<"mvn $Wd, $Wm, $sh",
725 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift32:$sh)>;
726 def : InstAlias<"mvn $Xd, $Xm, $sh",
727 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift64:$sh)>;
729 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
730 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
733 //===----------------------------------------------------------------------===//
734 // One operand data processing instructions.
735 //===----------------------------------------------------------------------===//
737 defm CLS : OneOperandData<0b101, "cls">;
738 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
739 defm RBIT : OneOperandData<0b000, "rbit">;
740 def REV16Wr : OneWRegData<0b001, "rev16",
741 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
742 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
744 def : Pat<(cttz GPR32:$Rn),
745 (CLZWr (RBITWr GPR32:$Rn))>;
746 def : Pat<(cttz GPR64:$Rn),
747 (CLZXr (RBITXr GPR64:$Rn))>;
748 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
751 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
755 // Unlike the other one operand instructions, the instructions with the "rev"
756 // mnemonic do *not* just different in the size bit, but actually use different
757 // opcode bits for the different sizes.
758 def REVWr : OneWRegData<0b010, "rev", bswap>;
759 def REVXr : OneXRegData<0b011, "rev", bswap>;
760 def REV32Xr : OneXRegData<0b010, "rev32",
761 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
763 // The bswap commutes with the rotr so we want a pattern for both possible
765 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
766 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
768 //===----------------------------------------------------------------------===//
769 // Bitfield immediate extraction instruction.
770 //===----------------------------------------------------------------------===//
771 let neverHasSideEffects = 1 in
772 defm EXTR : ExtractImm<"extr">;
773 def : InstAlias<"ror $dst, $src, $shift",
774 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
775 def : InstAlias<"ror $dst, $src, $shift",
776 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
778 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
779 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
780 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
781 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
783 //===----------------------------------------------------------------------===//
784 // Other bitfield immediate instructions.
785 //===----------------------------------------------------------------------===//
786 let neverHasSideEffects = 1 in {
787 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
788 defm SBFM : BitfieldImm<0b00, "sbfm">;
789 defm UBFM : BitfieldImm<0b10, "ubfm">;
792 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
793 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
794 return CurDAG->getTargetConstant(enc, MVT::i64);
797 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
798 uint64_t enc = 31 - N->getZExtValue();
799 return CurDAG->getTargetConstant(enc, MVT::i64);
802 // min(7, 31 - shift_amt)
803 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
804 uint64_t enc = 31 - N->getZExtValue();
805 enc = enc > 7 ? 7 : enc;
806 return CurDAG->getTargetConstant(enc, MVT::i64);
809 // min(15, 31 - shift_amt)
810 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
811 uint64_t enc = 31 - N->getZExtValue();
812 enc = enc > 15 ? 15 : enc;
813 return CurDAG->getTargetConstant(enc, MVT::i64);
816 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
817 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
818 return CurDAG->getTargetConstant(enc, MVT::i64);
821 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
822 uint64_t enc = 63 - N->getZExtValue();
823 return CurDAG->getTargetConstant(enc, MVT::i64);
826 // min(7, 63 - shift_amt)
827 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
828 uint64_t enc = 63 - N->getZExtValue();
829 enc = enc > 7 ? 7 : enc;
830 return CurDAG->getTargetConstant(enc, MVT::i64);
833 // min(15, 63 - shift_amt)
834 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
835 uint64_t enc = 63 - N->getZExtValue();
836 enc = enc > 15 ? 15 : enc;
837 return CurDAG->getTargetConstant(enc, MVT::i64);
840 // min(31, 63 - shift_amt)
841 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
842 uint64_t enc = 63 - N->getZExtValue();
843 enc = enc > 31 ? 31 : enc;
844 return CurDAG->getTargetConstant(enc, MVT::i64);
847 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
848 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
849 (i64 (i32shift_b imm0_31:$imm)))>;
850 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
851 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
852 (i64 (i64shift_b imm0_63:$imm)))>;
854 let AddedComplexity = 10 in {
855 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
856 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
857 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
858 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
861 def : InstAlias<"asr $dst, $src, $shift",
862 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
863 def : InstAlias<"asr $dst, $src, $shift",
864 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
865 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
866 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
867 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
868 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
869 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
871 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
872 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
873 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
874 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
876 def : InstAlias<"lsr $dst, $src, $shift",
877 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
878 def : InstAlias<"lsr $dst, $src, $shift",
879 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
880 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
881 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
882 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
883 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
884 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
886 //===----------------------------------------------------------------------===//
887 // Conditionally set flags instructions.
888 //===----------------------------------------------------------------------===//
889 defm CCMN : CondSetFlagsImm<0, "ccmn">;
890 defm CCMP : CondSetFlagsImm<1, "ccmp">;
892 defm CCMN : CondSetFlagsReg<0, "ccmn">;
893 defm CCMP : CondSetFlagsReg<1, "ccmp">;
895 //===----------------------------------------------------------------------===//
896 // Conditional select instructions.
897 //===----------------------------------------------------------------------===//
898 defm CSEL : CondSelect<0, 0b00, "csel">;
900 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
901 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
902 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
903 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
905 def : Pat<(ARM64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
906 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
907 def : Pat<(ARM64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
908 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
909 def : Pat<(ARM64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
910 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
911 def : Pat<(ARM64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
912 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
913 def : Pat<(ARM64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), NZCV),
914 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
915 def : Pat<(ARM64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), NZCV),
916 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
918 def : Pat<(ARM64csel (i32 0), (i32 1), (i32 imm:$cc), NZCV),
919 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
920 def : Pat<(ARM64csel (i64 0), (i64 1), (i32 imm:$cc), NZCV),
921 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
922 def : Pat<(ARM64csel (i32 0), (i32 -1), (i32 imm:$cc), NZCV),
923 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
924 def : Pat<(ARM64csel (i64 0), (i64 -1), (i32 imm:$cc), NZCV),
925 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
927 // The inverse of the condition code from the alias instruction is what is used
928 // in the aliased instruction. The parser all ready inverts the condition code
929 // for these aliases.
930 def : InstAlias<"cset $dst, $cc",
931 (CSINCWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
932 def : InstAlias<"cset $dst, $cc",
933 (CSINCXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
935 def : InstAlias<"csetm $dst, $cc",
936 (CSINVWr GPR32:$dst, WZR, WZR, inv_ccode:$cc)>;
937 def : InstAlias<"csetm $dst, $cc",
938 (CSINVXr GPR64:$dst, XZR, XZR, inv_ccode:$cc)>;
940 def : InstAlias<"cinc $dst, $src, $cc",
941 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
942 def : InstAlias<"cinc $dst, $src, $cc",
943 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
945 def : InstAlias<"cinv $dst, $src, $cc",
946 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
947 def : InstAlias<"cinv $dst, $src, $cc",
948 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
950 def : InstAlias<"cneg $dst, $src, $cc",
951 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, inv_ccode:$cc)>;
952 def : InstAlias<"cneg $dst, $src, $cc",
953 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, inv_ccode:$cc)>;
955 //===----------------------------------------------------------------------===//
956 // PC-relative instructions.
957 //===----------------------------------------------------------------------===//
958 let isReMaterializable = 1 in {
959 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
960 def ADR : ADRI<0, "adr", adrlabel, []>;
961 } // neverHasSideEffects = 1
963 def ADRP : ADRI<1, "adrp", adrplabel,
964 [(set GPR64:$Xd, (ARM64adrp tglobaladdr:$label))]>;
965 } // isReMaterializable = 1
967 // page address of a constant pool entry, block address
968 def : Pat<(ARM64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
969 def : Pat<(ARM64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
971 //===----------------------------------------------------------------------===//
972 // Unconditional branch (register) instructions.
973 //===----------------------------------------------------------------------===//
975 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
976 def RET : BranchReg<0b0010, "ret", []>;
977 def DRPS : SpecialReturn<0b0101, "drps">;
978 def ERET : SpecialReturn<0b0100, "eret">;
979 } // isReturn = 1, isTerminator = 1, isBarrier = 1
981 // Default to the LR register.
982 def : InstAlias<"ret", (RET LR)>;
984 let isCall = 1, Defs = [LR], Uses = [SP] in {
985 def BLR : BranchReg<0b0001, "blr", [(ARM64call GPR64:$Rn)]>;
988 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
989 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
990 } // isBranch, isTerminator, isBarrier, isIndirectBranch
992 // Create a separate pseudo-instruction for codegen to use so that we don't
993 // flag lr as used in every function. It'll be restored before the RET by the
994 // epilogue if it's legitimately used.
995 def RET_ReallyLR : Pseudo<(outs), (ins), [(ARM64retflag)]> {
996 let isTerminator = 1;
1001 // This is a directive-like pseudo-instruction. The purpose is to insert an
1002 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
1003 // (which in the usual case is a BLR).
1004 let hasSideEffects = 1 in
1005 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
1006 let AsmString = ".tlsdesccall $sym";
1009 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
1010 // gets expanded to two MCInsts during lowering.
1011 let isCall = 1, Defs = [LR] in
1013 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
1014 [(ARM64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
1016 def : Pat<(ARM64tlsdesc_call GPR64:$dest, texternalsym:$sym),
1017 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
1018 //===----------------------------------------------------------------------===//
1019 // Conditional branch (immediate) instruction.
1020 //===----------------------------------------------------------------------===//
1021 def Bcc : BranchCond;
1023 //===----------------------------------------------------------------------===//
1024 // Compare-and-branch instructions.
1025 //===----------------------------------------------------------------------===//
1026 defm CBZ : CmpBranch<0, "cbz", ARM64cbz>;
1027 defm CBNZ : CmpBranch<1, "cbnz", ARM64cbnz>;
1029 //===----------------------------------------------------------------------===//
1030 // Test-bit-and-branch instructions.
1031 //===----------------------------------------------------------------------===//
1032 def TBZ : TestBranch<0, "tbz", ARM64tbz>;
1033 def TBNZ : TestBranch<1, "tbnz", ARM64tbnz>;
1035 //===----------------------------------------------------------------------===//
1036 // Unconditional branch (immediate) instructions.
1037 //===----------------------------------------------------------------------===//
1038 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
1039 def B : BranchImm<0, "b", [(br bb:$addr)]>;
1040 } // isBranch, isTerminator, isBarrier
1042 let isCall = 1, Defs = [LR], Uses = [SP] in {
1043 def BL : CallImm<1, "bl", [(ARM64call tglobaladdr:$addr)]>;
1045 def : Pat<(ARM64call texternalsym:$func), (BL texternalsym:$func)>;
1047 //===----------------------------------------------------------------------===//
1048 // Exception generation instructions.
1049 //===----------------------------------------------------------------------===//
1050 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
1051 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
1052 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
1053 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
1054 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
1055 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
1056 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
1057 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
1059 // DCPSn defaults to an immediate operand of zero if unspecified.
1060 def : InstAlias<"dcps1", (DCPS1 0)>;
1061 def : InstAlias<"dcps2", (DCPS2 0)>;
1062 def : InstAlias<"dcps3", (DCPS3 0)>;
1064 //===----------------------------------------------------------------------===//
1065 // Load instructions.
1066 //===----------------------------------------------------------------------===//
1068 // Pair (indexed, offset)
1069 def LDPWi : LoadPairOffset<0b00, 0, GPR32, am_indexed32simm7, "ldp">;
1070 def LDPXi : LoadPairOffset<0b10, 0, GPR64, am_indexed64simm7, "ldp">;
1071 def LDPSi : LoadPairOffset<0b00, 1, FPR32, am_indexed32simm7, "ldp">;
1072 def LDPDi : LoadPairOffset<0b01, 1, FPR64, am_indexed64simm7, "ldp">;
1073 def LDPQi : LoadPairOffset<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
1075 def LDPSWi : LoadPairOffset<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
1077 // Pair (pre-indexed)
1078 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "ldp">;
1079 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "ldp">;
1080 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "ldp">;
1081 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "ldp">;
1082 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "ldp">;
1084 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7_wb, "ldpsw">;
1086 // Pair (post-indexed)
1087 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1088 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1089 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1090 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1091 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1093 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1096 // Pair (no allocate)
1097 def LDNPWi : LoadPairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "ldnp">;
1098 def LDNPXi : LoadPairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "ldnp">;
1099 def LDNPSi : LoadPairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "ldnp">;
1100 def LDNPDi : LoadPairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "ldnp">;
1101 def LDNPQi : LoadPairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "ldnp">;
1104 // (register offset)
1107 let AddedComplexity = 10 in {
1109 def LDRBBro : Load8RO<0b00, 0, 0b01, GPR32, "ldrb",
1110 [(set GPR32:$Rt, (zextloadi8 ro_indexed8:$addr))]>;
1111 def LDRHHro : Load16RO<0b01, 0, 0b01, GPR32, "ldrh",
1112 [(set GPR32:$Rt, (zextloadi16 ro_indexed16:$addr))]>;
1113 def LDRWro : Load32RO<0b10, 0, 0b01, GPR32, "ldr",
1114 [(set GPR32:$Rt, (load ro_indexed32:$addr))]>;
1115 def LDRXro : Load64RO<0b11, 0, 0b01, GPR64, "ldr",
1116 [(set GPR64:$Rt, (load ro_indexed64:$addr))]>;
1119 def LDRBro : Load8RO<0b00, 1, 0b01, FPR8, "ldr",
1120 [(set FPR8:$Rt, (load ro_indexed8:$addr))]>;
1121 def LDRHro : Load16RO<0b01, 1, 0b01, FPR16, "ldr",
1122 [(set (f16 FPR16:$Rt), (load ro_indexed16:$addr))]>;
1123 def LDRSro : Load32RO<0b10, 1, 0b01, FPR32, "ldr",
1124 [(set (f32 FPR32:$Rt), (load ro_indexed32:$addr))]>;
1125 def LDRDro : Load64RO<0b11, 1, 0b01, FPR64, "ldr",
1126 [(set (f64 FPR64:$Rt), (load ro_indexed64:$addr))]>;
1127 def LDRQro : Load128RO<0b00, 1, 0b11, FPR128, "ldr", []> {
1131 // For regular load, we do not have any alignment requirement.
1132 // Thus, it is safe to directly map the vector loads with interesting
1133 // addressing modes.
1134 // FIXME: We could do the same for bitconvert to floating point vectors.
1135 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1136 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1137 (LDRBro ro_indexed8:$addr), bsub)>;
1138 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1139 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1140 (LDRBro ro_indexed8:$addr), bsub)>;
1141 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1142 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1143 (LDRHro ro_indexed16:$addr), hsub)>;
1144 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1145 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1146 (LDRHro ro_indexed16:$addr), hsub)>;
1147 def : Pat <(v2i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1148 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1149 (LDRSro ro_indexed32:$addr), ssub)>;
1150 def : Pat <(v4i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1151 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1152 (LDRSro ro_indexed32:$addr), ssub)>;
1153 def : Pat <(v1i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1154 (LDRDro ro_indexed64:$addr)>;
1155 def : Pat <(v2i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1156 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1157 (LDRDro ro_indexed64:$addr), dsub)>;
1159 // Match all load 64 bits width whose type is compatible with FPR64
1160 let Predicates = [IsLE] in {
1161 // We must do vector loads with LD1 in big-endian.
1162 def : Pat<(v2f32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1163 def : Pat<(v8i8 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1164 def : Pat<(v4i16 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1165 def : Pat<(v2i32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1167 def : Pat<(v1f64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1168 def : Pat<(v1i64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1170 // Match all load 128 bits width whose type is compatible with FPR128
1171 let Predicates = [IsLE] in {
1172 // We must do vector loads with LD1 in big-endian.
1173 def : Pat<(v4f32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1174 def : Pat<(v2f64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1175 def : Pat<(v16i8 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1176 def : Pat<(v8i16 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1177 def : Pat<(v4i32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1178 def : Pat<(v2i64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1180 def : Pat<(f128 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1182 // Load sign-extended half-word
1183 def LDRSHWro : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh",
1184 [(set GPR32:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1185 def LDRSHXro : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh",
1186 [(set GPR64:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1188 // Load sign-extended byte
1189 def LDRSBWro : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb",
1190 [(set GPR32:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1191 def LDRSBXro : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb",
1192 [(set GPR64:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1194 // Load sign-extended word
1195 def LDRSWro : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw",
1196 [(set GPR64:$Rt, (sextloadi32 ro_indexed32:$addr))]>;
1199 def PRFMro : PrefetchRO<0b11, 0, 0b10, "prfm",
1200 [(ARM64Prefetch imm:$Rt, ro_indexed64:$addr)]>;
1203 def : Pat<(i64 (zextloadi8 ro_indexed8:$addr)),
1204 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1205 def : Pat<(i64 (zextloadi16 ro_indexed16:$addr)),
1206 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1207 def : Pat<(i64 (zextloadi32 ro_indexed32:$addr)),
1208 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1210 // zextloadi1 -> zextloadi8
1211 def : Pat<(i32 (zextloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1212 def : Pat<(i64 (zextloadi1 ro_indexed8:$addr)),
1213 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1215 // extload -> zextload
1216 def : Pat<(i32 (extloadi16 ro_indexed16:$addr)), (LDRHHro ro_indexed16:$addr)>;
1217 def : Pat<(i32 (extloadi8 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1218 def : Pat<(i32 (extloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1219 def : Pat<(i64 (extloadi32 ro_indexed32:$addr)),
1220 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1221 def : Pat<(i64 (extloadi16 ro_indexed16:$addr)),
1222 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1223 def : Pat<(i64 (extloadi8 ro_indexed8:$addr)),
1224 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1225 def : Pat<(i64 (extloadi1 ro_indexed8:$addr)),
1226 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1228 } // AddedComplexity = 10
1231 // (unsigned immediate)
1233 def LDRXui : LoadUI<0b11, 0, 0b01, GPR64, am_indexed64, "ldr",
1234 [(set GPR64:$Rt, (load am_indexed64:$addr))]>;
1235 def LDRWui : LoadUI<0b10, 0, 0b01, GPR32, am_indexed32, "ldr",
1236 [(set GPR32:$Rt, (load am_indexed32:$addr))]>;
1237 def LDRBui : LoadUI<0b00, 1, 0b01, FPR8, am_indexed8, "ldr",
1238 [(set FPR8:$Rt, (load am_indexed8:$addr))]>;
1239 def LDRHui : LoadUI<0b01, 1, 0b01, FPR16, am_indexed16, "ldr",
1240 [(set (f16 FPR16:$Rt), (load am_indexed16:$addr))]>;
1241 def LDRSui : LoadUI<0b10, 1, 0b01, FPR32, am_indexed32, "ldr",
1242 [(set (f32 FPR32:$Rt), (load am_indexed32:$addr))]>;
1243 def LDRDui : LoadUI<0b11, 1, 0b01, FPR64, am_indexed64, "ldr",
1244 [(set (f64 FPR64:$Rt), (load am_indexed64:$addr))]>;
1245 def LDRQui : LoadUI<0b00, 1, 0b11, FPR128, am_indexed128, "ldr",
1246 [(set (f128 FPR128:$Rt), (load am_indexed128:$addr))]>;
1248 // For regular load, we do not have any alignment requirement.
1249 // Thus, it is safe to directly map the vector loads with interesting
1250 // addressing modes.
1251 // FIXME: We could do the same for bitconvert to floating point vectors.
1252 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1253 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1254 (LDRBui am_indexed8:$addr), bsub)>;
1255 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1256 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1257 (LDRBui am_indexed8:$addr), bsub)>;
1258 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1259 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1260 (LDRHui am_indexed16:$addr), hsub)>;
1261 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1262 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1263 (LDRHui am_indexed16:$addr), hsub)>;
1264 def : Pat <(v2i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1265 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1266 (LDRSui am_indexed32:$addr), ssub)>;
1267 def : Pat <(v4i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1268 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1269 (LDRSui am_indexed32:$addr), ssub)>;
1270 def : Pat <(v1i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1271 (LDRDui am_indexed64:$addr)>;
1272 def : Pat <(v2i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1273 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1274 (LDRDui am_indexed64:$addr), dsub)>;
1276 // Match all load 64 bits width whose type is compatible with FPR64
1277 let Predicates = [IsLE] in {
1278 // We must use LD1 to perform vector loads in big-endian.
1279 def : Pat<(v2f32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1280 def : Pat<(v8i8 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1281 def : Pat<(v4i16 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1282 def : Pat<(v2i32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1284 def : Pat<(v1f64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1285 def : Pat<(v1i64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1287 // Match all load 128 bits width whose type is compatible with FPR128
1288 let Predicates = [IsLE] in {
1289 // We must use LD1 to perform vector loads in big-endian.
1290 def : Pat<(v4f32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1291 def : Pat<(v2f64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1292 def : Pat<(v16i8 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1293 def : Pat<(v8i16 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1294 def : Pat<(v4i32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1295 def : Pat<(v2i64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1297 def : Pat<(f128 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1299 def LDRHHui : LoadUI<0b01, 0, 0b01, GPR32, am_indexed16, "ldrh",
1300 [(set GPR32:$Rt, (zextloadi16 am_indexed16:$addr))]>;
1301 def LDRBBui : LoadUI<0b00, 0, 0b01, GPR32, am_indexed8, "ldrb",
1302 [(set GPR32:$Rt, (zextloadi8 am_indexed8:$addr))]>;
1304 def : Pat<(i64 (zextloadi8 am_indexed8:$addr)),
1305 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1306 def : Pat<(i64 (zextloadi16 am_indexed16:$addr)),
1307 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1309 // zextloadi1 -> zextloadi8
1310 def : Pat<(i32 (zextloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1311 def : Pat<(i64 (zextloadi1 am_indexed8:$addr)),
1312 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1314 // extload -> zextload
1315 def : Pat<(i32 (extloadi16 am_indexed16:$addr)), (LDRHHui am_indexed16:$addr)>;
1316 def : Pat<(i32 (extloadi8 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1317 def : Pat<(i32 (extloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1318 def : Pat<(i64 (extloadi32 am_indexed32:$addr)),
1319 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1320 def : Pat<(i64 (extloadi16 am_indexed16:$addr)),
1321 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1322 def : Pat<(i64 (extloadi8 am_indexed8:$addr)),
1323 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1324 def : Pat<(i64 (extloadi1 am_indexed8:$addr)),
1325 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1327 // load sign-extended half-word
1328 def LDRSHWui : LoadUI<0b01, 0, 0b11, GPR32, am_indexed16, "ldrsh",
1329 [(set GPR32:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1330 def LDRSHXui : LoadUI<0b01, 0, 0b10, GPR64, am_indexed16, "ldrsh",
1331 [(set GPR64:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1333 // load sign-extended byte
1334 def LDRSBWui : LoadUI<0b00, 0, 0b11, GPR32, am_indexed8, "ldrsb",
1335 [(set GPR32:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1336 def LDRSBXui : LoadUI<0b00, 0, 0b10, GPR64, am_indexed8, "ldrsb",
1337 [(set GPR64:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1339 // load sign-extended word
1340 def LDRSWui : LoadUI<0b10, 0, 0b10, GPR64, am_indexed32, "ldrsw",
1341 [(set GPR64:$Rt, (sextloadi32 am_indexed32:$addr))]>;
1343 // load zero-extended word
1344 def : Pat<(i64 (zextloadi32 am_indexed32:$addr)),
1345 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1348 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1349 [(ARM64Prefetch imm:$Rt, am_indexed64:$addr)]>;
1353 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1354 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1355 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1356 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1357 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1359 // load sign-extended word
1360 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1363 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1364 // [(ARM64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1367 // (unscaled immediate)
1368 def LDURXi : LoadUnscaled<0b11, 0, 0b01, GPR64, am_unscaled64, "ldur",
1369 [(set GPR64:$Rt, (load am_unscaled64:$addr))]>;
1370 def LDURWi : LoadUnscaled<0b10, 0, 0b01, GPR32, am_unscaled32, "ldur",
1371 [(set GPR32:$Rt, (load am_unscaled32:$addr))]>;
1372 def LDURBi : LoadUnscaled<0b00, 1, 0b01, FPR8, am_unscaled8, "ldur",
1373 [(set FPR8:$Rt, (load am_unscaled8:$addr))]>;
1374 def LDURHi : LoadUnscaled<0b01, 1, 0b01, FPR16, am_unscaled16, "ldur",
1375 [(set (f16 FPR16:$Rt), (load am_unscaled16:$addr))]>;
1376 def LDURSi : LoadUnscaled<0b10, 1, 0b01, FPR32, am_unscaled32, "ldur",
1377 [(set (f32 FPR32:$Rt), (load am_unscaled32:$addr))]>;
1378 def LDURDi : LoadUnscaled<0b11, 1, 0b01, FPR64, am_unscaled64, "ldur",
1379 [(set (f64 FPR64:$Rt), (load am_unscaled64:$addr))]>;
1380 def LDURQi : LoadUnscaled<0b00, 1, 0b11, FPR128, am_unscaled128, "ldur",
1381 [(set (f128 FPR128:$Rt), (load am_unscaled128:$addr))]>;
1384 : LoadUnscaled<0b01, 0, 0b01, GPR32, am_unscaled16, "ldurh",
1385 [(set GPR32:$Rt, (zextloadi16 am_unscaled16:$addr))]>;
1387 : LoadUnscaled<0b00, 0, 0b01, GPR32, am_unscaled8, "ldurb",
1388 [(set GPR32:$Rt, (zextloadi8 am_unscaled8:$addr))]>;
1390 // Match all load 64 bits width whose type is compatible with FPR64
1391 let Predicates = [IsLE] in {
1392 def : Pat<(v2f32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1393 def : Pat<(v8i8 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1394 def : Pat<(v4i16 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1395 def : Pat<(v2i32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1397 def : Pat<(v1f64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1398 def : Pat<(v1i64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1400 // Match all load 128 bits width whose type is compatible with FPR128
1401 let Predicates = [IsLE] in {
1402 def : Pat<(v4f32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1403 def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1404 def : Pat<(v16i8 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1405 def : Pat<(v8i16 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1406 def : Pat<(v4i32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1407 def : Pat<(v2i64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1408 def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1412 def : Pat<(i32 (extloadi16 am_unscaled16:$addr)), (LDURHHi am_unscaled16:$addr)>;
1413 def : Pat<(i32 (extloadi8 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1414 def : Pat<(i32 (extloadi1 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1415 def : Pat<(i64 (extloadi32 am_unscaled32:$addr)),
1416 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1417 def : Pat<(i64 (extloadi16 am_unscaled16:$addr)),
1418 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1419 def : Pat<(i64 (extloadi8 am_unscaled8:$addr)),
1420 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1421 def : Pat<(i64 (extloadi1 am_unscaled8:$addr)),
1422 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1424 def : Pat<(i32 (zextloadi16 am_unscaled16:$addr)),
1425 (LDURHHi am_unscaled16:$addr)>;
1426 def : Pat<(i32 (zextloadi8 am_unscaled8:$addr)),
1427 (LDURBBi am_unscaled8:$addr)>;
1428 def : Pat<(i32 (zextloadi1 am_unscaled8:$addr)),
1429 (LDURBBi am_unscaled8:$addr)>;
1430 def : Pat<(i64 (zextloadi32 am_unscaled32:$addr)),
1431 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1432 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1433 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1434 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1435 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1436 def : Pat<(i64 (zextloadi1 am_unscaled8:$addr)),
1437 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1441 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1443 // Define new assembler match classes as we want to only match these when
1444 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1445 // associate a DiagnosticType either, as we want the diagnostic for the
1446 // canonical form (the scaled operand) to take precedence.
1447 def MemoryUnscaledFB8Operand : AsmOperandClass {
1448 let Name = "MemoryUnscaledFB8";
1449 let RenderMethod = "addMemoryUnscaledOperands";
1451 def MemoryUnscaledFB16Operand : AsmOperandClass {
1452 let Name = "MemoryUnscaledFB16";
1453 let RenderMethod = "addMemoryUnscaledOperands";
1455 def MemoryUnscaledFB32Operand : AsmOperandClass {
1456 let Name = "MemoryUnscaledFB32";
1457 let RenderMethod = "addMemoryUnscaledOperands";
1459 def MemoryUnscaledFB64Operand : AsmOperandClass {
1460 let Name = "MemoryUnscaledFB64";
1461 let RenderMethod = "addMemoryUnscaledOperands";
1463 def MemoryUnscaledFB128Operand : AsmOperandClass {
1464 let Name = "MemoryUnscaledFB128";
1465 let RenderMethod = "addMemoryUnscaledOperands";
1467 def am_unscaled_fb8 : Operand<i64> {
1468 let ParserMatchClass = MemoryUnscaledFB8Operand;
1469 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1471 def am_unscaled_fb16 : Operand<i64> {
1472 let ParserMatchClass = MemoryUnscaledFB16Operand;
1473 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1475 def am_unscaled_fb32 : Operand<i64> {
1476 let ParserMatchClass = MemoryUnscaledFB32Operand;
1477 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1479 def am_unscaled_fb64 : Operand<i64> {
1480 let ParserMatchClass = MemoryUnscaledFB64Operand;
1481 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1483 def am_unscaled_fb128 : Operand<i64> {
1484 let ParserMatchClass = MemoryUnscaledFB128Operand;
1485 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1487 def : InstAlias<"ldr $Rt, $addr", (LDURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1488 def : InstAlias<"ldr $Rt, $addr", (LDURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1489 def : InstAlias<"ldr $Rt, $addr", (LDURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1490 def : InstAlias<"ldr $Rt, $addr", (LDURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1491 def : InstAlias<"ldr $Rt, $addr", (LDURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1492 def : InstAlias<"ldr $Rt, $addr", (LDURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1493 def : InstAlias<"ldr $Rt, $addr", (LDURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1496 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1497 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1498 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1499 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1501 // load sign-extended half-word
1503 : LoadUnscaled<0b01, 0, 0b11, GPR32, am_unscaled16, "ldursh",
1504 [(set GPR32:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1506 : LoadUnscaled<0b01, 0, 0b10, GPR64, am_unscaled16, "ldursh",
1507 [(set GPR64:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1509 // load sign-extended byte
1511 : LoadUnscaled<0b00, 0, 0b11, GPR32, am_unscaled8, "ldursb",
1512 [(set GPR32:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1514 : LoadUnscaled<0b00, 0, 0b10, GPR64, am_unscaled8, "ldursb",
1515 [(set GPR64:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1517 // load sign-extended word
1519 : LoadUnscaled<0b10, 0, 0b10, GPR64, am_unscaled32, "ldursw",
1520 [(set GPR64:$Rt, (sextloadi32 am_unscaled32:$addr))]>;
1522 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1523 def : InstAlias<"ldrb $Rt, $addr", (LDURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1524 def : InstAlias<"ldrh $Rt, $addr", (LDURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1525 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBWi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1526 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBXi GPR64:$Rt, am_unscaled_fb8:$addr)>;
1527 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHWi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1528 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHXi GPR64:$Rt, am_unscaled_fb16:$addr)>;
1529 def : InstAlias<"ldrsw $Rt, $addr", (LDURSWi GPR64:$Rt, am_unscaled_fb32:$addr)>;
1532 def PRFUMi : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1533 [(ARM64Prefetch imm:$Rt, am_unscaled64:$addr)]>;
1536 // (unscaled immediate, unprivileged)
1537 def LDTRXi : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1538 def LDTRWi : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1540 def LDTRHi : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1541 def LDTRBi : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1543 // load sign-extended half-word
1544 def LDTRSHWi : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1545 def LDTRSHXi : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1547 // load sign-extended byte
1548 def LDTRSBWi : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1549 def LDTRSBXi : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1551 // load sign-extended word
1552 def LDTRSWi : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1555 // (immediate pre-indexed)
1556 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1557 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1558 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1559 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1560 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1561 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1562 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1564 // load sign-extended half-word
1565 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1566 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1568 // load sign-extended byte
1569 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1570 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1572 // load zero-extended byte
1573 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1574 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1576 // load sign-extended word
1577 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1579 // ISel pseudos and patterns. See expanded comment on LoadPreIdxPseudo.
1580 def LDRQpre_isel : LoadPreIdxPseudo<FPR128>;
1581 def LDRDpre_isel : LoadPreIdxPseudo<FPR64>;
1582 def LDRSpre_isel : LoadPreIdxPseudo<FPR32>;
1583 def LDRXpre_isel : LoadPreIdxPseudo<GPR64>;
1584 def LDRWpre_isel : LoadPreIdxPseudo<GPR32>;
1585 def LDRHHpre_isel : LoadPreIdxPseudo<GPR32>;
1586 def LDRBBpre_isel : LoadPreIdxPseudo<GPR32>;
1588 def LDRSWpre_isel : LoadPreIdxPseudo<GPR64>;
1589 def LDRSHWpre_isel : LoadPreIdxPseudo<GPR32>;
1590 def LDRSHXpre_isel : LoadPreIdxPseudo<GPR64>;
1591 def LDRSBWpre_isel : LoadPreIdxPseudo<GPR32>;
1592 def LDRSBXpre_isel : LoadPreIdxPseudo<GPR64>;
1595 // (immediate post-indexed)
1596 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1597 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1598 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1599 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1600 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1601 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1602 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1604 // load sign-extended half-word
1605 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1606 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1608 // load sign-extended byte
1609 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1610 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1612 // load zero-extended byte
1613 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1614 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1616 // load sign-extended word
1617 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1619 // ISel pseudos and patterns. See expanded comment on LoadPostIdxPseudo.
1620 def LDRQpost_isel : LoadPostIdxPseudo<FPR128>;
1621 def LDRDpost_isel : LoadPostIdxPseudo<FPR64>;
1622 def LDRSpost_isel : LoadPostIdxPseudo<FPR32>;
1623 def LDRXpost_isel : LoadPostIdxPseudo<GPR64>;
1624 def LDRWpost_isel : LoadPostIdxPseudo<GPR32>;
1625 def LDRHHpost_isel : LoadPostIdxPseudo<GPR32>;
1626 def LDRBBpost_isel : LoadPostIdxPseudo<GPR32>;
1628 def LDRSWpost_isel : LoadPostIdxPseudo<GPR64>;
1629 def LDRSHWpost_isel : LoadPostIdxPseudo<GPR32>;
1630 def LDRSHXpost_isel : LoadPostIdxPseudo<GPR64>;
1631 def LDRSBWpost_isel : LoadPostIdxPseudo<GPR32>;
1632 def LDRSBXpost_isel : LoadPostIdxPseudo<GPR64>;
1634 //===----------------------------------------------------------------------===//
1635 // Store instructions.
1636 //===----------------------------------------------------------------------===//
1638 // Pair (indexed, offset)
1639 // FIXME: Use dedicated range-checked addressing mode operand here.
1640 def STPWi : StorePairOffset<0b00, 0, GPR32, am_indexed32simm7, "stp">;
1641 def STPXi : StorePairOffset<0b10, 0, GPR64, am_indexed64simm7, "stp">;
1642 def STPSi : StorePairOffset<0b00, 1, FPR32, am_indexed32simm7, "stp">;
1643 def STPDi : StorePairOffset<0b01, 1, FPR64, am_indexed64simm7, "stp">;
1644 def STPQi : StorePairOffset<0b10, 1, FPR128, am_indexed128simm7, "stp">;
1646 // Pair (pre-indexed)
1647 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "stp">;
1648 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "stp">;
1649 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "stp">;
1650 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "stp">;
1651 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "stp">;
1653 // Pair (pre-indexed)
1654 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1655 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1656 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1657 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1658 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1660 // Pair (no allocate)
1661 def STNPWi : StorePairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "stnp">;
1662 def STNPXi : StorePairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "stnp">;
1663 def STNPSi : StorePairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "stnp">;
1664 def STNPDi : StorePairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "stnp">;
1665 def STNPQi : StorePairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "stnp">;
1668 // (Register offset)
1670 let AddedComplexity = 10 in {
1673 def STRHHro : Store16RO<0b01, 0, 0b00, GPR32, "strh",
1674 [(truncstorei16 GPR32:$Rt, ro_indexed16:$addr)]>;
1675 def STRBBro : Store8RO<0b00, 0, 0b00, GPR32, "strb",
1676 [(truncstorei8 GPR32:$Rt, ro_indexed8:$addr)]>;
1677 def STRWro : Store32RO<0b10, 0, 0b00, GPR32, "str",
1678 [(store GPR32:$Rt, ro_indexed32:$addr)]>;
1679 def STRXro : Store64RO<0b11, 0, 0b00, GPR64, "str",
1680 [(store GPR64:$Rt, ro_indexed64:$addr)]>;
1683 def : Pat<(truncstorei8 GPR64:$Rt, ro_indexed8:$addr),
1684 (STRBBro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed8:$addr)>;
1685 def : Pat<(truncstorei16 GPR64:$Rt, ro_indexed16:$addr),
1686 (STRHHro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed16:$addr)>;
1687 def : Pat<(truncstorei32 GPR64:$Rt, ro_indexed32:$addr),
1688 (STRWro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed32:$addr)>;
1692 def STRBro : Store8RO<0b00, 1, 0b00, FPR8, "str",
1693 [(store FPR8:$Rt, ro_indexed8:$addr)]>;
1694 def STRHro : Store16RO<0b01, 1, 0b00, FPR16, "str",
1695 [(store (f16 FPR16:$Rt), ro_indexed16:$addr)]>;
1696 def STRSro : Store32RO<0b10, 1, 0b00, FPR32, "str",
1697 [(store (f32 FPR32:$Rt), ro_indexed32:$addr)]>;
1698 def STRDro : Store64RO<0b11, 1, 0b00, FPR64, "str",
1699 [(store (f64 FPR64:$Rt), ro_indexed64:$addr)]>;
1700 def STRQro : Store128RO<0b00, 1, 0b10, FPR128, "str", []> {
1704 // Match all store 64 bits width whose type is compatible with FPR64
1705 let Predicates = [IsLE] in {
1706 // We must use ST1 to store vectors in big-endian.
1707 def : Pat<(store (v2f32 FPR64:$Rn), ro_indexed64:$addr),
1708 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1709 def : Pat<(store (v8i8 FPR64:$Rn), ro_indexed64:$addr),
1710 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1711 def : Pat<(store (v4i16 FPR64:$Rn), ro_indexed64:$addr),
1712 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1713 def : Pat<(store (v2i32 FPR64:$Rn), ro_indexed64:$addr),
1714 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1716 def : Pat<(store (v1f64 FPR64:$Rn), ro_indexed64:$addr),
1717 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1718 def : Pat<(store (v1i64 FPR64:$Rn), ro_indexed64:$addr),
1719 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1721 // Match all store 128 bits width whose type is compatible with FPR128
1722 let Predicates = [IsLE] in {
1723 // We must use ST1 to store vectors in big-endian.
1724 def : Pat<(store (v4f32 FPR128:$Rn), ro_indexed128:$addr),
1725 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1726 def : Pat<(store (v2f64 FPR128:$Rn), ro_indexed128:$addr),
1727 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1728 def : Pat<(store (v16i8 FPR128:$Rn), ro_indexed128:$addr),
1729 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1730 def : Pat<(store (v8i16 FPR128:$Rn), ro_indexed128:$addr),
1731 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1732 def : Pat<(store (v4i32 FPR128:$Rn), ro_indexed128:$addr),
1733 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1734 def : Pat<(store (v2i64 FPR128:$Rn), ro_indexed128:$addr),
1735 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1737 def : Pat<(store (f128 FPR128:$Rn), ro_indexed128:$addr),
1738 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1741 // (unsigned immediate)
1742 def STRXui : StoreUI<0b11, 0, 0b00, GPR64, am_indexed64, "str",
1743 [(store GPR64:$Rt, am_indexed64:$addr)]>;
1744 def STRWui : StoreUI<0b10, 0, 0b00, GPR32, am_indexed32, "str",
1745 [(store GPR32:$Rt, am_indexed32:$addr)]>;
1746 def STRBui : StoreUI<0b00, 1, 0b00, FPR8, am_indexed8, "str",
1747 [(store FPR8:$Rt, am_indexed8:$addr)]>;
1748 def STRHui : StoreUI<0b01, 1, 0b00, FPR16, am_indexed16, "str",
1749 [(store (f16 FPR16:$Rt), am_indexed16:$addr)]>;
1750 def STRSui : StoreUI<0b10, 1, 0b00, FPR32, am_indexed32, "str",
1751 [(store (f32 FPR32:$Rt), am_indexed32:$addr)]>;
1752 def STRDui : StoreUI<0b11, 1, 0b00, FPR64, am_indexed64, "str",
1753 [(store (f64 FPR64:$Rt), am_indexed64:$addr)]>;
1754 def STRQui : StoreUI<0b00, 1, 0b10, FPR128, am_indexed128, "str", []> {
1758 // Match all store 64 bits width whose type is compatible with FPR64
1759 let Predicates = [IsLE] in {
1760 // We must use ST1 to store vectors in big-endian.
1761 def : Pat<(store (v2f32 FPR64:$Rn), am_indexed64:$addr),
1762 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1763 def : Pat<(store (v8i8 FPR64:$Rn), am_indexed64:$addr),
1764 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1765 def : Pat<(store (v4i16 FPR64:$Rn), am_indexed64:$addr),
1766 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1767 def : Pat<(store (v2i32 FPR64:$Rn), am_indexed64:$addr),
1768 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1770 def : Pat<(store (v1f64 FPR64:$Rn), am_indexed64:$addr),
1771 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1772 def : Pat<(store (v1i64 FPR64:$Rn), am_indexed64:$addr),
1773 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1775 // Match all store 128 bits width whose type is compatible with FPR128
1776 let Predicates = [IsLE] in {
1777 // We must use ST1 to store vectors in big-endian.
1778 def : Pat<(store (v4f32 FPR128:$Rn), am_indexed128:$addr),
1779 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1780 def : Pat<(store (v2f64 FPR128:$Rn), am_indexed128:$addr),
1781 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1782 def : Pat<(store (v16i8 FPR128:$Rn), am_indexed128:$addr),
1783 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1784 def : Pat<(store (v8i16 FPR128:$Rn), am_indexed128:$addr),
1785 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1786 def : Pat<(store (v4i32 FPR128:$Rn), am_indexed128:$addr),
1787 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1788 def : Pat<(store (v2i64 FPR128:$Rn), am_indexed128:$addr),
1789 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1791 def : Pat<(store (f128 FPR128:$Rn), am_indexed128:$addr),
1792 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1794 def STRHHui : StoreUI<0b01, 0, 0b00, GPR32, am_indexed16, "strh",
1795 [(truncstorei16 GPR32:$Rt, am_indexed16:$addr)]>;
1796 def STRBBui : StoreUI<0b00, 0, 0b00, GPR32, am_indexed8, "strb",
1797 [(truncstorei8 GPR32:$Rt, am_indexed8:$addr)]>;
1800 def : Pat<(truncstorei32 GPR64:$Rt, am_indexed32:$addr),
1801 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed32:$addr)>;
1802 def : Pat<(truncstorei16 GPR64:$Rt, am_indexed16:$addr),
1803 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed16:$addr)>;
1804 def : Pat<(truncstorei8 GPR64:$Rt, am_indexed8:$addr),
1805 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed8:$addr)>;
1807 } // AddedComplexity = 10
1810 // (unscaled immediate)
1811 def STURXi : StoreUnscaled<0b11, 0, 0b00, GPR64, am_unscaled64, "stur",
1812 [(store GPR64:$Rt, am_unscaled64:$addr)]>;
1813 def STURWi : StoreUnscaled<0b10, 0, 0b00, GPR32, am_unscaled32, "stur",
1814 [(store GPR32:$Rt, am_unscaled32:$addr)]>;
1815 def STURBi : StoreUnscaled<0b00, 1, 0b00, FPR8, am_unscaled8, "stur",
1816 [(store FPR8:$Rt, am_unscaled8:$addr)]>;
1817 def STURHi : StoreUnscaled<0b01, 1, 0b00, FPR16, am_unscaled16, "stur",
1818 [(store (f16 FPR16:$Rt), am_unscaled16:$addr)]>;
1819 def STURSi : StoreUnscaled<0b10, 1, 0b00, FPR32, am_unscaled32, "stur",
1820 [(store (f32 FPR32:$Rt), am_unscaled32:$addr)]>;
1821 def STURDi : StoreUnscaled<0b11, 1, 0b00, FPR64, am_unscaled64, "stur",
1822 [(store (f64 FPR64:$Rt), am_unscaled64:$addr)]>;
1823 def STURQi : StoreUnscaled<0b00, 1, 0b10, FPR128, am_unscaled128, "stur",
1824 [(store (f128 FPR128:$Rt), am_unscaled128:$addr)]>;
1825 def STURHHi : StoreUnscaled<0b01, 0, 0b00, GPR32, am_unscaled16, "sturh",
1826 [(truncstorei16 GPR32:$Rt, am_unscaled16:$addr)]>;
1827 def STURBBi : StoreUnscaled<0b00, 0, 0b00, GPR32, am_unscaled8, "sturb",
1828 [(truncstorei8 GPR32:$Rt, am_unscaled8:$addr)]>;
1830 // Match all store 64 bits width whose type is compatible with FPR64
1831 let Predicates = [IsLE] in {
1832 // We must use ST1 to store vectors in big-endian.
1833 def : Pat<(store (v2f32 FPR64:$Rn), am_unscaled64:$addr),
1834 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1835 def : Pat<(store (v8i8 FPR64:$Rn), am_unscaled64:$addr),
1836 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1837 def : Pat<(store (v4i16 FPR64:$Rn), am_unscaled64:$addr),
1838 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1839 def : Pat<(store (v2i32 FPR64:$Rn), am_unscaled64:$addr),
1840 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1842 def : Pat<(store (v1f64 FPR64:$Rn), am_unscaled64:$addr),
1843 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1844 def : Pat<(store (v1i64 FPR64:$Rn), am_unscaled64:$addr),
1845 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1847 // Match all store 128 bits width whose type is compatible with FPR128
1848 let Predicates = [IsLE] in {
1849 // We must use ST1 to store vectors in big-endian.
1850 def : Pat<(store (v4f32 FPR128:$Rn), am_unscaled128:$addr),
1851 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1852 def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
1853 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1854 def : Pat<(store (v16i8 FPR128:$Rn), am_unscaled128:$addr),
1855 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1856 def : Pat<(store (v8i16 FPR128:$Rn), am_unscaled128:$addr),
1857 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1858 def : Pat<(store (v4i32 FPR128:$Rn), am_unscaled128:$addr),
1859 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1860 def : Pat<(store (v2i64 FPR128:$Rn), am_unscaled128:$addr),
1861 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1862 def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
1863 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1866 // unscaled i64 truncating stores
1867 def : Pat<(truncstorei32 GPR64:$Rt, am_unscaled32:$addr),
1868 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled32:$addr)>;
1869 def : Pat<(truncstorei16 GPR64:$Rt, am_unscaled16:$addr),
1870 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled16:$addr)>;
1871 def : Pat<(truncstorei8 GPR64:$Rt, am_unscaled8:$addr),
1872 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled8:$addr)>;
1875 // STR mnemonics fall back to STUR for negative or unaligned offsets.
1876 def : InstAlias<"str $Rt, $addr", (STURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1877 def : InstAlias<"str $Rt, $addr", (STURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1878 def : InstAlias<"str $Rt, $addr", (STURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1879 def : InstAlias<"str $Rt, $addr", (STURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1880 def : InstAlias<"str $Rt, $addr", (STURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1881 def : InstAlias<"str $Rt, $addr", (STURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1882 def : InstAlias<"str $Rt, $addr", (STURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1884 def : InstAlias<"strb $Rt, $addr", (STURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1885 def : InstAlias<"strh $Rt, $addr", (STURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1888 // (unscaled immediate, unprivileged)
1889 def STTRWi : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
1890 def STTRXi : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
1892 def STTRHi : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
1893 def STTRBi : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
1896 // (immediate pre-indexed)
1897 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str">;
1898 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str">;
1899 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str">;
1900 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str">;
1901 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str">;
1902 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str">;
1903 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str">;
1905 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb">;
1906 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh">;
1908 // ISel pseudos and patterns. See expanded comment on StorePreIdxPseudo.
1909 defm STRQpre : StorePreIdxPseudo<FPR128, f128, pre_store>;
1910 defm STRDpre : StorePreIdxPseudo<FPR64, f64, pre_store>;
1911 defm STRSpre : StorePreIdxPseudo<FPR32, f32, pre_store>;
1912 defm STRXpre : StorePreIdxPseudo<GPR64, i64, pre_store>;
1913 defm STRWpre : StorePreIdxPseudo<GPR32, i32, pre_store>;
1914 defm STRHHpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti16>;
1915 defm STRBBpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti8>;
1917 def : Pat<(pre_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1918 (STRWpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1920 def : Pat<(pre_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1921 (STRHHpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1923 def : Pat<(pre_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1924 (STRBBpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1927 def : Pat<(pre_store (v8i8 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1928 (STRDpre_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1929 def : Pat<(pre_store (v4i16 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1930 (STRDpre_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1931 def : Pat<(pre_store (v2i32 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1932 (STRDpre_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1933 def : Pat<(pre_store (v2f32 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1934 (STRDpre_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1935 def : Pat<(pre_store (v1i64 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1936 (STRDpre_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1937 def : Pat<(pre_store (v1f64 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1938 (STRDpre_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1940 def : Pat<(pre_store (v16i8 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1941 (STRQpre_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1942 def : Pat<(pre_store (v8i16 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1943 (STRQpre_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1944 def : Pat<(pre_store (v4i32 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1945 (STRQpre_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1946 def : Pat<(pre_store (v4f32 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1947 (STRQpre_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1948 def : Pat<(pre_store (v2i64 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1949 (STRQpre_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1950 def : Pat<(pre_store (v2f64 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1951 (STRQpre_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
1954 // (immediate post-indexed)
1955 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str">;
1956 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str">;
1957 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str">;
1958 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str">;
1959 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str">;
1960 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str">;
1961 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str">;
1963 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb">;
1964 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh">;
1966 // ISel pseudos and patterns. See expanded comment on StorePostIdxPseudo.
1967 defm STRQpost : StorePostIdxPseudo<FPR128, f128, post_store, STRQpost>;
1968 defm STRDpost : StorePostIdxPseudo<FPR64, f64, post_store, STRDpost>;
1969 defm STRSpost : StorePostIdxPseudo<FPR32, f32, post_store, STRSpost>;
1970 defm STRXpost : StorePostIdxPseudo<GPR64, i64, post_store, STRXpost>;
1971 defm STRWpost : StorePostIdxPseudo<GPR32, i32, post_store, STRWpost>;
1972 defm STRHHpost : StorePostIdxPseudo<GPR32, i32, post_truncsti16, STRHHpost>;
1973 defm STRBBpost : StorePostIdxPseudo<GPR32, i32, post_truncsti8, STRBBpost>;
1975 def : Pat<(post_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1976 (STRWpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1978 def : Pat<(post_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1979 (STRHHpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1981 def : Pat<(post_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1982 (STRBBpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1985 def : Pat<(post_store (v8i8 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1986 (STRDpost_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1987 def : Pat<(post_store (v4i16 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1988 (STRDpost_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1989 def : Pat<(post_store (v2i32 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1990 (STRDpost_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1991 def : Pat<(post_store (v2f32 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1992 (STRDpost_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1993 def : Pat<(post_store (v1i64 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1994 (STRDpost_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1995 def : Pat<(post_store (v1f64 FPR64:$Rt), am_noindex:$addr, simm9:$off),
1996 (STRDpost_isel FPR64:$Rt, am_noindex:$addr, simm9:$off)>;
1998 def : Pat<(post_store (v16i8 FPR128:$Rt), am_noindex:$addr, simm9:$off),
1999 (STRQpost_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
2000 def : Pat<(post_store (v8i16 FPR128:$Rt), am_noindex:$addr, simm9:$off),
2001 (STRQpost_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
2002 def : Pat<(post_store (v4i32 FPR128:$Rt), am_noindex:$addr, simm9:$off),
2003 (STRQpost_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
2004 def : Pat<(post_store (v4f32 FPR128:$Rt), am_noindex:$addr, simm9:$off),
2005 (STRQpost_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
2006 def : Pat<(post_store (v2i64 FPR128:$Rt), am_noindex:$addr, simm9:$off),
2007 (STRQpost_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
2008 def : Pat<(post_store (v2f64 FPR128:$Rt), am_noindex:$addr, simm9:$off),
2009 (STRQpost_isel FPR128:$Rt, am_noindex:$addr, simm9:$off)>;
2011 //===----------------------------------------------------------------------===//
2012 // Load/store exclusive instructions.
2013 //===----------------------------------------------------------------------===//
2015 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
2016 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
2017 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
2018 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
2020 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
2021 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
2022 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
2023 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
2025 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
2026 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
2027 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
2028 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
2030 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
2031 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
2032 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
2033 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
2035 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
2036 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
2037 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
2038 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
2040 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
2041 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
2042 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
2043 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
2045 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
2046 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
2048 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
2049 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
2051 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
2052 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
2054 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
2055 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
2057 //===----------------------------------------------------------------------===//
2058 // Scaled floating point to integer conversion instructions.
2059 //===----------------------------------------------------------------------===//
2061 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
2062 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
2063 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
2064 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
2065 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
2066 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
2067 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
2068 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
2069 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2070 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2071 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
2072 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
2073 let isCodeGenOnly = 1 in {
2074 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
2075 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
2076 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
2077 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
2080 //===----------------------------------------------------------------------===//
2081 // Scaled integer to floating point conversion instructions.
2082 //===----------------------------------------------------------------------===//
2084 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
2085 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
2087 //===----------------------------------------------------------------------===//
2088 // Unscaled integer to floating point conversion instruction.
2089 //===----------------------------------------------------------------------===//
2091 defm FMOV : UnscaledConversion<"fmov">;
2093 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
2094 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
2096 //===----------------------------------------------------------------------===//
2097 // Floating point conversion instruction.
2098 //===----------------------------------------------------------------------===//
2100 defm FCVT : FPConversion<"fcvt">;
2102 def : Pat<(f32_to_f16 FPR32:$Rn),
2103 (i32 (COPY_TO_REGCLASS
2104 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
2107 def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
2108 [(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
2110 //===----------------------------------------------------------------------===//
2111 // Floating point single operand instructions.
2112 //===----------------------------------------------------------------------===//
2114 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
2115 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
2116 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
2117 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
2118 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
2119 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
2120 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_arm64_neon_frintn>;
2121 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
2123 def : Pat<(v1f64 (int_arm64_neon_frintn (v1f64 FPR64:$Rn))),
2124 (FRINTNDr FPR64:$Rn)>;
2126 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
2127 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2128 // <rdar://problem/13715968>
2129 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2130 let hasSideEffects = 1 in {
2131 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2134 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2136 let SchedRW = [WriteFDiv] in {
2137 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2140 //===----------------------------------------------------------------------===//
2141 // Floating point two operand instructions.
2142 //===----------------------------------------------------------------------===//
2144 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2145 let SchedRW = [WriteFDiv] in {
2146 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2148 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_arm64_neon_fmaxnm>;
2149 defm FMAX : TwoOperandFPData<0b0100, "fmax", ARM64fmax>;
2150 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_arm64_neon_fminnm>;
2151 defm FMIN : TwoOperandFPData<0b0101, "fmin", ARM64fmin>;
2152 let SchedRW = [WriteFMul] in {
2153 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2154 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2156 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2158 def : Pat<(v1f64 (ARM64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2159 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2160 def : Pat<(v1f64 (ARM64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2161 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2162 def : Pat<(v1f64 (int_arm64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2163 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2164 def : Pat<(v1f64 (int_arm64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2165 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2167 //===----------------------------------------------------------------------===//
2168 // Floating point three operand instructions.
2169 //===----------------------------------------------------------------------===//
2171 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2172 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2173 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2174 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2175 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2176 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2177 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2179 // The following def pats catch the case where the LHS of an FMA is negated.
2180 // The TriOpFrag above catches the case where the middle operand is negated.
2182 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2183 // the NEON variant.
2184 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2185 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2187 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2188 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2190 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2192 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2193 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2195 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2196 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2198 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2199 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2201 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2202 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2204 //===----------------------------------------------------------------------===//
2205 // Floating point comparison instructions.
2206 //===----------------------------------------------------------------------===//
2208 defm FCMPE : FPComparison<1, "fcmpe">;
2209 defm FCMP : FPComparison<0, "fcmp", ARM64fcmp>;
2211 //===----------------------------------------------------------------------===//
2212 // Floating point conditional comparison instructions.
2213 //===----------------------------------------------------------------------===//
2215 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2216 defm FCCMP : FPCondComparison<0, "fccmp">;
2218 //===----------------------------------------------------------------------===//
2219 // Floating point conditional select instruction.
2220 //===----------------------------------------------------------------------===//
2222 defm FCSEL : FPCondSelect<"fcsel">;
2224 // CSEL instructions providing f128 types need to be handled by a
2225 // pseudo-instruction since the eventual code will need to introduce basic
2226 // blocks and control flow.
2227 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2228 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2229 [(set (f128 FPR128:$Rd),
2230 (ARM64csel FPR128:$Rn, FPR128:$Rm,
2231 (i32 imm:$cond), NZCV))]> {
2233 let usesCustomInserter = 1;
2237 //===----------------------------------------------------------------------===//
2238 // Floating point immediate move.
2239 //===----------------------------------------------------------------------===//
2241 let isReMaterializable = 1 in {
2242 defm FMOV : FPMoveImmediate<"fmov">;
2245 //===----------------------------------------------------------------------===//
2246 // Advanced SIMD two vector instructions.
2247 //===----------------------------------------------------------------------===//
2249 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_arm64_neon_abs>;
2250 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_arm64_neon_cls>;
2251 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2252 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", ARM64cmeqz>;
2253 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", ARM64cmgez>;
2254 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", ARM64cmgtz>;
2255 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", ARM64cmlez>;
2256 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", ARM64cmltz>;
2257 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2258 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2260 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2261 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2262 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2263 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2264 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2265 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_arm64_neon_fcvtas>;
2266 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_arm64_neon_fcvtau>;
2267 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2268 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2269 (FCVTLv4i16 V64:$Rn)>;
2270 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2272 (FCVTLv8i16 V128:$Rn)>;
2273 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2274 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2276 (FCVTLv4i32 V128:$Rn)>;
2278 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_arm64_neon_fcvtms>;
2279 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_arm64_neon_fcvtmu>;
2280 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_arm64_neon_fcvtns>;
2281 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_arm64_neon_fcvtnu>;
2282 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2283 def : Pat<(v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2284 (FCVTNv4i16 V128:$Rn)>;
2285 def : Pat<(concat_vectors V64:$Rd,
2286 (v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2287 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2288 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2289 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2290 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2291 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_arm64_neon_fcvtps>;
2292 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_arm64_neon_fcvtpu>;
2293 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2294 int_arm64_neon_fcvtxn>;
2295 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2296 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2297 let isCodeGenOnly = 1 in {
2298 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2299 int_arm64_neon_fcvtzs>;
2300 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2301 int_arm64_neon_fcvtzu>;
2303 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2304 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_arm64_neon_frecpe>;
2305 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2306 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2307 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2308 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_arm64_neon_frintn>;
2309 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2310 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2311 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2312 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_arm64_neon_frsqrte>;
2313 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2314 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2315 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2316 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2317 // Aliases for MVN -> NOT.
2318 def : InstAlias<"mvn.8b $Vd, $Vn", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2319 def : InstAlias<"mvn.16b $Vd, $Vn", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2320 def : InstAlias<"mvn $Vd.8b, $Vn.8b", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2321 def : InstAlias<"mvn $Vd.16b, $Vn.16b", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2323 def : Pat<(ARM64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2324 def : Pat<(ARM64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2325 def : Pat<(ARM64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2326 def : Pat<(ARM64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2327 def : Pat<(ARM64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2328 def : Pat<(ARM64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2329 def : Pat<(ARM64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2331 def : Pat<(ARM64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2332 def : Pat<(ARM64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2333 def : Pat<(ARM64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2334 def : Pat<(ARM64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2335 def : Pat<(ARM64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2336 def : Pat<(ARM64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2337 def : Pat<(ARM64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2338 def : Pat<(ARM64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2340 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2341 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2342 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2343 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2344 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2346 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_arm64_neon_rbit>;
2347 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", ARM64rev16>;
2348 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", ARM64rev32>;
2349 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", ARM64rev64>;
2350 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2351 BinOpFrag<(add node:$LHS, (int_arm64_neon_saddlp node:$RHS))> >;
2352 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_arm64_neon_saddlp>;
2353 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2354 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2355 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2356 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2357 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_arm64_neon_sqxtn>;
2358 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_arm64_neon_sqxtun>;
2359 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_arm64_neon_suqadd>;
2360 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2361 BinOpFrag<(add node:$LHS, (int_arm64_neon_uaddlp node:$RHS))> >;
2362 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2363 int_arm64_neon_uaddlp>;
2364 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2365 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_arm64_neon_uqxtn>;
2366 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_arm64_neon_urecpe>;
2367 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_arm64_neon_ursqrte>;
2368 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_arm64_neon_usqadd>;
2369 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2371 def : Pat<(v2f32 (ARM64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2372 def : Pat<(v4f32 (ARM64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2374 // Patterns for vector long shift (by element width). These need to match all
2375 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2377 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2378 def : Pat<(ARM64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2379 (SHLLv8i8 V64:$Rn)>;
2380 def : Pat<(ARM64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2381 (SHLLv16i8 V128:$Rn)>;
2382 def : Pat<(ARM64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2383 (SHLLv4i16 V64:$Rn)>;
2384 def : Pat<(ARM64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2385 (SHLLv8i16 V128:$Rn)>;
2386 def : Pat<(ARM64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2387 (SHLLv2i32 V64:$Rn)>;
2388 def : Pat<(ARM64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2389 (SHLLv4i32 V128:$Rn)>;
2392 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2393 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2394 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2396 //===----------------------------------------------------------------------===//
2397 // Advanced SIMD three vector instructions.
2398 //===----------------------------------------------------------------------===//
2400 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2401 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_arm64_neon_addp>;
2402 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", ARM64cmeq>;
2403 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", ARM64cmge>;
2404 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", ARM64cmgt>;
2405 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", ARM64cmhi>;
2406 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", ARM64cmhs>;
2407 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", ARM64cmtst>;
2408 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_arm64_neon_fabd>;
2409 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_arm64_neon_facge>;
2410 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_arm64_neon_facgt>;
2411 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_arm64_neon_addp>;
2412 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2413 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2414 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2415 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2416 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2417 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_arm64_neon_fmaxnmp>;
2418 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_arm64_neon_fmaxnm>;
2419 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_arm64_neon_fmaxp>;
2420 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", ARM64fmax>;
2421 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_arm64_neon_fminnmp>;
2422 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_arm64_neon_fminnm>;
2423 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_arm64_neon_fminp>;
2424 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", ARM64fmin>;
2426 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2427 // instruction expects the addend first, while the fma intrinsic puts it last.
2428 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2429 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2430 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2431 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2433 // The following def pats catch the case where the LHS of an FMA is negated.
2434 // The TriOpFrag above catches the case where the middle operand is negated.
2435 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2436 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2438 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2439 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2441 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2442 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2444 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_arm64_neon_fmulx>;
2445 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2446 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_arm64_neon_frecps>;
2447 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_arm64_neon_frsqrts>;
2448 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2449 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2450 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2451 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2452 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2453 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2454 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_arm64_neon_pmul>;
2455 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2456 TriOpFrag<(add node:$LHS, (int_arm64_neon_sabd node:$MHS, node:$RHS))> >;
2457 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_arm64_neon_sabd>;
2458 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_arm64_neon_shadd>;
2459 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_arm64_neon_shsub>;
2460 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_arm64_neon_smaxp>;
2461 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_arm64_neon_smax>;
2462 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_arm64_neon_sminp>;
2463 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_arm64_neon_smin>;
2464 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_arm64_neon_sqadd>;
2465 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_arm64_neon_sqdmulh>;
2466 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_arm64_neon_sqrdmulh>;
2467 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_arm64_neon_sqrshl>;
2468 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_arm64_neon_sqshl>;
2469 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_arm64_neon_sqsub>;
2470 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_arm64_neon_srhadd>;
2471 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_arm64_neon_srshl>;
2472 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_arm64_neon_sshl>;
2473 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2474 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2475 TriOpFrag<(add node:$LHS, (int_arm64_neon_uabd node:$MHS, node:$RHS))> >;
2476 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_arm64_neon_uabd>;
2477 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_arm64_neon_uhadd>;
2478 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_arm64_neon_uhsub>;
2479 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_arm64_neon_umaxp>;
2480 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_arm64_neon_umax>;
2481 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_arm64_neon_uminp>;
2482 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_arm64_neon_umin>;
2483 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_arm64_neon_uqadd>;
2484 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_arm64_neon_uqrshl>;
2485 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_arm64_neon_uqshl>;
2486 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_arm64_neon_uqsub>;
2487 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_arm64_neon_urhadd>;
2488 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_arm64_neon_urshl>;
2489 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_arm64_neon_ushl>;
2491 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2492 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2493 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2494 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2495 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", ARM64bit>;
2496 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2497 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2498 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2499 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2500 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2501 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2503 def : Pat<(ARM64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2504 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2505 def : Pat<(ARM64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2506 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2507 def : Pat<(ARM64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2508 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2509 def : Pat<(ARM64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2510 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2512 def : Pat<(ARM64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2513 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2514 def : Pat<(ARM64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2515 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2516 def : Pat<(ARM64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2517 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2518 def : Pat<(ARM64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2519 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2521 // FIXME: the .16b and .8b variantes should be emitted by the
2522 // AsmWriter. TableGen's AsmWriter-generator doesn't deal with variant syntaxes
2523 // in aliases yet though.
2524 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2525 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2526 def : InstAlias<"{mov\t$dst.8h, $src.8h|mov.8h\t$dst, $src}",
2527 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2528 def : InstAlias<"{mov\t$dst.4s, $src.4s|mov.4s\t$dst, $src}",
2529 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2530 def : InstAlias<"{mov\t$dst.2d, $src.2d|mov.2d\t$dst, $src}",
2531 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2533 def : InstAlias<"{mov\t$dst.8b, $src.8b|mov.8b\t$dst, $src}",
2534 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2535 def : InstAlias<"{mov\t$dst.4h, $src.4h|mov.4h\t$dst, $src}",
2536 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2537 def : InstAlias<"{mov\t$dst.2s, $src.2s|mov.2s\t$dst, $src}",
2538 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2539 def : InstAlias<"{mov\t$dst.1d, $src.1d|mov.1d\t$dst, $src}",
2540 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2542 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2543 "|cmls.8b\t$dst, $src1, $src2}",
2544 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2545 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2546 "|cmls.16b\t$dst, $src1, $src2}",
2547 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2548 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2549 "|cmls.4h\t$dst, $src1, $src2}",
2550 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2551 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2552 "|cmls.8h\t$dst, $src1, $src2}",
2553 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2554 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2555 "|cmls.2s\t$dst, $src1, $src2}",
2556 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2557 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2558 "|cmls.4s\t$dst, $src1, $src2}",
2559 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2560 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2561 "|cmls.2d\t$dst, $src1, $src2}",
2562 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2564 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2565 "|cmlo.8b\t$dst, $src1, $src2}",
2566 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2567 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2568 "|cmlo.16b\t$dst, $src1, $src2}",
2569 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2570 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2571 "|cmlo.4h\t$dst, $src1, $src2}",
2572 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2573 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2574 "|cmlo.8h\t$dst, $src1, $src2}",
2575 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2576 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2577 "|cmlo.2s\t$dst, $src1, $src2}",
2578 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2579 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2580 "|cmlo.4s\t$dst, $src1, $src2}",
2581 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2582 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2583 "|cmlo.2d\t$dst, $src1, $src2}",
2584 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2586 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2587 "|cmle.8b\t$dst, $src1, $src2}",
2588 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2589 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2590 "|cmle.16b\t$dst, $src1, $src2}",
2591 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2592 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2593 "|cmle.4h\t$dst, $src1, $src2}",
2594 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2595 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2596 "|cmle.8h\t$dst, $src1, $src2}",
2597 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2598 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2599 "|cmle.2s\t$dst, $src1, $src2}",
2600 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2601 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2602 "|cmle.4s\t$dst, $src1, $src2}",
2603 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2604 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2605 "|cmle.2d\t$dst, $src1, $src2}",
2606 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2608 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2609 "|cmlt.8b\t$dst, $src1, $src2}",
2610 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2611 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2612 "|cmlt.16b\t$dst, $src1, $src2}",
2613 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2614 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2615 "|cmlt.4h\t$dst, $src1, $src2}",
2616 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2617 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2618 "|cmlt.8h\t$dst, $src1, $src2}",
2619 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2620 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2621 "|cmlt.2s\t$dst, $src1, $src2}",
2622 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2623 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2624 "|cmlt.4s\t$dst, $src1, $src2}",
2625 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2626 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2627 "|cmlt.2d\t$dst, $src1, $src2}",
2628 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2630 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2631 "|fcmle.2s\t$dst, $src1, $src2}",
2632 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2633 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2634 "|fcmle.4s\t$dst, $src1, $src2}",
2635 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2636 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2637 "|fcmle.2d\t$dst, $src1, $src2}",
2638 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2640 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2641 "|fcmlt.2s\t$dst, $src1, $src2}",
2642 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2643 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2644 "|fcmlt.4s\t$dst, $src1, $src2}",
2645 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2646 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2647 "|fcmlt.2d\t$dst, $src1, $src2}",
2648 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2650 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2651 "|facle.2s\t$dst, $src1, $src2}",
2652 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2653 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2654 "|facle.4s\t$dst, $src1, $src2}",
2655 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2656 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2657 "|facle.2d\t$dst, $src1, $src2}",
2658 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2660 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2661 "|faclt.2s\t$dst, $src1, $src2}",
2662 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2663 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2664 "|faclt.4s\t$dst, $src1, $src2}",
2665 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2666 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2667 "|faclt.2d\t$dst, $src1, $src2}",
2668 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2670 //===----------------------------------------------------------------------===//
2671 // Advanced SIMD three scalar instructions.
2672 //===----------------------------------------------------------------------===//
2674 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2675 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", ARM64cmeq>;
2676 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", ARM64cmge>;
2677 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", ARM64cmgt>;
2678 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", ARM64cmhi>;
2679 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", ARM64cmhs>;
2680 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", ARM64cmtst>;
2681 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_arm64_sisd_fabd>;
2682 def : Pat<(v1f64 (int_arm64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2683 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2684 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2685 int_arm64_neon_facge>;
2686 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2687 int_arm64_neon_facgt>;
2688 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2689 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2690 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2691 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_arm64_neon_fmulx>;
2692 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_arm64_neon_frecps>;
2693 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_arm64_neon_frsqrts>;
2694 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_arm64_neon_sqadd>;
2695 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_arm64_neon_sqdmulh>;
2696 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_arm64_neon_sqrdmulh>;
2697 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_arm64_neon_sqrshl>;
2698 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_arm64_neon_sqshl>;
2699 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_arm64_neon_sqsub>;
2700 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_arm64_neon_srshl>;
2701 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_arm64_neon_sshl>;
2702 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2703 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_arm64_neon_uqadd>;
2704 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_arm64_neon_uqrshl>;
2705 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_arm64_neon_uqshl>;
2706 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_arm64_neon_uqsub>;
2707 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_arm64_neon_urshl>;
2708 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_arm64_neon_ushl>;
2710 def : InstAlias<"cmls $dst, $src1, $src2",
2711 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2712 def : InstAlias<"cmle $dst, $src1, $src2",
2713 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2714 def : InstAlias<"cmlo $dst, $src1, $src2",
2715 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2716 def : InstAlias<"cmlt $dst, $src1, $src2",
2717 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2718 def : InstAlias<"fcmle $dst, $src1, $src2",
2719 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2720 def : InstAlias<"fcmle $dst, $src1, $src2",
2721 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2722 def : InstAlias<"fcmlt $dst, $src1, $src2",
2723 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2724 def : InstAlias<"fcmlt $dst, $src1, $src2",
2725 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2726 def : InstAlias<"facle $dst, $src1, $src2",
2727 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2728 def : InstAlias<"facle $dst, $src1, $src2",
2729 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2730 def : InstAlias<"faclt $dst, $src1, $src2",
2731 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2732 def : InstAlias<"faclt $dst, $src1, $src2",
2733 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2735 //===----------------------------------------------------------------------===//
2736 // Advanced SIMD three scalar instructions (mixed operands).
2737 //===----------------------------------------------------------------------===//
2738 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2739 int_arm64_neon_sqdmulls_scalar>;
2740 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2741 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2743 def : Pat<(i64 (int_arm64_neon_sqadd (i64 FPR64:$Rd),
2744 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2745 (i32 FPR32:$Rm))))),
2746 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2747 def : Pat<(i64 (int_arm64_neon_sqsub (i64 FPR64:$Rd),
2748 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2749 (i32 FPR32:$Rm))))),
2750 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2752 //===----------------------------------------------------------------------===//
2753 // Advanced SIMD two scalar instructions.
2754 //===----------------------------------------------------------------------===//
2756 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_arm64_neon_abs>;
2757 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", ARM64cmeqz>;
2758 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", ARM64cmgez>;
2759 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", ARM64cmgtz>;
2760 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", ARM64cmlez>;
2761 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", ARM64cmltz>;
2762 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2763 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2764 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2765 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2766 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2767 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2768 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2769 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2770 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2771 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2772 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2773 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2774 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2775 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2776 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2777 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2778 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2779 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2780 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2781 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
2782 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2783 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", ARM64sitof>;
2784 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2785 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2786 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_arm64_neon_scalar_sqxtn>;
2787 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_arm64_neon_scalar_sqxtun>;
2788 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2789 int_arm64_neon_suqadd>;
2790 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", ARM64uitof>;
2791 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_arm64_neon_scalar_uqxtn>;
2792 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2793 int_arm64_neon_usqadd>;
2795 def : Pat<(ARM64neg (v1i64 V64:$Rn)), (NEGv1i64 V64:$Rn)>;
2797 def : Pat<(v1i64 (int_arm64_neon_fcvtas (v1f64 FPR64:$Rn))),
2798 (FCVTASv1i64 FPR64:$Rn)>;
2799 def : Pat<(v1i64 (int_arm64_neon_fcvtau (v1f64 FPR64:$Rn))),
2800 (FCVTAUv1i64 FPR64:$Rn)>;
2801 def : Pat<(v1i64 (int_arm64_neon_fcvtms (v1f64 FPR64:$Rn))),
2802 (FCVTMSv1i64 FPR64:$Rn)>;
2803 def : Pat<(v1i64 (int_arm64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2804 (FCVTMUv1i64 FPR64:$Rn)>;
2805 def : Pat<(v1i64 (int_arm64_neon_fcvtns (v1f64 FPR64:$Rn))),
2806 (FCVTNSv1i64 FPR64:$Rn)>;
2807 def : Pat<(v1i64 (int_arm64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2808 (FCVTNUv1i64 FPR64:$Rn)>;
2809 def : Pat<(v1i64 (int_arm64_neon_fcvtps (v1f64 FPR64:$Rn))),
2810 (FCVTPSv1i64 FPR64:$Rn)>;
2811 def : Pat<(v1i64 (int_arm64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2812 (FCVTPUv1i64 FPR64:$Rn)>;
2814 def : Pat<(f32 (int_arm64_neon_frecpe (f32 FPR32:$Rn))),
2815 (FRECPEv1i32 FPR32:$Rn)>;
2816 def : Pat<(f64 (int_arm64_neon_frecpe (f64 FPR64:$Rn))),
2817 (FRECPEv1i64 FPR64:$Rn)>;
2818 def : Pat<(v1f64 (int_arm64_neon_frecpe (v1f64 FPR64:$Rn))),
2819 (FRECPEv1i64 FPR64:$Rn)>;
2821 def : Pat<(f32 (int_arm64_neon_frecpx (f32 FPR32:$Rn))),
2822 (FRECPXv1i32 FPR32:$Rn)>;
2823 def : Pat<(f64 (int_arm64_neon_frecpx (f64 FPR64:$Rn))),
2824 (FRECPXv1i64 FPR64:$Rn)>;
2826 def : Pat<(f32 (int_arm64_neon_frsqrte (f32 FPR32:$Rn))),
2827 (FRSQRTEv1i32 FPR32:$Rn)>;
2828 def : Pat<(f64 (int_arm64_neon_frsqrte (f64 FPR64:$Rn))),
2829 (FRSQRTEv1i64 FPR64:$Rn)>;
2830 def : Pat<(v1f64 (int_arm64_neon_frsqrte (v1f64 FPR64:$Rn))),
2831 (FRSQRTEv1i64 FPR64:$Rn)>;
2833 // If an integer is about to be converted to a floating point value,
2834 // just load it on the floating point unit.
2835 // Here are the patterns for 8 and 16-bits to float.
2837 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2838 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2839 (LDRBro ro_indexed8:$addr), bsub))>;
2840 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2841 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2842 (LDRBui am_indexed8:$addr), bsub))>;
2843 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2844 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2845 (LDURBi am_unscaled8:$addr), bsub))>;
2846 // 16-bits -> float.
2847 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2848 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2849 (LDRHro ro_indexed16:$addr), hsub))>;
2850 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2851 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2852 (LDRHui am_indexed16:$addr), hsub))>;
2853 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2854 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2855 (LDURHi am_unscaled16:$addr), hsub))>;
2856 // 32-bits are handled in target specific dag combine:
2857 // performIntToFpCombine.
2858 // 64-bits integer to 32-bits floating point, not possible with
2859 // UCVTF on floating point registers (both source and destination
2860 // must have the same size).
2862 // Here are the patterns for 8, 16, 32, and 64-bits to double.
2863 // 8-bits -> double.
2864 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2865 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2866 (LDRBro ro_indexed8:$addr), bsub))>;
2867 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2868 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2869 (LDRBui am_indexed8:$addr), bsub))>;
2870 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2871 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2872 (LDURBi am_unscaled8:$addr), bsub))>;
2873 // 16-bits -> double.
2874 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2875 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2876 (LDRHro ro_indexed16:$addr), hsub))>;
2877 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2878 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2879 (LDRHui am_indexed16:$addr), hsub))>;
2880 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2881 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2882 (LDURHi am_unscaled16:$addr), hsub))>;
2883 // 32-bits -> double.
2884 def : Pat <(f64 (uint_to_fp (i32 (load ro_indexed32:$addr)))),
2885 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2886 (LDRSro ro_indexed32:$addr), ssub))>;
2887 def : Pat <(f64 (uint_to_fp (i32 (load am_indexed32:$addr)))),
2888 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2889 (LDRSui am_indexed32:$addr), ssub))>;
2890 def : Pat <(f64 (uint_to_fp (i32 (load am_unscaled32:$addr)))),
2891 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2892 (LDURSi am_unscaled32:$addr), ssub))>;
2893 // 64-bits -> double are handled in target specific dag combine:
2894 // performIntToFpCombine.
2896 //===----------------------------------------------------------------------===//
2897 // Advanced SIMD three different-sized vector instructions.
2898 //===----------------------------------------------------------------------===//
2900 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_arm64_neon_addhn>;
2901 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_arm64_neon_subhn>;
2902 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_arm64_neon_raddhn>;
2903 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_arm64_neon_rsubhn>;
2904 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_arm64_neon_pmull>;
2905 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
2906 int_arm64_neon_sabd>;
2907 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
2908 int_arm64_neon_sabd>;
2909 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
2910 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
2911 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
2912 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
2913 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
2914 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2915 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
2916 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2917 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_arm64_neon_smull>;
2918 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
2919 int_arm64_neon_sqadd>;
2920 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
2921 int_arm64_neon_sqsub>;
2922 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
2923 int_arm64_neon_sqdmull>;
2924 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
2925 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
2926 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
2927 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
2928 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
2929 int_arm64_neon_uabd>;
2930 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
2931 int_arm64_neon_uabd>;
2932 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
2933 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
2934 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
2935 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
2936 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
2937 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2938 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
2939 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2940 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_arm64_neon_umull>;
2941 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
2942 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
2943 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
2944 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
2946 // Patterns for 64-bit pmull
2947 def : Pat<(int_arm64_neon_pmull64 V64:$Rn, V64:$Rm),
2948 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
2949 def : Pat<(int_arm64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
2950 (vector_extract (v2i64 V128:$Rm), (i64 1))),
2951 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
2953 // CodeGen patterns for addhn and subhn instructions, which can actually be
2954 // written in LLVM IR without too much difficulty.
2957 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
2958 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2959 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2961 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2962 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2964 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2965 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2966 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2968 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2969 V128:$Rn, V128:$Rm)>;
2970 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2971 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2973 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2974 V128:$Rn, V128:$Rm)>;
2975 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2976 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2978 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2979 V128:$Rn, V128:$Rm)>;
2982 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
2983 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2984 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2986 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2987 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2989 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2990 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2991 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2993 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2994 V128:$Rn, V128:$Rm)>;
2995 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2996 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2998 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2999 V128:$Rn, V128:$Rm)>;
3000 def : Pat<(concat_vectors (v2i32 V64:$Rd),
3001 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
3003 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
3004 V128:$Rn, V128:$Rm)>;
3006 //----------------------------------------------------------------------------
3007 // AdvSIMD bitwise extract from vector instruction.
3008 //----------------------------------------------------------------------------
3010 defm EXT : SIMDBitwiseExtract<"ext">;
3012 def : Pat<(v4i16 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3013 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3014 def : Pat<(v8i16 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3015 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3016 def : Pat<(v2i32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3017 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3018 def : Pat<(v2f32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
3019 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
3020 def : Pat<(v4i32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3021 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3022 def : Pat<(v4f32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3023 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3024 def : Pat<(v2i64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3025 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3026 def : Pat<(v2f64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
3027 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
3029 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
3031 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
3032 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3033 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
3034 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3035 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
3036 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3037 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
3038 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3039 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
3040 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3041 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
3042 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
3045 //----------------------------------------------------------------------------
3046 // AdvSIMD zip vector
3047 //----------------------------------------------------------------------------
3049 defm TRN1 : SIMDZipVector<0b010, "trn1", ARM64trn1>;
3050 defm TRN2 : SIMDZipVector<0b110, "trn2", ARM64trn2>;
3051 defm UZP1 : SIMDZipVector<0b001, "uzp1", ARM64uzp1>;
3052 defm UZP2 : SIMDZipVector<0b101, "uzp2", ARM64uzp2>;
3053 defm ZIP1 : SIMDZipVector<0b011, "zip1", ARM64zip1>;
3054 defm ZIP2 : SIMDZipVector<0b111, "zip2", ARM64zip2>;
3056 //----------------------------------------------------------------------------
3057 // AdvSIMD TBL/TBX instructions
3058 //----------------------------------------------------------------------------
3060 defm TBL : SIMDTableLookup< 0, "tbl">;
3061 defm TBX : SIMDTableLookupTied<1, "tbx">;
3063 def : Pat<(v8i8 (int_arm64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3064 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
3065 def : Pat<(v16i8 (int_arm64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3066 (TBLv16i8One V128:$Ri, V128:$Rn)>;
3068 def : Pat<(v8i8 (int_arm64_neon_tbx1 (v8i8 V64:$Rd),
3069 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
3070 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
3071 def : Pat<(v16i8 (int_arm64_neon_tbx1 (v16i8 V128:$Rd),
3072 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
3073 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
3076 //----------------------------------------------------------------------------
3077 // AdvSIMD scalar CPY instruction
3078 //----------------------------------------------------------------------------
3080 defm CPY : SIMDScalarCPY<"cpy">;
3082 //----------------------------------------------------------------------------
3083 // AdvSIMD scalar pairwise instructions
3084 //----------------------------------------------------------------------------
3086 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
3087 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
3088 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
3089 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
3090 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
3091 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
3092 def : Pat<(i64 (int_arm64_neon_saddv (v2i64 V128:$Rn))),
3093 (ADDPv2i64p V128:$Rn)>;
3094 def : Pat<(i64 (int_arm64_neon_uaddv (v2i64 V128:$Rn))),
3095 (ADDPv2i64p V128:$Rn)>;
3096 def : Pat<(f32 (int_arm64_neon_faddv (v2f32 V64:$Rn))),
3097 (FADDPv2i32p V64:$Rn)>;
3098 def : Pat<(f32 (int_arm64_neon_faddv (v4f32 V128:$Rn))),
3099 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
3100 def : Pat<(f64 (int_arm64_neon_faddv (v2f64 V128:$Rn))),
3101 (FADDPv2i64p V128:$Rn)>;
3102 def : Pat<(f32 (int_arm64_neon_fmaxnmv (v2f32 V64:$Rn))),
3103 (FMAXNMPv2i32p V64:$Rn)>;
3104 def : Pat<(f64 (int_arm64_neon_fmaxnmv (v2f64 V128:$Rn))),
3105 (FMAXNMPv2i64p V128:$Rn)>;
3106 def : Pat<(f32 (int_arm64_neon_fmaxv (v2f32 V64:$Rn))),
3107 (FMAXPv2i32p V64:$Rn)>;
3108 def : Pat<(f64 (int_arm64_neon_fmaxv (v2f64 V128:$Rn))),
3109 (FMAXPv2i64p V128:$Rn)>;
3110 def : Pat<(f32 (int_arm64_neon_fminnmv (v2f32 V64:$Rn))),
3111 (FMINNMPv2i32p V64:$Rn)>;
3112 def : Pat<(f64 (int_arm64_neon_fminnmv (v2f64 V128:$Rn))),
3113 (FMINNMPv2i64p V128:$Rn)>;
3114 def : Pat<(f32 (int_arm64_neon_fminv (v2f32 V64:$Rn))),
3115 (FMINPv2i32p V64:$Rn)>;
3116 def : Pat<(f64 (int_arm64_neon_fminv (v2f64 V128:$Rn))),
3117 (FMINPv2i64p V128:$Rn)>;
3119 //----------------------------------------------------------------------------
3120 // AdvSIMD INS/DUP instructions
3121 //----------------------------------------------------------------------------
3123 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
3124 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
3125 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
3126 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
3127 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
3128 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
3129 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3131 def DUPv2i64lane : SIMDDup64FromElement;
3132 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3133 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3134 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3135 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3136 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3137 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3139 def : Pat<(v2f32 (ARM64dup (f32 FPR32:$Rn))),
3140 (v2f32 (DUPv2i32lane
3141 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3143 def : Pat<(v4f32 (ARM64dup (f32 FPR32:$Rn))),
3144 (v4f32 (DUPv4i32lane
3145 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3147 def : Pat<(v2f64 (ARM64dup (f64 FPR64:$Rn))),
3148 (v2f64 (DUPv2i64lane
3149 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3152 def : Pat<(v2f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3153 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3154 def : Pat<(v4f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3155 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3156 def : Pat<(v2f64 (ARM64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3157 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3159 // If there's an (ARM64dup (vector_extract ...) ...), we can use a duplane
3160 // instruction even if the types don't match: we just have to remap the lane
3161 // carefully. N.b. this trick only applies to truncations.
3162 def VecIndex_x2 : SDNodeXForm<imm, [{
3163 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3165 def VecIndex_x4 : SDNodeXForm<imm, [{
3166 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3168 def VecIndex_x8 : SDNodeXForm<imm, [{
3169 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3172 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3173 ValueType Src128VT, ValueType ScalVT,
3174 Instruction DUP, SDNodeXForm IdxXFORM> {
3175 def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3177 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3179 def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3181 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3184 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3185 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3186 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3188 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3189 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3190 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3192 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3193 SDNodeXForm IdxXFORM> {
3194 def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3196 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3198 def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3200 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3203 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3204 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3205 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3207 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3208 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3209 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3211 // SMOV and UMOV definitions, with some extra patterns for convenience
3215 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3216 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3217 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3218 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3219 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3220 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3221 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3222 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3223 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3224 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3225 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3226 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3228 // Extracting i8 or i16 elements will have the zero-extend transformed to
3229 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3230 // for ARM64. Match these patterns here since UMOV already zeroes out the high
3231 // bits of the destination register.
3232 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3234 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3235 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3237 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3241 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3242 (SUBREG_TO_REG (i32 0),
3243 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3244 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3245 (SUBREG_TO_REG (i32 0),
3246 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3248 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3249 (SUBREG_TO_REG (i32 0),
3250 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3251 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3252 (SUBREG_TO_REG (i32 0),
3253 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3255 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3256 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3257 (i32 FPR32:$Rn), ssub))>;
3258 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3259 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3260 (i32 FPR32:$Rn), ssub))>;
3261 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3262 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3263 (i64 FPR64:$Rn), dsub))>;
3265 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3266 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3267 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3268 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3269 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3270 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3272 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3273 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3276 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3278 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3281 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3282 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3284 V128:$Rn, VectorIndexS:$imm,
3285 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3287 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3288 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3290 V128:$Rn, VectorIndexD:$imm,
3291 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3294 // Copy an element at a constant index in one vector into a constant indexed
3295 // element of another.
3296 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3297 // index type and INS extension
3298 def : Pat<(v16i8 (int_arm64_neon_vcopy_lane
3299 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3300 VectorIndexB:$idx2)),
3302 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3304 def : Pat<(v8i16 (int_arm64_neon_vcopy_lane
3305 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3306 VectorIndexH:$idx2)),
3308 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3310 def : Pat<(v4i32 (int_arm64_neon_vcopy_lane
3311 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3312 VectorIndexS:$idx2)),
3314 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3316 def : Pat<(v2i64 (int_arm64_neon_vcopy_lane
3317 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3318 VectorIndexD:$idx2)),
3320 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3323 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3324 ValueType VTScal, Instruction INS> {
3325 def : Pat<(VT128 (vector_insert V128:$src,
3326 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3328 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3330 def : Pat<(VT128 (vector_insert V128:$src,
3331 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3333 (INS V128:$src, imm:$Immd,
3334 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3336 def : Pat<(VT64 (vector_insert V64:$src,
3337 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3339 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3340 imm:$Immd, V128:$Rn, imm:$Immn),
3343 def : Pat<(VT64 (vector_insert V64:$src,
3344 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3347 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3348 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3352 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3353 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3354 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3355 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3356 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3357 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3360 // Floating point vector extractions are codegen'd as either a sequence of
3361 // subregister extractions, possibly fed by an INS if the lane number is
3362 // anything other than zero.
3363 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3364 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3365 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3366 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3367 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3368 (f64 (EXTRACT_SUBREG
3369 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3370 V128:$Rn, VectorIndexD:$idx),
3372 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3373 (f32 (EXTRACT_SUBREG
3374 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3375 V128:$Rn, VectorIndexS:$idx),
3378 // All concat_vectors operations are canonicalised to act on i64 vectors for
3379 // ARM64. In the general case we need an instruction, which had just as well be
3381 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3382 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3383 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3384 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3386 def : ConcatPat<v2i64, v1i64>;
3387 def : ConcatPat<v2f64, v1f64>;
3388 def : ConcatPat<v4i32, v2i32>;
3389 def : ConcatPat<v4f32, v2f32>;
3390 def : ConcatPat<v8i16, v4i16>;
3391 def : ConcatPat<v16i8, v8i8>;
3393 // If the high lanes are undef, though, we can just ignore them:
3394 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3395 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3396 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3398 def : ConcatUndefPat<v2i64, v1i64>;
3399 def : ConcatUndefPat<v2f64, v1f64>;
3400 def : ConcatUndefPat<v4i32, v2i32>;
3401 def : ConcatUndefPat<v4f32, v2f32>;
3402 def : ConcatUndefPat<v8i16, v4i16>;
3403 def : ConcatUndefPat<v16i8, v8i8>;
3405 //----------------------------------------------------------------------------
3406 // AdvSIMD across lanes instructions
3407 //----------------------------------------------------------------------------
3409 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3410 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3411 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3412 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3413 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3414 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3415 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3416 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_arm64_neon_fmaxnmv>;
3417 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_arm64_neon_fmaxv>;
3418 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_arm64_neon_fminnmv>;
3419 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_arm64_neon_fminv>;
3421 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3422 // If there is a sign extension after this intrinsic, consume it as smov already
3424 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3426 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3427 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3429 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3431 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3432 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3434 // If there is a sign extension after this intrinsic, consume it as smov already
3436 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3438 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3439 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3441 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3443 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3444 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3446 // If there is a sign extension after this intrinsic, consume it as smov already
3448 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3450 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3451 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3453 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3455 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3456 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3458 // If there is a sign extension after this intrinsic, consume it as smov already
3460 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3462 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3463 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3465 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3467 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3468 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3471 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3472 (i32 (EXTRACT_SUBREG
3473 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3474 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3478 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3479 // If there is a masking operation keeping only what has been actually
3480 // generated, consume it.
3481 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3482 (i32 (EXTRACT_SUBREG
3483 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3484 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3486 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3487 (i32 (EXTRACT_SUBREG
3488 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3489 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3491 // If there is a masking operation keeping only what has been actually
3492 // generated, consume it.
3493 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3494 (i32 (EXTRACT_SUBREG
3495 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3496 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3498 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3499 (i32 (EXTRACT_SUBREG
3500 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3501 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3504 // If there is a masking operation keeping only what has been actually
3505 // generated, consume it.
3506 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3507 (i32 (EXTRACT_SUBREG
3508 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3509 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3511 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3512 (i32 (EXTRACT_SUBREG
3513 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3514 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3516 // If there is a masking operation keeping only what has been actually
3517 // generated, consume it.
3518 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3519 (i32 (EXTRACT_SUBREG
3520 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3521 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3523 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3524 (i32 (EXTRACT_SUBREG
3525 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3526 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3529 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3530 (i32 (EXTRACT_SUBREG
3531 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3532 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3537 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3538 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3540 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3541 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3543 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3545 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3546 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3549 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3550 (i32 (EXTRACT_SUBREG
3551 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3552 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3554 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3555 (i32 (EXTRACT_SUBREG
3556 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3557 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3560 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3561 (i64 (EXTRACT_SUBREG
3562 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3563 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3567 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3569 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3570 (i32 (EXTRACT_SUBREG
3571 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3572 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3574 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3575 (i32 (EXTRACT_SUBREG
3576 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3577 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3580 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3581 (i32 (EXTRACT_SUBREG
3582 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3583 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3585 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3586 (i32 (EXTRACT_SUBREG
3587 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3588 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3591 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3592 (i64 (EXTRACT_SUBREG
3593 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3594 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3598 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_arm64_neon_saddv>;
3599 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3600 def : Pat<(i32 (int_arm64_neon_saddv (v2i32 V64:$Rn))),
3601 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3603 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_arm64_neon_uaddv>;
3604 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3605 def : Pat<(i32 (int_arm64_neon_uaddv (v2i32 V64:$Rn))),
3606 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3608 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_arm64_neon_smaxv>;
3609 def : Pat<(i32 (int_arm64_neon_smaxv (v2i32 V64:$Rn))),
3610 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3612 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_arm64_neon_sminv>;
3613 def : Pat<(i32 (int_arm64_neon_sminv (v2i32 V64:$Rn))),
3614 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3616 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_arm64_neon_umaxv>;
3617 def : Pat<(i32 (int_arm64_neon_umaxv (v2i32 V64:$Rn))),
3618 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3620 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_arm64_neon_uminv>;
3621 def : Pat<(i32 (int_arm64_neon_uminv (v2i32 V64:$Rn))),
3622 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3624 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_arm64_neon_saddlv>;
3625 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_arm64_neon_uaddlv>;
3627 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3628 def : Pat<(i64 (int_arm64_neon_saddlv (v2i32 V64:$Rn))),
3629 (i64 (EXTRACT_SUBREG
3630 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3631 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3633 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3634 def : Pat<(i64 (int_arm64_neon_uaddlv (v2i32 V64:$Rn))),
3635 (i64 (EXTRACT_SUBREG
3636 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3637 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3640 //------------------------------------------------------------------------------
3641 // AdvSIMD modified immediate instructions
3642 //------------------------------------------------------------------------------
3645 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", ARM64bici>;
3647 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", ARM64orri>;
3649 def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3650 def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3651 def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3652 def : InstAlias<"bic $Vd.4s, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3654 def : InstAlias<"bic.4h $Vd, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3655 def : InstAlias<"bic.8h $Vd, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3656 def : InstAlias<"bic.2s $Vd, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3657 def : InstAlias<"bic.4s $Vd, $imm", (BICv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3659 def : InstAlias<"orr $Vd.4h, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>;
3660 def : InstAlias<"orr $Vd.8h, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>;
3661 def : InstAlias<"orr $Vd.2s, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>;
3662 def : InstAlias<"orr $Vd.4s, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>;
3664 def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3665 def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3666 def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3667 def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3670 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3672 [(set (v2f64 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3673 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3675 [(set (v2f32 V64:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3676 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3678 [(set (v4f32 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3682 // EDIT byte mask: scalar
3683 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3684 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3685 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3686 // The movi_edit node has the immediate value already encoded, so we use
3687 // a plain imm0_255 here.
3688 def : Pat<(f64 (ARM64movi_edit imm0_255:$shift)),
3689 (MOVID imm0_255:$shift)>;
3691 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3692 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3693 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3694 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3696 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3697 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3698 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3699 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3701 // EDIT byte mask: 2d
3703 // The movi_edit node has the immediate value already encoded, so we use
3704 // a plain imm0_255 in the pattern
3705 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3706 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3709 [(set (v2i64 V128:$Rd), (ARM64movi_edit imm0_255:$imm8))]>;
3712 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3713 // Complexity is added to break a tie with a plain MOVI.
3714 let AddedComplexity = 1 in {
3715 def : Pat<(f32 fpimm0),
3716 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3718 def : Pat<(f64 fpimm0),
3719 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3723 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3724 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3725 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3726 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3728 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3729 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3730 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3731 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3733 def : Pat<(v2f64 (ARM64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
3734 def : Pat<(v4f32 (ARM64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
3736 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3737 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3739 // FIXME: these should be canonical but the TableGen alias printer can't cope
3740 // with syntax variants.
3741 def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3742 def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3743 def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3744 def : InstAlias<"movi $Vd.4s, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3746 def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3747 def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3748 def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3749 def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3751 def : Pat<(v2i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3752 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
3753 def : Pat<(v4i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3754 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
3755 def : Pat<(v4i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3756 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
3757 def : Pat<(v8i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3758 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
3760 // EDIT per word: 2s & 4s with MSL shifter
3761 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
3762 [(set (v2i32 V64:$Rd),
3763 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3764 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
3765 [(set (v4i32 V128:$Rd),
3766 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3768 // Per byte: 8b & 16b
3769 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
3771 [(set (v8i8 V64:$Rd), (ARM64movi imm0_255:$imm8))]>;
3772 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
3774 [(set (v16i8 V128:$Rd), (ARM64movi imm0_255:$imm8))]>;
3778 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3779 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
3781 // FIXME: these should be canonical, but TableGen can't do aliases & syntax
3782 // variants together.
3783 def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3784 def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3785 def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3786 def : InstAlias<"mvni $Vd.4s, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3788 def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>;
3789 def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>;
3790 def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>;
3791 def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>;
3793 def : Pat<(v2i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3794 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
3795 def : Pat<(v4i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3796 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
3797 def : Pat<(v4i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3798 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
3799 def : Pat<(v8i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3800 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
3802 // EDIT per word: 2s & 4s with MSL shifter
3803 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
3804 [(set (v2i32 V64:$Rd),
3805 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3806 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
3807 [(set (v4i32 V128:$Rd),
3808 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3810 //----------------------------------------------------------------------------
3811 // AdvSIMD indexed element
3812 //----------------------------------------------------------------------------
3814 let neverHasSideEffects = 1 in {
3815 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
3816 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
3819 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
3820 // instruction expects the addend first, while the intrinsic expects it last.
3822 // On the other hand, there are quite a few valid combinatorial options due to
3823 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
3824 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3825 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
3826 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3827 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
3829 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3830 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
3831 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3832 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
3833 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3834 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
3835 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3836 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
3838 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
3839 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3841 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3842 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3843 VectorIndexS:$idx))),
3844 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3845 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3846 (v2f32 (ARM64duplane32
3847 (v4f32 (insert_subvector undef,
3848 (v2f32 (fneg V64:$Rm)),
3850 VectorIndexS:$idx)))),
3851 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3852 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3853 VectorIndexS:$idx)>;
3854 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3855 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3856 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3857 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3859 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3861 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3862 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3863 VectorIndexS:$idx))),
3864 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
3865 VectorIndexS:$idx)>;
3866 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3867 (v4f32 (ARM64duplane32
3868 (v4f32 (insert_subvector undef,
3869 (v2f32 (fneg V64:$Rm)),
3871 VectorIndexS:$idx)))),
3872 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3873 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3874 VectorIndexS:$idx)>;
3875 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3876 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3877 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3878 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3880 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
3881 // (DUPLANE from 64-bit would be trivial).
3882 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3883 (ARM64duplane64 (v2f64 (fneg V128:$Rm)),
3884 VectorIndexD:$idx))),
3886 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3887 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3888 (ARM64dup (f64 (fneg FPR64Op:$Rm))))),
3889 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
3890 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
3892 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
3893 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3894 (vector_extract (v4f32 (fneg V128:$Rm)),
3895 VectorIndexS:$idx))),
3896 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3897 V128:$Rm, VectorIndexS:$idx)>;
3898 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3899 (vector_extract (v2f32 (fneg V64:$Rm)),
3900 VectorIndexS:$idx))),
3901 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3902 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
3904 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
3905 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
3906 (vector_extract (v2f64 (fneg V128:$Rm)),
3907 VectorIndexS:$idx))),
3908 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
3909 V128:$Rm, VectorIndexS:$idx)>;
3912 defm : FMLSIndexedAfterNegPatterns<
3913 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
3914 defm : FMLSIndexedAfterNegPatterns<
3915 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
3917 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_arm64_neon_fmulx>;
3918 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
3920 def : Pat<(v2f32 (fmul V64:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3921 (FMULv2i32_indexed V64:$Rn,
3922 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3924 def : Pat<(v4f32 (fmul V128:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3925 (FMULv4i32_indexed V128:$Rn,
3926 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3928 def : Pat<(v2f64 (fmul V128:$Rn, (ARM64dup (f64 FPR64:$Rm)))),
3929 (FMULv2i64_indexed V128:$Rn,
3930 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
3933 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_arm64_neon_sqdmulh>;
3934 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_arm64_neon_sqrdmulh>;
3935 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
3936 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
3937 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
3938 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
3939 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
3940 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
3941 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3942 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
3943 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3944 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
3945 int_arm64_neon_smull>;
3946 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
3947 int_arm64_neon_sqadd>;
3948 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
3949 int_arm64_neon_sqsub>;
3950 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_arm64_neon_sqdmull>;
3951 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
3952 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3953 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
3954 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3955 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
3956 int_arm64_neon_umull>;
3958 // A scalar sqdmull with the second operand being a vector lane can be
3959 // handled directly with the indexed instruction encoding.
3960 def : Pat<(int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3961 (vector_extract (v4i32 V128:$Vm),
3962 VectorIndexS:$idx)),
3963 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
3965 //----------------------------------------------------------------------------
3966 // AdvSIMD scalar shift instructions
3967 //----------------------------------------------------------------------------
3968 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
3969 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
3970 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
3971 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
3972 // Codegen patterns for the above. We don't put these directly on the
3973 // instructions because TableGen's type inference can't handle the truth.
3974 // Having the same base pattern for fp <--> int totally freaks it out.
3975 def : Pat<(int_arm64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
3976 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
3977 def : Pat<(int_arm64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
3978 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
3979 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
3980 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3981 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
3982 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3983 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
3985 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3986 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
3988 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3989 def : Pat<(int_arm64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
3990 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3991 def : Pat<(int_arm64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
3992 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3993 def : Pat<(f64 (int_arm64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3994 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3995 def : Pat<(f64 (int_arm64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3996 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3997 def : Pat<(v1f64 (int_arm64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
3999 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4000 def : Pat<(v1f64 (int_arm64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
4002 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
4004 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", ARM64vshl>;
4005 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
4006 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
4007 int_arm64_neon_sqrshrn>;
4008 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
4009 int_arm64_neon_sqrshrun>;
4010 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
4011 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
4012 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
4013 int_arm64_neon_sqshrn>;
4014 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
4015 int_arm64_neon_sqshrun>;
4016 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
4017 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", ARM64srshri>;
4018 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
4019 TriOpFrag<(add node:$LHS,
4020 (ARM64srshri node:$MHS, node:$RHS))>>;
4021 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", ARM64vashr>;
4022 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
4023 TriOpFrag<(add node:$LHS,
4024 (ARM64vashr node:$MHS, node:$RHS))>>;
4025 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
4026 int_arm64_neon_uqrshrn>;
4027 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
4028 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
4029 int_arm64_neon_uqshrn>;
4030 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", ARM64urshri>;
4031 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
4032 TriOpFrag<(add node:$LHS,
4033 (ARM64urshri node:$MHS, node:$RHS))>>;
4034 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", ARM64vlshr>;
4035 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
4036 TriOpFrag<(add node:$LHS,
4037 (ARM64vlshr node:$MHS, node:$RHS))>>;
4039 //----------------------------------------------------------------------------
4040 // AdvSIMD vector shift instructions
4041 //----------------------------------------------------------------------------
4042 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_arm64_neon_vcvtfp2fxs>;
4043 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_arm64_neon_vcvtfp2fxu>;
4044 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
4045 int_arm64_neon_vcvtfxs2fp>;
4046 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
4047 int_arm64_neon_rshrn>;
4048 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", ARM64vshl>;
4049 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
4050 BinOpFrag<(trunc (ARM64vashr node:$LHS, node:$RHS))>>;
4051 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_arm64_neon_vsli>;
4052 def : Pat<(v1i64 (int_arm64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4053 (i32 vecshiftL64:$imm))),
4054 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
4055 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
4056 int_arm64_neon_sqrshrn>;
4057 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
4058 int_arm64_neon_sqrshrun>;
4059 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
4060 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
4061 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
4062 int_arm64_neon_sqshrn>;
4063 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
4064 int_arm64_neon_sqshrun>;
4065 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_arm64_neon_vsri>;
4066 def : Pat<(v1i64 (int_arm64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
4067 (i32 vecshiftR64:$imm))),
4068 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
4069 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", ARM64srshri>;
4070 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
4071 TriOpFrag<(add node:$LHS,
4072 (ARM64srshri node:$MHS, node:$RHS))> >;
4073 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
4074 BinOpFrag<(ARM64vshl (sext node:$LHS), node:$RHS)>>;
4076 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", ARM64vashr>;
4077 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
4078 TriOpFrag<(add node:$LHS, (ARM64vashr node:$MHS, node:$RHS))>>;
4079 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
4080 int_arm64_neon_vcvtfxu2fp>;
4081 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
4082 int_arm64_neon_uqrshrn>;
4083 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
4084 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
4085 int_arm64_neon_uqshrn>;
4086 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", ARM64urshri>;
4087 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
4088 TriOpFrag<(add node:$LHS,
4089 (ARM64urshri node:$MHS, node:$RHS))> >;
4090 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
4091 BinOpFrag<(ARM64vshl (zext node:$LHS), node:$RHS)>>;
4092 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", ARM64vlshr>;
4093 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
4094 TriOpFrag<(add node:$LHS, (ARM64vlshr node:$MHS, node:$RHS))> >;
4096 // SHRN patterns for when a logical right shift was used instead of arithmetic
4097 // (the immediate guarantees no sign bits actually end up in the result so it
4099 def : Pat<(v8i8 (trunc (ARM64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
4100 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
4101 def : Pat<(v4i16 (trunc (ARM64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
4102 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
4103 def : Pat<(v2i32 (trunc (ARM64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
4104 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
4106 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
4107 (trunc (ARM64vlshr (v8i16 V128:$Rn),
4108 vecshiftR16Narrow:$imm)))),
4109 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4110 V128:$Rn, vecshiftR16Narrow:$imm)>;
4111 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
4112 (trunc (ARM64vlshr (v4i32 V128:$Rn),
4113 vecshiftR32Narrow:$imm)))),
4114 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4115 V128:$Rn, vecshiftR32Narrow:$imm)>;
4116 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
4117 (trunc (ARM64vlshr (v2i64 V128:$Rn),
4118 vecshiftR64Narrow:$imm)))),
4119 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
4120 V128:$Rn, vecshiftR32Narrow:$imm)>;
4122 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
4123 // Anyexts are implemented as zexts.
4124 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
4125 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4126 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
4127 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
4128 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4129 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
4130 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
4131 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4132 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
4133 // Also match an extend from the upper half of a 128 bit source register.
4134 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4135 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4136 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4137 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
4138 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
4139 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
4140 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4141 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4142 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4143 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
4144 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
4145 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
4146 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4147 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4148 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4149 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
4150 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
4151 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
4153 // Vector shift sxtl aliases
4154 def : InstAlias<"sxtl.8h $dst, $src1",
4155 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4156 def : InstAlias<"sxtl $dst.8h, $src1.8b",
4157 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4158 def : InstAlias<"sxtl.4s $dst, $src1",
4159 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4160 def : InstAlias<"sxtl $dst.4s, $src1.4h",
4161 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4162 def : InstAlias<"sxtl.2d $dst, $src1",
4163 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4164 def : InstAlias<"sxtl $dst.2d, $src1.2s",
4165 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4167 // Vector shift sxtl2 aliases
4168 def : InstAlias<"sxtl2.8h $dst, $src1",
4169 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4170 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
4171 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4172 def : InstAlias<"sxtl2.4s $dst, $src1",
4173 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4174 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4175 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4176 def : InstAlias<"sxtl2.2d $dst, $src1",
4177 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4178 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4179 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4181 // Vector shift uxtl aliases
4182 def : InstAlias<"uxtl.8h $dst, $src1",
4183 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4184 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4185 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4186 def : InstAlias<"uxtl.4s $dst, $src1",
4187 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4188 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4189 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4190 def : InstAlias<"uxtl.2d $dst, $src1",
4191 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4192 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4193 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4195 // Vector shift uxtl2 aliases
4196 def : InstAlias<"uxtl2.8h $dst, $src1",
4197 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4198 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4199 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4200 def : InstAlias<"uxtl2.4s $dst, $src1",
4201 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4202 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4203 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4204 def : InstAlias<"uxtl2.2d $dst, $src1",
4205 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4206 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4207 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4209 // If an integer is about to be converted to a floating point value,
4210 // just load it on the floating point unit.
4211 // These patterns are more complex because floating point loads do not
4212 // support sign extension.
4213 // The sign extension has to be explicitly added and is only supported for
4214 // one step: byte-to-half, half-to-word, word-to-doubleword.
4215 // SCVTF GPR -> FPR is 9 cycles.
4216 // SCVTF FPR -> FPR is 4 cyclces.
4217 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4218 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4219 // and still being faster.
4220 // However, this is not good for code size.
4221 // 8-bits -> float. 2 sizes step-up.
4222 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 ro_indexed8:$addr)))),
4223 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4228 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4229 (LDRBro ro_indexed8:$addr),
4234 ssub)))>, Requires<[NotForCodeSize]>;
4235 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_indexed8:$addr)))),
4236 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4241 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4242 (LDRBui am_indexed8:$addr),
4247 ssub)))>, Requires<[NotForCodeSize]>;
4248 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_unscaled8:$addr)))),
4249 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4254 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4255 (LDURBi am_unscaled8:$addr),
4260 ssub)))>, Requires<[NotForCodeSize]>;
4261 // 16-bits -> float. 1 size step-up.
4262 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
4263 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4265 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4266 (LDRHro ro_indexed16:$addr),
4269 ssub)))>, Requires<[NotForCodeSize]>;
4270 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
4271 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4273 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4274 (LDRHui am_indexed16:$addr),
4277 ssub)))>, Requires<[NotForCodeSize]>;
4278 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
4279 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4281 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4282 (LDURHi am_unscaled16:$addr),
4285 ssub)))>, Requires<[NotForCodeSize]>;
4286 // 32-bits to 32-bits are handled in target specific dag combine:
4287 // performIntToFpCombine.
4288 // 64-bits integer to 32-bits floating point, not possible with
4289 // SCVTF on floating point registers (both source and destination
4290 // must have the same size).
4292 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4293 // 8-bits -> double. 3 size step-up: give up.
4294 // 16-bits -> double. 2 size step.
4295 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
4296 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4301 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4302 (LDRHro ro_indexed16:$addr),
4307 dsub)))>, Requires<[NotForCodeSize]>;
4308 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
4309 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4314 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4315 (LDRHui am_indexed16:$addr),
4320 dsub)))>, Requires<[NotForCodeSize]>;
4321 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
4322 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4327 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4328 (LDURHi am_unscaled16:$addr),
4333 dsub)))>, Requires<[NotForCodeSize]>;
4334 // 32-bits -> double. 1 size step-up.
4335 def : Pat <(f64 (sint_to_fp (i32 (load ro_indexed32:$addr)))),
4336 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4338 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4339 (LDRSro ro_indexed32:$addr),
4342 dsub)))>, Requires<[NotForCodeSize]>;
4343 def : Pat <(f64 (sint_to_fp (i32 (load am_indexed32:$addr)))),
4344 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4346 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4347 (LDRSui am_indexed32:$addr),
4350 dsub)))>, Requires<[NotForCodeSize]>;
4351 def : Pat <(f64 (sint_to_fp (i32 (load am_unscaled32:$addr)))),
4352 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4354 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4355 (LDURSi am_unscaled32:$addr),
4358 dsub)))>, Requires<[NotForCodeSize]>;
4359 // 64-bits -> double are handled in target specific dag combine:
4360 // performIntToFpCombine.
4363 //----------------------------------------------------------------------------
4364 // AdvSIMD Load-Store Structure
4365 //----------------------------------------------------------------------------
4366 defm LD1 : SIMDLd1Multiple<"ld1">;
4367 defm LD2 : SIMDLd2Multiple<"ld2">;
4368 defm LD3 : SIMDLd3Multiple<"ld3">;
4369 defm LD4 : SIMDLd4Multiple<"ld4">;
4371 defm ST1 : SIMDSt1Multiple<"st1">;
4372 defm ST2 : SIMDSt2Multiple<"st2">;
4373 defm ST3 : SIMDSt3Multiple<"st3">;
4374 defm ST4 : SIMDSt4Multiple<"st4">;
4376 class Ld1Pat<ValueType ty, Instruction INST>
4377 : Pat<(ty (load am_simdnoindex:$vaddr)), (INST am_simdnoindex:$vaddr)>;
4379 def : Ld1Pat<v16i8, LD1Onev16b>;
4380 def : Ld1Pat<v8i16, LD1Onev8h>;
4381 def : Ld1Pat<v4i32, LD1Onev4s>;
4382 def : Ld1Pat<v2i64, LD1Onev2d>;
4383 def : Ld1Pat<v8i8, LD1Onev8b>;
4384 def : Ld1Pat<v4i16, LD1Onev4h>;
4385 def : Ld1Pat<v2i32, LD1Onev2s>;
4386 def : Ld1Pat<v1i64, LD1Onev1d>;
4388 class St1Pat<ValueType ty, Instruction INST>
4389 : Pat<(store ty:$Vt, am_simdnoindex:$vaddr),
4390 (INST ty:$Vt, am_simdnoindex:$vaddr)>;
4392 def : St1Pat<v16i8, ST1Onev16b>;
4393 def : St1Pat<v8i16, ST1Onev8h>;
4394 def : St1Pat<v4i32, ST1Onev4s>;
4395 def : St1Pat<v2i64, ST1Onev2d>;
4396 def : St1Pat<v8i8, ST1Onev8b>;
4397 def : St1Pat<v4i16, ST1Onev4h>;
4398 def : St1Pat<v2i32, ST1Onev2s>;
4399 def : St1Pat<v1i64, ST1Onev1d>;
4405 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4406 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4407 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4408 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4409 let mayLoad = 1, neverHasSideEffects = 1 in {
4410 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4411 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4412 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4413 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4414 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4415 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4416 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4417 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4418 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4419 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4420 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4421 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4422 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4423 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4424 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4425 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4428 def : Pat<(v8i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4429 (LD1Rv8b am_simdnoindex:$vaddr)>;
4430 def : Pat<(v16i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4431 (LD1Rv16b am_simdnoindex:$vaddr)>;
4432 def : Pat<(v4i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4433 (LD1Rv4h am_simdnoindex:$vaddr)>;
4434 def : Pat<(v8i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4435 (LD1Rv8h am_simdnoindex:$vaddr)>;
4436 def : Pat<(v2i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4437 (LD1Rv2s am_simdnoindex:$vaddr)>;
4438 def : Pat<(v4i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4439 (LD1Rv4s am_simdnoindex:$vaddr)>;
4440 def : Pat<(v2i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4441 (LD1Rv2d am_simdnoindex:$vaddr)>;
4442 def : Pat<(v1i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4443 (LD1Rv1d am_simdnoindex:$vaddr)>;
4444 // Grab the floating point version too
4445 def : Pat<(v2f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4446 (LD1Rv2s am_simdnoindex:$vaddr)>;
4447 def : Pat<(v4f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4448 (LD1Rv4s am_simdnoindex:$vaddr)>;
4449 def : Pat<(v2f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4450 (LD1Rv2d am_simdnoindex:$vaddr)>;
4451 def : Pat<(v1f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4452 (LD1Rv1d am_simdnoindex:$vaddr)>;
4454 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4455 ValueType VTy, ValueType STy, Instruction LD1>
4456 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4457 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4458 (LD1 VecListOne128:$Rd, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4460 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4461 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4462 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4463 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4464 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4465 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4467 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4468 ValueType VTy, ValueType STy, Instruction LD1>
4469 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4470 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4472 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4473 VecIndex:$idx, am_simdnoindex:$vaddr),
4476 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4477 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4478 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4479 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4482 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4483 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4484 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4485 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4488 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4489 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4490 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4491 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4493 let AddedComplexity = 8 in
4494 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4495 ValueType VTy, ValueType STy, Instruction ST1>
4497 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4498 am_simdnoindex:$vaddr),
4499 (ST1 VecListOne128:$Vt, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4501 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4502 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4503 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4504 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4505 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4506 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4508 let AddedComplexity = 8 in
4509 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4510 ValueType VTy, ValueType STy, Instruction ST1>
4512 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4513 am_simdnoindex:$vaddr),
4514 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4515 VecIndex:$idx, am_simdnoindex:$vaddr)>;
4517 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4518 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4519 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4520 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4522 multiclass St1LanePost64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4523 ValueType VTy, ValueType STy, Instruction ST1,
4525 def : Pat<(scalar_store
4526 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4527 am_simdnoindex:$vaddr, offset),
4528 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4529 VecIndex:$idx, am_simdnoindex:$vaddr, XZR)>;
4531 def : Pat<(scalar_store
4532 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4533 am_simdnoindex:$vaddr, GPR64:$Rm),
4534 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4535 VecIndex:$idx, am_simdnoindex:$vaddr, $Rm)>;
4538 defm : St1LanePost64Pat<post_truncsti8, VectorIndexB, v8i8, i32, ST1i8_POST, 1>;
4539 defm : St1LanePost64Pat<post_truncsti16, VectorIndexH, v4i16, i32, ST1i16_POST,
4541 defm : St1LanePost64Pat<post_store, VectorIndexS, v2i32, i32, ST1i32_POST, 4>;
4542 defm : St1LanePost64Pat<post_store, VectorIndexS, v2f32, f32, ST1i32_POST, 4>;
4543 defm : St1LanePost64Pat<post_store, VectorIndexD, v1i64, i64, ST1i64_POST, 8>;
4544 defm : St1LanePost64Pat<post_store, VectorIndexD, v1f64, f64, ST1i64_POST, 8>;
4546 multiclass St1LanePost128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4547 ValueType VTy, ValueType STy, Instruction ST1,
4549 def : Pat<(scalar_store
4550 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4551 am_simdnoindex:$vaddr, offset),
4552 (ST1 VecListOne128:$Vt, VecIndex:$idx, am_simdnoindex:$vaddr, XZR)>;
4554 def : Pat<(scalar_store
4555 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4556 am_simdnoindex:$vaddr, GPR64:$Rm),
4557 (ST1 VecListOne128:$Vt, VecIndex:$idx, am_simdnoindex:$vaddr, $Rm)>;
4560 defm : St1LanePost128Pat<post_truncsti8, VectorIndexB, v16i8, i32, ST1i8_POST,
4562 defm : St1LanePost128Pat<post_truncsti16, VectorIndexH, v8i16, i32, ST1i16_POST,
4564 defm : St1LanePost128Pat<post_store, VectorIndexS, v4i32, i32, ST1i32_POST, 4>;
4565 defm : St1LanePost128Pat<post_store, VectorIndexS, v4f32, f32, ST1i32_POST, 4>;
4566 defm : St1LanePost128Pat<post_store, VectorIndexD, v2i64, i64, ST1i64_POST, 8>;
4567 defm : St1LanePost128Pat<post_store, VectorIndexD, v2f64, f64, ST1i64_POST, 8>;
4569 let mayStore = 1, neverHasSideEffects = 1 in {
4570 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4571 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4572 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4573 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4574 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4575 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4576 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4577 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4578 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4579 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4580 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4581 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4584 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4585 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4586 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4587 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4589 //----------------------------------------------------------------------------
4590 // Crypto extensions
4591 //----------------------------------------------------------------------------
4593 def AESErr : AESTiedInst<0b0100, "aese", int_arm64_crypto_aese>;
4594 def AESDrr : AESTiedInst<0b0101, "aesd", int_arm64_crypto_aesd>;
4595 def AESMCrr : AESInst< 0b0110, "aesmc", int_arm64_crypto_aesmc>;
4596 def AESIMCrr : AESInst< 0b0111, "aesimc", int_arm64_crypto_aesimc>;
4598 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_arm64_crypto_sha1c>;
4599 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_arm64_crypto_sha1p>;
4600 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_arm64_crypto_sha1m>;
4601 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_arm64_crypto_sha1su0>;
4602 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_arm64_crypto_sha256h>;
4603 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_arm64_crypto_sha256h2>;
4604 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_arm64_crypto_sha256su1>;
4606 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_arm64_crypto_sha1h>;
4607 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_arm64_crypto_sha1su1>;
4608 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_arm64_crypto_sha256su0>;
4610 //----------------------------------------------------------------------------
4612 //----------------------------------------------------------------------------
4613 // FIXME: Like for X86, these should go in their own separate .td file.
4615 // Any instruction that defines a 32-bit result leaves the high half of the
4616 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4617 // be copying from a truncate. But any other 32-bit operation will zero-extend
4619 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4620 def def32 : PatLeaf<(i32 GPR32:$src), [{
4621 return N->getOpcode() != ISD::TRUNCATE &&
4622 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4623 N->getOpcode() != ISD::CopyFromReg;
4626 // In the case of a 32-bit def that is known to implicitly zero-extend,
4627 // we can use a SUBREG_TO_REG.
4628 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4630 // For an anyext, we don't care what the high bits are, so we can perform an
4631 // INSERT_SUBREF into an IMPLICIT_DEF.
4632 def : Pat<(i64 (anyext GPR32:$src)),
4633 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4635 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4636 // instruction (UBFM) on the enclosing super-reg.
4637 def : Pat<(i64 (zext GPR32:$src)),
4638 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4640 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4641 // containing super-reg.
4642 def : Pat<(i64 (sext GPR32:$src)),
4643 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4644 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4645 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4646 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4647 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4648 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4649 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4650 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4652 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4653 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4654 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4655 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4656 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4657 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4659 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4660 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4661 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4662 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4663 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4664 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4666 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4667 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4668 (i64 (i64shift_a imm0_63:$imm)),
4669 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4671 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4672 // AddedComplexity for the following patterns since we want to match sext + sra
4673 // patterns before we attempt to match a single sra node.
4674 let AddedComplexity = 20 in {
4675 // We support all sext + sra combinations which preserve at least one bit of the
4676 // original value which is to be sign extended. E.g. we support shifts up to
4678 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4679 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4680 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4681 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4683 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4684 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4685 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4686 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4688 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4689 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4690 (i64 imm0_31:$imm), 31)>;
4691 } // AddedComplexity = 20
4693 // To truncate, we can simply extract from a subregister.
4694 def : Pat<(i32 (trunc GPR64sp:$src)),
4695 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4697 // __builtin_trap() uses the BRK instruction on ARM64.
4698 def : Pat<(trap), (BRK 1)>;
4700 // Conversions within AdvSIMD types in the same register size are free.
4701 // But because we need a consistent lane ordering, in big endian many
4702 // conversions require one or more REV instructions.
4704 // Consider a simple memory load followed by a bitconvert then a store.
4706 // v1 = BITCAST v2i32 v0 to v4i16
4709 // In big endian mode every memory access has an implicit byte swap. LDR and
4710 // STR do a 64-bit byte swap, whereas LD1/ST1 do a byte swap per lane - that
4711 // is, they treat the vector as a sequence of elements to be byte-swapped.
4712 // The two pairs of instructions are fundamentally incompatible. We've decided
4713 // to use LD1/ST1 only to simplify compiler implementation.
4715 // LD1/ST1 perform the equivalent of a sequence of LDR/STR + REV. This makes
4716 // the original code sequence:
4718 // v1 = REV v2i32 (implicit)
4719 // v2 = BITCAST v2i32 v1 to v4i16
4720 // v3 = REV v4i16 v2 (implicit)
4723 // But this is now broken - the value stored is different to the value loaded
4724 // due to lane reordering. To fix this, on every BITCAST we must perform two
4727 // v1 = REV v2i32 (implicit)
4729 // v3 = BITCAST v2i32 v2 to v4i16
4731 // v5 = REV v4i16 v4 (implicit)
4734 // This means an extra two instructions, but actually in most cases the two REV
4735 // instructions can be combined into one. For example:
4736 // (REV64_2s (REV64_4h X)) === (REV32_4h X)
4738 // There is also no 128-bit REV instruction. This must be synthesized with an
4741 // Most bitconverts require some sort of conversion. The only exceptions are:
4742 // a) Identity conversions - vNfX <-> vNiX
4743 // b) Single-lane-to-scalar - v1fX <-> fX or v1iX <-> iX
4746 let Predicates = [IsLE] in {
4747 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4748 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4749 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4750 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4752 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4753 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4754 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4755 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4756 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4757 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4758 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4759 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4760 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4761 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4763 let Predicates = [IsBE] in {
4764 def : Pat<(v8i8 (bitconvert GPR64:$Xn)),
4765 (REV64v8i8 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4766 def : Pat<(v4i16 (bitconvert GPR64:$Xn)),
4767 (REV64v4i16 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4768 def : Pat<(v2i32 (bitconvert GPR64:$Xn)),
4769 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4770 def : Pat<(v2f32 (bitconvert GPR64:$Xn)),
4771 (REV64v2i32 (COPY_TO_REGCLASS GPR64:$Xn, FPR64))>;
4773 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
4774 (REV64v8i8 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4775 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
4776 (REV64v4i16 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4777 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
4778 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4779 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
4780 (REV64v2i32 (COPY_TO_REGCLASS V64:$Vn, GPR64))>;
4782 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4783 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4784 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
4785 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4786 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
4787 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4788 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
4789 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4790 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
4792 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
4793 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
4794 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
4795 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
4796 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
4797 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
4798 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
4799 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
4800 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
4801 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
4803 let Predicates = [IsLE] in {
4804 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
4805 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
4806 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
4807 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
4809 let Predicates = [IsBE] in {
4810 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))),
4811 (v1i64 (REV64v2i32 FPR64:$src))>;
4812 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))),
4813 (v1i64 (REV64v4i16 FPR64:$src))>;
4814 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))),
4815 (v1i64 (REV64v8i8 FPR64:$src))>;
4816 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))),
4817 (v1i64 (REV64v2i32 FPR64:$src))>;
4819 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4820 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4822 let Predicates = [IsLE] in {
4823 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
4824 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
4825 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
4826 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4827 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4829 let Predicates = [IsBE] in {
4830 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))),
4831 (v2i32 (REV64v2i32 FPR64:$src))>;
4832 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))),
4833 (v2i32 (REV32v4i16 FPR64:$src))>;
4834 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))),
4835 (v2i32 (REV32v8i8 FPR64:$src))>;
4836 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))),
4837 (v2i32 (REV64v2i32 FPR64:$src))>;
4838 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))),
4839 (v2i32 (REV64v2i32 FPR64:$src))>;
4841 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
4843 let Predicates = [IsLE] in {
4844 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
4845 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
4846 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
4847 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4848 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
4849 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4851 let Predicates = [IsBE] in {
4852 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))),
4853 (v4i16 (REV64v4i16 FPR64:$src))>;
4854 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))),
4855 (v4i16 (REV32v4i16 FPR64:$src))>;
4856 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))),
4857 (v4i16 (REV16v8i8 FPR64:$src))>;
4858 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))),
4859 (v4i16 (REV64v4i16 FPR64:$src))>;
4860 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))),
4861 (v4i16 (REV32v4i16 FPR64:$src))>;
4862 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))),
4863 (v4i16 (REV64v4i16 FPR64:$src))>;
4866 let Predicates = [IsLE] in {
4867 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
4868 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
4869 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
4870 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4871 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
4872 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4874 let Predicates = [IsBE] in {
4875 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))),
4876 (v8i8 (REV64v8i8 FPR64:$src))>;
4877 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))),
4878 (v8i8 (REV32v8i8 FPR64:$src))>;
4879 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))),
4880 (v8i8 (REV16v8i8 FPR64:$src))>;
4881 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))),
4882 (v8i8 (REV64v8i8 FPR64:$src))>;
4883 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))),
4884 (v8i8 (REV32v8i8 FPR64:$src))>;
4885 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))),
4886 (v8i8 (REV64v8i8 FPR64:$src))>;
4889 let Predicates = [IsLE] in {
4890 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
4891 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
4892 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
4893 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
4895 let Predicates = [IsBE] in {
4896 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))),
4897 (f64 (REV64v2i32 FPR64:$src))>;
4898 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))),
4899 (f64 (REV64v4i16 FPR64:$src))>;
4900 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))),
4901 (f64 (REV64v2i32 FPR64:$src))>;
4902 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))),
4903 (f64 (REV64v8i8 FPR64:$src))>;
4905 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
4906 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
4908 let Predicates = [IsLE] in {
4909 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
4910 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
4911 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
4912 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
4914 let Predicates = [IsBE] in {
4915 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))),
4916 (v1f64 (REV64v2i32 FPR64:$src))>;
4917 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))),
4918 (v1f64 (REV64v4i16 FPR64:$src))>;
4919 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))),
4920 (v1f64 (REV64v8i8 FPR64:$src))>;
4921 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))),
4922 (v1f64 (REV64v2i32 FPR64:$src))>;
4924 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
4925 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
4927 let Predicates = [IsLE] in {
4928 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
4929 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
4930 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
4931 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4932 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4934 let Predicates = [IsBE] in {
4935 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))),
4936 (v2f32 (REV64v2i32 FPR64:$src))>;
4937 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))),
4938 (v2f32 (REV32v4i16 FPR64:$src))>;
4939 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))),
4940 (v2f32 (REV32v8i8 FPR64:$src))>;
4941 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))),
4942 (v2f32 (REV64v2i32 FPR64:$src))>;
4943 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))),
4944 (v2f32 (REV64v2i32 FPR64:$src))>;
4946 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
4948 let Predicates = [IsLE] in {
4949 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
4950 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
4951 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
4952 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
4953 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
4954 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))), (f128 FPR128:$src)>;
4956 let Predicates = [IsBE] in {
4957 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))),
4958 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
4959 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))),
4960 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
4961 (REV64v4i32 FPR128:$src), (i32 8)))>;
4962 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))),
4963 (f128 (EXTv16i8 (REV64v8i16 FPR128:$src),
4964 (REV64v8i16 FPR128:$src), (i32 8)))>;
4965 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))),
4966 (f128 (EXTv16i8 FPR128:$src, FPR128:$src, (i32 8)))>;
4967 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))),
4968 (f128 (EXTv16i8 (REV64v4i32 FPR128:$src),
4969 (REV64v4i32 FPR128:$src), (i32 8)))>;
4970 def : Pat<(f128 (bitconvert (v16i8 FPR128:$src))),
4971 (f128 (EXTv16i8 (REV64v16i8 FPR128:$src),
4972 (REV64v16i8 FPR128:$src), (i32 8)))>;
4975 let Predicates = [IsLE] in {
4976 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
4977 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
4978 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
4979 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
4980 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
4982 let Predicates = [IsBE] in {
4983 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))),
4984 (v2f64 (EXTv16i8 FPR128:$src,
4985 FPR128:$src, (i32 8)))>;
4986 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))),
4987 (v2f64 (REV64v4i32 FPR128:$src))>;
4988 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))),
4989 (v2f64 (REV64v8i16 FPR128:$src))>;
4990 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))),
4991 (v2f64 (REV64v16i8 FPR128:$src))>;
4992 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))),
4993 (v2f64 (REV64v4i32 FPR128:$src))>;
4995 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
4997 let Predicates = [IsLE] in {
4998 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
4999 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
5000 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
5001 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
5002 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
5004 let Predicates = [IsBE] in {
5005 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))),
5006 (v4f32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5007 (REV64v4i32 FPR128:$src), (i32 8)))>;
5008 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))),
5009 (v4f32 (REV32v8i16 FPR128:$src))>;
5010 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))),
5011 (v4f32 (REV32v16i8 FPR128:$src))>;
5012 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))),
5013 (v4f32 (REV64v4i32 FPR128:$src))>;
5014 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))),
5015 (v4f32 (REV64v4i32 FPR128:$src))>;
5017 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
5019 let Predicates = [IsLE] in {
5020 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
5021 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
5022 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
5023 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
5024 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
5026 let Predicates = [IsBE] in {
5027 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))),
5028 (v2i64 (EXTv16i8 FPR128:$src,
5029 FPR128:$src, (i32 8)))>;
5030 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))),
5031 (v2i64 (REV64v4i32 FPR128:$src))>;
5032 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))),
5033 (v2i64 (REV64v8i16 FPR128:$src))>;
5034 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))),
5035 (v2i64 (REV64v16i8 FPR128:$src))>;
5036 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))),
5037 (v2i64 (REV64v4i32 FPR128:$src))>;
5039 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
5041 let Predicates = [IsLE] in {
5042 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
5043 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
5044 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
5045 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
5046 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
5048 let Predicates = [IsBE] in {
5049 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))),
5050 (v4i32 (EXTv16i8 (REV64v4i32 FPR128:$src),
5051 (REV64v4i32 FPR128:$src),
5053 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))),
5054 (v4i32 (REV64v4i32 FPR128:$src))>;
5055 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))),
5056 (v4i32 (REV32v8i16 FPR128:$src))>;
5057 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))),
5058 (v4i32 (REV32v16i8 FPR128:$src))>;
5059 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))),
5060 (v4i32 (REV64v4i32 FPR128:$src))>;
5062 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
5064 let Predicates = [IsLE] in {
5065 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
5066 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
5067 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
5068 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
5069 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
5070 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
5072 let Predicates = [IsBE] in {
5073 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))),
5074 (v8i16 (EXTv16i8 (REV64v8i16 FPR128:$src),
5075 (REV64v8i16 FPR128:$src),
5077 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))),
5078 (v8i16 (REV64v8i16 FPR128:$src))>;
5079 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))),
5080 (v8i16 (REV32v8i16 FPR128:$src))>;
5081 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))),
5082 (v8i16 (REV16v16i8 FPR128:$src))>;
5083 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))),
5084 (v8i16 (REV64v8i16 FPR128:$src))>;
5085 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))),
5086 (v8i16 (REV32v8i16 FPR128:$src))>;
5089 let Predicates = [IsLE] in {
5090 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
5091 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
5092 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
5093 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
5094 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
5095 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
5097 let Predicates = [IsBE] in {
5098 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))),
5099 (v16i8 (EXTv16i8 (REV64v16i8 FPR128:$src),
5100 (REV64v16i8 FPR128:$src),
5102 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))),
5103 (v16i8 (REV64v16i8 FPR128:$src))>;
5104 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))),
5105 (v16i8 (REV32v16i8 FPR128:$src))>;
5106 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))),
5107 (v16i8 (REV16v16i8 FPR128:$src))>;
5108 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))),
5109 (v16i8 (REV64v16i8 FPR128:$src))>;
5110 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))),
5111 (v16i8 (REV32v16i8 FPR128:$src))>;
5114 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
5115 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5116 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
5117 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5118 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
5119 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5120 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
5121 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
5123 // A 64-bit subvector insert to the first 128-bit vector position
5124 // is a subregister copy that needs no instruction.
5125 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
5126 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5127 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
5128 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5129 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
5130 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5131 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
5132 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5133 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
5134 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5135 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
5136 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
5138 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
5140 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
5141 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
5142 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
5143 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
5144 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
5145 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
5146 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
5147 // so we match on v4f32 here, not v2f32. This will also catch adding
5148 // the low two lanes of a true v4f32 vector.
5149 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
5150 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
5151 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
5153 // Scalar 64-bit shifts in FPR64 registers.
5154 def : Pat<(i64 (int_arm64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5155 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5156 def : Pat<(i64 (int_arm64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5157 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5158 def : Pat<(i64 (int_arm64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5159 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5160 def : Pat<(i64 (int_arm64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
5161 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
5163 // Tail call return handling. These are all compiler pseudo-instructions,
5164 // so no encoding information or anything like that.
5165 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
5166 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst, i32imm:$FPDiff),[]>;
5167 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst, i32imm:$FPDiff), []>;
5170 def : Pat<(ARM64tcret tcGPR64:$dst, (i32 timm:$FPDiff)),
5171 (TCRETURNri tcGPR64:$dst, imm:$FPDiff)>;
5172 def : Pat<(ARM64tcret tglobaladdr:$dst, (i32 timm:$FPDiff)),
5173 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5174 def : Pat<(ARM64tcret texternalsym:$dst, (i32 timm:$FPDiff)),
5175 (TCRETURNdi texternalsym:$dst, imm:$FPDiff)>;
5177 include "ARM64InstrAtomics.td"