1 //===- ARM64InstrInfo.td - Describe the ARM64 Instructions -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // ARM64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM64-specific DAG Nodes.
18 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
19 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
22 SDTCisInt<0>, SDTCisVT<1, i32>]>;
24 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
25 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
31 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
32 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
39 def SDT_ARM64Brcond : SDTypeProfile<0, 3,
40 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
42 def SDT_ARM64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
43 def SDT_ARM64tbz : SDTypeProfile<0, 3, [SDTCisVT<0, i64>, SDTCisVT<1, i64>,
44 SDTCisVT<2, OtherVT>]>;
47 def SDT_ARM64CSel : SDTypeProfile<1, 4,
52 def SDT_ARM64FCmp : SDTypeProfile<0, 2,
55 def SDT_ARM64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
56 def SDT_ARM64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
57 def SDT_ARM64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
60 def SDT_ARM64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
61 def SDT_ARM64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
62 def SDT_ARM64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
63 SDTCisInt<2>, SDTCisInt<3>]>;
64 def SDT_ARM64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
65 def SDT_ARM64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
66 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
67 def SDT_ARM64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
69 def SDT_ARM64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
70 def SDT_ARM64fcmpz : SDTypeProfile<1, 1, []>;
71 def SDT_ARM64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
72 def SDT_ARM64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
74 def SDT_ARM64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
77 def SDT_ARM64TCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
78 def SDT_ARM64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
80 def SDT_ARM64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
82 def SDT_ARM64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
84 def SDT_ARM64WrapperLarge : SDTypeProfile<1, 4,
85 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
86 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
91 def ARM64adrp : SDNode<"ARM64ISD::ADRP", SDTIntUnaryOp, []>;
92 def ARM64addlow : SDNode<"ARM64ISD::ADDlow", SDTIntBinOp, []>;
93 def ARM64LOADgot : SDNode<"ARM64ISD::LOADgot", SDTIntUnaryOp>;
94 def ARM64callseq_start : SDNode<"ISD::CALLSEQ_START",
95 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
96 [SDNPHasChain, SDNPOutGlue]>;
97 def ARM64callseq_end : SDNode<"ISD::CALLSEQ_END",
98 SDCallSeqEnd<[ SDTCisVT<0, i32>,
100 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
101 def ARM64call : SDNode<"ARM64ISD::CALL",
102 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
103 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
105 def ARM64brcond : SDNode<"ARM64ISD::BRCOND", SDT_ARM64Brcond,
107 def ARM64cbz : SDNode<"ARM64ISD::CBZ", SDT_ARM64cbz,
109 def ARM64cbnz : SDNode<"ARM64ISD::CBNZ", SDT_ARM64cbz,
111 def ARM64tbz : SDNode<"ARM64ISD::TBZ", SDT_ARM64tbz,
113 def ARM64tbnz : SDNode<"ARM64ISD::TBNZ", SDT_ARM64tbz,
117 def ARM64csel : SDNode<"ARM64ISD::CSEL", SDT_ARM64CSel>;
118 def ARM64csinv : SDNode<"ARM64ISD::CSINV", SDT_ARM64CSel>;
119 def ARM64csneg : SDNode<"ARM64ISD::CSNEG", SDT_ARM64CSel>;
120 def ARM64csinc : SDNode<"ARM64ISD::CSINC", SDT_ARM64CSel>;
121 def ARM64retflag : SDNode<"ARM64ISD::RET_FLAG", SDTNone,
122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
123 def ARM64adc : SDNode<"ARM64ISD::ADC", SDTBinaryArithWithFlagsIn >;
124 def ARM64sbc : SDNode<"ARM64ISD::SBC", SDTBinaryArithWithFlagsIn>;
125 def ARM64add_flag : SDNode<"ARM64ISD::ADDS", SDTBinaryArithWithFlagsOut,
127 def ARM64sub_flag : SDNode<"ARM64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
128 def ARM64and_flag : SDNode<"ARM64ISD::ANDS", SDTBinaryArithWithFlagsOut>;
129 def ARM64adc_flag : SDNode<"ARM64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
130 def ARM64sbc_flag : SDNode<"ARM64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
132 def ARM64threadpointer : SDNode<"ARM64ISD::THREAD_POINTER", SDTPtrLeaf>;
134 def ARM64fcmp : SDNode<"ARM64ISD::FCMP", SDT_ARM64FCmp>;
136 def ARM64fmax : SDNode<"ARM64ISD::FMAX", SDTFPBinOp>;
137 def ARM64fmin : SDNode<"ARM64ISD::FMIN", SDTFPBinOp>;
139 def ARM64dup : SDNode<"ARM64ISD::DUP", SDT_ARM64Dup>;
140 def ARM64duplane8 : SDNode<"ARM64ISD::DUPLANE8", SDT_ARM64DupLane>;
141 def ARM64duplane16 : SDNode<"ARM64ISD::DUPLANE16", SDT_ARM64DupLane>;
142 def ARM64duplane32 : SDNode<"ARM64ISD::DUPLANE32", SDT_ARM64DupLane>;
143 def ARM64duplane64 : SDNode<"ARM64ISD::DUPLANE64", SDT_ARM64DupLane>;
145 def ARM64zip1 : SDNode<"ARM64ISD::ZIP1", SDT_ARM64Zip>;
146 def ARM64zip2 : SDNode<"ARM64ISD::ZIP2", SDT_ARM64Zip>;
147 def ARM64uzp1 : SDNode<"ARM64ISD::UZP1", SDT_ARM64Zip>;
148 def ARM64uzp2 : SDNode<"ARM64ISD::UZP2", SDT_ARM64Zip>;
149 def ARM64trn1 : SDNode<"ARM64ISD::TRN1", SDT_ARM64Zip>;
150 def ARM64trn2 : SDNode<"ARM64ISD::TRN2", SDT_ARM64Zip>;
152 def ARM64movi_edit : SDNode<"ARM64ISD::MOVIedit", SDT_ARM64MOVIedit>;
153 def ARM64movi_shift : SDNode<"ARM64ISD::MOVIshift", SDT_ARM64MOVIshift>;
154 def ARM64movi_msl : SDNode<"ARM64ISD::MOVImsl", SDT_ARM64MOVIshift>;
155 def ARM64mvni_shift : SDNode<"ARM64ISD::MVNIshift", SDT_ARM64MOVIshift>;
156 def ARM64mvni_msl : SDNode<"ARM64ISD::MVNImsl", SDT_ARM64MOVIshift>;
157 def ARM64movi : SDNode<"ARM64ISD::MOVI", SDT_ARM64MOVIedit>;
158 def ARM64fmov : SDNode<"ARM64ISD::FMOV", SDT_ARM64MOVIedit>;
160 def ARM64rev16 : SDNode<"ARM64ISD::REV16", SDT_ARM64UnaryVec>;
161 def ARM64rev32 : SDNode<"ARM64ISD::REV32", SDT_ARM64UnaryVec>;
162 def ARM64rev64 : SDNode<"ARM64ISD::REV64", SDT_ARM64UnaryVec>;
163 def ARM64ext : SDNode<"ARM64ISD::EXT", SDT_ARM64ExtVec>;
165 def ARM64vashr : SDNode<"ARM64ISD::VASHR", SDT_ARM64vshift>;
166 def ARM64vlshr : SDNode<"ARM64ISD::VLSHR", SDT_ARM64vshift>;
167 def ARM64vshl : SDNode<"ARM64ISD::VSHL", SDT_ARM64vshift>;
168 def ARM64sqshli : SDNode<"ARM64ISD::SQSHL_I", SDT_ARM64vshift>;
169 def ARM64uqshli : SDNode<"ARM64ISD::UQSHL_I", SDT_ARM64vshift>;
170 def ARM64sqshlui : SDNode<"ARM64ISD::SQSHLU_I", SDT_ARM64vshift>;
171 def ARM64srshri : SDNode<"ARM64ISD::SRSHR_I", SDT_ARM64vshift>;
172 def ARM64urshri : SDNode<"ARM64ISD::URSHR_I", SDT_ARM64vshift>;
174 def ARM64not: SDNode<"ARM64ISD::NOT", SDT_ARM64unvec>;
175 def ARM64bit: SDNode<"ARM64ISD::BIT", SDT_ARM64trivec>;
176 def ARM64bsl: SDNode<"ARM64ISD::BSL", SDT_ARM64trivec>;
178 def ARM64cmeq: SDNode<"ARM64ISD::CMEQ", SDT_ARM64binvec>;
179 def ARM64cmge: SDNode<"ARM64ISD::CMGE", SDT_ARM64binvec>;
180 def ARM64cmgt: SDNode<"ARM64ISD::CMGT", SDT_ARM64binvec>;
181 def ARM64cmhi: SDNode<"ARM64ISD::CMHI", SDT_ARM64binvec>;
182 def ARM64cmhs: SDNode<"ARM64ISD::CMHS", SDT_ARM64binvec>;
184 def ARM64fcmeq: SDNode<"ARM64ISD::FCMEQ", SDT_ARM64fcmp>;
185 def ARM64fcmge: SDNode<"ARM64ISD::FCMGE", SDT_ARM64fcmp>;
186 def ARM64fcmgt: SDNode<"ARM64ISD::FCMGT", SDT_ARM64fcmp>;
188 def ARM64cmeqz: SDNode<"ARM64ISD::CMEQz", SDT_ARM64unvec>;
189 def ARM64cmgez: SDNode<"ARM64ISD::CMGEz", SDT_ARM64unvec>;
190 def ARM64cmgtz: SDNode<"ARM64ISD::CMGTz", SDT_ARM64unvec>;
191 def ARM64cmlez: SDNode<"ARM64ISD::CMLEz", SDT_ARM64unvec>;
192 def ARM64cmltz: SDNode<"ARM64ISD::CMLTz", SDT_ARM64unvec>;
193 def ARM64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
194 (ARM64not (ARM64cmeqz (and node:$LHS, node:$RHS)))>;
196 def ARM64fcmeqz: SDNode<"ARM64ISD::FCMEQz", SDT_ARM64fcmpz>;
197 def ARM64fcmgez: SDNode<"ARM64ISD::FCMGEz", SDT_ARM64fcmpz>;
198 def ARM64fcmgtz: SDNode<"ARM64ISD::FCMGTz", SDT_ARM64fcmpz>;
199 def ARM64fcmlez: SDNode<"ARM64ISD::FCMLEz", SDT_ARM64fcmpz>;
200 def ARM64fcmltz: SDNode<"ARM64ISD::FCMLTz", SDT_ARM64fcmpz>;
202 def ARM64bici: SDNode<"ARM64ISD::BICi", SDT_ARM64vecimm>;
203 def ARM64orri: SDNode<"ARM64ISD::ORRi", SDT_ARM64vecimm>;
205 def ARM64neg : SDNode<"ARM64ISD::NEG", SDT_ARM64unvec>;
207 def ARM64tcret: SDNode<"ARM64ISD::TC_RETURN", SDT_ARM64TCRET,
208 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
210 def ARM64Prefetch : SDNode<"ARM64ISD::PREFETCH", SDT_ARM64PREFETCH,
211 [SDNPHasChain, SDNPSideEffect]>;
213 def ARM64sitof: SDNode<"ARM64ISD::SITOF", SDT_ARM64ITOF>;
214 def ARM64uitof: SDNode<"ARM64ISD::UITOF", SDT_ARM64ITOF>;
216 def ARM64tlsdesc_call : SDNode<"ARM64ISD::TLSDESC_CALL", SDT_ARM64TLSDescCall,
217 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
220 def ARM64WrapperLarge : SDNode<"ARM64ISD::WrapperLarge", SDT_ARM64WrapperLarge>;
223 //===----------------------------------------------------------------------===//
225 //===----------------------------------------------------------------------===//
227 // ARM64 Instruction Predicate Definitions.
229 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
230 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
231 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
232 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
233 def ForCodeSize : Predicate<"ForCodeSize">;
234 def NotForCodeSize : Predicate<"!ForCodeSize">;
236 include "ARM64InstrFormats.td"
238 //===----------------------------------------------------------------------===//
240 //===----------------------------------------------------------------------===//
241 // Miscellaneous instructions.
242 //===----------------------------------------------------------------------===//
244 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
245 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
246 [(ARM64callseq_start timm:$amt)]>;
247 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
248 [(ARM64callseq_end timm:$amt1, timm:$amt2)]>;
249 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
251 let isReMaterializable = 1, isCodeGenOnly = 1 in {
252 // FIXME: The following pseudo instructions are only needed because remat
253 // cannot handle multiple instructions. When that changes, they can be
254 // removed, along with the ARM64Wrapper node.
256 let AddedComplexity = 10 in
257 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
258 [(set GPR64:$dst, (ARM64LOADgot tglobaladdr:$addr))]>,
261 // The MOVaddr instruction should match only when the add is not folded
262 // into a load or store address.
264 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
265 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaladdr:$hi),
266 tglobaladdr:$low))]>,
267 Sched<[WriteAdrAdr]>;
269 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
270 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tjumptable:$hi),
272 Sched<[WriteAdrAdr]>;
274 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
275 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tconstpool:$hi),
277 Sched<[WriteAdrAdr]>;
279 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
280 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tblockaddress:$hi),
281 tblockaddress:$low))]>,
282 Sched<[WriteAdrAdr]>;
284 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
285 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaltlsaddr:$hi),
286 tglobaltlsaddr:$low))]>,
287 Sched<[WriteAdrAdr]>;
289 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
290 [(set GPR64:$dst, (ARM64addlow (ARM64adrp texternalsym:$hi),
291 texternalsym:$low))]>,
292 Sched<[WriteAdrAdr]>;
294 } // isReMaterializable, isCodeGenOnly
296 def : Pat<(ARM64LOADgot tglobaltlsaddr:$addr),
297 (LOADgot tglobaltlsaddr:$addr)>;
299 def : Pat<(ARM64LOADgot texternalsym:$addr),
300 (LOADgot texternalsym:$addr)>;
302 def : Pat<(ARM64LOADgot tconstpool:$addr),
303 (LOADgot tconstpool:$addr)>;
305 //===----------------------------------------------------------------------===//
306 // System instructions.
307 //===----------------------------------------------------------------------===//
309 def HINT : HintI<"hint">;
310 def : InstAlias<"nop", (HINT 0b000)>;
311 def : InstAlias<"yield",(HINT 0b001)>;
312 def : InstAlias<"wfe", (HINT 0b010)>;
313 def : InstAlias<"wfi", (HINT 0b011)>;
314 def : InstAlias<"sev", (HINT 0b100)>;
315 def : InstAlias<"sevl", (HINT 0b101)>;
317 // As far as LLVM is concerned this writes to the system's exclusive monitors.
318 let mayLoad = 1, mayStore = 1 in
319 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
321 def DMB : CRmSystemI<barrier_op, 0b101, "dmb">;
322 def DSB : CRmSystemI<barrier_op, 0b100, "dsb">;
323 def ISB : CRmSystemI<barrier_op, 0b110, "isb">;
324 def : InstAlias<"clrex", (CLREX 0xf)>;
325 def : InstAlias<"isb", (ISB 0xf)>;
329 def MSRcpsr: MSRcpsrI;
331 // The thread pointer (on Linux, at least, where this has been implemented) is
333 def : Pat<(ARM64threadpointer), (MRS 0xde82)>;
335 // Generic system instructions
336 def SYSxt : SystemXtI<0, "sys">;
337 def SYSLxt : SystemLXtI<1, "sysl">;
339 def : InstAlias<"sys $op1, $Cn, $Cm, $op2",
340 (SYSxt imm0_7:$op1, sys_cr_op:$Cn,
341 sys_cr_op:$Cm, imm0_7:$op2, XZR)>;
343 //===----------------------------------------------------------------------===//
344 // Move immediate instructions.
345 //===----------------------------------------------------------------------===//
347 defm MOVK : InsertImmediate<0b11, "movk">;
348 defm MOVN : MoveImmediate<0b00, "movn">;
350 let PostEncoderMethod = "fixMOVZ" in
351 defm MOVZ : MoveImmediate<0b10, "movz">;
353 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
354 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
355 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
356 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
357 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
358 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
360 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
361 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
362 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
363 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
365 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
366 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
367 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
368 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
370 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g3:$sym, 48)>;
371 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g2:$sym, 32)>;
372 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
373 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
375 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
376 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
377 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
379 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g2:$sym, 32)>;
380 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
381 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
383 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
384 isAsCheapAsAMove = 1 in {
385 // FIXME: The following pseudo instructions are only needed because remat
386 // cannot handle multiple instructions. When that changes, we can select
387 // directly to the real instructions and get rid of these pseudos.
390 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
391 [(set GPR32:$dst, imm:$src)]>,
394 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
395 [(set GPR64:$dst, imm:$src)]>,
397 } // isReMaterializable, isCodeGenOnly
399 // If possible, we want to use MOVi32imm even for 64-bit moves. This gives the
400 // eventual expansion code fewer bits to worry about getting right. Marshalling
401 // the types is a little tricky though:
402 def i64imm_32bit : ImmLeaf<i64, [{
403 return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm);
406 def trunc_imm : SDNodeXForm<imm, [{
407 return CurDAG->getTargetConstant(N->getZExtValue(), MVT::i32);
410 def : Pat<(i64 i64imm_32bit:$src),
411 (SUBREG_TO_REG (i64 0), (MOVi32imm (trunc_imm imm:$src)), sub_32)>;
413 // Deal with the various forms of (ELF) large addressing with MOVZ/MOVK
415 def : Pat<(ARM64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
416 tglobaladdr:$g1, tglobaladdr:$g0),
417 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
418 tglobaladdr:$g2, 32),
419 tglobaladdr:$g1, 16),
420 tglobaladdr:$g0, 0)>;
422 def : Pat<(ARM64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
423 tblockaddress:$g1, tblockaddress:$g0),
424 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
425 tblockaddress:$g2, 32),
426 tblockaddress:$g1, 16),
427 tblockaddress:$g0, 0)>;
429 def : Pat<(ARM64WrapperLarge tconstpool:$g3, tconstpool:$g2,
430 tconstpool:$g1, tconstpool:$g0),
431 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
436 def : Pat<(ARM64WrapperLarge tjumptable:$g3, tjumptable:$g2,
437 tjumptable:$g1, tjumptable:$g0),
438 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tjumptable:$g3, 48),
444 //===----------------------------------------------------------------------===//
445 // Arithmetic instructions.
446 //===----------------------------------------------------------------------===//
448 // Add/subtract with carry.
449 defm ADC : AddSubCarry<0, "adc", "adcs", ARM64adc, ARM64adc_flag>;
450 defm SBC : AddSubCarry<1, "sbc", "sbcs", ARM64sbc, ARM64sbc_flag>;
452 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
453 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
454 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
455 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
458 defm ADD : AddSub<0, "add", add>;
459 defm SUB : AddSub<1, "sub">;
461 defm ADDS : AddSubS<0, "adds", ARM64add_flag>;
462 defm SUBS : AddSubS<1, "subs", ARM64sub_flag>;
464 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
465 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
466 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
467 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
468 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
469 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
470 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
471 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
472 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
473 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
474 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
475 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
476 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
477 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
478 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
479 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
480 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
482 // Because of the immediate format for add/sub-imm instructions, the
483 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
484 // These patterns capture that transformation.
485 let AddedComplexity = 1 in {
486 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
487 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
488 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
489 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
490 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
491 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
492 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
493 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
496 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
497 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
498 def : InstAlias<"neg $dst, $src, $shift",
499 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift:$shift)>;
500 def : InstAlias<"neg $dst, $src, $shift",
501 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift:$shift)>;
503 // Because of the immediate format for add/sub-imm instructions, the
504 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
505 // These patterns capture that transformation.
506 let AddedComplexity = 1 in {
507 def : Pat<(ARM64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
508 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
509 def : Pat<(ARM64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
510 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
511 def : Pat<(ARM64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
512 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
513 def : Pat<(ARM64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
514 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
517 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
518 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
519 def : InstAlias<"negs $dst, $src, $shift",
520 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift:$shift)>;
521 def : InstAlias<"negs $dst, $src, $shift",
522 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift:$shift)>;
524 // Unsigned/Signed divide
525 defm UDIV : Div<0, "udiv", udiv>;
526 defm SDIV : Div<1, "sdiv", sdiv>;
527 let isCodeGenOnly = 1 in {
528 defm UDIV_Int : Div<0, "udiv", int_arm64_udiv>;
529 defm SDIV_Int : Div<1, "sdiv", int_arm64_sdiv>;
533 defm ASRV : Shift<0b10, "asrv", sra>;
534 defm LSLV : Shift<0b00, "lslv", shl>;
535 defm LSRV : Shift<0b01, "lsrv", srl>;
536 defm RORV : Shift<0b11, "rorv", rotr>;
538 def : ShiftAlias<"asr", ASRVWr, GPR32>;
539 def : ShiftAlias<"asr", ASRVXr, GPR64>;
540 def : ShiftAlias<"lsl", LSLVWr, GPR32>;
541 def : ShiftAlias<"lsl", LSLVXr, GPR64>;
542 def : ShiftAlias<"lsr", LSRVWr, GPR32>;
543 def : ShiftAlias<"lsr", LSRVXr, GPR64>;
544 def : ShiftAlias<"ror", RORVWr, GPR32>;
545 def : ShiftAlias<"ror", RORVXr, GPR64>;
548 let AddedComplexity = 7 in {
549 defm MADD : MulAccum<0, "madd", add>;
550 defm MSUB : MulAccum<1, "msub", sub>;
552 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
553 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
554 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
555 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
557 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
558 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
559 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
560 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
561 } // AddedComplexity = 7
563 let AddedComplexity = 5 in {
564 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
565 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
566 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
567 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
569 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
570 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
571 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
572 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
574 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
575 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
576 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
577 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
578 } // AddedComplexity = 5
580 def : MulAccumWAlias<"mul", MADDWrrr>;
581 def : MulAccumXAlias<"mul", MADDXrrr>;
582 def : MulAccumWAlias<"mneg", MSUBWrrr>;
583 def : MulAccumXAlias<"mneg", MSUBXrrr>;
584 def : WideMulAccumAlias<"smull", SMADDLrrr>;
585 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
586 def : WideMulAccumAlias<"umull", UMADDLrrr>;
587 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
590 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
591 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
594 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_arm64_crc32b, "crc32b">;
595 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_arm64_crc32h, "crc32h">;
596 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_arm64_crc32w, "crc32w">;
597 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_arm64_crc32x, "crc32x">;
599 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_arm64_crc32cb, "crc32cb">;
600 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_arm64_crc32ch, "crc32ch">;
601 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_arm64_crc32cw, "crc32cw">;
602 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_arm64_crc32cx, "crc32cx">;
605 //===----------------------------------------------------------------------===//
606 // Logical instructions.
607 //===----------------------------------------------------------------------===//
610 defm ANDS : LogicalImmS<0b11, "ands", ARM64and_flag>;
611 defm AND : LogicalImm<0b00, "and", and>;
612 defm EOR : LogicalImm<0b10, "eor", xor>;
613 defm ORR : LogicalImm<0b01, "orr", or>;
615 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
616 logical_imm32:$imm)>;
617 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
618 logical_imm64:$imm)>;
622 defm ANDS : LogicalRegS<0b11, 0, "ands">;
623 defm BICS : LogicalRegS<0b11, 1, "bics">;
624 defm AND : LogicalReg<0b00, 0, "and", and>;
625 defm BIC : LogicalReg<0b00, 1, "bic",
626 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
627 defm EON : LogicalReg<0b10, 1, "eon",
628 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
629 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
630 defm ORN : LogicalReg<0b01, 1, "orn",
631 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
632 defm ORR : LogicalReg<0b01, 0, "orr", or>;
634 def : InstAlias<"tst $src1, $src2",
635 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
636 def : InstAlias<"tst $src1, $src2",
637 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>;
639 def : InstAlias<"tst $src1, $src2",
640 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>;
641 def : InstAlias<"tst $src1, $src2",
642 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>;
644 def : InstAlias<"tst $src1, $src2, $sh",
645 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift:$sh)>;
646 def : InstAlias<"tst $src1, $src2, $sh",
647 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift:$sh)>;
649 def : InstAlias<"mvn $Wd, $Wm",
650 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0)>;
651 def : InstAlias<"mvn $Xd, $Xm",
652 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>;
654 def : InstAlias<"mvn $Wd, $Wm, $sh",
655 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, logical_shift:$sh)>;
656 def : InstAlias<"mvn $Xd, $Xm, $sh",
657 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, logical_shift:$sh)>;
659 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
660 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
663 //===----------------------------------------------------------------------===//
664 // One operand data processing instructions.
665 //===----------------------------------------------------------------------===//
667 defm CLS : OneOperandData<0b101, "cls">;
668 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
669 defm RBIT : OneOperandData<0b000, "rbit">;
670 def REV16Wr : OneWRegData<0b001, "rev16",
671 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
672 def REV16Xr : OneXRegData<0b001, "rev16", null_frag>;
674 def : Pat<(cttz GPR32:$Rn),
675 (CLZWr (RBITWr GPR32:$Rn))>;
676 def : Pat<(cttz GPR64:$Rn),
677 (CLZXr (RBITXr GPR64:$Rn))>;
678 def : Pat<(ctlz (or (shl (xor (sra GPR32:$Rn, (i64 31)), GPR32:$Rn), (i64 1)),
681 def : Pat<(ctlz (or (shl (xor (sra GPR64:$Rn, (i64 63)), GPR64:$Rn), (i64 1)),
685 // Unlike the other one operand instructions, the instructions with the "rev"
686 // mnemonic do *not* just different in the size bit, but actually use different
687 // opcode bits for the different sizes.
688 def REVWr : OneWRegData<0b010, "rev", bswap>;
689 def REVXr : OneXRegData<0b011, "rev", bswap>;
690 def REV32Xr : OneXRegData<0b010, "rev32",
691 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
693 // The bswap commutes with the rotr so we want a pattern for both possible
695 def : Pat<(bswap (rotr GPR32:$Rn, (i64 16))), (REV16Wr GPR32:$Rn)>;
696 def : Pat<(bswap (rotr GPR64:$Rn, (i64 32))), (REV32Xr GPR64:$Rn)>;
698 //===----------------------------------------------------------------------===//
699 // Bitfield immediate extraction instruction.
700 //===----------------------------------------------------------------------===//
701 let neverHasSideEffects = 1 in
702 defm EXTR : ExtractImm<"extr">;
703 def : InstAlias<"ror $dst, $src, $shift",
704 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
705 def : InstAlias<"ror $dst, $src, $shift",
706 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
708 def : Pat<(rotr GPR32:$Rn, (i64 imm0_31:$imm)),
709 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
710 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
711 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
713 //===----------------------------------------------------------------------===//
714 // Other bitfield immediate instructions.
715 //===----------------------------------------------------------------------===//
716 let neverHasSideEffects = 1 in {
717 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
718 defm SBFM : BitfieldImm<0b00, "sbfm">;
719 defm UBFM : BitfieldImm<0b10, "ubfm">;
722 def i32shift_a : Operand<i64>, SDNodeXForm<imm, [{
723 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
724 return CurDAG->getTargetConstant(enc, MVT::i64);
727 def i32shift_b : Operand<i64>, SDNodeXForm<imm, [{
728 uint64_t enc = 31 - N->getZExtValue();
729 return CurDAG->getTargetConstant(enc, MVT::i64);
732 // min(7, 31 - shift_amt)
733 def i32shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
734 uint64_t enc = 31 - N->getZExtValue();
735 enc = enc > 7 ? 7 : enc;
736 return CurDAG->getTargetConstant(enc, MVT::i64);
739 // min(15, 31 - shift_amt)
740 def i32shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
741 uint64_t enc = 31 - N->getZExtValue();
742 enc = enc > 15 ? 15 : enc;
743 return CurDAG->getTargetConstant(enc, MVT::i64);
746 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
747 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
748 return CurDAG->getTargetConstant(enc, MVT::i64);
751 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
752 uint64_t enc = 63 - N->getZExtValue();
753 return CurDAG->getTargetConstant(enc, MVT::i64);
756 // min(7, 63 - shift_amt)
757 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
758 uint64_t enc = 63 - N->getZExtValue();
759 enc = enc > 7 ? 7 : enc;
760 return CurDAG->getTargetConstant(enc, MVT::i64);
763 // min(15, 63 - shift_amt)
764 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
765 uint64_t enc = 63 - N->getZExtValue();
766 enc = enc > 15 ? 15 : enc;
767 return CurDAG->getTargetConstant(enc, MVT::i64);
770 // min(31, 63 - shift_amt)
771 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
772 uint64_t enc = 63 - N->getZExtValue();
773 enc = enc > 31 ? 31 : enc;
774 return CurDAG->getTargetConstant(enc, MVT::i64);
777 def : Pat<(shl GPR32:$Rn, (i64 imm0_31:$imm)),
778 (UBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
779 (i64 (i32shift_b imm0_31:$imm)))>;
780 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
781 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
782 (i64 (i64shift_b imm0_63:$imm)))>;
784 let AddedComplexity = 10 in {
785 def : Pat<(sra GPR32:$Rn, (i64 imm0_31:$imm)),
786 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
787 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
788 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
791 def : InstAlias<"asr $dst, $src, $shift",
792 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
793 def : InstAlias<"asr $dst, $src, $shift",
794 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
795 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
796 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
797 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
798 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
799 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
801 def : Pat<(srl GPR32:$Rn, (i64 imm0_31:$imm)),
802 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
803 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
804 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
806 def : InstAlias<"lsr $dst, $src, $shift",
807 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
808 def : InstAlias<"lsr $dst, $src, $shift",
809 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
810 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
811 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
812 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
813 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
814 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
816 //===----------------------------------------------------------------------===//
817 // Conditionally set flags instructions.
818 //===----------------------------------------------------------------------===//
819 defm CCMN : CondSetFlagsImm<0, "ccmn">;
820 defm CCMP : CondSetFlagsImm<1, "ccmp">;
822 defm CCMN : CondSetFlagsReg<0, "ccmn">;
823 defm CCMP : CondSetFlagsReg<1, "ccmp">;
825 //===----------------------------------------------------------------------===//
826 // Conditional select instructions.
827 //===----------------------------------------------------------------------===//
828 defm CSEL : CondSelect<0, 0b00, "csel">;
830 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
831 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
832 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
833 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
835 def : Pat<(ARM64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
836 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
837 def : Pat<(ARM64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
838 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
839 def : Pat<(ARM64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
840 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
841 def : Pat<(ARM64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
842 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
843 def : Pat<(ARM64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
844 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
845 def : Pat<(ARM64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
846 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
848 def : Pat<(ARM64csel (i32 0), (i32 1), (i32 imm:$cc), CPSR),
849 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
850 def : Pat<(ARM64csel (i64 0), (i64 1), (i32 imm:$cc), CPSR),
851 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
852 def : Pat<(ARM64csel (i32 0), (i32 -1), (i32 imm:$cc), CPSR),
853 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
854 def : Pat<(ARM64csel (i64 0), (i64 -1), (i32 imm:$cc), CPSR),
855 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
857 // The inverse of the condition code from the alias instruction is what is used
858 // in the aliased instruction. The parser all ready inverts the condition code
859 // for these aliases.
860 // FIXME: Is this the correct way to handle these aliases?
861 def : InstAlias<"cset $dst, $cc", (CSINCWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
862 def : InstAlias<"cset $dst, $cc", (CSINCXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
864 def : InstAlias<"csetm $dst, $cc", (CSINVWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
865 def : InstAlias<"csetm $dst, $cc", (CSINVXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
867 def : InstAlias<"cinc $dst, $src, $cc",
868 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
869 def : InstAlias<"cinc $dst, $src, $cc",
870 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
872 def : InstAlias<"cinv $dst, $src, $cc",
873 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
874 def : InstAlias<"cinv $dst, $src, $cc",
875 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
877 def : InstAlias<"cneg $dst, $src, $cc",
878 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
879 def : InstAlias<"cneg $dst, $src, $cc",
880 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
882 //===----------------------------------------------------------------------===//
883 // PC-relative instructions.
884 //===----------------------------------------------------------------------===//
885 let isReMaterializable = 1 in {
886 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
887 def ADR : ADRI<0, "adr", adrlabel, []>;
888 } // neverHasSideEffects = 1
890 def ADRP : ADRI<1, "adrp", adrplabel,
891 [(set GPR64:$Xd, (ARM64adrp tglobaladdr:$label))]>;
892 } // isReMaterializable = 1
894 // page address of a constant pool entry, block address
895 def : Pat<(ARM64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
896 def : Pat<(ARM64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
898 //===----------------------------------------------------------------------===//
899 // Unconditional branch (register) instructions.
900 //===----------------------------------------------------------------------===//
902 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
903 def RET : BranchReg<0b0010, "ret", []>;
904 def DRPS : SpecialReturn<0b0101, "drps">;
905 def ERET : SpecialReturn<0b0100, "eret">;
906 } // isReturn = 1, isTerminator = 1, isBarrier = 1
908 // Default to the LR register.
909 def : InstAlias<"ret", (RET LR)>;
911 let isCall = 1, Defs = [LR], Uses = [SP] in {
912 def BLR : BranchReg<0b0001, "blr", [(ARM64call GPR64:$Rn)]>;
915 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
916 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
917 } // isBranch, isTerminator, isBarrier, isIndirectBranch
919 // Create a separate pseudo-instruction for codegen to use so that we don't
920 // flag lr as used in every function. It'll be restored before the RET by the
921 // epilogue if it's legitimately used.
922 def RET_ReallyLR : Pseudo<(outs), (ins), [(ARM64retflag)]> {
923 let isTerminator = 1;
928 // This is a directive-like pseudo-instruction. The purpose is to insert an
929 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
930 // (which in the usual case is a BLR).
931 let hasSideEffects = 1 in
932 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
933 let AsmString = ".tlsdesccall $sym";
936 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
937 // gets expanded to two MCInsts during lowering.
938 let isCall = 1, Defs = [LR] in
940 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
941 [(ARM64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
943 def : Pat<(ARM64tlsdesc_call GPR64:$dest, texternalsym:$sym),
944 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
945 //===----------------------------------------------------------------------===//
946 // Conditional branch (immediate) instruction.
947 //===----------------------------------------------------------------------===//
948 def Bcc : BranchCond;
950 //===----------------------------------------------------------------------===//
951 // Compare-and-branch instructions.
952 //===----------------------------------------------------------------------===//
953 defm CBZ : CmpBranch<0, "cbz", ARM64cbz>;
954 defm CBNZ : CmpBranch<1, "cbnz", ARM64cbnz>;
956 //===----------------------------------------------------------------------===//
957 // Test-bit-and-branch instructions.
958 //===----------------------------------------------------------------------===//
959 def TBZ : TestBranch<0, "tbz", ARM64tbz>;
960 def TBNZ : TestBranch<1, "tbnz", ARM64tbnz>;
962 //===----------------------------------------------------------------------===//
963 // Unconditional branch (immediate) instructions.
964 //===----------------------------------------------------------------------===//
965 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
966 def B : BranchImm<0, "b", [(br bb:$addr)]>;
967 } // isBranch, isTerminator, isBarrier
969 let isCall = 1, Defs = [LR], Uses = [SP] in {
970 def BL : CallImm<1, "bl", [(ARM64call tglobaladdr:$addr)]>;
972 def : Pat<(ARM64call texternalsym:$func), (BL texternalsym:$func)>;
974 //===----------------------------------------------------------------------===//
975 // Exception generation instructions.
976 //===----------------------------------------------------------------------===//
977 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
978 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
979 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
980 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
981 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
982 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
983 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
984 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
986 // DCPSn defaults to an immediate operand of zero if unspecified.
987 def : InstAlias<"dcps1", (DCPS1 0)>;
988 def : InstAlias<"dcps2", (DCPS2 0)>;
989 def : InstAlias<"dcps3", (DCPS3 0)>;
991 //===----------------------------------------------------------------------===//
992 // Load instructions.
993 //===----------------------------------------------------------------------===//
995 // Pair (indexed, offset)
996 def LDPWi : LoadPairOffset<0b00, 0, GPR32, am_indexed32simm7, "ldp">;
997 def LDPXi : LoadPairOffset<0b10, 0, GPR64, am_indexed64simm7, "ldp">;
998 def LDPSi : LoadPairOffset<0b00, 1, FPR32, am_indexed32simm7, "ldp">;
999 def LDPDi : LoadPairOffset<0b01, 1, FPR64, am_indexed64simm7, "ldp">;
1000 def LDPQi : LoadPairOffset<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
1002 def LDPSWi : LoadPairOffset<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
1004 // Pair (pre-indexed)
1005 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "ldp">;
1006 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "ldp">;
1007 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "ldp">;
1008 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "ldp">;
1009 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "ldp">;
1011 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7_wb, "ldpsw">;
1013 // Pair (post-indexed)
1014 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
1015 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
1016 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
1017 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
1018 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
1020 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
1023 // Pair (no allocate)
1024 def LDNPWi : LoadPairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "ldnp">;
1025 def LDNPXi : LoadPairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "ldnp">;
1026 def LDNPSi : LoadPairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "ldnp">;
1027 def LDNPDi : LoadPairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "ldnp">;
1028 def LDNPQi : LoadPairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "ldnp">;
1031 // (register offset)
1034 let AddedComplexity = 10 in {
1036 def LDRBBro : Load8RO<0b00, 0, 0b01, GPR32, "ldrb",
1037 [(set GPR32:$Rt, (zextloadi8 ro_indexed8:$addr))]>;
1038 def LDRHHro : Load16RO<0b01, 0, 0b01, GPR32, "ldrh",
1039 [(set GPR32:$Rt, (zextloadi16 ro_indexed16:$addr))]>;
1040 def LDRWro : Load32RO<0b10, 0, 0b01, GPR32, "ldr",
1041 [(set GPR32:$Rt, (load ro_indexed32:$addr))]>;
1042 def LDRXro : Load64RO<0b11, 0, 0b01, GPR64, "ldr",
1043 [(set GPR64:$Rt, (load ro_indexed64:$addr))]>;
1046 def LDRBro : Load8RO<0b00, 1, 0b01, FPR8, "ldr",
1047 [(set FPR8:$Rt, (load ro_indexed8:$addr))]>;
1048 def LDRHro : Load16RO<0b01, 1, 0b01, FPR16, "ldr",
1049 [(set (f16 FPR16:$Rt), (load ro_indexed16:$addr))]>;
1050 def LDRSro : Load32RO<0b10, 1, 0b01, FPR32, "ldr",
1051 [(set (f32 FPR32:$Rt), (load ro_indexed32:$addr))]>;
1052 def LDRDro : Load64RO<0b11, 1, 0b01, FPR64, "ldr",
1053 [(set (f64 FPR64:$Rt), (load ro_indexed64:$addr))]>;
1054 def LDRQro : Load128RO<0b00, 1, 0b11, FPR128, "ldr", []> {
1058 // For regular load, we do not have any alignment requirement.
1059 // Thus, it is safe to directly map the vector loads with interesting
1060 // addressing modes.
1061 // FIXME: We could do the same for bitconvert to floating point vectors.
1062 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1063 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1064 (LDRBro ro_indexed8:$addr), bsub)>;
1065 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1066 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1067 (LDRBro ro_indexed8:$addr), bsub)>;
1068 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1069 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1070 (LDRHro ro_indexed16:$addr), hsub)>;
1071 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1072 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1073 (LDRHro ro_indexed16:$addr), hsub)>;
1074 def : Pat <(v2i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1075 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1076 (LDRSro ro_indexed32:$addr), ssub)>;
1077 def : Pat <(v4i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1078 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1079 (LDRSro ro_indexed32:$addr), ssub)>;
1080 def : Pat <(v1i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1081 (LDRDro ro_indexed64:$addr)>;
1082 def : Pat <(v2i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1083 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1084 (LDRDro ro_indexed64:$addr), dsub)>;
1086 // Match all load 64 bits width whose type is compatible with FPR64
1087 def : Pat<(v2f32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1088 def : Pat<(v1f64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1089 def : Pat<(v8i8 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1090 def : Pat<(v4i16 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1091 def : Pat<(v2i32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1092 def : Pat<(v1i64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1094 // Match all load 128 bits width whose type is compatible with FPR128
1095 def : Pat<(v4f32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1096 def : Pat<(v2f64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1097 def : Pat<(v16i8 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1098 def : Pat<(v8i16 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1099 def : Pat<(v4i32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1100 def : Pat<(v2i64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1101 def : Pat<(f128 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1103 // Load sign-extended half-word
1104 def LDRSHWro : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh",
1105 [(set GPR32:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1106 def LDRSHXro : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh",
1107 [(set GPR64:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1109 // Load sign-extended byte
1110 def LDRSBWro : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb",
1111 [(set GPR32:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1112 def LDRSBXro : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb",
1113 [(set GPR64:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1115 // Load sign-extended word
1116 def LDRSWro : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw",
1117 [(set GPR64:$Rt, (sextloadi32 ro_indexed32:$addr))]>;
1120 def PRFMro : PrefetchRO<0b11, 0, 0b10, "prfm",
1121 [(ARM64Prefetch imm:$Rt, ro_indexed64:$addr)]>;
1124 def : Pat<(i64 (zextloadi8 ro_indexed8:$addr)),
1125 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1126 def : Pat<(i64 (zextloadi16 ro_indexed16:$addr)),
1127 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1128 def : Pat<(i64 (zextloadi32 ro_indexed32:$addr)),
1129 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1131 // zextloadi1 -> zextloadi8
1132 def : Pat<(i32 (zextloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1133 def : Pat<(i64 (zextloadi1 ro_indexed8:$addr)),
1134 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1136 // extload -> zextload
1137 def : Pat<(i32 (extloadi16 ro_indexed16:$addr)), (LDRHHro ro_indexed16:$addr)>;
1138 def : Pat<(i32 (extloadi8 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1139 def : Pat<(i32 (extloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1140 def : Pat<(i64 (extloadi32 ro_indexed32:$addr)),
1141 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1142 def : Pat<(i64 (extloadi16 ro_indexed16:$addr)),
1143 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1144 def : Pat<(i64 (extloadi8 ro_indexed8:$addr)),
1145 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1146 def : Pat<(i64 (extloadi1 ro_indexed8:$addr)),
1147 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1149 } // AddedComplexity = 10
1152 // (unsigned immediate)
1154 def LDRXui : LoadUI<0b11, 0, 0b01, GPR64, am_indexed64, "ldr",
1155 [(set GPR64:$Rt, (load am_indexed64:$addr))]>;
1156 def LDRWui : LoadUI<0b10, 0, 0b01, GPR32, am_indexed32, "ldr",
1157 [(set GPR32:$Rt, (load am_indexed32:$addr))]>;
1158 def LDRBui : LoadUI<0b00, 1, 0b01, FPR8, am_indexed8, "ldr",
1159 [(set FPR8:$Rt, (load am_indexed8:$addr))]>;
1160 def LDRHui : LoadUI<0b01, 1, 0b01, FPR16, am_indexed16, "ldr",
1161 [(set (f16 FPR16:$Rt), (load am_indexed16:$addr))]>;
1162 def LDRSui : LoadUI<0b10, 1, 0b01, FPR32, am_indexed32, "ldr",
1163 [(set (f32 FPR32:$Rt), (load am_indexed32:$addr))]>;
1164 def LDRDui : LoadUI<0b11, 1, 0b01, FPR64, am_indexed64, "ldr",
1165 [(set (f64 FPR64:$Rt), (load am_indexed64:$addr))]>;
1166 def LDRQui : LoadUI<0b00, 1, 0b11, FPR128, am_indexed128, "ldr",
1167 [(set (f128 FPR128:$Rt), (load am_indexed128:$addr))]>;
1169 // For regular load, we do not have any alignment requirement.
1170 // Thus, it is safe to directly map the vector loads with interesting
1171 // addressing modes.
1172 // FIXME: We could do the same for bitconvert to floating point vectors.
1173 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1174 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1175 (LDRBui am_indexed8:$addr), bsub)>;
1176 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1177 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1178 (LDRBui am_indexed8:$addr), bsub)>;
1179 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1180 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1181 (LDRHui am_indexed16:$addr), hsub)>;
1182 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1183 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1184 (LDRHui am_indexed16:$addr), hsub)>;
1185 def : Pat <(v2i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1186 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1187 (LDRSui am_indexed32:$addr), ssub)>;
1188 def : Pat <(v4i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1189 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1190 (LDRSui am_indexed32:$addr), ssub)>;
1191 def : Pat <(v1i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1192 (LDRDui am_indexed64:$addr)>;
1193 def : Pat <(v2i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1194 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1195 (LDRDui am_indexed64:$addr), dsub)>;
1197 // Match all load 64 bits width whose type is compatible with FPR64
1198 def : Pat<(v2f32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1199 def : Pat<(v1f64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1200 def : Pat<(v8i8 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1201 def : Pat<(v4i16 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1202 def : Pat<(v2i32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1203 def : Pat<(v1i64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1205 // Match all load 128 bits width whose type is compatible with FPR128
1206 def : Pat<(v4f32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1207 def : Pat<(v2f64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1208 def : Pat<(v16i8 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1209 def : Pat<(v8i16 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1210 def : Pat<(v4i32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1211 def : Pat<(v2i64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1212 def : Pat<(f128 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1214 def LDRHHui : LoadUI<0b01, 0, 0b01, GPR32, am_indexed16, "ldrh",
1215 [(set GPR32:$Rt, (zextloadi16 am_indexed16:$addr))]>;
1216 def LDRBBui : LoadUI<0b00, 0, 0b01, GPR32, am_indexed8, "ldrb",
1217 [(set GPR32:$Rt, (zextloadi8 am_indexed8:$addr))]>;
1219 def : Pat<(i64 (zextloadi8 am_indexed8:$addr)),
1220 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1221 def : Pat<(i64 (zextloadi16 am_indexed16:$addr)),
1222 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1224 // zextloadi1 -> zextloadi8
1225 def : Pat<(i32 (zextloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1226 def : Pat<(i64 (zextloadi1 am_indexed8:$addr)),
1227 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1229 // extload -> zextload
1230 def : Pat<(i32 (extloadi16 am_indexed16:$addr)), (LDRHHui am_indexed16:$addr)>;
1231 def : Pat<(i32 (extloadi8 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1232 def : Pat<(i32 (extloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1233 def : Pat<(i64 (extloadi32 am_indexed32:$addr)),
1234 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1235 def : Pat<(i64 (extloadi16 am_indexed16:$addr)),
1236 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1237 def : Pat<(i64 (extloadi8 am_indexed8:$addr)),
1238 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1239 def : Pat<(i64 (extloadi1 am_indexed8:$addr)),
1240 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1242 // load sign-extended half-word
1243 def LDRSHWui : LoadUI<0b01, 0, 0b11, GPR32, am_indexed16, "ldrsh",
1244 [(set GPR32:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1245 def LDRSHXui : LoadUI<0b01, 0, 0b10, GPR64, am_indexed16, "ldrsh",
1246 [(set GPR64:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1248 // load sign-extended byte
1249 def LDRSBWui : LoadUI<0b00, 0, 0b11, GPR32, am_indexed8, "ldrsb",
1250 [(set GPR32:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1251 def LDRSBXui : LoadUI<0b00, 0, 0b10, GPR64, am_indexed8, "ldrsb",
1252 [(set GPR64:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1254 // load sign-extended word
1255 def LDRSWui : LoadUI<0b10, 0, 0b10, GPR64, am_indexed32, "ldrsw",
1256 [(set GPR64:$Rt, (sextloadi32 am_indexed32:$addr))]>;
1258 // load zero-extended word
1259 def : Pat<(i64 (zextloadi32 am_indexed32:$addr)),
1260 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1263 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1264 [(ARM64Prefetch imm:$Rt, am_indexed64:$addr)]>;
1268 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1269 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1270 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1271 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1272 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1274 // load sign-extended word
1275 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1278 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1279 // [(ARM64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1282 // (unscaled immediate)
1283 def LDURXi : LoadUnscaled<0b11, 0, 0b01, GPR64, am_unscaled64, "ldur",
1284 [(set GPR64:$Rt, (load am_unscaled64:$addr))]>;
1285 def LDURWi : LoadUnscaled<0b10, 0, 0b01, GPR32, am_unscaled32, "ldur",
1286 [(set GPR32:$Rt, (load am_unscaled32:$addr))]>;
1287 def LDURBi : LoadUnscaled<0b00, 1, 0b01, FPR8, am_unscaled8, "ldur",
1288 [(set FPR8:$Rt, (load am_unscaled8:$addr))]>;
1289 def LDURHi : LoadUnscaled<0b01, 1, 0b01, FPR16, am_unscaled16, "ldur",
1290 [(set (f16 FPR16:$Rt), (load am_unscaled16:$addr))]>;
1291 def LDURSi : LoadUnscaled<0b10, 1, 0b01, FPR32, am_unscaled32, "ldur",
1292 [(set (f32 FPR32:$Rt), (load am_unscaled32:$addr))]>;
1293 def LDURDi : LoadUnscaled<0b11, 1, 0b01, FPR64, am_unscaled64, "ldur",
1294 [(set (f64 FPR64:$Rt), (load am_unscaled64:$addr))]>;
1295 def LDURQi : LoadUnscaled<0b00, 1, 0b11, FPR128, am_unscaled128, "ldur",
1296 [(set (v2f64 FPR128:$Rt), (load am_unscaled128:$addr))]>;
1299 : LoadUnscaled<0b01, 0, 0b01, GPR32, am_unscaled16, "ldurh",
1300 [(set GPR32:$Rt, (zextloadi16 am_unscaled16:$addr))]>;
1302 : LoadUnscaled<0b00, 0, 0b01, GPR32, am_unscaled8, "ldurb",
1303 [(set GPR32:$Rt, (zextloadi8 am_unscaled8:$addr))]>;
1305 // Match all load 64 bits width whose type is compatible with FPR64
1306 def : Pat<(v2f32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1307 def : Pat<(v1f64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1308 def : Pat<(v8i8 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1309 def : Pat<(v4i16 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1310 def : Pat<(v2i32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1311 def : Pat<(v1i64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1313 // Match all load 128 bits width whose type is compatible with FPR128
1314 def : Pat<(v4f32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1315 def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1316 def : Pat<(v16i8 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1317 def : Pat<(v8i16 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1318 def : Pat<(v4i32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1319 def : Pat<(v2i64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1320 def : Pat<(f128 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1323 def : Pat<(i32 (extloadi16 am_unscaled16:$addr)), (LDURHHi am_unscaled16:$addr)>;
1324 def : Pat<(i32 (extloadi8 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1325 def : Pat<(i32 (extloadi1 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1326 def : Pat<(i64 (extloadi32 am_unscaled32:$addr)),
1327 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1328 def : Pat<(i64 (extloadi16 am_unscaled16:$addr)),
1329 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1330 def : Pat<(i64 (extloadi8 am_unscaled8:$addr)),
1331 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1332 def : Pat<(i64 (extloadi1 am_unscaled8:$addr)),
1333 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1335 def : Pat<(i32 (zextloadi16 am_unscaled16:$addr)),
1336 (LDURHHi am_unscaled16:$addr)>;
1337 def : Pat<(i32 (zextloadi8 am_unscaled8:$addr)),
1338 (LDURBBi am_unscaled8:$addr)>;
1339 def : Pat<(i32 (zextloadi1 am_unscaled8:$addr)),
1340 (LDURBBi am_unscaled8:$addr)>;
1341 def : Pat<(i64 (zextloadi32 am_unscaled32:$addr)),
1342 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1343 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1344 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1345 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1346 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1347 def : Pat<(i64 (zextloadi1 am_unscaled8:$addr)),
1348 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1352 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1354 // Define new assembler match classes as we want to only match these when
1355 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1356 // associate a DiagnosticType either, as we want the diagnostic for the
1357 // canonical form (the scaled operand) to take precedence.
1358 def MemoryUnscaledFB8Operand : AsmOperandClass {
1359 let Name = "MemoryUnscaledFB8";
1360 let RenderMethod = "addMemoryUnscaledOperands";
1362 def MemoryUnscaledFB16Operand : AsmOperandClass {
1363 let Name = "MemoryUnscaledFB16";
1364 let RenderMethod = "addMemoryUnscaledOperands";
1366 def MemoryUnscaledFB32Operand : AsmOperandClass {
1367 let Name = "MemoryUnscaledFB32";
1368 let RenderMethod = "addMemoryUnscaledOperands";
1370 def MemoryUnscaledFB64Operand : AsmOperandClass {
1371 let Name = "MemoryUnscaledFB64";
1372 let RenderMethod = "addMemoryUnscaledOperands";
1374 def MemoryUnscaledFB128Operand : AsmOperandClass {
1375 let Name = "MemoryUnscaledFB128";
1376 let RenderMethod = "addMemoryUnscaledOperands";
1378 def am_unscaled_fb8 : Operand<i64> {
1379 let ParserMatchClass = MemoryUnscaledFB8Operand;
1380 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1382 def am_unscaled_fb16 : Operand<i64> {
1383 let ParserMatchClass = MemoryUnscaledFB16Operand;
1384 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1386 def am_unscaled_fb32 : Operand<i64> {
1387 let ParserMatchClass = MemoryUnscaledFB32Operand;
1388 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1390 def am_unscaled_fb64 : Operand<i64> {
1391 let ParserMatchClass = MemoryUnscaledFB64Operand;
1392 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1394 def am_unscaled_fb128 : Operand<i64> {
1395 let ParserMatchClass = MemoryUnscaledFB128Operand;
1396 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1398 def : InstAlias<"ldr $Rt, $addr", (LDURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1399 def : InstAlias<"ldr $Rt, $addr", (LDURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1400 def : InstAlias<"ldr $Rt, $addr", (LDURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1401 def : InstAlias<"ldr $Rt, $addr", (LDURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1402 def : InstAlias<"ldr $Rt, $addr", (LDURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1403 def : InstAlias<"ldr $Rt, $addr", (LDURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1404 def : InstAlias<"ldr $Rt, $addr", (LDURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1407 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1408 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1409 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1410 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1412 // load sign-extended half-word
1414 : LoadUnscaled<0b01, 0, 0b11, GPR32, am_unscaled16, "ldursh",
1415 [(set GPR32:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1417 : LoadUnscaled<0b01, 0, 0b10, GPR64, am_unscaled16, "ldursh",
1418 [(set GPR64:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1420 // load sign-extended byte
1422 : LoadUnscaled<0b00, 0, 0b11, GPR32, am_unscaled8, "ldursb",
1423 [(set GPR32:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1425 : LoadUnscaled<0b00, 0, 0b10, GPR64, am_unscaled8, "ldursb",
1426 [(set GPR64:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1428 // load sign-extended word
1430 : LoadUnscaled<0b10, 0, 0b10, GPR64, am_unscaled32, "ldursw",
1431 [(set GPR64:$Rt, (sextloadi32 am_unscaled32:$addr))]>;
1433 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1434 def : InstAlias<"ldrb $Rt, $addr", (LDURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1435 def : InstAlias<"ldrh $Rt, $addr", (LDURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1436 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBWi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1437 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBXi GPR64:$Rt, am_unscaled_fb8:$addr)>;
1438 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHWi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1439 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHXi GPR64:$Rt, am_unscaled_fb16:$addr)>;
1440 def : InstAlias<"ldrsw $Rt, $addr", (LDURSWi GPR64:$Rt, am_unscaled_fb32:$addr)>;
1443 def PRFUMi : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1444 [(ARM64Prefetch imm:$Rt, am_unscaled64:$addr)]>;
1447 // (unscaled immediate, unprivileged)
1448 def LDTRXi : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1449 def LDTRWi : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1451 def LDTRHi : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1452 def LDTRBi : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1454 // load sign-extended half-word
1455 def LDTRSHWi : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1456 def LDTRSHXi : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1458 // load sign-extended byte
1459 def LDTRSBWi : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1460 def LDTRSBXi : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1462 // load sign-extended word
1463 def LDTRSWi : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1466 // (immediate pre-indexed)
1467 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1468 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1469 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1470 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1471 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1472 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1473 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1475 // load sign-extended half-word
1476 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1477 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1479 // load sign-extended byte
1480 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1481 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1483 // load zero-extended byte
1484 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1485 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1487 // load sign-extended word
1488 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1490 // ISel pseudos and patterns. See expanded comment on LoadPreIdxPseudo.
1491 def LDRDpre_isel : LoadPreIdxPseudo<FPR64>;
1492 def LDRSpre_isel : LoadPreIdxPseudo<FPR32>;
1493 def LDRXpre_isel : LoadPreIdxPseudo<GPR64>;
1494 def LDRWpre_isel : LoadPreIdxPseudo<GPR32>;
1495 def LDRHHpre_isel : LoadPreIdxPseudo<GPR32>;
1496 def LDRBBpre_isel : LoadPreIdxPseudo<GPR32>;
1498 def LDRSWpre_isel : LoadPreIdxPseudo<GPR64>;
1499 def LDRSHWpre_isel : LoadPreIdxPseudo<GPR32>;
1500 def LDRSHXpre_isel : LoadPreIdxPseudo<GPR64>;
1501 def LDRSBWpre_isel : LoadPreIdxPseudo<GPR32>;
1502 def LDRSBXpre_isel : LoadPreIdxPseudo<GPR64>;
1505 // (immediate post-indexed)
1506 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1507 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1508 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1509 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1510 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1511 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1512 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1514 // load sign-extended half-word
1515 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1516 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1518 // load sign-extended byte
1519 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1520 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1522 // load zero-extended byte
1523 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1524 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1526 // load sign-extended word
1527 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1529 // ISel pseudos and patterns. See expanded comment on LoadPostIdxPseudo.
1530 def LDRDpost_isel : LoadPostIdxPseudo<FPR64>;
1531 def LDRSpost_isel : LoadPostIdxPseudo<FPR32>;
1532 def LDRXpost_isel : LoadPostIdxPseudo<GPR64>;
1533 def LDRWpost_isel : LoadPostIdxPseudo<GPR32>;
1534 def LDRHHpost_isel : LoadPostIdxPseudo<GPR32>;
1535 def LDRBBpost_isel : LoadPostIdxPseudo<GPR32>;
1537 def LDRSWpost_isel : LoadPostIdxPseudo<GPR64>;
1538 def LDRSHWpost_isel : LoadPostIdxPseudo<GPR32>;
1539 def LDRSHXpost_isel : LoadPostIdxPseudo<GPR64>;
1540 def LDRSBWpost_isel : LoadPostIdxPseudo<GPR32>;
1541 def LDRSBXpost_isel : LoadPostIdxPseudo<GPR64>;
1543 //===----------------------------------------------------------------------===//
1544 // Store instructions.
1545 //===----------------------------------------------------------------------===//
1547 // Pair (indexed, offset)
1548 // FIXME: Use dedicated range-checked addressing mode operand here.
1549 def STPWi : StorePairOffset<0b00, 0, GPR32, am_indexed32simm7, "stp">;
1550 def STPXi : StorePairOffset<0b10, 0, GPR64, am_indexed64simm7, "stp">;
1551 def STPSi : StorePairOffset<0b00, 1, FPR32, am_indexed32simm7, "stp">;
1552 def STPDi : StorePairOffset<0b01, 1, FPR64, am_indexed64simm7, "stp">;
1553 def STPQi : StorePairOffset<0b10, 1, FPR128, am_indexed128simm7, "stp">;
1555 // Pair (pre-indexed)
1556 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7_wb, "stp">;
1557 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7_wb, "stp">;
1558 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7_wb, "stp">;
1559 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7_wb, "stp">;
1560 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7_wb, "stp">;
1562 // Pair (pre-indexed)
1563 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1564 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1565 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1566 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1567 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1569 // Pair (no allocate)
1570 def STNPWi : StorePairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "stnp">;
1571 def STNPXi : StorePairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "stnp">;
1572 def STNPSi : StorePairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "stnp">;
1573 def STNPDi : StorePairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "stnp">;
1574 def STNPQi : StorePairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "stnp">;
1577 // (Register offset)
1579 let AddedComplexity = 10 in {
1582 def STRHHro : Store16RO<0b01, 0, 0b00, GPR32, "strh",
1583 [(truncstorei16 GPR32:$Rt, ro_indexed16:$addr)]>;
1584 def STRBBro : Store8RO<0b00, 0, 0b00, GPR32, "strb",
1585 [(truncstorei8 GPR32:$Rt, ro_indexed8:$addr)]>;
1586 def STRWro : Store32RO<0b10, 0, 0b00, GPR32, "str",
1587 [(store GPR32:$Rt, ro_indexed32:$addr)]>;
1588 def STRXro : Store64RO<0b11, 0, 0b00, GPR64, "str",
1589 [(store GPR64:$Rt, ro_indexed64:$addr)]>;
1592 def : Pat<(truncstorei8 GPR64:$Rt, ro_indexed8:$addr),
1593 (STRBBro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed8:$addr)>;
1594 def : Pat<(truncstorei16 GPR64:$Rt, ro_indexed16:$addr),
1595 (STRHHro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed16:$addr)>;
1596 def : Pat<(truncstorei32 GPR64:$Rt, ro_indexed32:$addr),
1597 (STRWro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed32:$addr)>;
1601 def STRBro : Store8RO<0b00, 1, 0b00, FPR8, "str",
1602 [(store FPR8:$Rt, ro_indexed8:$addr)]>;
1603 def STRHro : Store16RO<0b01, 1, 0b00, FPR16, "str",
1604 [(store (f16 FPR16:$Rt), ro_indexed16:$addr)]>;
1605 def STRSro : Store32RO<0b10, 1, 0b00, FPR32, "str",
1606 [(store (f32 FPR32:$Rt), ro_indexed32:$addr)]>;
1607 def STRDro : Store64RO<0b11, 1, 0b00, FPR64, "str",
1608 [(store (f64 FPR64:$Rt), ro_indexed64:$addr)]>;
1609 def STRQro : Store128RO<0b00, 1, 0b10, FPR128, "str", []> {
1613 // Match all store 64 bits width whose type is compatible with FPR64
1614 def : Pat<(store (v2f32 FPR64:$Rn), ro_indexed64:$addr),
1615 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1616 def : Pat<(store (v1f64 FPR64:$Rn), ro_indexed64:$addr),
1617 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1618 def : Pat<(store (v8i8 FPR64:$Rn), ro_indexed64:$addr),
1619 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1620 def : Pat<(store (v4i16 FPR64:$Rn), ro_indexed64:$addr),
1621 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1622 def : Pat<(store (v2i32 FPR64:$Rn), ro_indexed64:$addr),
1623 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1624 def : Pat<(store (v1i64 FPR64:$Rn), ro_indexed64:$addr),
1625 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1627 // Match all store 128 bits width whose type is compatible with FPR128
1628 def : Pat<(store (v4f32 FPR128:$Rn), ro_indexed128:$addr),
1629 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1630 def : Pat<(store (v2f64 FPR128:$Rn), ro_indexed128:$addr),
1631 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1632 def : Pat<(store (v16i8 FPR128:$Rn), ro_indexed128:$addr),
1633 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1634 def : Pat<(store (v8i16 FPR128:$Rn), ro_indexed128:$addr),
1635 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1636 def : Pat<(store (v4i32 FPR128:$Rn), ro_indexed128:$addr),
1637 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1638 def : Pat<(store (v2i64 FPR128:$Rn), ro_indexed128:$addr),
1639 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1640 def : Pat<(store (f128 FPR128:$Rn), ro_indexed128:$addr),
1641 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1644 // (unsigned immediate)
1645 def STRXui : StoreUI<0b11, 0, 0b00, GPR64, am_indexed64, "str",
1646 [(store GPR64:$Rt, am_indexed64:$addr)]>;
1647 def STRWui : StoreUI<0b10, 0, 0b00, GPR32, am_indexed32, "str",
1648 [(store GPR32:$Rt, am_indexed32:$addr)]>;
1649 def STRBui : StoreUI<0b00, 1, 0b00, FPR8, am_indexed8, "str",
1650 [(store FPR8:$Rt, am_indexed8:$addr)]>;
1651 def STRHui : StoreUI<0b01, 1, 0b00, FPR16, am_indexed16, "str",
1652 [(store (f16 FPR16:$Rt), am_indexed16:$addr)]>;
1653 def STRSui : StoreUI<0b10, 1, 0b00, FPR32, am_indexed32, "str",
1654 [(store (f32 FPR32:$Rt), am_indexed32:$addr)]>;
1655 def STRDui : StoreUI<0b11, 1, 0b00, FPR64, am_indexed64, "str",
1656 [(store (f64 FPR64:$Rt), am_indexed64:$addr)]>;
1657 def STRQui : StoreUI<0b00, 1, 0b10, FPR128, am_indexed128, "str", []> {
1661 // Match all store 64 bits width whose type is compatible with FPR64
1662 def : Pat<(store (v2f32 FPR64:$Rn), am_indexed64:$addr),
1663 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1664 def : Pat<(store (v1f64 FPR64:$Rn), am_indexed64:$addr),
1665 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1666 def : Pat<(store (v8i8 FPR64:$Rn), am_indexed64:$addr),
1667 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1668 def : Pat<(store (v4i16 FPR64:$Rn), am_indexed64:$addr),
1669 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1670 def : Pat<(store (v2i32 FPR64:$Rn), am_indexed64:$addr),
1671 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1672 def : Pat<(store (v1i64 FPR64:$Rn), am_indexed64:$addr),
1673 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1675 // Match all store 128 bits width whose type is compatible with FPR128
1676 def : Pat<(store (v4f32 FPR128:$Rn), am_indexed128:$addr),
1677 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1678 def : Pat<(store (v2f64 FPR128:$Rn), am_indexed128:$addr),
1679 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1680 def : Pat<(store (v16i8 FPR128:$Rn), am_indexed128:$addr),
1681 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1682 def : Pat<(store (v8i16 FPR128:$Rn), am_indexed128:$addr),
1683 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1684 def : Pat<(store (v4i32 FPR128:$Rn), am_indexed128:$addr),
1685 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1686 def : Pat<(store (v2i64 FPR128:$Rn), am_indexed128:$addr),
1687 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1688 def : Pat<(store (f128 FPR128:$Rn), am_indexed128:$addr),
1689 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1691 def STRHHui : StoreUI<0b01, 0, 0b00, GPR32, am_indexed16, "strh",
1692 [(truncstorei16 GPR32:$Rt, am_indexed16:$addr)]>;
1693 def STRBBui : StoreUI<0b00, 0, 0b00, GPR32, am_indexed8, "strb",
1694 [(truncstorei8 GPR32:$Rt, am_indexed8:$addr)]>;
1697 def : Pat<(truncstorei32 GPR64:$Rt, am_indexed32:$addr),
1698 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed32:$addr)>;
1699 def : Pat<(truncstorei16 GPR64:$Rt, am_indexed16:$addr),
1700 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed16:$addr)>;
1701 def : Pat<(truncstorei8 GPR64:$Rt, am_indexed8:$addr),
1702 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed8:$addr)>;
1704 } // AddedComplexity = 10
1707 // (unscaled immediate)
1708 def STURXi : StoreUnscaled<0b11, 0, 0b00, GPR64, am_unscaled64, "stur",
1709 [(store GPR64:$Rt, am_unscaled64:$addr)]>;
1710 def STURWi : StoreUnscaled<0b10, 0, 0b00, GPR32, am_unscaled32, "stur",
1711 [(store GPR32:$Rt, am_unscaled32:$addr)]>;
1712 def STURBi : StoreUnscaled<0b00, 1, 0b00, FPR8, am_unscaled8, "stur",
1713 [(store FPR8:$Rt, am_unscaled8:$addr)]>;
1714 def STURHi : StoreUnscaled<0b01, 1, 0b00, FPR16, am_unscaled16, "stur",
1715 [(store (f16 FPR16:$Rt), am_unscaled16:$addr)]>;
1716 def STURSi : StoreUnscaled<0b10, 1, 0b00, FPR32, am_unscaled32, "stur",
1717 [(store (f32 FPR32:$Rt), am_unscaled32:$addr)]>;
1718 def STURDi : StoreUnscaled<0b11, 1, 0b00, FPR64, am_unscaled64, "stur",
1719 [(store (f64 FPR64:$Rt), am_unscaled64:$addr)]>;
1720 def STURQi : StoreUnscaled<0b00, 1, 0b10, FPR128, am_unscaled128, "stur",
1721 [(store (v2f64 FPR128:$Rt), am_unscaled128:$addr)]>;
1722 def STURHHi : StoreUnscaled<0b01, 0, 0b00, GPR32, am_unscaled16, "sturh",
1723 [(truncstorei16 GPR32:$Rt, am_unscaled16:$addr)]>;
1724 def STURBBi : StoreUnscaled<0b00, 0, 0b00, GPR32, am_unscaled8, "sturb",
1725 [(truncstorei8 GPR32:$Rt, am_unscaled8:$addr)]>;
1727 // Match all store 64 bits width whose type is compatible with FPR64
1728 def : Pat<(store (v2f32 FPR64:$Rn), am_unscaled64:$addr),
1729 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1730 def : Pat<(store (v1f64 FPR64:$Rn), am_unscaled64:$addr),
1731 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1732 def : Pat<(store (v8i8 FPR64:$Rn), am_unscaled64:$addr),
1733 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1734 def : Pat<(store (v4i16 FPR64:$Rn), am_unscaled64:$addr),
1735 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1736 def : Pat<(store (v2i32 FPR64:$Rn), am_unscaled64:$addr),
1737 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1738 def : Pat<(store (v1i64 FPR64:$Rn), am_unscaled64:$addr),
1739 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1741 // Match all store 128 bits width whose type is compatible with FPR128
1742 def : Pat<(store (v4f32 FPR128:$Rn), am_unscaled128:$addr),
1743 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1744 def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
1745 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1746 def : Pat<(store (v16i8 FPR128:$Rn), am_unscaled128:$addr),
1747 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1748 def : Pat<(store (v8i16 FPR128:$Rn), am_unscaled128:$addr),
1749 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1750 def : Pat<(store (v4i32 FPR128:$Rn), am_unscaled128:$addr),
1751 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1752 def : Pat<(store (v2i64 FPR128:$Rn), am_unscaled128:$addr),
1753 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1754 def : Pat<(store (f128 FPR128:$Rn), am_unscaled128:$addr),
1755 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1757 // unscaled i64 truncating stores
1758 def : Pat<(truncstorei32 GPR64:$Rt, am_unscaled32:$addr),
1759 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled32:$addr)>;
1760 def : Pat<(truncstorei16 GPR64:$Rt, am_unscaled16:$addr),
1761 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled16:$addr)>;
1762 def : Pat<(truncstorei8 GPR64:$Rt, am_unscaled8:$addr),
1763 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled8:$addr)>;
1766 // STR mnemonics fall back to STUR for negative or unaligned offsets.
1767 def : InstAlias<"str $Rt, $addr", (STURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1768 def : InstAlias<"str $Rt, $addr", (STURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1769 def : InstAlias<"str $Rt, $addr", (STURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1770 def : InstAlias<"str $Rt, $addr", (STURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1771 def : InstAlias<"str $Rt, $addr", (STURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1772 def : InstAlias<"str $Rt, $addr", (STURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1773 def : InstAlias<"str $Rt, $addr", (STURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1775 def : InstAlias<"strb $Rt, $addr", (STURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1776 def : InstAlias<"strh $Rt, $addr", (STURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1779 // (unscaled immediate, unprivileged)
1780 def STTRWi : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
1781 def STTRXi : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
1783 def STTRHi : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
1784 def STTRBi : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
1787 // (immediate pre-indexed)
1788 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str">;
1789 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str">;
1790 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str">;
1791 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str">;
1792 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str">;
1793 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str">;
1794 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str">;
1796 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb">;
1797 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh">;
1799 // ISel pseudos and patterns. See expanded comment on StorePreIdxPseudo.
1800 defm STRDpre : StorePreIdxPseudo<FPR64, f64, pre_store>;
1801 defm STRSpre : StorePreIdxPseudo<FPR32, f32, pre_store>;
1802 defm STRXpre : StorePreIdxPseudo<GPR64, i64, pre_store>;
1803 defm STRWpre : StorePreIdxPseudo<GPR32, i32, pre_store>;
1804 defm STRHHpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti16>;
1805 defm STRBBpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti8>;
1807 def : Pat<(pre_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1808 (STRWpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1810 def : Pat<(pre_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1811 (STRHHpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1813 def : Pat<(pre_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1814 (STRBBpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1818 // (immediate post-indexed)
1819 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str">;
1820 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str">;
1821 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str">;
1822 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str">;
1823 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str">;
1824 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str">;
1825 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str">;
1827 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb">;
1828 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh">;
1830 // ISel pseudos and patterns. See expanded comment on StorePostIdxPseudo.
1831 defm STRDpost : StorePostIdxPseudo<FPR64, f64, post_store, STRDpost>;
1832 defm STRSpost : StorePostIdxPseudo<FPR32, f32, post_store, STRSpost>;
1833 defm STRXpost : StorePostIdxPseudo<GPR64, i64, post_store, STRXpost>;
1834 defm STRWpost : StorePostIdxPseudo<GPR32, i32, post_store, STRWpost>;
1835 defm STRHHpost : StorePostIdxPseudo<GPR32, i32, post_truncsti16, STRHHpost>;
1836 defm STRBBpost : StorePostIdxPseudo<GPR32, i32, post_truncsti8, STRBBpost>;
1838 def : Pat<(post_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1839 (STRWpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1841 def : Pat<(post_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1842 (STRHHpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1844 def : Pat<(post_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1845 (STRBBpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1849 //===----------------------------------------------------------------------===//
1850 // Load/store exclusive instructions.
1851 //===----------------------------------------------------------------------===//
1853 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
1854 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
1855 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
1856 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
1858 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
1859 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
1860 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
1861 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
1863 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
1864 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
1865 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
1866 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
1868 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
1869 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
1870 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
1871 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
1873 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
1874 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
1875 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
1876 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
1878 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
1879 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
1880 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
1881 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
1883 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
1884 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
1886 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
1887 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
1889 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
1890 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
1892 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
1893 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
1895 //===----------------------------------------------------------------------===//
1896 // Scaled floating point to integer conversion instructions.
1897 //===----------------------------------------------------------------------===//
1899 defm FCVTAS : FPToIntegerUnscaled<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
1900 defm FCVTAU : FPToIntegerUnscaled<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
1901 defm FCVTMS : FPToIntegerUnscaled<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
1902 defm FCVTMU : FPToIntegerUnscaled<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
1903 defm FCVTNS : FPToIntegerUnscaled<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
1904 defm FCVTNU : FPToIntegerUnscaled<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
1905 defm FCVTPS : FPToIntegerUnscaled<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
1906 defm FCVTPU : FPToIntegerUnscaled<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
1907 defm FCVTZS : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
1908 defm FCVTZU : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
1909 defm FCVTZS : FPToIntegerScaled<0b11, 0b000, "fcvtzs", fp_to_sint>;
1910 defm FCVTZU : FPToIntegerScaled<0b11, 0b001, "fcvtzu", fp_to_uint>;
1911 let isCodeGenOnly = 1 in {
1912 defm FCVTZS_Int : FPToIntegerUnscaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
1913 defm FCVTZU_Int : FPToIntegerUnscaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
1914 defm FCVTZS_Int : FPToIntegerScaled<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
1915 defm FCVTZU_Int : FPToIntegerScaled<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
1918 //===----------------------------------------------------------------------===//
1919 // Scaled integer to floating point conversion instructions.
1920 //===----------------------------------------------------------------------===//
1922 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
1923 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
1925 //===----------------------------------------------------------------------===//
1926 // Unscaled integer to floating point conversion instruction.
1927 //===----------------------------------------------------------------------===//
1929 defm FMOV : UnscaledConversion<"fmov">;
1931 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
1932 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
1934 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1935 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1936 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1937 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1938 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1939 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1940 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)),
1941 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1942 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)),
1943 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1944 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
1946 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))),
1947 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1948 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))),
1949 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1950 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))),
1951 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1952 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))),
1953 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1954 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))),
1955 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1956 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))),
1957 (COPY_TO_REGCLASS V64:$Vn, GPR64)>;
1959 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))),
1960 (COPY_TO_REGCLASS GPR32:$Xn, FPR32)>;
1961 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))),
1962 (COPY_TO_REGCLASS FPR32:$Xn, GPR32)>;
1963 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))),
1964 (COPY_TO_REGCLASS GPR64:$Xn, FPR64)>;
1965 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))),
1966 (COPY_TO_REGCLASS FPR64:$Xn, GPR64)>;
1968 //===----------------------------------------------------------------------===//
1969 // Floating point conversion instruction.
1970 //===----------------------------------------------------------------------===//
1972 defm FCVT : FPConversion<"fcvt">;
1974 def : Pat<(f32_to_f16 FPR32:$Rn),
1975 (i32 (COPY_TO_REGCLASS
1976 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
1979 def FCVTSHpseudo : Pseudo<(outs FPR32:$Rd), (ins FPR32:$Rn),
1980 [(set (f32 FPR32:$Rd), (f16_to_f32 i32:$Rn))]>;
1982 //===----------------------------------------------------------------------===//
1983 // Floating point single operand instructions.
1984 //===----------------------------------------------------------------------===//
1986 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
1987 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
1988 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
1989 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
1990 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
1991 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
1992 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_arm64_neon_frintn>;
1993 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
1995 def : Pat<(v1f64 (int_arm64_neon_frintn (v1f64 FPR64:$Rn))),
1996 (FRINTNDr FPR64:$Rn)>;
1998 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
1999 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
2000 // <rdar://problem/13715968>
2001 // TODO: We should really model the FPSR flags correctly. This is really ugly.
2002 let hasSideEffects = 1 in {
2003 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
2006 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
2008 let SchedRW = [WriteFDiv] in {
2009 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
2012 //===----------------------------------------------------------------------===//
2013 // Floating point two operand instructions.
2014 //===----------------------------------------------------------------------===//
2016 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
2017 let SchedRW = [WriteFDiv] in {
2018 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
2020 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_arm64_neon_fmaxnm>;
2021 defm FMAX : TwoOperandFPData<0b0100, "fmax", ARM64fmax>;
2022 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_arm64_neon_fminnm>;
2023 defm FMIN : TwoOperandFPData<0b0101, "fmin", ARM64fmin>;
2024 let SchedRW = [WriteFMul] in {
2025 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
2026 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
2028 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
2030 def : Pat<(v1f64 (ARM64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2031 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
2032 def : Pat<(v1f64 (ARM64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2033 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
2034 def : Pat<(v1f64 (int_arm64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2035 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
2036 def : Pat<(v1f64 (int_arm64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2037 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
2039 //===----------------------------------------------------------------------===//
2040 // Floating point three operand instructions.
2041 //===----------------------------------------------------------------------===//
2043 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
2044 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
2045 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
2046 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
2047 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
2048 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
2049 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2051 // The following def pats catch the case where the LHS of an FMA is negated.
2052 // The TriOpFrag above catches the case where the middle operand is negated.
2054 // N.b. FMSUB etc have the accumulator at the *end* of (outs), unlike
2055 // the NEON variant.
2056 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, FPR32:$Ra)),
2057 (FMSUBSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2059 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, FPR64:$Ra)),
2060 (FMSUBDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2062 // We handled -(a + b*c) for FNMADD above, now it's time for "(-a) + (-b)*c" and
2064 def : Pat<(f32 (fma (fneg FPR32:$Rn), FPR32:$Rm, (fneg FPR32:$Ra))),
2065 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2067 def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
2068 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2070 def : Pat<(f32 (fma FPR32:$Rn, (fneg FPR32:$Rm), (fneg FPR32:$Ra))),
2071 (FNMADDSrrr FPR32:$Rn, FPR32:$Rm, FPR32:$Ra)>;
2073 def : Pat<(f64 (fma FPR64:$Rn, (fneg FPR64:$Rm), (fneg FPR64:$Ra))),
2074 (FNMADDDrrr FPR64:$Rn, FPR64:$Rm, FPR64:$Ra)>;
2076 //===----------------------------------------------------------------------===//
2077 // Floating point comparison instructions.
2078 //===----------------------------------------------------------------------===//
2080 defm FCMPE : FPComparison<1, "fcmpe">;
2081 defm FCMP : FPComparison<0, "fcmp", ARM64fcmp>;
2083 //===----------------------------------------------------------------------===//
2084 // Floating point conditional comparison instructions.
2085 //===----------------------------------------------------------------------===//
2087 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2088 defm FCCMP : FPCondComparison<0, "fccmp">;
2090 //===----------------------------------------------------------------------===//
2091 // Floating point conditional select instruction.
2092 //===----------------------------------------------------------------------===//
2094 defm FCSEL : FPCondSelect<"fcsel">;
2096 // CSEL instructions providing f128 types need to be handled by a
2097 // pseudo-instruction since the eventual code will need to introduce basic
2098 // blocks and control flow.
2099 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2100 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2101 [(set (f128 FPR128:$Rd),
2102 (ARM64csel FPR128:$Rn, FPR128:$Rm,
2103 (i32 imm:$cond), CPSR))]> {
2105 let usesCustomInserter = 1;
2109 //===----------------------------------------------------------------------===//
2110 // Floating point immediate move.
2111 //===----------------------------------------------------------------------===//
2113 let isReMaterializable = 1 in {
2114 defm FMOV : FPMoveImmediate<"fmov">;
2117 //===----------------------------------------------------------------------===//
2118 // Advanced SIMD two vector instructions.
2119 //===----------------------------------------------------------------------===//
2121 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_arm64_neon_abs>;
2122 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_arm64_neon_cls>;
2123 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2124 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", ARM64cmeqz>;
2125 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", ARM64cmgez>;
2126 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", ARM64cmgtz>;
2127 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", ARM64cmlez>;
2128 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", ARM64cmltz>;
2129 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2130 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2132 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2133 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2134 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2135 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2136 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2137 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_arm64_neon_fcvtas>;
2138 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_arm64_neon_fcvtau>;
2139 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2140 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2141 (FCVTLv4i16 V64:$Rn)>;
2142 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2144 (FCVTLv8i16 V128:$Rn)>;
2145 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2146 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2148 (FCVTLv4i32 V128:$Rn)>;
2150 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_arm64_neon_fcvtms>;
2151 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_arm64_neon_fcvtmu>;
2152 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_arm64_neon_fcvtns>;
2153 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_arm64_neon_fcvtnu>;
2154 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2155 def : Pat<(v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2156 (FCVTNv4i16 V128:$Rn)>;
2157 def : Pat<(concat_vectors V64:$Rd,
2158 (v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2159 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2160 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2161 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2162 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2163 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_arm64_neon_fcvtps>;
2164 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_arm64_neon_fcvtpu>;
2165 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2166 int_arm64_neon_fcvtxn>;
2167 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2168 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2169 let isCodeGenOnly = 1 in {
2170 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2171 int_arm64_neon_fcvtzs>;
2172 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2173 int_arm64_neon_fcvtzu>;
2175 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2176 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_arm64_neon_frecpe>;
2177 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2178 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2179 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2180 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_arm64_neon_frintn>;
2181 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2182 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2183 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2184 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_arm64_neon_frsqrte>;
2185 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2186 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2187 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2188 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2189 // Aliases for MVN -> NOT.
2190 def : InstAlias<"mvn.8b $Vd, $Vn", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2191 def : InstAlias<"mvn.16b $Vd, $Vn", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2192 def : InstAlias<"mvn $Vd.8b, $Vn.8b", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2193 def : InstAlias<"mvn $Vd.16b, $Vn.16b", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2195 def : Pat<(ARM64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2196 def : Pat<(ARM64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2197 def : Pat<(ARM64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2198 def : Pat<(ARM64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2199 def : Pat<(ARM64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2200 def : Pat<(ARM64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2201 def : Pat<(ARM64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2203 def : Pat<(ARM64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2204 def : Pat<(ARM64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2205 def : Pat<(ARM64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2206 def : Pat<(ARM64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2207 def : Pat<(ARM64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2208 def : Pat<(ARM64not (v1i64 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2209 def : Pat<(ARM64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2210 def : Pat<(ARM64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2212 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2213 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2214 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2215 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2216 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2218 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_arm64_neon_rbit>;
2219 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", ARM64rev16>;
2220 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", ARM64rev32>;
2221 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", ARM64rev64>;
2222 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2223 BinOpFrag<(add node:$LHS, (int_arm64_neon_saddlp node:$RHS))> >;
2224 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_arm64_neon_saddlp>;
2225 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2226 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2227 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2228 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2229 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_arm64_neon_sqxtn>;
2230 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_arm64_neon_sqxtun>;
2231 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_arm64_neon_suqadd>;
2232 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2233 BinOpFrag<(add node:$LHS, (int_arm64_neon_uaddlp node:$RHS))> >;
2234 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2235 int_arm64_neon_uaddlp>;
2236 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2237 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_arm64_neon_uqxtn>;
2238 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_arm64_neon_urecpe>;
2239 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_arm64_neon_ursqrte>;
2240 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_arm64_neon_usqadd>;
2241 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2243 def : Pat<(v2f32 (ARM64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2244 def : Pat<(v4f32 (ARM64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2246 // Patterns for vector long shift (by element width). These need to match all
2247 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2249 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2250 def : Pat<(ARM64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2251 (SHLLv8i8 V64:$Rn)>;
2252 def : Pat<(ARM64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2253 (SHLLv16i8 V128:$Rn)>;
2254 def : Pat<(ARM64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2255 (SHLLv4i16 V64:$Rn)>;
2256 def : Pat<(ARM64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2257 (SHLLv8i16 V128:$Rn)>;
2258 def : Pat<(ARM64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2259 (SHLLv2i32 V64:$Rn)>;
2260 def : Pat<(ARM64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2261 (SHLLv4i32 V128:$Rn)>;
2264 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2265 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2266 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2268 //===----------------------------------------------------------------------===//
2269 // Advanced SIMD three vector instructions.
2270 //===----------------------------------------------------------------------===//
2272 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2273 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_arm64_neon_addp>;
2274 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", ARM64cmeq>;
2275 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", ARM64cmge>;
2276 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", ARM64cmgt>;
2277 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", ARM64cmhi>;
2278 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", ARM64cmhs>;
2279 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", ARM64cmtst>;
2280 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_arm64_neon_fabd>;
2281 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_arm64_neon_facge>;
2282 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_arm64_neon_facgt>;
2283 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_arm64_neon_addp>;
2284 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2285 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2286 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2287 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2288 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2289 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_arm64_neon_fmaxnmp>;
2290 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_arm64_neon_fmaxnm>;
2291 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_arm64_neon_fmaxp>;
2292 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", ARM64fmax>;
2293 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_arm64_neon_fminnmp>;
2294 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_arm64_neon_fminnm>;
2295 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_arm64_neon_fminp>;
2296 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", ARM64fmin>;
2298 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2299 // instruction expects the addend first, while the fma intrinsic puts it last.
2300 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2301 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2302 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2303 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2305 // The following def pats catch the case where the LHS of an FMA is negated.
2306 // The TriOpFrag above catches the case where the middle operand is negated.
2307 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2308 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2310 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2311 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2313 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2314 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2316 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_arm64_neon_fmulx>;
2317 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2318 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_arm64_neon_frecps>;
2319 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_arm64_neon_frsqrts>;
2320 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2321 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2322 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2323 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2324 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2325 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2326 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_arm64_neon_pmul>;
2327 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2328 TriOpFrag<(add node:$LHS, (int_arm64_neon_sabd node:$MHS, node:$RHS))> >;
2329 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_arm64_neon_sabd>;
2330 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_arm64_neon_shadd>;
2331 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_arm64_neon_shsub>;
2332 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_arm64_neon_smaxp>;
2333 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_arm64_neon_smax>;
2334 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_arm64_neon_sminp>;
2335 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_arm64_neon_smin>;
2336 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_arm64_neon_sqadd>;
2337 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_arm64_neon_sqdmulh>;
2338 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_arm64_neon_sqrdmulh>;
2339 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_arm64_neon_sqrshl>;
2340 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_arm64_neon_sqshl>;
2341 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_arm64_neon_sqsub>;
2342 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_arm64_neon_srhadd>;
2343 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_arm64_neon_srshl>;
2344 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_arm64_neon_sshl>;
2345 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2346 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2347 TriOpFrag<(add node:$LHS, (int_arm64_neon_uabd node:$MHS, node:$RHS))> >;
2348 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_arm64_neon_uabd>;
2349 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_arm64_neon_uhadd>;
2350 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_arm64_neon_uhsub>;
2351 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_arm64_neon_umaxp>;
2352 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_arm64_neon_umax>;
2353 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_arm64_neon_uminp>;
2354 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_arm64_neon_umin>;
2355 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_arm64_neon_uqadd>;
2356 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_arm64_neon_uqrshl>;
2357 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_arm64_neon_uqshl>;
2358 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_arm64_neon_uqsub>;
2359 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_arm64_neon_urhadd>;
2360 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_arm64_neon_urshl>;
2361 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_arm64_neon_ushl>;
2363 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2364 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2365 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2366 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2367 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", ARM64bit>;
2368 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2369 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2370 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2371 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2372 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2373 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2375 def : Pat<(ARM64bsl (v8i8 V64:$Rd), V64:$Rn, V64:$Rm),
2376 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2377 def : Pat<(ARM64bsl (v4i16 V64:$Rd), V64:$Rn, V64:$Rm),
2378 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2379 def : Pat<(ARM64bsl (v2i32 V64:$Rd), V64:$Rn, V64:$Rm),
2380 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2381 def : Pat<(ARM64bsl (v1i64 V64:$Rd), V64:$Rn, V64:$Rm),
2382 (BSLv8i8 V64:$Rd, V64:$Rn, V64:$Rm)>;
2384 def : Pat<(ARM64bsl (v16i8 V128:$Rd), V128:$Rn, V128:$Rm),
2385 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2386 def : Pat<(ARM64bsl (v8i16 V128:$Rd), V128:$Rn, V128:$Rm),
2387 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2388 def : Pat<(ARM64bsl (v4i32 V128:$Rd), V128:$Rn, V128:$Rm),
2389 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2390 def : Pat<(ARM64bsl (v2i64 V128:$Rd), V128:$Rn, V128:$Rm),
2391 (BSLv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>;
2393 // FIXME: the .16b and .8b variantes should be emitted by the
2394 // AsmWriter. TableGen's AsmWriter-generator doesn't deal with variant syntaxes
2395 // in aliases yet though.
2396 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2397 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2398 def : InstAlias<"{mov\t$dst.8h, $src.8h|mov.8h\t$dst, $src}",
2399 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2400 def : InstAlias<"{mov\t$dst.4s, $src.4s|mov.4s\t$dst, $src}",
2401 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2402 def : InstAlias<"{mov\t$dst.2d, $src.2d|mov.2d\t$dst, $src}",
2403 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2405 def : InstAlias<"{mov\t$dst.8b, $src.8b|mov.8b\t$dst, $src}",
2406 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2407 def : InstAlias<"{mov\t$dst.4h, $src.4h|mov.4h\t$dst, $src}",
2408 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2409 def : InstAlias<"{mov\t$dst.2s, $src.2s|mov.2s\t$dst, $src}",
2410 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2411 def : InstAlias<"{mov\t$dst.1d, $src.1d|mov.1d\t$dst, $src}",
2412 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2414 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2415 "|cmls.8b\t$dst, $src1, $src2}",
2416 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2417 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2418 "|cmls.16b\t$dst, $src1, $src2}",
2419 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2420 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2421 "|cmls.4h\t$dst, $src1, $src2}",
2422 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2423 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2424 "|cmls.8h\t$dst, $src1, $src2}",
2425 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2426 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2427 "|cmls.2s\t$dst, $src1, $src2}",
2428 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2429 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2430 "|cmls.4s\t$dst, $src1, $src2}",
2431 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2432 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2433 "|cmls.2d\t$dst, $src1, $src2}",
2434 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2436 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2437 "|cmlo.8b\t$dst, $src1, $src2}",
2438 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2439 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2440 "|cmlo.16b\t$dst, $src1, $src2}",
2441 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2442 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2443 "|cmlo.4h\t$dst, $src1, $src2}",
2444 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2445 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2446 "|cmlo.8h\t$dst, $src1, $src2}",
2447 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2448 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2449 "|cmlo.2s\t$dst, $src1, $src2}",
2450 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2451 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2452 "|cmlo.4s\t$dst, $src1, $src2}",
2453 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2454 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2455 "|cmlo.2d\t$dst, $src1, $src2}",
2456 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2458 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2459 "|cmle.8b\t$dst, $src1, $src2}",
2460 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2461 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2462 "|cmle.16b\t$dst, $src1, $src2}",
2463 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2464 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2465 "|cmle.4h\t$dst, $src1, $src2}",
2466 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2467 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2468 "|cmle.8h\t$dst, $src1, $src2}",
2469 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2470 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2471 "|cmle.2s\t$dst, $src1, $src2}",
2472 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2473 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2474 "|cmle.4s\t$dst, $src1, $src2}",
2475 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2476 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2477 "|cmle.2d\t$dst, $src1, $src2}",
2478 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2480 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2481 "|cmlt.8b\t$dst, $src1, $src2}",
2482 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2483 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2484 "|cmlt.16b\t$dst, $src1, $src2}",
2485 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2486 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2487 "|cmlt.4h\t$dst, $src1, $src2}",
2488 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2489 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2490 "|cmlt.8h\t$dst, $src1, $src2}",
2491 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2492 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2493 "|cmlt.2s\t$dst, $src1, $src2}",
2494 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2495 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2496 "|cmlt.4s\t$dst, $src1, $src2}",
2497 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2498 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2499 "|cmlt.2d\t$dst, $src1, $src2}",
2500 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2502 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2503 "|fcmle.2s\t$dst, $src1, $src2}",
2504 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2505 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2506 "|fcmle.4s\t$dst, $src1, $src2}",
2507 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2508 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2509 "|fcmle.2d\t$dst, $src1, $src2}",
2510 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2512 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2513 "|fcmlt.2s\t$dst, $src1, $src2}",
2514 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2515 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2516 "|fcmlt.4s\t$dst, $src1, $src2}",
2517 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2518 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2519 "|fcmlt.2d\t$dst, $src1, $src2}",
2520 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2522 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2523 "|facle.2s\t$dst, $src1, $src2}",
2524 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2525 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2526 "|facle.4s\t$dst, $src1, $src2}",
2527 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2528 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2529 "|facle.2d\t$dst, $src1, $src2}",
2530 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2532 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2533 "|faclt.2s\t$dst, $src1, $src2}",
2534 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2535 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2536 "|faclt.4s\t$dst, $src1, $src2}",
2537 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2538 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2539 "|faclt.2d\t$dst, $src1, $src2}",
2540 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2542 //===----------------------------------------------------------------------===//
2543 // Advanced SIMD three scalar instructions.
2544 //===----------------------------------------------------------------------===//
2546 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2547 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", ARM64cmeq>;
2548 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", ARM64cmge>;
2549 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", ARM64cmgt>;
2550 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", ARM64cmhi>;
2551 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", ARM64cmhs>;
2552 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", ARM64cmtst>;
2553 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_arm64_sisd_fabd>;
2554 def : Pat<(v1f64 (int_arm64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2555 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2556 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2557 int_arm64_neon_facge>;
2558 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2559 int_arm64_neon_facgt>;
2560 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2561 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2562 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2563 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_arm64_neon_fmulx>;
2564 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_arm64_neon_frecps>;
2565 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_arm64_neon_frsqrts>;
2566 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_arm64_neon_sqadd>;
2567 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_arm64_neon_sqdmulh>;
2568 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_arm64_neon_sqrdmulh>;
2569 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_arm64_neon_sqrshl>;
2570 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_arm64_neon_sqshl>;
2571 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_arm64_neon_sqsub>;
2572 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_arm64_neon_srshl>;
2573 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_arm64_neon_sshl>;
2574 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2575 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_arm64_neon_uqadd>;
2576 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_arm64_neon_uqrshl>;
2577 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_arm64_neon_uqshl>;
2578 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_arm64_neon_uqsub>;
2579 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_arm64_neon_urshl>;
2580 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_arm64_neon_ushl>;
2582 def : InstAlias<"cmls $dst, $src1, $src2",
2583 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2584 def : InstAlias<"cmle $dst, $src1, $src2",
2585 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2586 def : InstAlias<"cmlo $dst, $src1, $src2",
2587 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2588 def : InstAlias<"cmlt $dst, $src1, $src2",
2589 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2590 def : InstAlias<"fcmle $dst, $src1, $src2",
2591 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2592 def : InstAlias<"fcmle $dst, $src1, $src2",
2593 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2594 def : InstAlias<"fcmlt $dst, $src1, $src2",
2595 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2596 def : InstAlias<"fcmlt $dst, $src1, $src2",
2597 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2598 def : InstAlias<"facle $dst, $src1, $src2",
2599 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2600 def : InstAlias<"facle $dst, $src1, $src2",
2601 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2602 def : InstAlias<"faclt $dst, $src1, $src2",
2603 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2604 def : InstAlias<"faclt $dst, $src1, $src2",
2605 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2607 //===----------------------------------------------------------------------===//
2608 // Advanced SIMD three scalar instructions (mixed operands).
2609 //===----------------------------------------------------------------------===//
2610 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2611 int_arm64_neon_sqdmulls_scalar>;
2612 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2613 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2615 def : Pat<(i64 (int_arm64_neon_sqadd (i64 FPR64:$Rd),
2616 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2617 (i32 FPR32:$Rm))))),
2618 (SQDMLALi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2619 def : Pat<(i64 (int_arm64_neon_sqsub (i64 FPR64:$Rd),
2620 (i64 (int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
2621 (i32 FPR32:$Rm))))),
2622 (SQDMLSLi32 FPR64:$Rd, FPR32:$Rn, FPR32:$Rm)>;
2624 //===----------------------------------------------------------------------===//
2625 // Advanced SIMD two scalar instructions.
2626 //===----------------------------------------------------------------------===//
2628 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_arm64_neon_abs>;
2629 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", ARM64cmeqz>;
2630 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", ARM64cmgez>;
2631 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", ARM64cmgtz>;
2632 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", ARM64cmlez>;
2633 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", ARM64cmltz>;
2634 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2635 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2636 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2637 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2638 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2639 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2640 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2641 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2642 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2643 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2644 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2645 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2646 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2647 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2648 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2649 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2650 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2651 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2652 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2653 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg",
2654 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2655 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", ARM64sitof>;
2656 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2657 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2658 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_arm64_neon_scalar_sqxtn>;
2659 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_arm64_neon_scalar_sqxtun>;
2660 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2661 int_arm64_neon_suqadd>;
2662 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", ARM64uitof>;
2663 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_arm64_neon_scalar_uqxtn>;
2664 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2665 int_arm64_neon_usqadd>;
2667 def : Pat<(v1i64 (int_arm64_neon_fcvtas (v1f64 FPR64:$Rn))),
2668 (FCVTASv1i64 FPR64:$Rn)>;
2669 def : Pat<(v1i64 (int_arm64_neon_fcvtau (v1f64 FPR64:$Rn))),
2670 (FCVTAUv1i64 FPR64:$Rn)>;
2671 def : Pat<(v1i64 (int_arm64_neon_fcvtms (v1f64 FPR64:$Rn))),
2672 (FCVTMSv1i64 FPR64:$Rn)>;
2673 def : Pat<(v1i64 (int_arm64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2674 (FCVTMUv1i64 FPR64:$Rn)>;
2675 def : Pat<(v1i64 (int_arm64_neon_fcvtns (v1f64 FPR64:$Rn))),
2676 (FCVTNSv1i64 FPR64:$Rn)>;
2677 def : Pat<(v1i64 (int_arm64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2678 (FCVTNUv1i64 FPR64:$Rn)>;
2679 def : Pat<(v1i64 (int_arm64_neon_fcvtps (v1f64 FPR64:$Rn))),
2680 (FCVTPSv1i64 FPR64:$Rn)>;
2681 def : Pat<(v1i64 (int_arm64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2682 (FCVTPUv1i64 FPR64:$Rn)>;
2684 def : Pat<(f32 (int_arm64_neon_frecpe (f32 FPR32:$Rn))),
2685 (FRECPEv1i32 FPR32:$Rn)>;
2686 def : Pat<(f64 (int_arm64_neon_frecpe (f64 FPR64:$Rn))),
2687 (FRECPEv1i64 FPR64:$Rn)>;
2688 def : Pat<(v1f64 (int_arm64_neon_frecpe (v1f64 FPR64:$Rn))),
2689 (FRECPEv1i64 FPR64:$Rn)>;
2691 def : Pat<(f32 (int_arm64_neon_frecpx (f32 FPR32:$Rn))),
2692 (FRECPXv1i32 FPR32:$Rn)>;
2693 def : Pat<(f64 (int_arm64_neon_frecpx (f64 FPR64:$Rn))),
2694 (FRECPXv1i64 FPR64:$Rn)>;
2696 def : Pat<(f32 (int_arm64_neon_frsqrte (f32 FPR32:$Rn))),
2697 (FRSQRTEv1i32 FPR32:$Rn)>;
2698 def : Pat<(f64 (int_arm64_neon_frsqrte (f64 FPR64:$Rn))),
2699 (FRSQRTEv1i64 FPR64:$Rn)>;
2700 def : Pat<(v1f64 (int_arm64_neon_frsqrte (v1f64 FPR64:$Rn))),
2701 (FRSQRTEv1i64 FPR64:$Rn)>;
2703 // If an integer is about to be converted to a floating point value,
2704 // just load it on the floating point unit.
2705 // Here are the patterns for 8 and 16-bits to float.
2707 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2708 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2709 (LDRBro ro_indexed8:$addr), bsub))>;
2710 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2711 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2712 (LDRBui am_indexed8:$addr), bsub))>;
2713 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2714 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2715 (LDURBi am_unscaled8:$addr), bsub))>;
2716 // 16-bits -> float.
2717 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2718 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2719 (LDRHro ro_indexed16:$addr), hsub))>;
2720 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2721 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2722 (LDRHui am_indexed16:$addr), hsub))>;
2723 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2724 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2725 (LDURHi am_unscaled16:$addr), hsub))>;
2726 // 32-bits are handled in target specific dag combine:
2727 // performIntToFpCombine.
2728 // 64-bits integer to 32-bits floating point, not possible with
2729 // UCVTF on floating point registers (both source and destination
2730 // must have the same size).
2732 // Here are the patterns for 8, 16, 32, and 64-bits to double.
2733 // 8-bits -> double.
2734 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2735 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2736 (LDRBro ro_indexed8:$addr), bsub))>;
2737 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2738 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2739 (LDRBui am_indexed8:$addr), bsub))>;
2740 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2741 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2742 (LDURBi am_unscaled8:$addr), bsub))>;
2743 // 16-bits -> double.
2744 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2745 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2746 (LDRHro ro_indexed16:$addr), hsub))>;
2747 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2748 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2749 (LDRHui am_indexed16:$addr), hsub))>;
2750 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2751 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2752 (LDURHi am_unscaled16:$addr), hsub))>;
2753 // 32-bits -> double.
2754 def : Pat <(f64 (uint_to_fp (i32 (load ro_indexed32:$addr)))),
2755 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2756 (LDRSro ro_indexed32:$addr), ssub))>;
2757 def : Pat <(f64 (uint_to_fp (i32 (load am_indexed32:$addr)))),
2758 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2759 (LDRSui am_indexed32:$addr), ssub))>;
2760 def : Pat <(f64 (uint_to_fp (i32 (load am_unscaled32:$addr)))),
2761 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2762 (LDURSi am_unscaled32:$addr), ssub))>;
2763 // 64-bits -> double are handled in target specific dag combine:
2764 // performIntToFpCombine.
2766 //===----------------------------------------------------------------------===//
2767 // Advanced SIMD three different-sized vector instructions.
2768 //===----------------------------------------------------------------------===//
2770 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_arm64_neon_addhn>;
2771 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_arm64_neon_subhn>;
2772 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_arm64_neon_raddhn>;
2773 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_arm64_neon_rsubhn>;
2774 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_arm64_neon_pmull>;
2775 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
2776 int_arm64_neon_sabd>;
2777 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
2778 int_arm64_neon_sabd>;
2779 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
2780 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
2781 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
2782 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
2783 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
2784 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2785 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
2786 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2787 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_arm64_neon_smull>;
2788 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
2789 int_arm64_neon_sqadd>;
2790 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
2791 int_arm64_neon_sqsub>;
2792 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
2793 int_arm64_neon_sqdmull>;
2794 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
2795 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
2796 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
2797 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
2798 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
2799 int_arm64_neon_uabd>;
2800 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
2801 int_arm64_neon_uabd>;
2802 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
2803 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
2804 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
2805 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
2806 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
2807 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2808 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
2809 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2810 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_arm64_neon_umull>;
2811 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
2812 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
2813 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
2814 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
2816 // Patterns for 64-bit pmull
2817 def : Pat<(int_arm64_neon_pmull64 V64:$Rn, V64:$Rm),
2818 (PMULLv1i64 V64:$Rn, V64:$Rm)>;
2819 def : Pat<(int_arm64_neon_pmull64 (vector_extract (v2i64 V128:$Rn), (i64 1)),
2820 (vector_extract (v2i64 V128:$Rm), (i64 1))),
2821 (PMULLv2i64 V128:$Rn, V128:$Rm)>;
2823 // CodeGen patterns for addhn and subhn instructions, which can actually be
2824 // written in LLVM IR without too much difficulty.
2827 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
2828 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2829 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2831 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2832 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2834 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2835 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2836 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2838 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2839 V128:$Rn, V128:$Rm)>;
2840 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2841 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2843 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2844 V128:$Rn, V128:$Rm)>;
2845 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2846 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2848 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2849 V128:$Rn, V128:$Rm)>;
2852 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
2853 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2854 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2856 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2857 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2859 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2860 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2861 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2863 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2864 V128:$Rn, V128:$Rm)>;
2865 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2866 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2868 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2869 V128:$Rn, V128:$Rm)>;
2870 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2871 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2873 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2874 V128:$Rn, V128:$Rm)>;
2876 //----------------------------------------------------------------------------
2877 // AdvSIMD bitwise extract from vector instruction.
2878 //----------------------------------------------------------------------------
2880 defm EXT : SIMDBitwiseExtract<"ext">;
2882 def : Pat<(v4i16 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2883 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2884 def : Pat<(v8i16 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2885 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2886 def : Pat<(v2i32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2887 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2888 def : Pat<(v2f32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2889 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2890 def : Pat<(v4i32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2891 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2892 def : Pat<(v4f32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2893 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2894 def : Pat<(v2i64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2895 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2896 def : Pat<(v2f64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2897 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2899 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
2901 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
2902 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2903 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
2904 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2905 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
2906 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2907 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
2908 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2909 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
2910 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2911 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
2912 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2915 //----------------------------------------------------------------------------
2916 // AdvSIMD zip vector
2917 //----------------------------------------------------------------------------
2919 defm TRN1 : SIMDZipVector<0b010, "trn1", ARM64trn1>;
2920 defm TRN2 : SIMDZipVector<0b110, "trn2", ARM64trn2>;
2921 defm UZP1 : SIMDZipVector<0b001, "uzp1", ARM64uzp1>;
2922 defm UZP2 : SIMDZipVector<0b101, "uzp2", ARM64uzp2>;
2923 defm ZIP1 : SIMDZipVector<0b011, "zip1", ARM64zip1>;
2924 defm ZIP2 : SIMDZipVector<0b111, "zip2", ARM64zip2>;
2926 //----------------------------------------------------------------------------
2927 // AdvSIMD TBL/TBX instructions
2928 //----------------------------------------------------------------------------
2930 defm TBL : SIMDTableLookup< 0, "tbl">;
2931 defm TBX : SIMDTableLookupTied<1, "tbx">;
2933 def : Pat<(v8i8 (int_arm64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
2934 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
2935 def : Pat<(v16i8 (int_arm64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
2936 (TBLv16i8One V128:$Ri, V128:$Rn)>;
2938 def : Pat<(v8i8 (int_arm64_neon_tbx1 (v8i8 V64:$Rd),
2939 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
2940 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
2941 def : Pat<(v16i8 (int_arm64_neon_tbx1 (v16i8 V128:$Rd),
2942 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
2943 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
2946 //----------------------------------------------------------------------------
2947 // AdvSIMD scalar CPY instruction
2948 //----------------------------------------------------------------------------
2950 defm CPY : SIMDScalarCPY<"cpy">;
2952 //----------------------------------------------------------------------------
2953 // AdvSIMD scalar pairwise instructions
2954 //----------------------------------------------------------------------------
2956 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
2957 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
2958 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
2959 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
2960 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
2961 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
2962 def : Pat<(i64 (int_arm64_neon_saddv (v2i64 V128:$Rn))),
2963 (ADDPv2i64p V128:$Rn)>;
2964 def : Pat<(i64 (int_arm64_neon_uaddv (v2i64 V128:$Rn))),
2965 (ADDPv2i64p V128:$Rn)>;
2966 def : Pat<(f32 (int_arm64_neon_faddv (v2f32 V64:$Rn))),
2967 (FADDPv2i32p V64:$Rn)>;
2968 def : Pat<(f32 (int_arm64_neon_faddv (v4f32 V128:$Rn))),
2969 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
2970 def : Pat<(f64 (int_arm64_neon_faddv (v2f64 V128:$Rn))),
2971 (FADDPv2i64p V128:$Rn)>;
2972 def : Pat<(f32 (int_arm64_neon_fmaxnmv (v2f32 V64:$Rn))),
2973 (FMAXNMPv2i32p V64:$Rn)>;
2974 def : Pat<(f64 (int_arm64_neon_fmaxnmv (v2f64 V128:$Rn))),
2975 (FMAXNMPv2i64p V128:$Rn)>;
2976 def : Pat<(f32 (int_arm64_neon_fmaxv (v2f32 V64:$Rn))),
2977 (FMAXPv2i32p V64:$Rn)>;
2978 def : Pat<(f64 (int_arm64_neon_fmaxv (v2f64 V128:$Rn))),
2979 (FMAXPv2i64p V128:$Rn)>;
2980 def : Pat<(f32 (int_arm64_neon_fminnmv (v2f32 V64:$Rn))),
2981 (FMINNMPv2i32p V64:$Rn)>;
2982 def : Pat<(f64 (int_arm64_neon_fminnmv (v2f64 V128:$Rn))),
2983 (FMINNMPv2i64p V128:$Rn)>;
2984 def : Pat<(f32 (int_arm64_neon_fminv (v2f32 V64:$Rn))),
2985 (FMINPv2i32p V64:$Rn)>;
2986 def : Pat<(f64 (int_arm64_neon_fminv (v2f64 V128:$Rn))),
2987 (FMINPv2i64p V128:$Rn)>;
2989 //----------------------------------------------------------------------------
2990 // AdvSIMD INS/DUP instructions
2991 //----------------------------------------------------------------------------
2993 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
2994 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
2995 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
2996 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
2997 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
2998 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
2999 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
3001 def DUPv2i64lane : SIMDDup64FromElement;
3002 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
3003 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
3004 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
3005 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
3006 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
3007 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
3009 def : Pat<(v2f32 (ARM64dup (f32 FPR32:$Rn))),
3010 (v2f32 (DUPv2i32lane
3011 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3013 def : Pat<(v4f32 (ARM64dup (f32 FPR32:$Rn))),
3014 (v4f32 (DUPv4i32lane
3015 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
3017 def : Pat<(v2f64 (ARM64dup (f64 FPR64:$Rn))),
3018 (v2f64 (DUPv2i64lane
3019 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
3022 def : Pat<(v2f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3023 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
3024 def : Pat<(v4f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
3025 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
3026 def : Pat<(v2f64 (ARM64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
3027 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
3029 // If there's an (ARM64dup (vector_extract ...) ...), we can use a duplane
3030 // instruction even if the types don't match: we just have to remap the lane
3031 // carefully. N.b. this trick only applies to truncations.
3032 def VecIndex_x2 : SDNodeXForm<imm, [{
3033 return CurDAG->getTargetConstant(2 * N->getZExtValue(), MVT::i64);
3035 def VecIndex_x4 : SDNodeXForm<imm, [{
3036 return CurDAG->getTargetConstant(4 * N->getZExtValue(), MVT::i64);
3038 def VecIndex_x8 : SDNodeXForm<imm, [{
3039 return CurDAG->getTargetConstant(8 * N->getZExtValue(), MVT::i64);
3042 multiclass DUPWithTruncPats<ValueType ResVT, ValueType Src64VT,
3043 ValueType Src128VT, ValueType ScalVT,
3044 Instruction DUP, SDNodeXForm IdxXFORM> {
3045 def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src128VT V128:$Rn),
3047 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3049 def : Pat<(ResVT (ARM64dup (ScalVT (vector_extract (Src64VT V64:$Rn),
3051 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3054 defm : DUPWithTruncPats<v8i8, v4i16, v8i16, i32, DUPv8i8lane, VecIndex_x2>;
3055 defm : DUPWithTruncPats<v8i8, v2i32, v4i32, i32, DUPv8i8lane, VecIndex_x4>;
3056 defm : DUPWithTruncPats<v4i16, v2i32, v4i32, i32, DUPv4i16lane, VecIndex_x2>;
3058 defm : DUPWithTruncPats<v16i8, v4i16, v8i16, i32, DUPv16i8lane, VecIndex_x2>;
3059 defm : DUPWithTruncPats<v16i8, v2i32, v4i32, i32, DUPv16i8lane, VecIndex_x4>;
3060 defm : DUPWithTruncPats<v8i16, v2i32, v4i32, i32, DUPv8i16lane, VecIndex_x2>;
3062 multiclass DUPWithTrunci64Pats<ValueType ResVT, Instruction DUP,
3063 SDNodeXForm IdxXFORM> {
3064 def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v2i64 V128:$Rn),
3066 (DUP V128:$Rn, (IdxXFORM imm:$idx))>;
3068 def : Pat<(ResVT (ARM64dup (i32 (trunc (vector_extract (v1i64 V64:$Rn),
3070 (DUP (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), (IdxXFORM imm:$idx))>;
3073 defm : DUPWithTrunci64Pats<v8i8, DUPv8i8lane, VecIndex_x8>;
3074 defm : DUPWithTrunci64Pats<v4i16, DUPv4i16lane, VecIndex_x4>;
3075 defm : DUPWithTrunci64Pats<v2i32, DUPv2i32lane, VecIndex_x2>;
3077 defm : DUPWithTrunci64Pats<v16i8, DUPv16i8lane, VecIndex_x8>;
3078 defm : DUPWithTrunci64Pats<v8i16, DUPv8i16lane, VecIndex_x4>;
3079 defm : DUPWithTrunci64Pats<v4i32, DUPv4i32lane, VecIndex_x2>;
3081 // SMOV and UMOV definitions, with some extra patterns for convenience
3085 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3086 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
3087 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
3088 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
3089 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3090 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3091 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3092 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
3093 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
3094 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
3095 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
3096 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
3098 // Extracting i8 or i16 elements will have the zero-extend transformed to
3099 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
3100 // for ARM64. Match these patterns here since UMOV already zeroes out the high
3101 // bits of the destination register.
3102 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
3104 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
3105 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
3107 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
3111 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
3112 (SUBREG_TO_REG (i32 0),
3113 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3114 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
3115 (SUBREG_TO_REG (i32 0),
3116 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3118 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
3119 (SUBREG_TO_REG (i32 0),
3120 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3121 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
3122 (SUBREG_TO_REG (i32 0),
3123 (f32 (COPY_TO_REGCLASS GPR32:$Rn, FPR32)), ssub)>;
3125 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
3126 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
3127 (i32 FPR32:$Rn), ssub))>;
3128 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
3129 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
3130 (i32 FPR32:$Rn), ssub))>;
3131 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
3132 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
3133 (i64 FPR64:$Rn), dsub))>;
3135 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
3136 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3137 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
3138 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
3139 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
3140 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
3142 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
3143 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3146 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
3148 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3151 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
3152 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
3154 V128:$Rn, VectorIndexS:$imm,
3155 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
3157 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
3158 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
3160 V128:$Rn, VectorIndexD:$imm,
3161 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
3164 // Copy an element at a constant index in one vector into a constant indexed
3165 // element of another.
3166 // FIXME refactor to a shared class/dev parameterized on vector type, vector
3167 // index type and INS extension
3168 def : Pat<(v16i8 (int_arm64_neon_vcopy_lane
3169 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3170 VectorIndexB:$idx2)),
3172 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3174 def : Pat<(v8i16 (int_arm64_neon_vcopy_lane
3175 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3176 VectorIndexH:$idx2)),
3178 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3180 def : Pat<(v4i32 (int_arm64_neon_vcopy_lane
3181 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3182 VectorIndexS:$idx2)),
3184 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
3186 def : Pat<(v2i64 (int_arm64_neon_vcopy_lane
3187 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
3188 VectorIndexD:$idx2)),
3190 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3193 multiclass Neon_INS_elt_pattern<ValueType VT128, ValueType VT64,
3194 ValueType VTScal, Instruction INS> {
3195 def : Pat<(VT128 (vector_insert V128:$src,
3196 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3198 (INS V128:$src, imm:$Immd, V128:$Rn, imm:$Immn)>;
3200 def : Pat<(VT128 (vector_insert V128:$src,
3201 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3203 (INS V128:$src, imm:$Immd,
3204 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn)>;
3206 def : Pat<(VT64 (vector_insert V64:$src,
3207 (VTScal (vector_extract (VT128 V128:$Rn), imm:$Immn)),
3209 (EXTRACT_SUBREG (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub),
3210 imm:$Immd, V128:$Rn, imm:$Immn),
3213 def : Pat<(VT64 (vector_insert V64:$src,
3214 (VTScal (vector_extract (VT64 V64:$Rn), imm:$Immn)),
3217 (INS (SUBREG_TO_REG (i64 0), V64:$src, dsub), imm:$Immd,
3218 (SUBREG_TO_REG (i64 0), V64:$Rn, dsub), imm:$Immn),
3222 defm : Neon_INS_elt_pattern<v4f32, v2f32, f32, INSvi32lane>;
3223 defm : Neon_INS_elt_pattern<v2f64, v1f64, f64, INSvi64lane>;
3224 defm : Neon_INS_elt_pattern<v16i8, v8i8, i32, INSvi8lane>;
3225 defm : Neon_INS_elt_pattern<v8i16, v4i16, i32, INSvi16lane>;
3226 defm : Neon_INS_elt_pattern<v4i32, v2i32, i32, INSvi32lane>;
3227 defm : Neon_INS_elt_pattern<v2i64, v1i64, i64, INSvi32lane>;
3230 // Floating point vector extractions are codegen'd as either a sequence of
3231 // subregister extractions, possibly fed by an INS if the lane number is
3232 // anything other than zero.
3233 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3234 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3235 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3236 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3237 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3238 (f64 (EXTRACT_SUBREG
3239 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3240 V128:$Rn, VectorIndexD:$idx),
3242 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3243 (f32 (EXTRACT_SUBREG
3244 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3245 V128:$Rn, VectorIndexS:$idx),
3248 // All concat_vectors operations are canonicalised to act on i64 vectors for
3249 // ARM64. In the general case we need an instruction, which had just as well be
3251 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3252 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3253 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3254 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3256 def : ConcatPat<v2i64, v1i64>;
3257 def : ConcatPat<v2f64, v1f64>;
3258 def : ConcatPat<v4i32, v2i32>;
3259 def : ConcatPat<v4f32, v2f32>;
3260 def : ConcatPat<v8i16, v4i16>;
3261 def : ConcatPat<v16i8, v8i8>;
3263 // If the high lanes are undef, though, we can just ignore them:
3264 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3265 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3266 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3268 def : ConcatUndefPat<v2i64, v1i64>;
3269 def : ConcatUndefPat<v2f64, v1f64>;
3270 def : ConcatUndefPat<v4i32, v2i32>;
3271 def : ConcatUndefPat<v4f32, v2f32>;
3272 def : ConcatUndefPat<v8i16, v4i16>;
3273 def : ConcatUndefPat<v16i8, v8i8>;
3275 //----------------------------------------------------------------------------
3276 // AdvSIMD across lanes instructions
3277 //----------------------------------------------------------------------------
3279 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3280 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3281 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3282 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3283 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3284 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3285 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3286 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_arm64_neon_fmaxnmv>;
3287 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_arm64_neon_fmaxv>;
3288 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_arm64_neon_fminnmv>;
3289 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_arm64_neon_fminv>;
3291 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3292 // If there is a sign extension after this intrinsic, consume it as smov already
3294 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3296 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3297 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3299 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3301 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3302 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3304 // If there is a sign extension after this intrinsic, consume it as smov already
3306 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3308 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3309 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3311 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3313 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3314 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3316 // If there is a sign extension after this intrinsic, consume it as smov already
3318 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3320 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3321 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3323 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3325 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3326 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3328 // If there is a sign extension after this intrinsic, consume it as smov already
3330 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3332 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3333 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3335 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3337 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3338 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3341 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3342 (i32 (EXTRACT_SUBREG
3343 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3344 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3348 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3349 // If there is a masking operation keeping only what has been actually
3350 // generated, consume it.
3351 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3352 (i32 (EXTRACT_SUBREG
3353 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3354 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3356 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3357 (i32 (EXTRACT_SUBREG
3358 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3359 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3361 // If there is a masking operation keeping only what has been actually
3362 // generated, consume it.
3363 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3364 (i32 (EXTRACT_SUBREG
3365 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3366 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3368 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3369 (i32 (EXTRACT_SUBREG
3370 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3371 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3374 // If there is a masking operation keeping only what has been actually
3375 // generated, consume it.
3376 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3377 (i32 (EXTRACT_SUBREG
3378 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3379 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3381 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3382 (i32 (EXTRACT_SUBREG
3383 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3384 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3386 // If there is a masking operation keeping only what has been actually
3387 // generated, consume it.
3388 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3389 (i32 (EXTRACT_SUBREG
3390 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3391 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3393 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3394 (i32 (EXTRACT_SUBREG
3395 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3396 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3399 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3400 (i32 (EXTRACT_SUBREG
3401 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3402 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3407 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3408 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3410 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3411 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3413 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3415 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3416 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3419 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3420 (i32 (EXTRACT_SUBREG
3421 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3422 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3424 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3425 (i32 (EXTRACT_SUBREG
3426 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3427 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3430 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3431 (i64 (EXTRACT_SUBREG
3432 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3433 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3437 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3439 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3440 (i32 (EXTRACT_SUBREG
3441 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3442 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3444 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3445 (i32 (EXTRACT_SUBREG
3446 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3447 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3450 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3451 (i32 (EXTRACT_SUBREG
3452 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3453 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3455 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3456 (i32 (EXTRACT_SUBREG
3457 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3458 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3461 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3462 (i64 (EXTRACT_SUBREG
3463 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3464 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3468 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_arm64_neon_saddv>;
3469 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3470 def : Pat<(i32 (int_arm64_neon_saddv (v2i32 V64:$Rn))),
3471 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3473 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_arm64_neon_uaddv>;
3474 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3475 def : Pat<(i32 (int_arm64_neon_uaddv (v2i32 V64:$Rn))),
3476 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3478 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_arm64_neon_smaxv>;
3479 def : Pat<(i32 (int_arm64_neon_smaxv (v2i32 V64:$Rn))),
3480 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3482 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_arm64_neon_sminv>;
3483 def : Pat<(i32 (int_arm64_neon_sminv (v2i32 V64:$Rn))),
3484 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3486 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_arm64_neon_umaxv>;
3487 def : Pat<(i32 (int_arm64_neon_umaxv (v2i32 V64:$Rn))),
3488 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3490 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_arm64_neon_uminv>;
3491 def : Pat<(i32 (int_arm64_neon_uminv (v2i32 V64:$Rn))),
3492 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3494 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_arm64_neon_saddlv>;
3495 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_arm64_neon_uaddlv>;
3497 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3498 def : Pat<(i64 (int_arm64_neon_saddlv (v2i32 V64:$Rn))),
3499 (i64 (EXTRACT_SUBREG
3500 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3501 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3503 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3504 def : Pat<(i64 (int_arm64_neon_uaddlv (v2i32 V64:$Rn))),
3505 (i64 (EXTRACT_SUBREG
3506 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3507 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3510 //------------------------------------------------------------------------------
3511 // AdvSIMD modified immediate instructions
3512 //------------------------------------------------------------------------------
3515 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", ARM64bici>;
3517 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", ARM64orri>;
3521 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3523 [(set (v2f64 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3524 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3526 [(set (v2f32 V64:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3527 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3529 [(set (v4f32 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3533 // EDIT byte mask: scalar
3534 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3535 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3536 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3537 // The movi_edit node has the immediate value already encoded, so we use
3538 // a plain imm0_255 here.
3539 def : Pat<(f64 (ARM64movi_edit imm0_255:$shift)),
3540 (MOVID imm0_255:$shift)>;
3542 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3543 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3544 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3545 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3547 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3548 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3549 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3550 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3552 // EDIT byte mask: 2d
3554 // The movi_edit node has the immediate value already encoded, so we use
3555 // a plain imm0_255 in the pattern
3556 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3557 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3560 [(set (v2i64 V128:$Rd), (ARM64movi_edit imm0_255:$imm8))]>;
3563 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3564 // Complexity is added to break a tie with a plain MOVI.
3565 let AddedComplexity = 1 in {
3566 def : Pat<(f32 fpimm0),
3567 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3569 def : Pat<(f64 fpimm0),
3570 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3574 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3575 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3576 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3577 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3579 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3580 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3581 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3582 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3584 def : Pat<(v2f64 (ARM64dup (f64 fpimm0))), (MOVIv2d_ns (i32 0))>;
3585 def : Pat<(v4f32 (ARM64dup (f32 fpimm0))), (MOVIv2d_ns (i32 0))>;
3587 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3588 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3589 def : Pat<(v2i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3590 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
3591 def : Pat<(v4i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3592 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
3593 def : Pat<(v4i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3594 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
3595 def : Pat<(v8i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3596 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
3598 // EDIT per word: 2s & 4s with MSL shifter
3599 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
3600 [(set (v2i32 V64:$Rd),
3601 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3602 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
3603 [(set (v4i32 V128:$Rd),
3604 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3606 // Per byte: 8b & 16b
3607 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
3609 [(set (v8i8 V64:$Rd), (ARM64movi imm0_255:$imm8))]>;
3610 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
3612 [(set (v16i8 V128:$Rd), (ARM64movi imm0_255:$imm8))]>;
3616 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3617 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
3618 def : Pat<(v2i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3619 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
3620 def : Pat<(v4i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3621 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
3622 def : Pat<(v4i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3623 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
3624 def : Pat<(v8i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3625 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
3627 // EDIT per word: 2s & 4s with MSL shifter
3628 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
3629 [(set (v2i32 V64:$Rd),
3630 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3631 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
3632 [(set (v4i32 V128:$Rd),
3633 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3635 //----------------------------------------------------------------------------
3636 // AdvSIMD indexed element
3637 //----------------------------------------------------------------------------
3639 let neverHasSideEffects = 1 in {
3640 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
3641 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
3644 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
3645 // instruction expects the addend first, while the intrinsic expects it last.
3647 // On the other hand, there are quite a few valid combinatorial options due to
3648 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
3649 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3650 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
3651 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3652 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
3654 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3655 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
3656 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3657 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
3658 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3659 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
3660 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3661 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
3663 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
3664 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3666 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3667 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3668 VectorIndexS:$idx))),
3669 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3670 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3671 (v2f32 (ARM64duplane32
3672 (v4f32 (insert_subvector undef,
3673 (v2f32 (fneg V64:$Rm)),
3675 VectorIndexS:$idx)))),
3676 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3677 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3678 VectorIndexS:$idx)>;
3679 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3680 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3681 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3682 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3684 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3686 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3687 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3688 VectorIndexS:$idx))),
3689 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
3690 VectorIndexS:$idx)>;
3691 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3692 (v4f32 (ARM64duplane32
3693 (v4f32 (insert_subvector undef,
3694 (v2f32 (fneg V64:$Rm)),
3696 VectorIndexS:$idx)))),
3697 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3698 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3699 VectorIndexS:$idx)>;
3700 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3701 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3702 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3703 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3705 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
3706 // (DUPLANE from 64-bit would be trivial).
3707 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3708 (ARM64duplane64 (v2f64 (fneg V128:$Rm)),
3709 VectorIndexD:$idx))),
3711 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3712 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3713 (ARM64dup (f64 (fneg FPR64Op:$Rm))))),
3714 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
3715 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
3717 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
3718 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3719 (vector_extract (v4f32 (fneg V128:$Rm)),
3720 VectorIndexS:$idx))),
3721 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3722 V128:$Rm, VectorIndexS:$idx)>;
3723 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3724 (vector_extract (v2f32 (fneg V64:$Rm)),
3725 VectorIndexS:$idx))),
3726 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3727 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
3729 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
3730 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
3731 (vector_extract (v2f64 (fneg V128:$Rm)),
3732 VectorIndexS:$idx))),
3733 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
3734 V128:$Rm, VectorIndexS:$idx)>;
3737 defm : FMLSIndexedAfterNegPatterns<
3738 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
3739 defm : FMLSIndexedAfterNegPatterns<
3740 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
3742 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_arm64_neon_fmulx>;
3743 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
3745 def : Pat<(v2f32 (fmul V64:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3746 (FMULv2i32_indexed V64:$Rn,
3747 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3749 def : Pat<(v4f32 (fmul V128:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3750 (FMULv4i32_indexed V128:$Rn,
3751 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3753 def : Pat<(v2f64 (fmul V128:$Rn, (ARM64dup (f64 FPR64:$Rm)))),
3754 (FMULv2i64_indexed V128:$Rn,
3755 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
3758 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_arm64_neon_sqdmulh>;
3759 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_arm64_neon_sqrdmulh>;
3760 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
3761 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
3762 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
3763 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
3764 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
3765 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
3766 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3767 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
3768 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3769 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
3770 int_arm64_neon_smull>;
3771 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
3772 int_arm64_neon_sqadd>;
3773 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
3774 int_arm64_neon_sqsub>;
3775 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_arm64_neon_sqdmull>;
3776 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
3777 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3778 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
3779 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3780 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
3781 int_arm64_neon_umull>;
3783 // A scalar sqdmull with the second operand being a vector lane can be
3784 // handled directly with the indexed instruction encoding.
3785 def : Pat<(int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3786 (vector_extract (v4i32 V128:$Vm),
3787 VectorIndexS:$idx)),
3788 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
3790 //----------------------------------------------------------------------------
3791 // AdvSIMD scalar shift instructions
3792 //----------------------------------------------------------------------------
3793 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
3794 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
3795 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
3796 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
3797 // Codegen patterns for the above. We don't put these directly on the
3798 // instructions because TableGen's type inference can't handle the truth.
3799 // Having the same base pattern for fp <--> int totally freaks it out.
3800 def : Pat<(int_arm64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
3801 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
3802 def : Pat<(int_arm64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
3803 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
3804 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
3805 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3806 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
3807 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3808 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
3810 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3811 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
3813 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3814 def : Pat<(int_arm64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
3815 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3816 def : Pat<(int_arm64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
3817 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3818 def : Pat<(f64 (int_arm64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3819 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3820 def : Pat<(f64 (int_arm64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3821 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3822 def : Pat<(v1f64 (int_arm64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
3824 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3825 def : Pat<(v1f64 (int_arm64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
3827 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3829 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", ARM64vshl>;
3830 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
3831 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
3832 int_arm64_neon_sqrshrn>;
3833 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
3834 int_arm64_neon_sqrshrun>;
3835 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3836 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3837 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
3838 int_arm64_neon_sqshrn>;
3839 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
3840 int_arm64_neon_sqshrun>;
3841 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
3842 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", ARM64srshri>;
3843 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
3844 TriOpFrag<(add node:$LHS,
3845 (ARM64srshri node:$MHS, node:$RHS))>>;
3846 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", ARM64vashr>;
3847 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
3848 TriOpFrag<(add node:$LHS,
3849 (ARM64vashr node:$MHS, node:$RHS))>>;
3850 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
3851 int_arm64_neon_uqrshrn>;
3852 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3853 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
3854 int_arm64_neon_uqshrn>;
3855 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", ARM64urshri>;
3856 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
3857 TriOpFrag<(add node:$LHS,
3858 (ARM64urshri node:$MHS, node:$RHS))>>;
3859 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", ARM64vlshr>;
3860 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
3861 TriOpFrag<(add node:$LHS,
3862 (ARM64vlshr node:$MHS, node:$RHS))>>;
3864 //----------------------------------------------------------------------------
3865 // AdvSIMD vector shift instructions
3866 //----------------------------------------------------------------------------
3867 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_arm64_neon_vcvtfp2fxs>;
3868 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_arm64_neon_vcvtfp2fxu>;
3869 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
3870 int_arm64_neon_vcvtfxs2fp>;
3871 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
3872 int_arm64_neon_rshrn>;
3873 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", ARM64vshl>;
3874 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
3875 BinOpFrag<(trunc (ARM64vashr node:$LHS, node:$RHS))>>;
3876 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_arm64_neon_vsli>;
3877 def : Pat<(v1i64 (int_arm64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3878 (i32 vecshiftL64:$imm))),
3879 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
3880 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
3881 int_arm64_neon_sqrshrn>;
3882 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
3883 int_arm64_neon_sqrshrun>;
3884 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3885 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3886 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
3887 int_arm64_neon_sqshrn>;
3888 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
3889 int_arm64_neon_sqshrun>;
3890 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_arm64_neon_vsri>;
3891 def : Pat<(v1i64 (int_arm64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3892 (i32 vecshiftR64:$imm))),
3893 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
3894 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", ARM64srshri>;
3895 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
3896 TriOpFrag<(add node:$LHS,
3897 (ARM64srshri node:$MHS, node:$RHS))> >;
3898 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
3899 BinOpFrag<(ARM64vshl (sext node:$LHS), node:$RHS)>>;
3901 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", ARM64vashr>;
3902 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
3903 TriOpFrag<(add node:$LHS, (ARM64vashr node:$MHS, node:$RHS))>>;
3904 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
3905 int_arm64_neon_vcvtfxu2fp>;
3906 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
3907 int_arm64_neon_uqrshrn>;
3908 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3909 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
3910 int_arm64_neon_uqshrn>;
3911 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", ARM64urshri>;
3912 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
3913 TriOpFrag<(add node:$LHS,
3914 (ARM64urshri node:$MHS, node:$RHS))> >;
3915 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
3916 BinOpFrag<(ARM64vshl (zext node:$LHS), node:$RHS)>>;
3917 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", ARM64vlshr>;
3918 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
3919 TriOpFrag<(add node:$LHS, (ARM64vlshr node:$MHS, node:$RHS))> >;
3921 // SHRN patterns for when a logical right shift was used instead of arithmetic
3922 // (the immediate guarantees no sign bits actually end up in the result so it
3924 def : Pat<(v8i8 (trunc (ARM64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
3925 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
3926 def : Pat<(v4i16 (trunc (ARM64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
3927 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
3928 def : Pat<(v2i32 (trunc (ARM64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
3929 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
3931 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
3932 (trunc (ARM64vlshr (v8i16 V128:$Rn),
3933 vecshiftR16Narrow:$imm)))),
3934 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3935 V128:$Rn, vecshiftR16Narrow:$imm)>;
3936 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
3937 (trunc (ARM64vlshr (v4i32 V128:$Rn),
3938 vecshiftR32Narrow:$imm)))),
3939 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3940 V128:$Rn, vecshiftR32Narrow:$imm)>;
3941 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
3942 (trunc (ARM64vlshr (v2i64 V128:$Rn),
3943 vecshiftR64Narrow:$imm)))),
3944 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3945 V128:$Rn, vecshiftR32Narrow:$imm)>;
3947 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
3948 // Anyexts are implemented as zexts.
3949 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
3950 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
3951 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
3952 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
3953 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
3954 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
3955 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
3956 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
3957 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
3958 // Also match an extend from the upper half of a 128 bit source register.
3959 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3960 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
3961 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3962 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
3963 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3964 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
3965 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3966 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
3967 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3968 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
3969 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3970 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
3971 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3972 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
3973 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3974 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
3975 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3976 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
3978 // Vector shift sxtl aliases
3979 def : InstAlias<"sxtl.8h $dst, $src1",
3980 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3981 def : InstAlias<"sxtl $dst.8h, $src1.8b",
3982 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3983 def : InstAlias<"sxtl.4s $dst, $src1",
3984 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3985 def : InstAlias<"sxtl $dst.4s, $src1.4h",
3986 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3987 def : InstAlias<"sxtl.2d $dst, $src1",
3988 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3989 def : InstAlias<"sxtl $dst.2d, $src1.2s",
3990 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3992 // Vector shift sxtl2 aliases
3993 def : InstAlias<"sxtl2.8h $dst, $src1",
3994 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3995 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
3996 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3997 def : InstAlias<"sxtl2.4s $dst, $src1",
3998 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3999 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
4000 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4001 def : InstAlias<"sxtl2.2d $dst, $src1",
4002 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4003 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
4004 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4006 // Vector shift uxtl aliases
4007 def : InstAlias<"uxtl.8h $dst, $src1",
4008 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4009 def : InstAlias<"uxtl $dst.8h, $src1.8b",
4010 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
4011 def : InstAlias<"uxtl.4s $dst, $src1",
4012 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4013 def : InstAlias<"uxtl $dst.4s, $src1.4h",
4014 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
4015 def : InstAlias<"uxtl.2d $dst, $src1",
4016 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4017 def : InstAlias<"uxtl $dst.2d, $src1.2s",
4018 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
4020 // Vector shift uxtl2 aliases
4021 def : InstAlias<"uxtl2.8h $dst, $src1",
4022 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4023 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
4024 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
4025 def : InstAlias<"uxtl2.4s $dst, $src1",
4026 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4027 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
4028 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
4029 def : InstAlias<"uxtl2.2d $dst, $src1",
4030 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4031 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
4032 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
4034 // If an integer is about to be converted to a floating point value,
4035 // just load it on the floating point unit.
4036 // These patterns are more complex because floating point loads do not
4037 // support sign extension.
4038 // The sign extension has to be explicitly added and is only supported for
4039 // one step: byte-to-half, half-to-word, word-to-doubleword.
4040 // SCVTF GPR -> FPR is 9 cycles.
4041 // SCVTF FPR -> FPR is 4 cyclces.
4042 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
4043 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
4044 // and still being faster.
4045 // However, this is not good for code size.
4046 // 8-bits -> float. 2 sizes step-up.
4047 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 ro_indexed8:$addr)))),
4048 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4053 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4054 (LDRBro ro_indexed8:$addr),
4059 ssub)))>, Requires<[NotForCodeSize]>;
4060 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_indexed8:$addr)))),
4061 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4066 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4067 (LDRBui am_indexed8:$addr),
4072 ssub)))>, Requires<[NotForCodeSize]>;
4073 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_unscaled8:$addr)))),
4074 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4079 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4080 (LDURBi am_unscaled8:$addr),
4085 ssub)))>, Requires<[NotForCodeSize]>;
4086 // 16-bits -> float. 1 size step-up.
4087 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
4088 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4090 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4091 (LDRHro ro_indexed16:$addr),
4094 ssub)))>, Requires<[NotForCodeSize]>;
4095 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
4096 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4098 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4099 (LDRHui am_indexed16:$addr),
4102 ssub)))>, Requires<[NotForCodeSize]>;
4103 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
4104 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
4106 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4107 (LDURHi am_unscaled16:$addr),
4110 ssub)))>, Requires<[NotForCodeSize]>;
4111 // 32-bits to 32-bits are handled in target specific dag combine:
4112 // performIntToFpCombine.
4113 // 64-bits integer to 32-bits floating point, not possible with
4114 // SCVTF on floating point registers (both source and destination
4115 // must have the same size).
4117 // Here are the patterns for 8, 16, 32, and 64-bits to double.
4118 // 8-bits -> double. 3 size step-up: give up.
4119 // 16-bits -> double. 2 size step.
4120 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
4121 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4126 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4127 (LDRHro ro_indexed16:$addr),
4132 dsub)))>, Requires<[NotForCodeSize]>;
4133 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
4134 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4139 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4140 (LDRHui am_indexed16:$addr),
4145 dsub)))>, Requires<[NotForCodeSize]>;
4146 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
4147 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4152 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4153 (LDURHi am_unscaled16:$addr),
4158 dsub)))>, Requires<[NotForCodeSize]>;
4159 // 32-bits -> double. 1 size step-up.
4160 def : Pat <(f64 (sint_to_fp (i32 (load ro_indexed32:$addr)))),
4161 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4163 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4164 (LDRSro ro_indexed32:$addr),
4167 dsub)))>, Requires<[NotForCodeSize]>;
4168 def : Pat <(f64 (sint_to_fp (i32 (load am_indexed32:$addr)))),
4169 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4171 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4172 (LDRSui am_indexed32:$addr),
4175 dsub)))>, Requires<[NotForCodeSize]>;
4176 def : Pat <(f64 (sint_to_fp (i32 (load am_unscaled32:$addr)))),
4177 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
4179 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
4180 (LDURSi am_unscaled32:$addr),
4183 dsub)))>, Requires<[NotForCodeSize]>;
4184 // 64-bits -> double are handled in target specific dag combine:
4185 // performIntToFpCombine.
4188 //----------------------------------------------------------------------------
4189 // AdvSIMD Load-Store Structure
4190 //----------------------------------------------------------------------------
4191 defm LD1 : SIMDLd1Multiple<"ld1">;
4192 defm LD2 : SIMDLd2Multiple<"ld2">;
4193 defm LD3 : SIMDLd3Multiple<"ld3">;
4194 defm LD4 : SIMDLd4Multiple<"ld4">;
4196 defm ST1 : SIMDSt1Multiple<"st1">;
4197 defm ST2 : SIMDSt2Multiple<"st2">;
4198 defm ST3 : SIMDSt3Multiple<"st3">;
4199 defm ST4 : SIMDSt4Multiple<"st4">;
4201 class Ld1Pat<ValueType ty, Instruction INST>
4202 : Pat<(ty (load am_simdnoindex:$vaddr)), (INST am_simdnoindex:$vaddr)>;
4204 def : Ld1Pat<v16i8, LD1Onev16b>;
4205 def : Ld1Pat<v8i16, LD1Onev8h>;
4206 def : Ld1Pat<v4i32, LD1Onev4s>;
4207 def : Ld1Pat<v2i64, LD1Onev2d>;
4208 def : Ld1Pat<v8i8, LD1Onev8b>;
4209 def : Ld1Pat<v4i16, LD1Onev4h>;
4210 def : Ld1Pat<v2i32, LD1Onev2s>;
4211 def : Ld1Pat<v1i64, LD1Onev1d>;
4213 class St1Pat<ValueType ty, Instruction INST>
4214 : Pat<(store ty:$Vt, am_simdnoindex:$vaddr),
4215 (INST ty:$Vt, am_simdnoindex:$vaddr)>;
4217 def : St1Pat<v16i8, ST1Onev16b>;
4218 def : St1Pat<v8i16, ST1Onev8h>;
4219 def : St1Pat<v4i32, ST1Onev4s>;
4220 def : St1Pat<v2i64, ST1Onev2d>;
4221 def : St1Pat<v8i8, ST1Onev8b>;
4222 def : St1Pat<v4i16, ST1Onev4h>;
4223 def : St1Pat<v2i32, ST1Onev2s>;
4224 def : St1Pat<v1i64, ST1Onev1d>;
4230 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4231 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4232 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4233 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4234 let mayLoad = 1, neverHasSideEffects = 1 in {
4235 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4236 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4237 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4238 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4239 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4240 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4241 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4242 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4243 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4244 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4245 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4246 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4247 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4248 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4249 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4250 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4253 def : Pat<(v8i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4254 (LD1Rv8b am_simdnoindex:$vaddr)>;
4255 def : Pat<(v16i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4256 (LD1Rv16b am_simdnoindex:$vaddr)>;
4257 def : Pat<(v4i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4258 (LD1Rv4h am_simdnoindex:$vaddr)>;
4259 def : Pat<(v8i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4260 (LD1Rv8h am_simdnoindex:$vaddr)>;
4261 def : Pat<(v2i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4262 (LD1Rv2s am_simdnoindex:$vaddr)>;
4263 def : Pat<(v4i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4264 (LD1Rv4s am_simdnoindex:$vaddr)>;
4265 def : Pat<(v2i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4266 (LD1Rv2d am_simdnoindex:$vaddr)>;
4267 def : Pat<(v1i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4268 (LD1Rv1d am_simdnoindex:$vaddr)>;
4269 // Grab the floating point version too
4270 def : Pat<(v2f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4271 (LD1Rv2s am_simdnoindex:$vaddr)>;
4272 def : Pat<(v4f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4273 (LD1Rv4s am_simdnoindex:$vaddr)>;
4274 def : Pat<(v2f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4275 (LD1Rv2d am_simdnoindex:$vaddr)>;
4276 def : Pat<(v1f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4277 (LD1Rv1d am_simdnoindex:$vaddr)>;
4279 class Ld1Lane128Pat<SDPatternOperator scalar_load, Operand VecIndex,
4280 ValueType VTy, ValueType STy, Instruction LD1>
4281 : Pat<(vector_insert (VTy VecListOne128:$Rd),
4282 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4283 (LD1 VecListOne128:$Rd, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4285 def : Ld1Lane128Pat<extloadi8, VectorIndexB, v16i8, i32, LD1i8>;
4286 def : Ld1Lane128Pat<extloadi16, VectorIndexH, v8i16, i32, LD1i16>;
4287 def : Ld1Lane128Pat<load, VectorIndexS, v4i32, i32, LD1i32>;
4288 def : Ld1Lane128Pat<load, VectorIndexS, v4f32, f32, LD1i32>;
4289 def : Ld1Lane128Pat<load, VectorIndexD, v2i64, i64, LD1i64>;
4290 def : Ld1Lane128Pat<load, VectorIndexD, v2f64, f64, LD1i64>;
4292 class Ld1Lane64Pat<SDPatternOperator scalar_load, Operand VecIndex,
4293 ValueType VTy, ValueType STy, Instruction LD1>
4294 : Pat<(vector_insert (VTy VecListOne64:$Rd),
4295 (STy (scalar_load am_simdnoindex:$vaddr)), VecIndex:$idx),
4297 (LD1 (SUBREG_TO_REG (i32 0), VecListOne64:$Rd, dsub),
4298 VecIndex:$idx, am_simdnoindex:$vaddr),
4301 def : Ld1Lane64Pat<extloadi8, VectorIndexB, v8i8, i32, LD1i8>;
4302 def : Ld1Lane64Pat<extloadi16, VectorIndexH, v4i16, i32, LD1i16>;
4303 def : Ld1Lane64Pat<load, VectorIndexS, v2i32, i32, LD1i32>;
4304 def : Ld1Lane64Pat<load, VectorIndexS, v2f32, f32, LD1i32>;
4307 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4308 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4309 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4310 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4313 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb, GPR64pi1>;
4314 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh, GPR64pi2>;
4315 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes, GPR64pi4>;
4316 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned, GPR64pi8>;
4318 let AddedComplexity = 8 in
4319 class St1Lane128Pat<SDPatternOperator scalar_store, Operand VecIndex,
4320 ValueType VTy, ValueType STy, Instruction ST1>
4322 (STy (vector_extract (VTy VecListOne128:$Vt), VecIndex:$idx)),
4323 am_simdnoindex:$vaddr),
4324 (ST1 VecListOne128:$Vt, VecIndex:$idx, am_simdnoindex:$vaddr)>;
4326 def : St1Lane128Pat<truncstorei8, VectorIndexB, v16i8, i32, ST1i8>;
4327 def : St1Lane128Pat<truncstorei16, VectorIndexH, v8i16, i32, ST1i16>;
4328 def : St1Lane128Pat<store, VectorIndexS, v4i32, i32, ST1i32>;
4329 def : St1Lane128Pat<store, VectorIndexS, v4f32, f32, ST1i32>;
4330 def : St1Lane128Pat<store, VectorIndexD, v2i64, i64, ST1i64>;
4331 def : St1Lane128Pat<store, VectorIndexD, v2f64, f64, ST1i64>;
4333 let AddedComplexity = 8 in
4334 class St1Lane64Pat<SDPatternOperator scalar_store, Operand VecIndex,
4335 ValueType VTy, ValueType STy, Instruction ST1>
4337 (STy (vector_extract (VTy VecListOne64:$Vt), VecIndex:$idx)),
4338 am_simdnoindex:$vaddr),
4339 (ST1 (SUBREG_TO_REG (i32 0), VecListOne64:$Vt, dsub),
4340 VecIndex:$idx, am_simdnoindex:$vaddr)>;
4342 def : St1Lane64Pat<truncstorei8, VectorIndexB, v8i8, i32, ST1i8>;
4343 def : St1Lane64Pat<truncstorei16, VectorIndexH, v4i16, i32, ST1i16>;
4344 def : St1Lane64Pat<store, VectorIndexS, v2i32, i32, ST1i32>;
4345 def : St1Lane64Pat<store, VectorIndexS, v2f32, f32, ST1i32>;
4347 let mayStore = 1, neverHasSideEffects = 1 in {
4348 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, GPR64pi2>;
4349 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, GPR64pi4>;
4350 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, GPR64pi8>;
4351 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, GPR64pi16>;
4352 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, GPR64pi3>;
4353 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, GPR64pi6>;
4354 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, GPR64pi12>;
4355 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, GPR64pi24>;
4356 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, GPR64pi4>;
4357 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, GPR64pi8>;
4358 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, GPR64pi16>;
4359 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, GPR64pi32>;
4362 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4363 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4364 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4365 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4367 //----------------------------------------------------------------------------
4368 // Crypto extensions
4369 //----------------------------------------------------------------------------
4371 def AESErr : AESTiedInst<0b0100, "aese", int_arm64_crypto_aese>;
4372 def AESDrr : AESTiedInst<0b0101, "aesd", int_arm64_crypto_aesd>;
4373 def AESMCrr : AESInst< 0b0110, "aesmc", int_arm64_crypto_aesmc>;
4374 def AESIMCrr : AESInst< 0b0111, "aesimc", int_arm64_crypto_aesimc>;
4376 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_arm64_crypto_sha1c>;
4377 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_arm64_crypto_sha1p>;
4378 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_arm64_crypto_sha1m>;
4379 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_arm64_crypto_sha1su0>;
4380 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_arm64_crypto_sha256h>;
4381 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_arm64_crypto_sha256h2>;
4382 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_arm64_crypto_sha256su1>;
4384 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_arm64_crypto_sha1h>;
4385 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_arm64_crypto_sha1su1>;
4386 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_arm64_crypto_sha256su0>;
4388 //----------------------------------------------------------------------------
4390 //----------------------------------------------------------------------------
4391 // FIXME: Like for X86, these should go in their own separate .td file.
4393 // Any instruction that defines a 32-bit result leaves the high half of the
4394 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4395 // be copying from a truncate. But any other 32-bit operation will zero-extend
4397 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4398 def def32 : PatLeaf<(i32 GPR32:$src), [{
4399 return N->getOpcode() != ISD::TRUNCATE &&
4400 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4401 N->getOpcode() != ISD::CopyFromReg;
4404 // In the case of a 32-bit def that is known to implicitly zero-extend,
4405 // we can use a SUBREG_TO_REG.
4406 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4408 // For an anyext, we don't care what the high bits are, so we can perform an
4409 // INSERT_SUBREF into an IMPLICIT_DEF.
4410 def : Pat<(i64 (anyext GPR32:$src)),
4411 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4413 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4414 // instruction (UBFM) on the enclosing super-reg.
4415 def : Pat<(i64 (zext GPR32:$src)),
4416 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4418 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4419 // containing super-reg.
4420 def : Pat<(i64 (sext GPR32:$src)),
4421 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4422 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4423 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4424 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4425 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4426 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4427 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4428 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4430 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i64 imm0_31:$imm)),
4431 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4432 (i64 (i32shift_sext_i8 imm0_31:$imm)))>;
4433 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4434 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4435 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4437 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i64 imm0_31:$imm)),
4438 (SBFMWri GPR32:$Rn, (i64 (i32shift_a imm0_31:$imm)),
4439 (i64 (i32shift_sext_i16 imm0_31:$imm)))>;
4440 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4441 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4442 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4444 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4445 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4446 (i64 (i64shift_a imm0_63:$imm)),
4447 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4449 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4450 // AddedComplexity for the following patterns since we want to match sext + sra
4451 // patterns before we attempt to match a single sra node.
4452 let AddedComplexity = 20 in {
4453 // We support all sext + sra combinations which preserve at least one bit of the
4454 // original value which is to be sign extended. E.g. we support shifts up to
4456 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i64 imm0_7:$imm)),
4457 (SBFMWri GPR32:$Rn, (i64 imm0_7:$imm), 7)>;
4458 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7:$imm)),
4459 (SBFMXri GPR64:$Rn, (i64 imm0_7:$imm), 7)>;
4461 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i64 imm0_15:$imm)),
4462 (SBFMWri GPR32:$Rn, (i64 imm0_15:$imm), 15)>;
4463 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15:$imm)),
4464 (SBFMXri GPR64:$Rn, (i64 imm0_15:$imm), 15)>;
4466 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31:$imm)),
4467 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4468 (i64 imm0_31:$imm), 31)>;
4469 } // AddedComplexity = 20
4471 // To truncate, we can simply extract from a subregister.
4472 def : Pat<(i32 (trunc GPR64sp:$src)),
4473 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4475 // __builtin_trap() uses the BRK instruction on ARM64.
4476 def : Pat<(trap), (BRK 1)>;
4478 // Conversions within AdvSIMD types in the same register size are free.
4480 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
4481 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
4482 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
4483 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4484 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
4485 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4487 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
4488 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
4489 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
4490 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4491 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
4492 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4494 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
4495 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
4496 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
4497 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4498 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
4499 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4501 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
4502 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
4503 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
4504 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4505 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
4506 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4508 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
4509 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
4510 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
4511 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
4512 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
4513 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
4515 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
4516 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
4517 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
4518 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
4519 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
4520 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
4522 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4523 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
4524 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
4525 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
4526 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
4527 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4530 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
4531 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
4532 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
4533 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
4534 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
4536 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
4537 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
4538 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
4539 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
4540 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
4541 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
4543 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
4544 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
4545 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
4546 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
4547 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
4548 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
4550 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
4551 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
4552 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
4553 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
4554 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
4555 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
4557 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
4558 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
4559 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
4560 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
4561 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
4562 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
4564 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
4565 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
4566 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
4567 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
4568 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
4569 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
4571 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
4572 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
4573 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
4574 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
4575 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
4576 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
4578 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
4579 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4580 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
4581 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4582 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
4583 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4584 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
4585 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4587 // A 64-bit subvector insert to the first 128-bit vector position
4588 // is a subregister copy that needs no instruction.
4589 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
4590 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4591 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
4592 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4593 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
4594 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4595 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
4596 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4597 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
4598 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4599 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
4600 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4602 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
4604 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
4605 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
4606 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
4607 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
4608 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
4609 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
4610 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
4611 // so we match on v4f32 here, not v2f32. This will also catch adding
4612 // the low two lanes of a true v4f32 vector.
4613 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
4614 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
4615 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
4617 // Scalar 64-bit shifts in FPR64 registers.
4618 def : Pat<(i64 (int_arm64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4619 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4620 def : Pat<(i64 (int_arm64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4621 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4622 def : Pat<(i64 (int_arm64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4623 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4624 def : Pat<(i64 (int_arm64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4625 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4627 // Tail call return handling. These are all compiler pseudo-instructions,
4628 // so no encoding information or anything like that.
4629 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
4630 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst), []>;
4631 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst), []>;
4634 def : Pat<(ARM64tcret tcGPR64:$dst), (TCRETURNri tcGPR64:$dst)>;
4635 def : Pat<(ARM64tcret (i64 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4636 def : Pat<(ARM64tcret (i64 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4638 include "ARM64InstrAtomics.td"