1 //===- ARM64InstrInfo.td - Describe the ARM64 Instructions -*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // ARM64 Instruction definitions.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // ARM64-specific DAG Nodes.
18 // SDTBinaryArithWithFlagsOut - RES1, FLAGS = op LHS, RHS
19 def SDTBinaryArithWithFlagsOut : SDTypeProfile<2, 2,
22 SDTCisInt<0>, SDTCisVT<1, i32>]>;
24 // SDTBinaryArithWithFlagsIn - RES1, FLAGS = op LHS, RHS, FLAGS
25 def SDTBinaryArithWithFlagsIn : SDTypeProfile<1, 3,
31 // SDTBinaryArithWithFlagsInOut - RES1, FLAGS = op LHS, RHS, FLAGS
32 def SDTBinaryArithWithFlagsInOut : SDTypeProfile<2, 3,
39 def SDT_ARM64Brcond : SDTypeProfile<0, 3,
40 [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
42 def SDT_ARM64cbz : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisVT<1, OtherVT>]>;
43 def SDT_ARM64tbz : SDTypeProfile<0, 3, [SDTCisVT<0, i64>, SDTCisVT<1, i64>,
44 SDTCisVT<2, OtherVT>]>;
47 def SDT_ARM64CSel : SDTypeProfile<1, 4,
52 def SDT_ARM64FCmp : SDTypeProfile<0, 2,
55 def SDT_ARM64Dup : SDTypeProfile<1, 1, [SDTCisVec<0>]>;
56 def SDT_ARM64DupLane : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisInt<2>]>;
57 def SDT_ARM64Zip : SDTypeProfile<1, 2, [SDTCisVec<0>,
60 def SDT_ARM64MOVIedit : SDTypeProfile<1, 1, [SDTCisInt<1>]>;
61 def SDT_ARM64MOVIshift : SDTypeProfile<1, 2, [SDTCisInt<1>, SDTCisInt<2>]>;
62 def SDT_ARM64vecimm : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
63 SDTCisInt<2>, SDTCisInt<3>]>;
64 def SDT_ARM64UnaryVec: SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
65 def SDT_ARM64ExtVec: SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
66 SDTCisSameAs<0,2>, SDTCisInt<3>]>;
67 def SDT_ARM64vshift : SDTypeProfile<1, 2, [SDTCisSameAs<0,1>, SDTCisInt<2>]>;
69 def SDT_ARM64unvec : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0,1>]>;
70 def SDT_ARM64fcmpz : SDTypeProfile<1, 1, []>;
71 def SDT_ARM64fcmp : SDTypeProfile<1, 2, [SDTCisSameAs<1,2>]>;
72 def SDT_ARM64binvec : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0,1>,
74 def SDT_ARM64trivec : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0,1>,
77 def SDT_ARM64TCRET : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
78 def SDT_ARM64PREFETCH : SDTypeProfile<0, 2, [SDTCisVT<0, i32>, SDTCisPtrTy<1>]>;
80 def SDT_ARM64ITOF : SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisSameAs<0,1>]>;
82 def SDT_ARM64TLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>,
84 def SDT_ARM64WrapperLarge : SDTypeProfile<1, 4,
85 [SDTCisVT<0, i64>, SDTCisVT<1, i32>,
86 SDTCisSameAs<1, 2>, SDTCisSameAs<1, 3>,
91 def ARM64adrp : SDNode<"ARM64ISD::ADRP", SDTIntUnaryOp, []>;
92 def ARM64addlow : SDNode<"ARM64ISD::ADDlow", SDTIntBinOp, []>;
93 def ARM64LOADgot : SDNode<"ARM64ISD::LOADgot", SDTIntUnaryOp>;
94 def ARM64callseq_start : SDNode<"ISD::CALLSEQ_START",
95 SDCallSeqStart<[ SDTCisVT<0, i32> ]>,
96 [SDNPHasChain, SDNPOutGlue]>;
97 def ARM64callseq_end : SDNode<"ISD::CALLSEQ_END",
98 SDCallSeqEnd<[ SDTCisVT<0, i32>,
100 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
101 def ARM64call : SDNode<"ARM64ISD::CALL",
102 SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>,
103 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
105 def ARM64brcond : SDNode<"ARM64ISD::BRCOND", SDT_ARM64Brcond,
107 def ARM64cbz : SDNode<"ARM64ISD::CBZ", SDT_ARM64cbz,
109 def ARM64cbnz : SDNode<"ARM64ISD::CBNZ", SDT_ARM64cbz,
111 def ARM64tbz : SDNode<"ARM64ISD::TBZ", SDT_ARM64tbz,
113 def ARM64tbnz : SDNode<"ARM64ISD::TBNZ", SDT_ARM64tbz,
117 def ARM64csel : SDNode<"ARM64ISD::CSEL", SDT_ARM64CSel>;
118 def ARM64csinv : SDNode<"ARM64ISD::CSINV", SDT_ARM64CSel>;
119 def ARM64csneg : SDNode<"ARM64ISD::CSNEG", SDT_ARM64CSel>;
120 def ARM64csinc : SDNode<"ARM64ISD::CSINC", SDT_ARM64CSel>;
121 def ARM64retflag : SDNode<"ARM64ISD::RET_FLAG", SDTNone,
122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
123 def ARM64adc : SDNode<"ARM64ISD::ADC", SDTBinaryArithWithFlagsIn >;
124 def ARM64sbc : SDNode<"ARM64ISD::SBC", SDTBinaryArithWithFlagsIn>;
125 def ARM64add_flag : SDNode<"ARM64ISD::ADDS", SDTBinaryArithWithFlagsOut,
127 def ARM64sub_flag : SDNode<"ARM64ISD::SUBS", SDTBinaryArithWithFlagsOut>;
128 def ARM64and_flag : SDNode<"ARM64ISD::ANDS", SDTBinaryArithWithFlagsOut>;
129 def ARM64adc_flag : SDNode<"ARM64ISD::ADCS", SDTBinaryArithWithFlagsInOut>;
130 def ARM64sbc_flag : SDNode<"ARM64ISD::SBCS", SDTBinaryArithWithFlagsInOut>;
132 def ARM64threadpointer : SDNode<"ARM64ISD::THREAD_POINTER", SDTPtrLeaf>;
134 def ARM64fcmp : SDNode<"ARM64ISD::FCMP", SDT_ARM64FCmp>;
136 def ARM64fmax : SDNode<"ARM64ISD::FMAX", SDTFPBinOp>;
137 def ARM64fmin : SDNode<"ARM64ISD::FMIN", SDTFPBinOp>;
139 def ARM64dup : SDNode<"ARM64ISD::DUP", SDT_ARM64Dup>;
140 def ARM64duplane8 : SDNode<"ARM64ISD::DUPLANE8", SDT_ARM64DupLane>;
141 def ARM64duplane16 : SDNode<"ARM64ISD::DUPLANE16", SDT_ARM64DupLane>;
142 def ARM64duplane32 : SDNode<"ARM64ISD::DUPLANE32", SDT_ARM64DupLane>;
143 def ARM64duplane64 : SDNode<"ARM64ISD::DUPLANE64", SDT_ARM64DupLane>;
145 def ARM64zip1 : SDNode<"ARM64ISD::ZIP1", SDT_ARM64Zip>;
146 def ARM64zip2 : SDNode<"ARM64ISD::ZIP2", SDT_ARM64Zip>;
147 def ARM64uzp1 : SDNode<"ARM64ISD::UZP1", SDT_ARM64Zip>;
148 def ARM64uzp2 : SDNode<"ARM64ISD::UZP2", SDT_ARM64Zip>;
149 def ARM64trn1 : SDNode<"ARM64ISD::TRN1", SDT_ARM64Zip>;
150 def ARM64trn2 : SDNode<"ARM64ISD::TRN2", SDT_ARM64Zip>;
152 def ARM64movi_edit : SDNode<"ARM64ISD::MOVIedit", SDT_ARM64MOVIedit>;
153 def ARM64movi_shift : SDNode<"ARM64ISD::MOVIshift", SDT_ARM64MOVIshift>;
154 def ARM64movi_msl : SDNode<"ARM64ISD::MOVImsl", SDT_ARM64MOVIshift>;
155 def ARM64mvni_shift : SDNode<"ARM64ISD::MVNIshift", SDT_ARM64MOVIshift>;
156 def ARM64mvni_msl : SDNode<"ARM64ISD::MVNImsl", SDT_ARM64MOVIshift>;
157 def ARM64movi : SDNode<"ARM64ISD::MOVI", SDT_ARM64MOVIedit>;
158 def ARM64fmov : SDNode<"ARM64ISD::FMOV", SDT_ARM64MOVIedit>;
160 def ARM64rev16 : SDNode<"ARM64ISD::REV16", SDT_ARM64UnaryVec>;
161 def ARM64rev32 : SDNode<"ARM64ISD::REV32", SDT_ARM64UnaryVec>;
162 def ARM64rev64 : SDNode<"ARM64ISD::REV64", SDT_ARM64UnaryVec>;
163 def ARM64ext : SDNode<"ARM64ISD::EXT", SDT_ARM64ExtVec>;
165 def ARM64vashr : SDNode<"ARM64ISD::VASHR", SDT_ARM64vshift>;
166 def ARM64vlshr : SDNode<"ARM64ISD::VLSHR", SDT_ARM64vshift>;
167 def ARM64vshl : SDNode<"ARM64ISD::VSHL", SDT_ARM64vshift>;
168 def ARM64sqshli : SDNode<"ARM64ISD::SQSHL_I", SDT_ARM64vshift>;
169 def ARM64uqshli : SDNode<"ARM64ISD::UQSHL_I", SDT_ARM64vshift>;
170 def ARM64sqshlui : SDNode<"ARM64ISD::SQSHLU_I", SDT_ARM64vshift>;
171 def ARM64srshri : SDNode<"ARM64ISD::SRSHR_I", SDT_ARM64vshift>;
172 def ARM64urshri : SDNode<"ARM64ISD::URSHR_I", SDT_ARM64vshift>;
174 def ARM64not: SDNode<"ARM64ISD::NOT", SDT_ARM64unvec>;
175 def ARM64bit: SDNode<"ARM64ISD::BIT", SDT_ARM64trivec>;
177 def ARM64cmeq: SDNode<"ARM64ISD::CMEQ", SDT_ARM64binvec>;
178 def ARM64cmge: SDNode<"ARM64ISD::CMGE", SDT_ARM64binvec>;
179 def ARM64cmgt: SDNode<"ARM64ISD::CMGT", SDT_ARM64binvec>;
180 def ARM64cmhi: SDNode<"ARM64ISD::CMHI", SDT_ARM64binvec>;
181 def ARM64cmhs: SDNode<"ARM64ISD::CMHS", SDT_ARM64binvec>;
183 def ARM64fcmeq: SDNode<"ARM64ISD::FCMEQ", SDT_ARM64fcmp>;
184 def ARM64fcmge: SDNode<"ARM64ISD::FCMGE", SDT_ARM64fcmp>;
185 def ARM64fcmgt: SDNode<"ARM64ISD::FCMGT", SDT_ARM64fcmp>;
187 def ARM64cmeqz: SDNode<"ARM64ISD::CMEQz", SDT_ARM64unvec>;
188 def ARM64cmgez: SDNode<"ARM64ISD::CMGEz", SDT_ARM64unvec>;
189 def ARM64cmgtz: SDNode<"ARM64ISD::CMGTz", SDT_ARM64unvec>;
190 def ARM64cmlez: SDNode<"ARM64ISD::CMLEz", SDT_ARM64unvec>;
191 def ARM64cmltz: SDNode<"ARM64ISD::CMLTz", SDT_ARM64unvec>;
192 def ARM64cmtst : PatFrag<(ops node:$LHS, node:$RHS),
193 (ARM64not (ARM64cmeqz (and node:$LHS, node:$RHS)))>;
195 def ARM64fcmeqz: SDNode<"ARM64ISD::FCMEQz", SDT_ARM64fcmpz>;
196 def ARM64fcmgez: SDNode<"ARM64ISD::FCMGEz", SDT_ARM64fcmpz>;
197 def ARM64fcmgtz: SDNode<"ARM64ISD::FCMGTz", SDT_ARM64fcmpz>;
198 def ARM64fcmlez: SDNode<"ARM64ISD::FCMLEz", SDT_ARM64fcmpz>;
199 def ARM64fcmltz: SDNode<"ARM64ISD::FCMLTz", SDT_ARM64fcmpz>;
201 def ARM64bici: SDNode<"ARM64ISD::BICi", SDT_ARM64vecimm>;
202 def ARM64orri: SDNode<"ARM64ISD::ORRi", SDT_ARM64vecimm>;
204 def ARM64neg : SDNode<"ARM64ISD::NEG", SDT_ARM64unvec>;
206 def ARM64tcret: SDNode<"ARM64ISD::TC_RETURN", SDT_ARM64TCRET,
207 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
209 def ARM64Prefetch : SDNode<"ARM64ISD::PREFETCH", SDT_ARM64PREFETCH,
210 [SDNPHasChain, SDNPSideEffect]>;
212 def ARM64sitof: SDNode<"ARM64ISD::SITOF", SDT_ARM64ITOF>;
213 def ARM64uitof: SDNode<"ARM64ISD::UITOF", SDT_ARM64ITOF>;
215 def ARM64tlsdesc_call : SDNode<"ARM64ISD::TLSDESC_CALL", SDT_ARM64TLSDescCall,
216 [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
219 def ARM64WrapperLarge : SDNode<"ARM64ISD::WrapperLarge", SDT_ARM64WrapperLarge>;
222 //===----------------------------------------------------------------------===//
224 //===----------------------------------------------------------------------===//
226 // ARM64 Instruction Predicate Definitions.
228 def HasZCZ : Predicate<"Subtarget->hasZeroCycleZeroing()">;
229 def NoZCZ : Predicate<"!Subtarget->hasZeroCycleZeroing()">;
230 def IsDarwin : Predicate<"Subtarget->isTargetDarwin()">;
231 def IsNotDarwin: Predicate<"!Subtarget->isTargetDarwin()">;
232 def ForCodeSize : Predicate<"ForCodeSize">;
233 def NotForCodeSize : Predicate<"!ForCodeSize">;
235 include "ARM64InstrFormats.td"
237 //===----------------------------------------------------------------------===//
239 //===----------------------------------------------------------------------===//
240 // Miscellaneous instructions.
241 //===----------------------------------------------------------------------===//
243 let Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1 in {
244 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
245 [(ARM64callseq_start timm:$amt)]>;
246 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
247 [(ARM64callseq_end timm:$amt1, timm:$amt2)]>;
248 } // Defs = [SP], Uses = [SP], hasSideEffects = 1, isCodeGenOnly = 1
250 let isReMaterializable = 1, isCodeGenOnly = 1 in {
251 // FIXME: The following pseudo instructions are only needed because remat
252 // cannot handle multiple instructions. When that changes, they can be
253 // removed, along with the ARM64Wrapper node.
255 let AddedComplexity = 10 in
256 def LOADgot : Pseudo<(outs GPR64:$dst), (ins i64imm:$addr),
257 [(set GPR64:$dst, (ARM64LOADgot tglobaladdr:$addr))]>,
260 // The MOVaddr instruction should match only when the add is not folded
261 // into a load or store address.
263 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
264 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaladdr:$hi),
265 tglobaladdr:$low))]>,
266 Sched<[WriteAdrAdr]>;
268 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
269 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tjumptable:$hi),
271 Sched<[WriteAdrAdr]>;
273 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
274 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tconstpool:$hi),
276 Sched<[WriteAdrAdr]>;
278 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
279 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tblockaddress:$hi),
280 tblockaddress:$low))]>,
281 Sched<[WriteAdrAdr]>;
283 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
284 [(set GPR64:$dst, (ARM64addlow (ARM64adrp tglobaltlsaddr:$hi),
285 tglobaltlsaddr:$low))]>,
286 Sched<[WriteAdrAdr]>;
288 : Pseudo<(outs GPR64:$dst), (ins i64imm:$hi, i64imm:$low),
289 [(set GPR64:$dst, (ARM64addlow (ARM64adrp texternalsym:$hi),
290 texternalsym:$low))]>,
291 Sched<[WriteAdrAdr]>;
293 } // isReMaterializable, isCodeGenOnly
295 def : Pat<(ARM64LOADgot tglobaltlsaddr:$addr),
296 (LOADgot tglobaltlsaddr:$addr)>;
298 def : Pat<(ARM64LOADgot texternalsym:$addr),
299 (LOADgot texternalsym:$addr)>;
301 def : Pat<(ARM64LOADgot tconstpool:$addr),
302 (LOADgot tconstpool:$addr)>;
304 //===----------------------------------------------------------------------===//
305 // System instructions.
306 //===----------------------------------------------------------------------===//
308 def HINT : HintI<"hint">;
309 def : InstAlias<"nop", (HINT 0b000)>;
310 def : InstAlias<"yield",(HINT 0b001)>;
311 def : InstAlias<"wfe", (HINT 0b010)>;
312 def : InstAlias<"wfi", (HINT 0b011)>;
313 def : InstAlias<"sev", (HINT 0b100)>;
314 def : InstAlias<"sevl", (HINT 0b101)>;
316 // As far as LLVM is concerned this writes to the system's exclusive monitors.
317 let mayLoad = 1, mayStore = 1 in
318 def CLREX : CRmSystemI<imm0_15, 0b010, "clrex">;
320 def DMB : CRmSystemI<barrier_op, 0b101, "dmb">;
321 def DSB : CRmSystemI<barrier_op, 0b100, "dsb">;
322 def ISB : CRmSystemI<barrier_op, 0b110, "isb">;
323 def : InstAlias<"clrex", (CLREX 0xf)>;
324 def : InstAlias<"isb", (ISB 0xf)>;
328 def MSRcpsr: MSRcpsrI;
330 // The thread pointer (on Linux, at least, where this has been implemented) is
332 def : Pat<(ARM64threadpointer), (MRS 0xde82)>;
334 // Generic system instructions
335 def SYS : SystemI<0, "sys">;
336 def SYSxt : SystemXtI<0, "sys">;
337 def SYSLxt : SystemLXtI<1, "sysl">;
339 //===----------------------------------------------------------------------===//
340 // Move immediate instructions.
341 //===----------------------------------------------------------------------===//
343 defm MOVK : InsertImmediate<0b11, "movk">;
344 defm MOVN : MoveImmediate<0b00, "movn">;
346 let PostEncoderMethod = "fixMOVZ" in
347 defm MOVZ : MoveImmediate<0b10, "movz">;
349 def : InstAlias<"movk $dst, $imm", (MOVKWi GPR32:$dst, imm0_65535:$imm, 0)>;
350 def : InstAlias<"movk $dst, $imm", (MOVKXi GPR64:$dst, imm0_65535:$imm, 0)>;
351 def : InstAlias<"movn $dst, $imm", (MOVNWi GPR32:$dst, imm0_65535:$imm, 0)>;
352 def : InstAlias<"movn $dst, $imm", (MOVNXi GPR64:$dst, imm0_65535:$imm, 0)>;
353 def : InstAlias<"movz $dst, $imm", (MOVZWi GPR32:$dst, imm0_65535:$imm, 0)>;
354 def : InstAlias<"movz $dst, $imm", (MOVZXi GPR64:$dst, imm0_65535:$imm, 0)>;
356 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
357 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
358 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
359 def : InstAlias<"movz $Rd, $sym", (MOVZXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
361 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g3:$sym, 48)>;
362 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g2:$sym, 32)>;
363 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g1:$sym, 16)>;
364 def : InstAlias<"movn $Rd, $sym", (MOVNXi GPR64:$Rd, movz_symbol_g0:$sym, 0)>;
366 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g3:$sym, 48)>;
367 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g2:$sym, 32)>;
368 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g1:$sym, 16)>;
369 def : InstAlias<"movz $Rd, $sym", (MOVZWi GPR32:$Rd, movz_symbol_g0:$sym, 0)>;
371 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g2:$sym, 32)>;
372 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g1:$sym, 16)>;
373 def : InstAlias<"movk $Rd, $sym", (MOVKXi GPR64:$Rd, movk_symbol_g0:$sym, 0)>;
375 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g2:$sym, 32)>;
376 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g1:$sym, 16)>;
377 def : InstAlias<"movk $Rd, $sym", (MOVKWi GPR32:$Rd, movk_symbol_g0:$sym, 0)>;
379 let isReMaterializable = 1, isCodeGenOnly = 1, isMoveImm = 1,
380 isAsCheapAsAMove = 1 in {
381 // FIXME: The following pseudo instructions are only needed because remat
382 // cannot handle multiple instructions. When that changes, we can select
383 // directly to the real instructions and get rid of these pseudos.
386 : Pseudo<(outs GPR32:$dst), (ins i32imm:$src),
387 [(set GPR32:$dst, imm:$src)]>,
390 : Pseudo<(outs GPR64:$dst), (ins i64imm:$src),
391 [(set GPR64:$dst, imm:$src)]>,
393 } // isReMaterializable, isCodeGenOnly
395 def : Pat<(ARM64WrapperLarge tglobaladdr:$g3, tglobaladdr:$g2,
396 tglobaladdr:$g1, tglobaladdr:$g0),
397 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tglobaladdr:$g3, 48),
398 tglobaladdr:$g2, 32),
399 tglobaladdr:$g1, 16),
400 tglobaladdr:$g0, 0)>;
402 def : Pat<(ARM64WrapperLarge tblockaddress:$g3, tblockaddress:$g2,
403 tblockaddress:$g1, tblockaddress:$g0),
404 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tblockaddress:$g3, 48),
405 tblockaddress:$g2, 32),
406 tblockaddress:$g1, 16),
407 tblockaddress:$g0, 0)>;
409 def : Pat<(ARM64WrapperLarge tconstpool:$g3, tconstpool:$g2,
410 tconstpool:$g1, tconstpool:$g0),
411 (MOVKXi (MOVKXi (MOVKXi (MOVZXi tconstpool:$g3, 48),
417 //===----------------------------------------------------------------------===//
418 // Arithmetic instructions.
419 //===----------------------------------------------------------------------===//
421 // Add/subtract with carry.
422 defm ADC : AddSubCarry<0, "adc", "adcs", ARM64adc, ARM64adc_flag>;
423 defm SBC : AddSubCarry<1, "sbc", "sbcs", ARM64sbc, ARM64sbc_flag>;
425 def : InstAlias<"ngc $dst, $src", (SBCWr GPR32:$dst, WZR, GPR32:$src)>;
426 def : InstAlias<"ngc $dst, $src", (SBCXr GPR64:$dst, XZR, GPR64:$src)>;
427 def : InstAlias<"ngcs $dst, $src", (SBCSWr GPR32:$dst, WZR, GPR32:$src)>;
428 def : InstAlias<"ngcs $dst, $src", (SBCSXr GPR64:$dst, XZR, GPR64:$src)>;
431 defm ADD : AddSub<0, "add", add>;
432 defm SUB : AddSub<1, "sub">;
434 defm ADDS : AddSubS<0, "adds", ARM64add_flag>;
435 defm SUBS : AddSubS<1, "subs", ARM64sub_flag>;
437 // Use SUBS instead of SUB to enable CSE between SUBS and SUB.
438 def : Pat<(sub GPR32sp:$Rn, addsub_shifted_imm32:$imm),
439 (SUBSWri GPR32sp:$Rn, addsub_shifted_imm32:$imm)>;
440 def : Pat<(sub GPR64sp:$Rn, addsub_shifted_imm64:$imm),
441 (SUBSXri GPR64sp:$Rn, addsub_shifted_imm64:$imm)>;
442 def : Pat<(sub GPR32:$Rn, GPR32:$Rm),
443 (SUBSWrr GPR32:$Rn, GPR32:$Rm)>;
444 def : Pat<(sub GPR64:$Rn, GPR64:$Rm),
445 (SUBSXrr GPR64:$Rn, GPR64:$Rm)>;
446 def : Pat<(sub GPR32:$Rn, arith_shifted_reg32:$Rm),
447 (SUBSWrs GPR32:$Rn, arith_shifted_reg32:$Rm)>;
448 def : Pat<(sub GPR64:$Rn, arith_shifted_reg64:$Rm),
449 (SUBSXrs GPR64:$Rn, arith_shifted_reg64:$Rm)>;
450 def : Pat<(sub GPR32sp:$R2, arith_extended_reg32<i32>:$R3),
451 (SUBSWrx GPR32sp:$R2, arith_extended_reg32<i32>:$R3)>;
452 def : Pat<(sub GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3),
453 (SUBSXrx GPR64sp:$R2, arith_extended_reg32to64<i64>:$R3)>;
455 // Because of the immediate format for add/sub-imm instructions, the
456 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
457 // These patterns capture that transformation.
458 let AddedComplexity = 1 in {
459 def : Pat<(add GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
460 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
461 def : Pat<(add GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
462 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
463 def : Pat<(sub GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
464 (ADDWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
465 def : Pat<(sub GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
466 (ADDXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
469 def : InstAlias<"neg $dst, $src", (SUBWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
470 def : InstAlias<"neg $dst, $src", (SUBXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
471 def : InstAlias<"neg $dst, $src, $shift",
472 (SUBWrs GPR32:$dst, WZR, GPR32:$src, arith_shift:$shift)>;
473 def : InstAlias<"neg $dst, $src, $shift",
474 (SUBXrs GPR64:$dst, XZR, GPR64:$src, arith_shift:$shift)>;
476 // Because of the immediate format for add/sub-imm instructions, the
477 // expression (add x, -1) must be transformed to (SUB{W,X}ri x, 1).
478 // These patterns capture that transformation.
479 let AddedComplexity = 1 in {
480 def : Pat<(ARM64add_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
481 (SUBSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
482 def : Pat<(ARM64add_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
483 (SUBSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
484 def : Pat<(ARM64sub_flag GPR32:$Rn, neg_addsub_shifted_imm32:$imm),
485 (ADDSWri GPR32:$Rn, neg_addsub_shifted_imm32:$imm)>;
486 def : Pat<(ARM64sub_flag GPR64:$Rn, neg_addsub_shifted_imm64:$imm),
487 (ADDSXri GPR64:$Rn, neg_addsub_shifted_imm64:$imm)>;
490 def : InstAlias<"negs $dst, $src", (SUBSWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
491 def : InstAlias<"negs $dst, $src", (SUBSXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
492 def : InstAlias<"negs $dst, $src, $shift",
493 (SUBSWrs GPR32:$dst, WZR, GPR32:$src, arith_shift:$shift)>;
494 def : InstAlias<"negs $dst, $src, $shift",
495 (SUBSXrs GPR64:$dst, XZR, GPR64:$src, arith_shift:$shift)>;
497 // Unsigned/Signed divide
498 defm UDIV : Div<0, "udiv", udiv>;
499 defm SDIV : Div<1, "sdiv", sdiv>;
500 let isCodeGenOnly = 1 in {
501 defm UDIV_Int : Div<0, "udiv", int_arm64_udiv>;
502 defm SDIV_Int : Div<1, "sdiv", int_arm64_sdiv>;
506 defm ASRV : Shift<0b10, "asrv", sra>;
507 defm LSLV : Shift<0b00, "lslv", shl>;
508 defm LSRV : Shift<0b01, "lsrv", srl>;
509 defm RORV : Shift<0b11, "rorv", rotr>;
511 def : ShiftAlias<"asr", ASRVWr, GPR32>;
512 def : ShiftAlias<"asr", ASRVXr, GPR64>;
513 def : ShiftAlias<"lsl", LSLVWr, GPR32>;
514 def : ShiftAlias<"lsl", LSLVXr, GPR64>;
515 def : ShiftAlias<"lsr", LSRVWr, GPR32>;
516 def : ShiftAlias<"lsr", LSRVXr, GPR64>;
517 def : ShiftAlias<"ror", RORVWr, GPR32>;
518 def : ShiftAlias<"ror", RORVXr, GPR64>;
521 let AddedComplexity = 7 in {
522 defm MADD : MulAccum<0, "madd", add>;
523 defm MSUB : MulAccum<1, "msub", sub>;
525 def : Pat<(i32 (mul GPR32:$Rn, GPR32:$Rm)),
526 (MADDWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
527 def : Pat<(i64 (mul GPR64:$Rn, GPR64:$Rm)),
528 (MADDXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
530 def : Pat<(i32 (ineg (mul GPR32:$Rn, GPR32:$Rm))),
531 (MSUBWrrr GPR32:$Rn, GPR32:$Rm, WZR)>;
532 def : Pat<(i64 (ineg (mul GPR64:$Rn, GPR64:$Rm))),
533 (MSUBXrrr GPR64:$Rn, GPR64:$Rm, XZR)>;
534 } // AddedComplexity = 7
536 let AddedComplexity = 5 in {
537 def SMADDLrrr : WideMulAccum<0, 0b001, "smaddl", add, sext>;
538 def SMSUBLrrr : WideMulAccum<1, 0b001, "smsubl", sub, sext>;
539 def UMADDLrrr : WideMulAccum<0, 0b101, "umaddl", add, zext>;
540 def UMSUBLrrr : WideMulAccum<1, 0b101, "umsubl", sub, zext>;
542 def : Pat<(i64 (mul (sext GPR32:$Rn), (sext GPR32:$Rm))),
543 (SMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
544 def : Pat<(i64 (mul (zext GPR32:$Rn), (zext GPR32:$Rm))),
545 (UMADDLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
547 def : Pat<(i64 (ineg (mul (sext GPR32:$Rn), (sext GPR32:$Rm)))),
548 (SMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
549 def : Pat<(i64 (ineg (mul (zext GPR32:$Rn), (zext GPR32:$Rm)))),
550 (UMSUBLrrr GPR32:$Rn, GPR32:$Rm, XZR)>;
551 } // AddedComplexity = 5
553 def : MulAccumWAlias<"mul", MADDWrrr>;
554 def : MulAccumXAlias<"mul", MADDXrrr>;
555 def : MulAccumWAlias<"mneg", MSUBWrrr>;
556 def : MulAccumXAlias<"mneg", MSUBXrrr>;
557 def : WideMulAccumAlias<"smull", SMADDLrrr>;
558 def : WideMulAccumAlias<"smnegl", SMSUBLrrr>;
559 def : WideMulAccumAlias<"umull", UMADDLrrr>;
560 def : WideMulAccumAlias<"umnegl", UMSUBLrrr>;
563 def SMULHrr : MulHi<0b010, "smulh", mulhs>;
564 def UMULHrr : MulHi<0b110, "umulh", mulhu>;
567 def CRC32Brr : BaseCRC32<0, 0b00, 0, GPR32, int_arm64_crc32b, "crc32b">;
568 def CRC32Hrr : BaseCRC32<0, 0b01, 0, GPR32, int_arm64_crc32h, "crc32h">;
569 def CRC32Wrr : BaseCRC32<0, 0b10, 0, GPR32, int_arm64_crc32w, "crc32w">;
570 def CRC32Xrr : BaseCRC32<1, 0b11, 0, GPR64, int_arm64_crc32x, "crc32x">;
572 def CRC32CBrr : BaseCRC32<0, 0b00, 1, GPR32, int_arm64_crc32cb, "crc32cb">;
573 def CRC32CHrr : BaseCRC32<0, 0b01, 1, GPR32, int_arm64_crc32ch, "crc32ch">;
574 def CRC32CWrr : BaseCRC32<0, 0b10, 1, GPR32, int_arm64_crc32cw, "crc32cw">;
575 def CRC32CXrr : BaseCRC32<1, 0b11, 1, GPR64, int_arm64_crc32cx, "crc32cx">;
578 //===----------------------------------------------------------------------===//
579 // Logical instructions.
580 //===----------------------------------------------------------------------===//
583 defm ANDS : LogicalImmS<0b11, "ands", ARM64and_flag>;
584 defm AND : LogicalImm<0b00, "and", and>;
585 defm EOR : LogicalImm<0b10, "eor", xor>;
586 defm ORR : LogicalImm<0b01, "orr", or>;
588 def : InstAlias<"mov $dst, $imm", (ORRWri GPR32sp:$dst, WZR,
589 logical_imm32:$imm)>;
590 def : InstAlias<"mov $dst, $imm", (ORRXri GPR64sp:$dst, XZR,
591 logical_imm64:$imm)>;
595 defm ANDS : LogicalRegS<0b11, 0, "ands">;
596 defm BICS : LogicalRegS<0b11, 1, "bics">;
597 defm AND : LogicalReg<0b00, 0, "and", and>;
598 defm BIC : LogicalReg<0b00, 1, "bic",
599 BinOpFrag<(and node:$LHS, (not node:$RHS))>>;
600 defm EON : LogicalReg<0b10, 1, "eon",
601 BinOpFrag<(xor node:$LHS, (not node:$RHS))>>;
602 defm EOR : LogicalReg<0b10, 0, "eor", xor>;
603 defm ORN : LogicalReg<0b01, 1, "orn",
604 BinOpFrag<(or node:$LHS, (not node:$RHS))>>;
605 defm ORR : LogicalReg<0b01, 0, "orr", or>;
607 def : InstAlias<"mov $dst, $src", (ORRWrs GPR32:$dst, WZR, GPR32:$src, 0)>;
608 def : InstAlias<"mov $dst, $src",
609 (ADDWri GPR32sp:$dst, GPR32sp:$src, 0, 0)>;
610 def : InstAlias<"mov $dst, $src", (ORRXrs GPR64:$dst, XZR, GPR64:$src, 0)>;
611 def : InstAlias<"mov $dst, $src",
612 (ADDXri GPR64sp:$dst, GPR64sp:$src, 0, 0)>;
614 def : InstAlias<"tst $src1, $src2",
615 (ANDSWri WZR, GPR32:$src1, logical_imm32:$src2)>;
616 def : InstAlias<"tst $src1, $src2",
617 (ANDSXri XZR, GPR64:$src1, logical_imm64:$src2)>;
619 def : InstAlias<"tst $src1, $src2",
620 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, 0)>;
621 def : InstAlias<"tst $src1, $src2",
622 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, 0)>;
624 def : InstAlias<"tst $src1, $src2, $sh",
625 (ANDSWrs WZR, GPR32:$src1, GPR32:$src2, logical_shift:$sh)>;
626 def : InstAlias<"tst $src1, $src2, $sh",
627 (ANDSXrs XZR, GPR64:$src1, GPR64:$src2, logical_shift:$sh)>;
629 def : InstAlias<"mvn $Wd, $Wm",
630 (ORNWrs GPR32:$Wd, WZR, GPR32:$Wm, 0)>;
631 def : InstAlias<"mvn $Xd, $Xm",
632 (ORNXrs GPR64:$Xd, XZR, GPR64:$Xm, 0)>;
634 def : Pat<(not GPR32:$Wm), (ORNWrr WZR, GPR32:$Wm)>;
635 def : Pat<(not GPR64:$Xm), (ORNXrr XZR, GPR64:$Xm)>;
638 //===----------------------------------------------------------------------===//
639 // One operand data processing instructions.
640 //===----------------------------------------------------------------------===//
642 defm CLS : OneOperandData<0b101, "cls">;
643 defm CLZ : OneOperandData<0b100, "clz", ctlz>;
644 defm RBIT : OneOperandData<0b000, "rbit">;
645 def REV16Wr : OneWRegData<0b001, "rev16",
646 UnOpFrag<(rotr (bswap node:$LHS), (i32 16))>>;
647 def REV16Xr : OneXRegData<0b001, "rev16",
648 UnOpFrag<(rotr (bswap node:$LHS), (i64 16))>>;
650 def : Pat<(cttz GPR32:$Rn),
651 (CLZWr (RBITWr GPR32:$Rn))>;
652 def : Pat<(cttz GPR64:$Rn),
653 (CLZXr (RBITXr GPR64:$Rn))>;
655 // Unlike the other one operand instructions, the instructions with the "rev"
656 // mnemonic do *not* just different in the size bit, but actually use different
657 // opcode bits for the different sizes.
658 def REVWr : OneWRegData<0b010, "rev", bswap>;
659 def REVXr : OneXRegData<0b011, "rev", bswap>;
660 def REV32Xr : OneXRegData<0b010, "rev32",
661 UnOpFrag<(rotr (bswap node:$LHS), (i64 32))>>;
663 //===----------------------------------------------------------------------===//
664 // Bitfield immediate extraction instruction.
665 //===----------------------------------------------------------------------===//
666 let neverHasSideEffects = 1 in
667 defm EXTR : ExtractImm<"extr">;
668 def : InstAlias<"ror $dst, $src, $shift",
669 (EXTRWrri GPR32:$dst, GPR32:$src, GPR32:$src, imm0_31:$shift)>;
670 def : InstAlias<"ror $dst, $src, $shift",
671 (EXTRXrri GPR64:$dst, GPR64:$src, GPR64:$src, imm0_63:$shift)>;
673 def : Pat<(rotr GPR32:$Rn, (i32 imm0_31:$imm)),
674 (EXTRWrri GPR32:$Rn, GPR32:$Rn, imm0_31:$imm)>;
675 def : Pat<(rotr GPR64:$Rn, (i64 imm0_63:$imm)),
676 (EXTRXrri GPR64:$Rn, GPR64:$Rn, imm0_63:$imm)>;
678 //===----------------------------------------------------------------------===//
679 // Other bitfield immediate instructions.
680 //===----------------------------------------------------------------------===//
681 let neverHasSideEffects = 1 in {
682 defm BFM : BitfieldImmWith2RegArgs<0b01, "bfm">;
683 defm SBFM : BitfieldImm<0b00, "sbfm">;
684 defm UBFM : BitfieldImm<0b10, "ubfm">;
687 def i32shift_a : Operand<i32>, SDNodeXForm<imm, [{
688 uint64_t enc = (32 - N->getZExtValue()) & 0x1f;
689 return CurDAG->getTargetConstant(enc, MVT::i32);
692 def i32shift_b : Operand<i32>, SDNodeXForm<imm, [{
693 uint64_t enc = 31 - N->getZExtValue();
694 return CurDAG->getTargetConstant(enc, MVT::i32);
697 // min(7, 31 - shift_amt)
698 def i32shift_sext_i8 : Operand<i32>, SDNodeXForm<imm, [{
699 uint64_t enc = 31 - N->getZExtValue();
700 enc = enc > 7 ? 7 : enc;
701 return CurDAG->getTargetConstant(enc, MVT::i32);
704 // min(15, 31 - shift_amt)
705 def i32shift_sext_i16 : Operand<i32>, SDNodeXForm<imm, [{
706 uint64_t enc = 31 - N->getZExtValue();
707 enc = enc > 15 ? 15 : enc;
708 return CurDAG->getTargetConstant(enc, MVT::i32);
711 def i64shift_a : Operand<i64>, SDNodeXForm<imm, [{
712 uint64_t enc = (64 - N->getZExtValue()) & 0x3f;
713 return CurDAG->getTargetConstant(enc, MVT::i64);
716 def i64shift_b : Operand<i64>, SDNodeXForm<imm, [{
717 uint64_t enc = 63 - N->getZExtValue();
718 return CurDAG->getTargetConstant(enc, MVT::i64);
721 // min(7, 63 - shift_amt)
722 def i64shift_sext_i8 : Operand<i64>, SDNodeXForm<imm, [{
723 uint64_t enc = 63 - N->getZExtValue();
724 enc = enc > 7 ? 7 : enc;
725 return CurDAG->getTargetConstant(enc, MVT::i64);
728 // min(15, 63 - shift_amt)
729 def i64shift_sext_i16 : Operand<i64>, SDNodeXForm<imm, [{
730 uint64_t enc = 63 - N->getZExtValue();
731 enc = enc > 15 ? 15 : enc;
732 return CurDAG->getTargetConstant(enc, MVT::i64);
735 // min(31, 63 - shift_amt)
736 def i64shift_sext_i32 : Operand<i64>, SDNodeXForm<imm, [{
737 uint64_t enc = 63 - N->getZExtValue();
738 enc = enc > 31 ? 31 : enc;
739 return CurDAG->getTargetConstant(enc, MVT::i64);
742 def : Pat<(shl GPR32:$Rn, (i32 imm0_31:$imm)),
743 (UBFMWri GPR32:$Rn, (i32 (i32shift_a imm0_31:$imm)),
744 (i32 (i32shift_b imm0_31:$imm)))>;
745 def : Pat<(shl GPR64:$Rn, (i64 imm0_63:$imm)),
746 (UBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
747 (i64 (i64shift_b imm0_63:$imm)))>;
749 let AddedComplexity = 10 in {
750 def : Pat<(sra GPR32:$Rn, (i32 imm0_31:$imm)),
751 (SBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
752 def : Pat<(sra GPR64:$Rn, (i64 imm0_63:$imm)),
753 (SBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
756 def : InstAlias<"asr $dst, $src, $shift",
757 (SBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
758 def : InstAlias<"asr $dst, $src, $shift",
759 (SBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
760 def : InstAlias<"sxtb $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
761 def : InstAlias<"sxtb $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
762 def : InstAlias<"sxth $dst, $src", (SBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
763 def : InstAlias<"sxth $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
764 def : InstAlias<"sxtw $dst, $src", (SBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
766 def : Pat<(srl GPR32:$Rn, (i32 imm0_31:$imm)),
767 (UBFMWri GPR32:$Rn, imm0_31:$imm, 31)>;
768 def : Pat<(srl GPR64:$Rn, (i64 imm0_63:$imm)),
769 (UBFMXri GPR64:$Rn, imm0_63:$imm, 63)>;
771 def : InstAlias<"lsr $dst, $src, $shift",
772 (UBFMWri GPR32:$dst, GPR32:$src, imm0_31:$shift, 31)>;
773 def : InstAlias<"lsr $dst, $src, $shift",
774 (UBFMXri GPR64:$dst, GPR64:$src, imm0_63:$shift, 63)>;
775 def : InstAlias<"uxtb $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 7)>;
776 def : InstAlias<"uxtb $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 7)>;
777 def : InstAlias<"uxth $dst, $src", (UBFMWri GPR32:$dst, GPR32:$src, 0, 15)>;
778 def : InstAlias<"uxth $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 15)>;
779 def : InstAlias<"uxtw $dst, $src", (UBFMXri GPR64:$dst, GPR64:$src, 0, 31)>;
781 //===----------------------------------------------------------------------===//
782 // Conditionally set flags instructions.
783 //===----------------------------------------------------------------------===//
784 defm CCMN : CondSetFlagsImm<0, "ccmn">;
785 defm CCMP : CondSetFlagsImm<1, "ccmp">;
787 defm CCMN : CondSetFlagsReg<0, "ccmn">;
788 defm CCMP : CondSetFlagsReg<1, "ccmp">;
790 //===----------------------------------------------------------------------===//
791 // Conditional select instructions.
792 //===----------------------------------------------------------------------===//
793 defm CSEL : CondSelect<0, 0b00, "csel">;
795 def inc : PatFrag<(ops node:$in), (add node:$in, 1)>;
796 defm CSINC : CondSelectOp<0, 0b01, "csinc", inc>;
797 defm CSINV : CondSelectOp<1, 0b00, "csinv", not>;
798 defm CSNEG : CondSelectOp<1, 0b01, "csneg", ineg>;
800 def : Pat<(ARM64csinv GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
801 (CSINVWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
802 def : Pat<(ARM64csinv GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
803 (CSINVXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
804 def : Pat<(ARM64csneg GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
805 (CSNEGWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
806 def : Pat<(ARM64csneg GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
807 (CSNEGXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
808 def : Pat<(ARM64csinc GPR32:$tval, GPR32:$fval, (i32 imm:$cc), CPSR),
809 (CSINCWr GPR32:$tval, GPR32:$fval, (i32 imm:$cc))>;
810 def : Pat<(ARM64csinc GPR64:$tval, GPR64:$fval, (i32 imm:$cc), CPSR),
811 (CSINCXr GPR64:$tval, GPR64:$fval, (i32 imm:$cc))>;
813 def : Pat<(ARM64csel (i32 0), (i32 1), (i32 imm:$cc), CPSR),
814 (CSINCWr WZR, WZR, (i32 imm:$cc))>;
815 def : Pat<(ARM64csel (i64 0), (i64 1), (i32 imm:$cc), CPSR),
816 (CSINCXr XZR, XZR, (i32 imm:$cc))>;
817 def : Pat<(ARM64csel (i32 0), (i32 -1), (i32 imm:$cc), CPSR),
818 (CSINVWr WZR, WZR, (i32 imm:$cc))>;
819 def : Pat<(ARM64csel (i64 0), (i64 -1), (i32 imm:$cc), CPSR),
820 (CSINVXr XZR, XZR, (i32 imm:$cc))>;
822 // The inverse of the condition code from the alias instruction is what is used
823 // in the aliased instruction. The parser all ready inverts the condition code
824 // for these aliases.
825 // FIXME: Is this the correct way to handle these aliases?
826 def : InstAlias<"cset $dst, $cc", (CSINCWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
827 def : InstAlias<"cset $dst, $cc", (CSINCXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
829 def : InstAlias<"csetm $dst, $cc", (CSINVWr GPR32:$dst, WZR, WZR, ccode:$cc)>;
830 def : InstAlias<"csetm $dst, $cc", (CSINVXr GPR64:$dst, XZR, XZR, ccode:$cc)>;
832 def : InstAlias<"cinc $dst, $src, $cc",
833 (CSINCWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
834 def : InstAlias<"cinc $dst, $src, $cc",
835 (CSINCXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
837 def : InstAlias<"cinv $dst, $src, $cc",
838 (CSINVWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
839 def : InstAlias<"cinv $dst, $src, $cc",
840 (CSINVXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
842 def : InstAlias<"cneg $dst, $src, $cc",
843 (CSNEGWr GPR32:$dst, GPR32:$src, GPR32:$src, ccode:$cc)>;
844 def : InstAlias<"cneg $dst, $src, $cc",
845 (CSNEGXr GPR64:$dst, GPR64:$src, GPR64:$src, ccode:$cc)>;
847 //===----------------------------------------------------------------------===//
848 // PC-relative instructions.
849 //===----------------------------------------------------------------------===//
850 let isReMaterializable = 1 in {
851 let neverHasSideEffects = 1, mayStore = 0, mayLoad = 0 in {
852 def ADR : ADRI<0, "adr", adrlabel, []>;
853 } // neverHasSideEffects = 1
855 def ADRP : ADRI<1, "adrp", adrplabel,
856 [(set GPR64:$Xd, (ARM64adrp tglobaladdr:$label))]>;
857 } // isReMaterializable = 1
859 // page address of a constant pool entry, block address
860 def : Pat<(ARM64adrp tconstpool:$cp), (ADRP tconstpool:$cp)>;
861 def : Pat<(ARM64adrp tblockaddress:$cp), (ADRP tblockaddress:$cp)>;
863 //===----------------------------------------------------------------------===//
864 // Unconditional branch (register) instructions.
865 //===----------------------------------------------------------------------===//
867 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
868 def RET : BranchReg<0b0010, "ret", []>;
869 def DRPS : SpecialReturn<0b0101, "drps">;
870 def ERET : SpecialReturn<0b0100, "eret">;
871 } // isReturn = 1, isTerminator = 1, isBarrier = 1
873 // Default to the LR register.
874 def : InstAlias<"ret", (RET LR)>;
876 let isCall = 1, Defs = [LR], Uses = [SP] in {
877 def BLR : BranchReg<0b0001, "blr", [(ARM64call GPR64:$Rn)]>;
880 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
881 def BR : BranchReg<0b0000, "br", [(brind GPR64:$Rn)]>;
882 } // isBranch, isTerminator, isBarrier, isIndirectBranch
884 // Create a separate pseudo-instruction for codegen to use so that we don't
885 // flag lr as used in every function. It'll be restored before the RET by the
886 // epilogue if it's legitimately used.
887 def RET_ReallyLR : Pseudo<(outs), (ins), [(ARM64retflag)]> {
888 let isTerminator = 1;
893 // This is a directive-like pseudo-instruction. The purpose is to insert an
894 // R_AARCH64_TLSDESC_CALL relocation at the offset of the following instruction
895 // (which in the usual case is a BLR).
896 let hasSideEffects = 1 in
897 def TLSDESCCALL : Pseudo<(outs), (ins i64imm:$sym), []> {
898 let AsmString = ".tlsdesccall $sym";
901 // Pseudo-instruction representing a BLR with attached TLSDESC relocation. It
902 // gets expanded to two MCInsts during lowering.
903 let isCall = 1, Defs = [LR] in
905 : Pseudo<(outs), (ins GPR64:$dest, i64imm:$sym),
906 [(ARM64tlsdesc_call GPR64:$dest, tglobaltlsaddr:$sym)]>;
908 def : Pat<(ARM64tlsdesc_call GPR64:$dest, texternalsym:$sym),
909 (TLSDESC_BLR GPR64:$dest, texternalsym:$sym)>;
910 //===----------------------------------------------------------------------===//
911 // Conditional branch (immediate) instruction.
912 //===----------------------------------------------------------------------===//
913 def Bcc : BranchCond;
915 //===----------------------------------------------------------------------===//
916 // Compare-and-branch instructions.
917 //===----------------------------------------------------------------------===//
918 defm CBZ : CmpBranch<0, "cbz", ARM64cbz>;
919 defm CBNZ : CmpBranch<1, "cbnz", ARM64cbnz>;
921 //===----------------------------------------------------------------------===//
922 // Test-bit-and-branch instructions.
923 //===----------------------------------------------------------------------===//
924 def TBZ : TestBranch<0, "tbz", ARM64tbz>;
925 def TBNZ : TestBranch<1, "tbnz", ARM64tbnz>;
927 //===----------------------------------------------------------------------===//
928 // Unconditional branch (immediate) instructions.
929 //===----------------------------------------------------------------------===//
930 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
931 def B : BranchImm<0, "b", [(br bb:$addr)]>;
932 } // isBranch, isTerminator, isBarrier
934 let isCall = 1, Defs = [LR], Uses = [SP] in {
935 def BL : CallImm<1, "bl", [(ARM64call tglobaladdr:$addr)]>;
937 def : Pat<(ARM64call texternalsym:$func), (BL texternalsym:$func)>;
939 //===----------------------------------------------------------------------===//
940 // Exception generation instructions.
941 //===----------------------------------------------------------------------===//
942 def BRK : ExceptionGeneration<0b001, 0b00, "brk">;
943 def DCPS1 : ExceptionGeneration<0b101, 0b01, "dcps1">;
944 def DCPS2 : ExceptionGeneration<0b101, 0b10, "dcps2">;
945 def DCPS3 : ExceptionGeneration<0b101, 0b11, "dcps3">;
946 def HLT : ExceptionGeneration<0b010, 0b00, "hlt">;
947 def HVC : ExceptionGeneration<0b000, 0b10, "hvc">;
948 def SMC : ExceptionGeneration<0b000, 0b11, "smc">;
949 def SVC : ExceptionGeneration<0b000, 0b01, "svc">;
951 // DCPSn defaults to an immediate operand of zero if unspecified.
952 def : InstAlias<"dcps1", (DCPS1 0)>;
953 def : InstAlias<"dcps2", (DCPS2 0)>;
954 def : InstAlias<"dcps3", (DCPS3 0)>;
956 //===----------------------------------------------------------------------===//
957 // Load instructions.
958 //===----------------------------------------------------------------------===//
960 // Pair (indexed, offset)
961 def LDPWi : LoadPairOffset<0b00, 0, GPR32, am_indexed32simm7, "ldp">;
962 def LDPXi : LoadPairOffset<0b10, 0, GPR64, am_indexed64simm7, "ldp">;
963 def LDPSi : LoadPairOffset<0b00, 1, FPR32, am_indexed32simm7, "ldp">;
964 def LDPDi : LoadPairOffset<0b01, 1, FPR64, am_indexed64simm7, "ldp">;
965 def LDPQi : LoadPairOffset<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
967 def LDPSWi : LoadPairOffset<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
969 // Pair (pre-indexed)
970 def LDPWpre : LoadPairPreIdx<0b00, 0, GPR32, am_indexed32simm7, "ldp">;
971 def LDPXpre : LoadPairPreIdx<0b10, 0, GPR64, am_indexed64simm7, "ldp">;
972 def LDPSpre : LoadPairPreIdx<0b00, 1, FPR32, am_indexed32simm7, "ldp">;
973 def LDPDpre : LoadPairPreIdx<0b01, 1, FPR64, am_indexed64simm7, "ldp">;
974 def LDPQpre : LoadPairPreIdx<0b10, 1, FPR128, am_indexed128simm7, "ldp">;
976 def LDPSWpre : LoadPairPreIdx<0b01, 0, GPR64, am_indexed32simm7, "ldpsw">;
978 // Pair (post-indexed)
979 def LDPWpost : LoadPairPostIdx<0b00, 0, GPR32, simm7s4, "ldp">;
980 def LDPXpost : LoadPairPostIdx<0b10, 0, GPR64, simm7s8, "ldp">;
981 def LDPSpost : LoadPairPostIdx<0b00, 1, FPR32, simm7s4, "ldp">;
982 def LDPDpost : LoadPairPostIdx<0b01, 1, FPR64, simm7s8, "ldp">;
983 def LDPQpost : LoadPairPostIdx<0b10, 1, FPR128, simm7s16, "ldp">;
985 def LDPSWpost : LoadPairPostIdx<0b01, 0, GPR64, simm7s4, "ldpsw">;
988 // Pair (no allocate)
989 def LDNPWi : LoadPairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "ldnp">;
990 def LDNPXi : LoadPairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "ldnp">;
991 def LDNPSi : LoadPairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "ldnp">;
992 def LDNPDi : LoadPairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "ldnp">;
993 def LDNPQi : LoadPairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "ldnp">;
999 let AddedComplexity = 10 in {
1001 def LDRBBro : Load8RO<0b00, 0, 0b01, GPR32, "ldrb",
1002 [(set GPR32:$Rt, (zextloadi8 ro_indexed8:$addr))]>;
1003 def LDRHHro : Load16RO<0b01, 0, 0b01, GPR32, "ldrh",
1004 [(set GPR32:$Rt, (zextloadi16 ro_indexed16:$addr))]>;
1005 def LDRWro : Load32RO<0b10, 0, 0b01, GPR32, "ldr",
1006 [(set GPR32:$Rt, (load ro_indexed32:$addr))]>;
1007 def LDRXro : Load64RO<0b11, 0, 0b01, GPR64, "ldr",
1008 [(set GPR64:$Rt, (load ro_indexed64:$addr))]>;
1011 def LDRBro : Load8RO<0b00, 1, 0b01, FPR8, "ldr",
1012 [(set FPR8:$Rt, (load ro_indexed8:$addr))]>;
1013 def LDRHro : Load16RO<0b01, 1, 0b01, FPR16, "ldr",
1014 [(set FPR16:$Rt, (load ro_indexed16:$addr))]>;
1015 def LDRSro : Load32RO<0b10, 1, 0b01, FPR32, "ldr",
1016 [(set (f32 FPR32:$Rt), (load ro_indexed32:$addr))]>;
1017 def LDRDro : Load64RO<0b11, 1, 0b01, FPR64, "ldr",
1018 [(set (f64 FPR64:$Rt), (load ro_indexed64:$addr))]>;
1019 def LDRQro : Load128RO<0b00, 1, 0b11, FPR128, "ldr", []> {
1023 // For regular load, we do not have any alignment requirement.
1024 // Thus, it is safe to directly map the vector loads with interesting
1025 // addressing modes.
1026 // FIXME: We could do the same for bitconvert to floating point vectors.
1027 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1028 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1029 (LDRBro ro_indexed8:$addr), bsub)>;
1030 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 ro_indexed8:$addr)))),
1031 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1032 (LDRBro ro_indexed8:$addr), bsub)>;
1033 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1034 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1035 (LDRHro ro_indexed16:$addr), hsub)>;
1036 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 ro_indexed16:$addr)))),
1037 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1038 (LDRHro ro_indexed16:$addr), hsub)>;
1039 def : Pat <(v2i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1040 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1041 (LDRSro ro_indexed32:$addr), ssub)>;
1042 def : Pat <(v4i32 (scalar_to_vector (i32 (load ro_indexed32:$addr)))),
1043 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1044 (LDRSro ro_indexed32:$addr), ssub)>;
1045 def : Pat <(v1i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1046 (LDRDro ro_indexed64:$addr)>;
1047 def : Pat <(v2i64 (scalar_to_vector (i64 (load ro_indexed64:$addr)))),
1048 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1049 (LDRDro ro_indexed64:$addr), dsub)>;
1051 // Match all load 64 bits width whose type is compatible with FPR64
1052 def : Pat<(v2f32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1053 def : Pat<(v1f64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1054 def : Pat<(v8i8 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1055 def : Pat<(v4i16 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1056 def : Pat<(v2i32 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1057 def : Pat<(v1i64 (load ro_indexed64:$addr)), (LDRDro ro_indexed64:$addr)>;
1059 // Match all load 128 bits width whose type is compatible with FPR128
1060 def : Pat<(v4f32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1061 def : Pat<(v2f64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1062 def : Pat<(v16i8 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1063 def : Pat<(v8i16 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1064 def : Pat<(v4i32 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1065 def : Pat<(v2i64 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1066 def : Pat<(f128 (load ro_indexed128:$addr)), (LDRQro ro_indexed128:$addr)>;
1068 // Load sign-extended half-word
1069 def LDRSHWro : Load16RO<0b01, 0, 0b11, GPR32, "ldrsh",
1070 [(set GPR32:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1071 def LDRSHXro : Load16RO<0b01, 0, 0b10, GPR64, "ldrsh",
1072 [(set GPR64:$Rt, (sextloadi16 ro_indexed16:$addr))]>;
1074 // Load sign-extended byte
1075 def LDRSBWro : Load8RO<0b00, 0, 0b11, GPR32, "ldrsb",
1076 [(set GPR32:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1077 def LDRSBXro : Load8RO<0b00, 0, 0b10, GPR64, "ldrsb",
1078 [(set GPR64:$Rt, (sextloadi8 ro_indexed8:$addr))]>;
1080 // Load sign-extended word
1081 def LDRSWro : Load32RO<0b10, 0, 0b10, GPR64, "ldrsw",
1082 [(set GPR64:$Rt, (sextloadi32 ro_indexed32:$addr))]>;
1085 def PRFMro : PrefetchRO<0b11, 0, 0b10, "prfm",
1086 [(ARM64Prefetch imm:$Rt, ro_indexed64:$addr)]>;
1089 def : Pat<(i64 (zextloadi8 ro_indexed8:$addr)),
1090 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1091 def : Pat<(i64 (zextloadi16 ro_indexed16:$addr)),
1092 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1094 // zextloadi1 -> zextloadi8
1095 def : Pat<(i32 (zextloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1096 def : Pat<(i64 (zextloadi1 ro_indexed8:$addr)),
1097 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1099 // extload -> zextload
1100 def : Pat<(i32 (extloadi16 ro_indexed16:$addr)), (LDRHHro ro_indexed16:$addr)>;
1101 def : Pat<(i32 (extloadi8 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1102 def : Pat<(i32 (extloadi1 ro_indexed8:$addr)), (LDRBBro ro_indexed8:$addr)>;
1103 def : Pat<(i64 (extloadi32 ro_indexed32:$addr)),
1104 (SUBREG_TO_REG (i64 0), (LDRWro ro_indexed32:$addr), sub_32)>;
1105 def : Pat<(i64 (extloadi16 ro_indexed16:$addr)),
1106 (SUBREG_TO_REG (i64 0), (LDRHHro ro_indexed16:$addr), sub_32)>;
1107 def : Pat<(i64 (extloadi8 ro_indexed8:$addr)),
1108 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1109 def : Pat<(i64 (extloadi1 ro_indexed8:$addr)),
1110 (SUBREG_TO_REG (i64 0), (LDRBBro ro_indexed8:$addr), sub_32)>;
1112 } // AddedComplexity = 10
1115 // (unsigned immediate)
1117 def LDRXui : LoadUI<0b11, 0, 0b01, GPR64, am_indexed64, "ldr",
1118 [(set GPR64:$Rt, (load am_indexed64:$addr))]>;
1119 def LDRWui : LoadUI<0b10, 0, 0b01, GPR32, am_indexed32, "ldr",
1120 [(set GPR32:$Rt, (load am_indexed32:$addr))]>;
1121 def LDRBui : LoadUI<0b00, 1, 0b01, FPR8, am_indexed8, "ldr",
1122 [(set FPR8:$Rt, (load am_indexed8:$addr))]>;
1123 def LDRHui : LoadUI<0b01, 1, 0b01, FPR16, am_indexed16, "ldr",
1124 [(set FPR16:$Rt, (load am_indexed16:$addr))]>;
1125 def LDRSui : LoadUI<0b10, 1, 0b01, FPR32, am_indexed32, "ldr",
1126 [(set (f32 FPR32:$Rt), (load am_indexed32:$addr))]>;
1127 def LDRDui : LoadUI<0b11, 1, 0b01, FPR64, am_indexed64, "ldr",
1128 [(set (f64 FPR64:$Rt), (load am_indexed64:$addr))]>;
1129 def LDRQui : LoadUI<0b00, 1, 0b11, FPR128, am_indexed128, "ldr",
1130 [(set (f128 FPR128:$Rt), (load am_indexed128:$addr))]>;
1132 // For regular load, we do not have any alignment requirement.
1133 // Thus, it is safe to directly map the vector loads with interesting
1134 // addressing modes.
1135 // FIXME: We could do the same for bitconvert to floating point vectors.
1136 def : Pat <(v8i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1137 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1138 (LDRBui am_indexed8:$addr), bsub)>;
1139 def : Pat <(v16i8 (scalar_to_vector (i32 (extloadi8 am_indexed8:$addr)))),
1140 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1141 (LDRBui am_indexed8:$addr), bsub)>;
1142 def : Pat <(v4i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1143 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1144 (LDRHui am_indexed16:$addr), hsub)>;
1145 def : Pat <(v8i16 (scalar_to_vector (i32 (extloadi16 am_indexed16:$addr)))),
1146 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1147 (LDRHui am_indexed16:$addr), hsub)>;
1148 def : Pat <(v2i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1149 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1150 (LDRSui am_indexed32:$addr), ssub)>;
1151 def : Pat <(v4i32 (scalar_to_vector (i32 (load am_indexed32:$addr)))),
1152 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1153 (LDRSui am_indexed32:$addr), ssub)>;
1154 def : Pat <(v1i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1155 (LDRDui am_indexed64:$addr)>;
1156 def : Pat <(v2i64 (scalar_to_vector (i64 (load am_indexed64:$addr)))),
1157 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
1158 (LDRDui am_indexed64:$addr), dsub)>;
1160 // Match all load 64 bits width whose type is compatible with FPR64
1161 def : Pat<(v2f32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1162 def : Pat<(v1f64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1163 def : Pat<(v8i8 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1164 def : Pat<(v4i16 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1165 def : Pat<(v2i32 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1166 def : Pat<(v1i64 (load am_indexed64:$addr)), (LDRDui am_indexed64:$addr)>;
1168 // Match all load 128 bits width whose type is compatible with FPR128
1169 def : Pat<(v4f32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1170 def : Pat<(v2f64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1171 def : Pat<(v16i8 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1172 def : Pat<(v8i16 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1173 def : Pat<(v4i32 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1174 def : Pat<(v2i64 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1175 def : Pat<(f128 (load am_indexed128:$addr)), (LDRQui am_indexed128:$addr)>;
1177 def LDRHHui : LoadUI<0b01, 0, 0b01, GPR32, am_indexed16, "ldrh",
1178 [(set GPR32:$Rt, (zextloadi16 am_indexed16:$addr))]>;
1179 def LDRBBui : LoadUI<0b00, 0, 0b01, GPR32, am_indexed8, "ldrb",
1180 [(set GPR32:$Rt, (zextloadi8 am_indexed8:$addr))]>;
1182 def : Pat<(i64 (zextloadi8 am_indexed8:$addr)),
1183 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1184 def : Pat<(i64 (zextloadi16 am_indexed16:$addr)),
1185 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1187 // zextloadi1 -> zextloadi8
1188 def : Pat<(i32 (zextloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1189 def : Pat<(i64 (zextloadi1 am_indexed8:$addr)),
1190 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1192 // extload -> zextload
1193 def : Pat<(i32 (extloadi16 am_indexed16:$addr)), (LDRHHui am_indexed16:$addr)>;
1194 def : Pat<(i32 (extloadi8 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1195 def : Pat<(i32 (extloadi1 am_indexed8:$addr)), (LDRBBui am_indexed8:$addr)>;
1196 def : Pat<(i64 (extloadi32 am_indexed32:$addr)),
1197 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1198 def : Pat<(i64 (extloadi16 am_indexed16:$addr)),
1199 (SUBREG_TO_REG (i64 0), (LDRHHui am_indexed16:$addr), sub_32)>;
1200 def : Pat<(i64 (extloadi8 am_indexed8:$addr)),
1201 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1202 def : Pat<(i64 (extloadi1 am_indexed8:$addr)),
1203 (SUBREG_TO_REG (i64 0), (LDRBBui am_indexed8:$addr), sub_32)>;
1205 // load sign-extended half-word
1206 def LDRSHWui : LoadUI<0b01, 0, 0b11, GPR32, am_indexed16, "ldrsh",
1207 [(set GPR32:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1208 def LDRSHXui : LoadUI<0b01, 0, 0b10, GPR64, am_indexed16, "ldrsh",
1209 [(set GPR64:$Rt, (sextloadi16 am_indexed16:$addr))]>;
1211 // load sign-extended byte
1212 def LDRSBWui : LoadUI<0b00, 0, 0b11, GPR32, am_indexed8, "ldrsb",
1213 [(set GPR32:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1214 def LDRSBXui : LoadUI<0b00, 0, 0b10, GPR64, am_indexed8, "ldrsb",
1215 [(set GPR64:$Rt, (sextloadi8 am_indexed8:$addr))]>;
1217 // load sign-extended word
1218 def LDRSWui : LoadUI<0b10, 0, 0b10, GPR64, am_indexed32, "ldrsw",
1219 [(set GPR64:$Rt, (sextloadi32 am_indexed32:$addr))]>;
1221 // load zero-extended word
1222 def : Pat<(i64 (zextloadi32 am_indexed32:$addr)),
1223 (SUBREG_TO_REG (i64 0), (LDRWui am_indexed32:$addr), sub_32)>;
1226 def PRFMui : PrefetchUI<0b11, 0, 0b10, "prfm",
1227 [(ARM64Prefetch imm:$Rt, am_indexed64:$addr)]>;
1231 def LDRWl : LoadLiteral<0b00, 0, GPR32, "ldr">;
1232 def LDRXl : LoadLiteral<0b01, 0, GPR64, "ldr">;
1233 def LDRSl : LoadLiteral<0b00, 1, FPR32, "ldr">;
1234 def LDRDl : LoadLiteral<0b01, 1, FPR64, "ldr">;
1235 def LDRQl : LoadLiteral<0b10, 1, FPR128, "ldr">;
1237 // load sign-extended word
1238 def LDRSWl : LoadLiteral<0b10, 0, GPR64, "ldrsw">;
1241 def PRFMl : PrefetchLiteral<0b11, 0, "prfm", []>;
1242 // [(ARM64Prefetch imm:$Rt, tglobaladdr:$label)]>;
1245 // (unscaled immediate)
1246 def LDURXi : LoadUnscaled<0b11, 0, 0b01, GPR64, am_unscaled64, "ldur",
1247 [(set GPR64:$Rt, (load am_unscaled64:$addr))]>;
1248 def LDURWi : LoadUnscaled<0b10, 0, 0b01, GPR32, am_unscaled32, "ldur",
1249 [(set GPR32:$Rt, (load am_unscaled32:$addr))]>;
1250 def LDURBi : LoadUnscaled<0b00, 1, 0b01, FPR8, am_unscaled8, "ldur",
1251 [(set FPR8:$Rt, (load am_unscaled8:$addr))]>;
1252 def LDURHi : LoadUnscaled<0b01, 1, 0b01, FPR16, am_unscaled16, "ldur",
1253 [(set FPR16:$Rt, (load am_unscaled16:$addr))]>;
1254 def LDURSi : LoadUnscaled<0b10, 1, 0b01, FPR32, am_unscaled32, "ldur",
1255 [(set (f32 FPR32:$Rt), (load am_unscaled32:$addr))]>;
1256 def LDURDi : LoadUnscaled<0b11, 1, 0b01, FPR64, am_unscaled64, "ldur",
1257 [(set (f64 FPR64:$Rt), (load am_unscaled64:$addr))]>;
1258 def LDURQi : LoadUnscaled<0b00, 1, 0b11, FPR128, am_unscaled128, "ldur",
1259 [(set (v2f64 FPR128:$Rt), (load am_unscaled128:$addr))]>;
1262 : LoadUnscaled<0b01, 0, 0b01, GPR32, am_unscaled16, "ldurh",
1263 [(set GPR32:$Rt, (zextloadi16 am_unscaled16:$addr))]>;
1265 : LoadUnscaled<0b00, 0, 0b01, GPR32, am_unscaled8, "ldurb",
1266 [(set GPR32:$Rt, (zextloadi8 am_unscaled8:$addr))]>;
1268 // Match all load 64 bits width whose type is compatible with FPR64
1269 def : Pat<(v2f32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1270 def : Pat<(v1f64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1271 def : Pat<(v8i8 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1272 def : Pat<(v4i16 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1273 def : Pat<(v2i32 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1274 def : Pat<(v1i64 (load am_unscaled64:$addr)), (LDURDi am_unscaled64:$addr)>;
1276 // Match all load 128 bits width whose type is compatible with FPR128
1277 def : Pat<(v4f32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1278 def : Pat<(v2f64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1279 def : Pat<(v16i8 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1280 def : Pat<(v8i16 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1281 def : Pat<(v4i32 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1282 def : Pat<(v2i64 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1283 def : Pat<(f128 (load am_unscaled128:$addr)), (LDURQi am_unscaled128:$addr)>;
1286 def : Pat<(i32 (extloadi16 am_unscaled16:$addr)), (LDURHHi am_unscaled16:$addr)>;
1287 def : Pat<(i32 (extloadi8 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1288 def : Pat<(i32 (extloadi1 am_unscaled8:$addr)), (LDURBBi am_unscaled8:$addr)>;
1289 def : Pat<(i64 (extloadi32 am_unscaled32:$addr)),
1290 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1291 def : Pat<(i64 (extloadi16 am_unscaled16:$addr)),
1292 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1293 def : Pat<(i64 (extloadi8 am_unscaled8:$addr)),
1294 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1295 def : Pat<(i64 (extloadi1 am_unscaled8:$addr)),
1296 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1298 def : Pat<(i32 (zextloadi16 am_unscaled16:$addr)),
1299 (LDURHHi am_unscaled16:$addr)>;
1300 def : Pat<(i32 (zextloadi8 am_unscaled8:$addr)),
1301 (LDURBBi am_unscaled8:$addr)>;
1302 def : Pat<(i32 (zextloadi1 am_unscaled8:$addr)),
1303 (LDURBBi am_unscaled8:$addr)>;
1304 def : Pat<(i64 (zextloadi32 am_unscaled32:$addr)),
1305 (SUBREG_TO_REG (i64 0), (LDURWi am_unscaled32:$addr), sub_32)>;
1306 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1307 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1308 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1309 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1310 def : Pat<(i64 (zextloadi1 am_unscaled8:$addr)),
1311 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1315 // LDR mnemonics fall back to LDUR for negative or unaligned offsets.
1317 // Define new assembler match classes as we want to only match these when
1318 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1319 // associate a DiagnosticType either, as we want the diagnostic for the
1320 // canonical form (the scaled operand) to take precedence.
1321 def MemoryUnscaledFB8Operand : AsmOperandClass {
1322 let Name = "MemoryUnscaledFB8";
1323 let RenderMethod = "addMemoryUnscaledOperands";
1325 def MemoryUnscaledFB16Operand : AsmOperandClass {
1326 let Name = "MemoryUnscaledFB16";
1327 let RenderMethod = "addMemoryUnscaledOperands";
1329 def MemoryUnscaledFB32Operand : AsmOperandClass {
1330 let Name = "MemoryUnscaledFB32";
1331 let RenderMethod = "addMemoryUnscaledOperands";
1333 def MemoryUnscaledFB64Operand : AsmOperandClass {
1334 let Name = "MemoryUnscaledFB64";
1335 let RenderMethod = "addMemoryUnscaledOperands";
1337 def MemoryUnscaledFB128Operand : AsmOperandClass {
1338 let Name = "MemoryUnscaledFB128";
1339 let RenderMethod = "addMemoryUnscaledOperands";
1341 def am_unscaled_fb8 : Operand<i64> {
1342 let ParserMatchClass = MemoryUnscaledFB8Operand;
1343 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1345 def am_unscaled_fb16 : Operand<i64> {
1346 let ParserMatchClass = MemoryUnscaledFB16Operand;
1347 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1349 def am_unscaled_fb32 : Operand<i64> {
1350 let ParserMatchClass = MemoryUnscaledFB32Operand;
1351 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1353 def am_unscaled_fb64 : Operand<i64> {
1354 let ParserMatchClass = MemoryUnscaledFB64Operand;
1355 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1357 def am_unscaled_fb128 : Operand<i64> {
1358 let ParserMatchClass = MemoryUnscaledFB128Operand;
1359 let MIOperandInfo = (ops GPR64sp:$base, i64imm:$offset);
1361 def : InstAlias<"ldr $Rt, $addr", (LDURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1362 def : InstAlias<"ldr $Rt, $addr", (LDURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1363 def : InstAlias<"ldr $Rt, $addr", (LDURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1364 def : InstAlias<"ldr $Rt, $addr", (LDURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1365 def : InstAlias<"ldr $Rt, $addr", (LDURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1366 def : InstAlias<"ldr $Rt, $addr", (LDURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1367 def : InstAlias<"ldr $Rt, $addr", (LDURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1370 def : Pat<(i64 (zextloadi8 am_unscaled8:$addr)),
1371 (SUBREG_TO_REG (i64 0), (LDURBBi am_unscaled8:$addr), sub_32)>;
1372 def : Pat<(i64 (zextloadi16 am_unscaled16:$addr)),
1373 (SUBREG_TO_REG (i64 0), (LDURHHi am_unscaled16:$addr), sub_32)>;
1375 // load sign-extended half-word
1377 : LoadUnscaled<0b01, 0, 0b11, GPR32, am_unscaled16, "ldursh",
1378 [(set GPR32:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1380 : LoadUnscaled<0b01, 0, 0b10, GPR64, am_unscaled16, "ldursh",
1381 [(set GPR64:$Rt, (sextloadi16 am_unscaled16:$addr))]>;
1383 // load sign-extended byte
1385 : LoadUnscaled<0b00, 0, 0b11, GPR32, am_unscaled8, "ldursb",
1386 [(set GPR32:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1388 : LoadUnscaled<0b00, 0, 0b10, GPR64, am_unscaled8, "ldursb",
1389 [(set GPR64:$Rt, (sextloadi8 am_unscaled8:$addr))]>;
1391 // load sign-extended word
1393 : LoadUnscaled<0b10, 0, 0b10, GPR64, am_unscaled32, "ldursw",
1394 [(set GPR64:$Rt, (sextloadi32 am_unscaled32:$addr))]>;
1396 // zero and sign extending aliases from generic LDR* mnemonics to LDUR*.
1397 def : InstAlias<"ldrb $Rt, $addr", (LDURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1398 def : InstAlias<"ldrh $Rt, $addr", (LDURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1399 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBWi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1400 def : InstAlias<"ldrsb $Rt, $addr", (LDURSBXi GPR64:$Rt, am_unscaled_fb8:$addr)>;
1401 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHWi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1402 def : InstAlias<"ldrsh $Rt, $addr", (LDURSHXi GPR64:$Rt, am_unscaled_fb16:$addr)>;
1403 def : InstAlias<"ldrsw $Rt, $addr", (LDURSWi GPR64:$Rt, am_unscaled_fb32:$addr)>;
1406 def PRFUMi : PrefetchUnscaled<0b11, 0, 0b10, "prfum",
1407 [(ARM64Prefetch imm:$Rt, am_unscaled64:$addr)]>;
1410 // (unscaled immediate, unprivileged)
1411 def LDTRXi : LoadUnprivileged<0b11, 0, 0b01, GPR64, "ldtr">;
1412 def LDTRWi : LoadUnprivileged<0b10, 0, 0b01, GPR32, "ldtr">;
1414 def LDTRHi : LoadUnprivileged<0b01, 0, 0b01, GPR32, "ldtrh">;
1415 def LDTRBi : LoadUnprivileged<0b00, 0, 0b01, GPR32, "ldtrb">;
1417 // load sign-extended half-word
1418 def LDTRSHWi : LoadUnprivileged<0b01, 0, 0b11, GPR32, "ldtrsh">;
1419 def LDTRSHXi : LoadUnprivileged<0b01, 0, 0b10, GPR64, "ldtrsh">;
1421 // load sign-extended byte
1422 def LDTRSBWi : LoadUnprivileged<0b00, 0, 0b11, GPR32, "ldtrsb">;
1423 def LDTRSBXi : LoadUnprivileged<0b00, 0, 0b10, GPR64, "ldtrsb">;
1425 // load sign-extended word
1426 def LDTRSWi : LoadUnprivileged<0b10, 0, 0b10, GPR64, "ldtrsw">;
1429 // (immediate pre-indexed)
1430 def LDRWpre : LoadPreIdx<0b10, 0, 0b01, GPR32, "ldr">;
1431 def LDRXpre : LoadPreIdx<0b11, 0, 0b01, GPR64, "ldr">;
1432 def LDRBpre : LoadPreIdx<0b00, 1, 0b01, FPR8, "ldr">;
1433 def LDRHpre : LoadPreIdx<0b01, 1, 0b01, FPR16, "ldr">;
1434 def LDRSpre : LoadPreIdx<0b10, 1, 0b01, FPR32, "ldr">;
1435 def LDRDpre : LoadPreIdx<0b11, 1, 0b01, FPR64, "ldr">;
1436 def LDRQpre : LoadPreIdx<0b00, 1, 0b11, FPR128, "ldr">;
1438 // load sign-extended half-word
1439 def LDRSHWpre : LoadPreIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1440 def LDRSHXpre : LoadPreIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1442 // load sign-extended byte
1443 def LDRSBWpre : LoadPreIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1444 def LDRSBXpre : LoadPreIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1446 // load zero-extended byte
1447 def LDRBBpre : LoadPreIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1448 def LDRHHpre : LoadPreIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1450 // load sign-extended word
1451 def LDRSWpre : LoadPreIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1453 // ISel pseudos and patterns. See expanded comment on LoadPreIdxPseudo.
1454 def LDRDpre_isel : LoadPreIdxPseudo<FPR64>;
1455 def LDRSpre_isel : LoadPreIdxPseudo<FPR32>;
1456 def LDRXpre_isel : LoadPreIdxPseudo<GPR64>;
1457 def LDRWpre_isel : LoadPreIdxPseudo<GPR32>;
1458 def LDRHHpre_isel : LoadPreIdxPseudo<GPR32>;
1459 def LDRBBpre_isel : LoadPreIdxPseudo<GPR32>;
1461 def LDRSWpre_isel : LoadPreIdxPseudo<GPR64>;
1462 def LDRSHWpre_isel : LoadPreIdxPseudo<GPR32>;
1463 def LDRSHXpre_isel : LoadPreIdxPseudo<GPR64>;
1464 def LDRSBWpre_isel : LoadPreIdxPseudo<GPR32>;
1465 def LDRSBXpre_isel : LoadPreIdxPseudo<GPR64>;
1468 // (immediate post-indexed)
1469 def LDRWpost : LoadPostIdx<0b10, 0, 0b01, GPR32, "ldr">;
1470 def LDRXpost : LoadPostIdx<0b11, 0, 0b01, GPR64, "ldr">;
1471 def LDRBpost : LoadPostIdx<0b00, 1, 0b01, FPR8, "ldr">;
1472 def LDRHpost : LoadPostIdx<0b01, 1, 0b01, FPR16, "ldr">;
1473 def LDRSpost : LoadPostIdx<0b10, 1, 0b01, FPR32, "ldr">;
1474 def LDRDpost : LoadPostIdx<0b11, 1, 0b01, FPR64, "ldr">;
1475 def LDRQpost : LoadPostIdx<0b00, 1, 0b11, FPR128, "ldr">;
1477 // load sign-extended half-word
1478 def LDRSHWpost : LoadPostIdx<0b01, 0, 0b11, GPR32, "ldrsh">;
1479 def LDRSHXpost : LoadPostIdx<0b01, 0, 0b10, GPR64, "ldrsh">;
1481 // load sign-extended byte
1482 def LDRSBWpost : LoadPostIdx<0b00, 0, 0b11, GPR32, "ldrsb">;
1483 def LDRSBXpost : LoadPostIdx<0b00, 0, 0b10, GPR64, "ldrsb">;
1485 // load zero-extended byte
1486 def LDRBBpost : LoadPostIdx<0b00, 0, 0b01, GPR32, "ldrb">;
1487 def LDRHHpost : LoadPostIdx<0b01, 0, 0b01, GPR32, "ldrh">;
1489 // load sign-extended word
1490 def LDRSWpost : LoadPostIdx<0b10, 0, 0b10, GPR64, "ldrsw">;
1492 // ISel pseudos and patterns. See expanded comment on LoadPostIdxPseudo.
1493 def LDRDpost_isel : LoadPostIdxPseudo<FPR64>;
1494 def LDRSpost_isel : LoadPostIdxPseudo<FPR32>;
1495 def LDRXpost_isel : LoadPostIdxPseudo<GPR64>;
1496 def LDRWpost_isel : LoadPostIdxPseudo<GPR32>;
1497 def LDRHHpost_isel : LoadPostIdxPseudo<GPR32>;
1498 def LDRBBpost_isel : LoadPostIdxPseudo<GPR32>;
1500 def LDRSWpost_isel : LoadPostIdxPseudo<GPR64>;
1501 def LDRSHWpost_isel : LoadPostIdxPseudo<GPR32>;
1502 def LDRSHXpost_isel : LoadPostIdxPseudo<GPR64>;
1503 def LDRSBWpost_isel : LoadPostIdxPseudo<GPR32>;
1504 def LDRSBXpost_isel : LoadPostIdxPseudo<GPR64>;
1506 //===----------------------------------------------------------------------===//
1507 // Store instructions.
1508 //===----------------------------------------------------------------------===//
1510 // Pair (indexed, offset)
1511 // FIXME: Use dedicated range-checked addressing mode operand here.
1512 def STPWi : StorePairOffset<0b00, 0, GPR32, am_indexed32simm7, "stp">;
1513 def STPXi : StorePairOffset<0b10, 0, GPR64, am_indexed64simm7, "stp">;
1514 def STPSi : StorePairOffset<0b00, 1, FPR32, am_indexed32simm7, "stp">;
1515 def STPDi : StorePairOffset<0b01, 1, FPR64, am_indexed64simm7, "stp">;
1516 def STPQi : StorePairOffset<0b10, 1, FPR128, am_indexed128simm7, "stp">;
1518 // Pair (pre-indexed)
1519 def STPWpre : StorePairPreIdx<0b00, 0, GPR32, am_indexed32simm7, "stp">;
1520 def STPXpre : StorePairPreIdx<0b10, 0, GPR64, am_indexed64simm7, "stp">;
1521 def STPSpre : StorePairPreIdx<0b00, 1, FPR32, am_indexed32simm7, "stp">;
1522 def STPDpre : StorePairPreIdx<0b01, 1, FPR64, am_indexed64simm7, "stp">;
1523 def STPQpre : StorePairPreIdx<0b10, 1, FPR128, am_indexed128simm7, "stp">;
1525 // Pair (pre-indexed)
1526 def STPWpost : StorePairPostIdx<0b00, 0, GPR32, simm7s4, "stp">;
1527 def STPXpost : StorePairPostIdx<0b10, 0, GPR64, simm7s8, "stp">;
1528 def STPSpost : StorePairPostIdx<0b00, 1, FPR32, simm7s4, "stp">;
1529 def STPDpost : StorePairPostIdx<0b01, 1, FPR64, simm7s8, "stp">;
1530 def STPQpost : StorePairPostIdx<0b10, 1, FPR128, simm7s16, "stp">;
1532 // Pair (no allocate)
1533 def STNPWi : StorePairNoAlloc<0b00, 0, GPR32, am_indexed32simm7, "stnp">;
1534 def STNPXi : StorePairNoAlloc<0b10, 0, GPR64, am_indexed64simm7, "stnp">;
1535 def STNPSi : StorePairNoAlloc<0b00, 1, FPR32, am_indexed32simm7, "stnp">;
1536 def STNPDi : StorePairNoAlloc<0b01, 1, FPR64, am_indexed64simm7, "stnp">;
1537 def STNPQi : StorePairNoAlloc<0b10, 1, FPR128, am_indexed128simm7, "stnp">;
1540 // (Register offset)
1542 let AddedComplexity = 10 in {
1545 def STRHHro : Store16RO<0b01, 0, 0b00, GPR32, "strh",
1546 [(truncstorei16 GPR32:$Rt, ro_indexed16:$addr)]>;
1547 def STRBBro : Store8RO<0b00, 0, 0b00, GPR32, "strb",
1548 [(truncstorei8 GPR32:$Rt, ro_indexed8:$addr)]>;
1549 def STRWro : Store32RO<0b10, 0, 0b00, GPR32, "str",
1550 [(store GPR32:$Rt, ro_indexed32:$addr)]>;
1551 def STRXro : Store64RO<0b11, 0, 0b00, GPR64, "str",
1552 [(store GPR64:$Rt, ro_indexed64:$addr)]>;
1555 def : Pat<(truncstorei8 GPR64:$Rt, ro_indexed8:$addr),
1556 (STRBBro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed8:$addr)>;
1557 def : Pat<(truncstorei16 GPR64:$Rt, ro_indexed16:$addr),
1558 (STRHHro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed16:$addr)>;
1559 def : Pat<(truncstorei32 GPR64:$Rt, ro_indexed32:$addr),
1560 (STRWro (EXTRACT_SUBREG GPR64:$Rt, sub_32), ro_indexed32:$addr)>;
1564 def STRBro : Store8RO<0b00, 1, 0b00, FPR8, "str",
1565 [(store FPR8:$Rt, ro_indexed8:$addr)]>;
1566 def STRHro : Store16RO<0b01, 1, 0b00, FPR16, "str",
1567 [(store FPR16:$Rt, ro_indexed16:$addr)]>;
1568 def STRSro : Store32RO<0b10, 1, 0b00, FPR32, "str",
1569 [(store (f32 FPR32:$Rt), ro_indexed32:$addr)]>;
1570 def STRDro : Store64RO<0b11, 1, 0b00, FPR64, "str",
1571 [(store (f64 FPR64:$Rt), ro_indexed64:$addr)]>;
1572 def STRQro : Store128RO<0b00, 1, 0b10, FPR128, "str", []> {
1576 // Match all store 64 bits width whose type is compatible with FPR64
1577 def : Pat<(store (v2f32 FPR64:$Rn), ro_indexed64:$addr),
1578 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1579 def : Pat<(store (v1f64 FPR64:$Rn), ro_indexed64:$addr),
1580 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1581 def : Pat<(store (v8i8 FPR64:$Rn), ro_indexed64:$addr),
1582 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1583 def : Pat<(store (v4i16 FPR64:$Rn), ro_indexed64:$addr),
1584 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1585 def : Pat<(store (v2i32 FPR64:$Rn), ro_indexed64:$addr),
1586 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1587 def : Pat<(store (v1i64 FPR64:$Rn), ro_indexed64:$addr),
1588 (STRDro FPR64:$Rn, ro_indexed64:$addr)>;
1590 // Match all store 128 bits width whose type is compatible with FPR128
1591 def : Pat<(store (v4f32 FPR128:$Rn), ro_indexed128:$addr),
1592 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1593 def : Pat<(store (v2f64 FPR128:$Rn), ro_indexed128:$addr),
1594 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1595 def : Pat<(store (v16i8 FPR128:$Rn), ro_indexed128:$addr),
1596 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1597 def : Pat<(store (v8i16 FPR128:$Rn), ro_indexed128:$addr),
1598 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1599 def : Pat<(store (v4i32 FPR128:$Rn), ro_indexed128:$addr),
1600 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1601 def : Pat<(store (v2i64 FPR128:$Rn), ro_indexed128:$addr),
1602 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1603 def : Pat<(store (f128 FPR128:$Rn), ro_indexed128:$addr),
1604 (STRQro FPR128:$Rn, ro_indexed128:$addr)>;
1607 // (unsigned immediate)
1608 def STRXui : StoreUI<0b11, 0, 0b00, GPR64, am_indexed64, "str",
1609 [(store GPR64:$Rt, am_indexed64:$addr)]>;
1610 def STRWui : StoreUI<0b10, 0, 0b00, GPR32, am_indexed32, "str",
1611 [(store GPR32:$Rt, am_indexed32:$addr)]>;
1612 def STRBui : StoreUI<0b00, 1, 0b00, FPR8, am_indexed8, "str",
1613 [(store FPR8:$Rt, am_indexed8:$addr)]>;
1614 def STRHui : StoreUI<0b01, 1, 0b00, FPR16, am_indexed16, "str",
1615 [(store FPR16:$Rt, am_indexed16:$addr)]>;
1616 def STRSui : StoreUI<0b10, 1, 0b00, FPR32, am_indexed32, "str",
1617 [(store (f32 FPR32:$Rt), am_indexed32:$addr)]>;
1618 def STRDui : StoreUI<0b11, 1, 0b00, FPR64, am_indexed64, "str",
1619 [(store (f64 FPR64:$Rt), am_indexed64:$addr)]>;
1620 def STRQui : StoreUI<0b00, 1, 0b10, FPR128, am_indexed128, "str", []> {
1624 // Match all store 64 bits width whose type is compatible with FPR64
1625 def : Pat<(store (v2f32 FPR64:$Rn), am_indexed64:$addr),
1626 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1627 def : Pat<(store (v1f64 FPR64:$Rn), am_indexed64:$addr),
1628 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1629 def : Pat<(store (v8i8 FPR64:$Rn), am_indexed64:$addr),
1630 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1631 def : Pat<(store (v4i16 FPR64:$Rn), am_indexed64:$addr),
1632 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1633 def : Pat<(store (v2i32 FPR64:$Rn), am_indexed64:$addr),
1634 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1635 def : Pat<(store (v1i64 FPR64:$Rn), am_indexed64:$addr),
1636 (STRDui FPR64:$Rn, am_indexed64:$addr)>;
1638 // Match all store 128 bits width whose type is compatible with FPR128
1639 def : Pat<(store (v4f32 FPR128:$Rn), am_indexed128:$addr),
1640 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1641 def : Pat<(store (v2f64 FPR128:$Rn), am_indexed128:$addr),
1642 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1643 def : Pat<(store (v16i8 FPR128:$Rn), am_indexed128:$addr),
1644 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1645 def : Pat<(store (v8i16 FPR128:$Rn), am_indexed128:$addr),
1646 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1647 def : Pat<(store (v4i32 FPR128:$Rn), am_indexed128:$addr),
1648 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1649 def : Pat<(store (v2i64 FPR128:$Rn), am_indexed128:$addr),
1650 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1651 def : Pat<(store (f128 FPR128:$Rn), am_indexed128:$addr),
1652 (STRQui FPR128:$Rn, am_indexed128:$addr)>;
1654 def STRHHui : StoreUI<0b01, 0, 0b00, GPR32, am_indexed16, "strh",
1655 [(truncstorei16 GPR32:$Rt, am_indexed16:$addr)]>;
1656 def STRBBui : StoreUI<0b00, 0, 0b00, GPR32, am_indexed8, "strb",
1657 [(truncstorei8 GPR32:$Rt, am_indexed8:$addr)]>;
1660 def : Pat<(truncstorei32 GPR64:$Rt, am_indexed32:$addr),
1661 (STRWui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed32:$addr)>;
1662 def : Pat<(truncstorei16 GPR64:$Rt, am_indexed16:$addr),
1663 (STRHHui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed16:$addr)>;
1664 def : Pat<(truncstorei8 GPR64:$Rt, am_indexed8:$addr),
1665 (STRBBui (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_indexed8:$addr)>;
1667 } // AddedComplexity = 10
1670 // (unscaled immediate)
1671 def STURXi : StoreUnscaled<0b11, 0, 0b00, GPR64, am_unscaled64, "stur",
1672 [(store GPR64:$Rt, am_unscaled64:$addr)]>;
1673 def STURWi : StoreUnscaled<0b10, 0, 0b00, GPR32, am_unscaled32, "stur",
1674 [(store GPR32:$Rt, am_unscaled32:$addr)]>;
1675 def STURBi : StoreUnscaled<0b00, 1, 0b00, FPR8, am_unscaled8, "stur",
1676 [(store FPR8:$Rt, am_unscaled8:$addr)]>;
1677 def STURHi : StoreUnscaled<0b01, 1, 0b00, FPR16, am_unscaled16, "stur",
1678 [(store FPR16:$Rt, am_unscaled16:$addr)]>;
1679 def STURSi : StoreUnscaled<0b10, 1, 0b00, FPR32, am_unscaled32, "stur",
1680 [(store (f32 FPR32:$Rt), am_unscaled32:$addr)]>;
1681 def STURDi : StoreUnscaled<0b11, 1, 0b00, FPR64, am_unscaled64, "stur",
1682 [(store (f64 FPR64:$Rt), am_unscaled64:$addr)]>;
1683 def STURQi : StoreUnscaled<0b00, 1, 0b10, FPR128, am_unscaled128, "stur",
1684 [(store (v2f64 FPR128:$Rt), am_unscaled128:$addr)]>;
1685 def STURHHi : StoreUnscaled<0b01, 0, 0b00, GPR32, am_unscaled16, "sturh",
1686 [(truncstorei16 GPR32:$Rt, am_unscaled16:$addr)]>;
1687 def STURBBi : StoreUnscaled<0b00, 0, 0b00, GPR32, am_unscaled8, "sturb",
1688 [(truncstorei8 GPR32:$Rt, am_unscaled8:$addr)]>;
1690 // Match all store 64 bits width whose type is compatible with FPR64
1691 def : Pat<(store (v2f32 FPR64:$Rn), am_unscaled64:$addr),
1692 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1693 def : Pat<(store (v1f64 FPR64:$Rn), am_unscaled64:$addr),
1694 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1695 def : Pat<(store (v8i8 FPR64:$Rn), am_unscaled64:$addr),
1696 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1697 def : Pat<(store (v4i16 FPR64:$Rn), am_unscaled64:$addr),
1698 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1699 def : Pat<(store (v2i32 FPR64:$Rn), am_unscaled64:$addr),
1700 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1701 def : Pat<(store (v1i64 FPR64:$Rn), am_unscaled64:$addr),
1702 (STURDi FPR64:$Rn, am_unscaled64:$addr)>;
1704 // Match all store 128 bits width whose type is compatible with FPR128
1705 def : Pat<(store (v4f32 FPR128:$Rn), am_unscaled128:$addr),
1706 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1707 def : Pat<(store (v2f64 FPR128:$Rn), am_unscaled128:$addr),
1708 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1709 def : Pat<(store (v16i8 FPR128:$Rn), am_unscaled128:$addr),
1710 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1711 def : Pat<(store (v8i16 FPR128:$Rn), am_unscaled128:$addr),
1712 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1713 def : Pat<(store (v4i32 FPR128:$Rn), am_unscaled128:$addr),
1714 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1715 def : Pat<(store (v2i64 FPR128:$Rn), am_unscaled128:$addr),
1716 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1717 def : Pat<(store (f128 FPR128:$Rn), am_unscaled128:$addr),
1718 (STURQi FPR128:$Rn, am_unscaled128:$addr)>;
1720 // unscaled i64 truncating stores
1721 def : Pat<(truncstorei32 GPR64:$Rt, am_unscaled32:$addr),
1722 (STURWi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled32:$addr)>;
1723 def : Pat<(truncstorei16 GPR64:$Rt, am_unscaled16:$addr),
1724 (STURHHi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled16:$addr)>;
1725 def : Pat<(truncstorei8 GPR64:$Rt, am_unscaled8:$addr),
1726 (STURBBi (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_unscaled8:$addr)>;
1729 // STR mnemonics fall back to STUR for negative or unaligned offsets.
1730 def : InstAlias<"str $Rt, $addr", (STURXi GPR64:$Rt, am_unscaled_fb64:$addr)>;
1731 def : InstAlias<"str $Rt, $addr", (STURWi GPR32:$Rt, am_unscaled_fb32:$addr)>;
1732 def : InstAlias<"str $Rt, $addr", (STURBi FPR8:$Rt, am_unscaled_fb8:$addr)>;
1733 def : InstAlias<"str $Rt, $addr", (STURHi FPR16:$Rt, am_unscaled_fb16:$addr)>;
1734 def : InstAlias<"str $Rt, $addr", (STURSi FPR32:$Rt, am_unscaled_fb32:$addr)>;
1735 def : InstAlias<"str $Rt, $addr", (STURDi FPR64:$Rt, am_unscaled_fb64:$addr)>;
1736 def : InstAlias<"str $Rt, $addr", (STURQi FPR128:$Rt, am_unscaled_fb128:$addr)>;
1738 def : InstAlias<"strb $Rt, $addr", (STURBBi GPR32:$Rt, am_unscaled_fb8:$addr)>;
1739 def : InstAlias<"strh $Rt, $addr", (STURHHi GPR32:$Rt, am_unscaled_fb16:$addr)>;
1742 // (unscaled immediate, unprivileged)
1743 def STTRWi : StoreUnprivileged<0b10, 0, 0b00, GPR32, "sttr">;
1744 def STTRXi : StoreUnprivileged<0b11, 0, 0b00, GPR64, "sttr">;
1746 def STTRHi : StoreUnprivileged<0b01, 0, 0b00, GPR32, "sttrh">;
1747 def STTRBi : StoreUnprivileged<0b00, 0, 0b00, GPR32, "sttrb">;
1750 // (immediate pre-indexed)
1751 def STRWpre : StorePreIdx<0b10, 0, 0b00, GPR32, "str">;
1752 def STRXpre : StorePreIdx<0b11, 0, 0b00, GPR64, "str">;
1753 def STRBpre : StorePreIdx<0b00, 1, 0b00, FPR8, "str">;
1754 def STRHpre : StorePreIdx<0b01, 1, 0b00, FPR16, "str">;
1755 def STRSpre : StorePreIdx<0b10, 1, 0b00, FPR32, "str">;
1756 def STRDpre : StorePreIdx<0b11, 1, 0b00, FPR64, "str">;
1757 def STRQpre : StorePreIdx<0b00, 1, 0b10, FPR128, "str">;
1759 def STRBBpre : StorePreIdx<0b00, 0, 0b00, GPR32, "strb">;
1760 def STRHHpre : StorePreIdx<0b01, 0, 0b00, GPR32, "strh">;
1762 // ISel pseudos and patterns. See expanded comment on StorePreIdxPseudo.
1763 defm STRDpre : StorePreIdxPseudo<FPR64, f64, pre_store>;
1764 defm STRSpre : StorePreIdxPseudo<FPR32, f32, pre_store>;
1765 defm STRXpre : StorePreIdxPseudo<GPR64, i64, pre_store>;
1766 defm STRWpre : StorePreIdxPseudo<GPR32, i32, pre_store>;
1767 defm STRHHpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti16>;
1768 defm STRBBpre : StorePreIdxPseudo<GPR32, i32, pre_truncsti8>;
1770 def : Pat<(pre_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1771 (STRWpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1773 def : Pat<(pre_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1774 (STRHHpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1776 def : Pat<(pre_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1777 (STRBBpre_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1781 // (immediate post-indexed)
1782 def STRWpost : StorePostIdx<0b10, 0, 0b00, GPR32, "str">;
1783 def STRXpost : StorePostIdx<0b11, 0, 0b00, GPR64, "str">;
1784 def STRBpost : StorePostIdx<0b00, 1, 0b00, FPR8, "str">;
1785 def STRHpost : StorePostIdx<0b01, 1, 0b00, FPR16, "str">;
1786 def STRSpost : StorePostIdx<0b10, 1, 0b00, FPR32, "str">;
1787 def STRDpost : StorePostIdx<0b11, 1, 0b00, FPR64, "str">;
1788 def STRQpost : StorePostIdx<0b00, 1, 0b10, FPR128, "str">;
1790 def STRBBpost : StorePostIdx<0b00, 0, 0b00, GPR32, "strb">;
1791 def STRHHpost : StorePostIdx<0b01, 0, 0b00, GPR32, "strh">;
1793 // ISel pseudos and patterns. See expanded comment on StorePostIdxPseudo.
1794 defm STRDpost : StorePostIdxPseudo<FPR64, f64, post_store, STRDpost>;
1795 defm STRSpost : StorePostIdxPseudo<FPR32, f32, post_store, STRSpost>;
1796 defm STRXpost : StorePostIdxPseudo<GPR64, i64, post_store, STRXpost>;
1797 defm STRWpost : StorePostIdxPseudo<GPR32, i32, post_store, STRWpost>;
1798 defm STRHHpost : StorePostIdxPseudo<GPR32, i32, post_truncsti16, STRHHpost>;
1799 defm STRBBpost : StorePostIdxPseudo<GPR32, i32, post_truncsti8, STRBBpost>;
1801 def : Pat<(post_truncsti32 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1802 (STRWpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1804 def : Pat<(post_truncsti16 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1805 (STRHHpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1807 def : Pat<(post_truncsti8 GPR64:$Rt, am_noindex:$addr, simm9:$off),
1808 (STRBBpost_isel (EXTRACT_SUBREG GPR64:$Rt, sub_32), am_noindex:$addr,
1812 //===----------------------------------------------------------------------===//
1813 // Load/store exclusive instructions.
1814 //===----------------------------------------------------------------------===//
1816 def LDARW : LoadAcquire <0b10, 1, 1, 0, 1, GPR32, "ldar">;
1817 def LDARX : LoadAcquire <0b11, 1, 1, 0, 1, GPR64, "ldar">;
1818 def LDARB : LoadAcquire <0b00, 1, 1, 0, 1, GPR32, "ldarb">;
1819 def LDARH : LoadAcquire <0b01, 1, 1, 0, 1, GPR32, "ldarh">;
1821 def LDAXRW : LoadExclusive <0b10, 0, 1, 0, 1, GPR32, "ldaxr">;
1822 def LDAXRX : LoadExclusive <0b11, 0, 1, 0, 1, GPR64, "ldaxr">;
1823 def LDAXRB : LoadExclusive <0b00, 0, 1, 0, 1, GPR32, "ldaxrb">;
1824 def LDAXRH : LoadExclusive <0b01, 0, 1, 0, 1, GPR32, "ldaxrh">;
1826 def LDXRW : LoadExclusive <0b10, 0, 1, 0, 0, GPR32, "ldxr">;
1827 def LDXRX : LoadExclusive <0b11, 0, 1, 0, 0, GPR64, "ldxr">;
1828 def LDXRB : LoadExclusive <0b00, 0, 1, 0, 0, GPR32, "ldxrb">;
1829 def LDXRH : LoadExclusive <0b01, 0, 1, 0, 0, GPR32, "ldxrh">;
1831 def STLRW : StoreRelease <0b10, 1, 0, 0, 1, GPR32, "stlr">;
1832 def STLRX : StoreRelease <0b11, 1, 0, 0, 1, GPR64, "stlr">;
1833 def STLRB : StoreRelease <0b00, 1, 0, 0, 1, GPR32, "stlrb">;
1834 def STLRH : StoreRelease <0b01, 1, 0, 0, 1, GPR32, "stlrh">;
1836 def STLXRW : StoreExclusive<0b10, 0, 0, 0, 1, GPR32, "stlxr">;
1837 def STLXRX : StoreExclusive<0b11, 0, 0, 0, 1, GPR64, "stlxr">;
1838 def STLXRB : StoreExclusive<0b00, 0, 0, 0, 1, GPR32, "stlxrb">;
1839 def STLXRH : StoreExclusive<0b01, 0, 0, 0, 1, GPR32, "stlxrh">;
1841 def STXRW : StoreExclusive<0b10, 0, 0, 0, 0, GPR32, "stxr">;
1842 def STXRX : StoreExclusive<0b11, 0, 0, 0, 0, GPR64, "stxr">;
1843 def STXRB : StoreExclusive<0b00, 0, 0, 0, 0, GPR32, "stxrb">;
1844 def STXRH : StoreExclusive<0b01, 0, 0, 0, 0, GPR32, "stxrh">;
1846 def LDAXPW : LoadExclusivePair<0b10, 0, 1, 1, 1, GPR32, "ldaxp">;
1847 def LDAXPX : LoadExclusivePair<0b11, 0, 1, 1, 1, GPR64, "ldaxp">;
1849 def LDXPW : LoadExclusivePair<0b10, 0, 1, 1, 0, GPR32, "ldxp">;
1850 def LDXPX : LoadExclusivePair<0b11, 0, 1, 1, 0, GPR64, "ldxp">;
1852 def STLXPW : StoreExclusivePair<0b10, 0, 0, 1, 1, GPR32, "stlxp">;
1853 def STLXPX : StoreExclusivePair<0b11, 0, 0, 1, 1, GPR64, "stlxp">;
1855 def STXPW : StoreExclusivePair<0b10, 0, 0, 1, 0, GPR32, "stxp">;
1856 def STXPX : StoreExclusivePair<0b11, 0, 0, 1, 0, GPR64, "stxp">;
1858 //===----------------------------------------------------------------------===//
1859 // Scaled floating point to integer conversion instructions.
1860 //===----------------------------------------------------------------------===//
1862 defm FCVTAS : FPToInteger<0b00, 0b100, "fcvtas", int_arm64_neon_fcvtas>;
1863 defm FCVTAU : FPToInteger<0b00, 0b101, "fcvtau", int_arm64_neon_fcvtau>;
1864 defm FCVTMS : FPToInteger<0b10, 0b000, "fcvtms", int_arm64_neon_fcvtms>;
1865 defm FCVTMU : FPToInteger<0b10, 0b001, "fcvtmu", int_arm64_neon_fcvtmu>;
1866 defm FCVTNS : FPToInteger<0b00, 0b000, "fcvtns", int_arm64_neon_fcvtns>;
1867 defm FCVTNU : FPToInteger<0b00, 0b001, "fcvtnu", int_arm64_neon_fcvtnu>;
1868 defm FCVTPS : FPToInteger<0b01, 0b000, "fcvtps", int_arm64_neon_fcvtps>;
1869 defm FCVTPU : FPToInteger<0b01, 0b001, "fcvtpu", int_arm64_neon_fcvtpu>;
1870 defm FCVTZS : FPToInteger<0b11, 0b000, "fcvtzs", fp_to_sint>;
1871 defm FCVTZU : FPToInteger<0b11, 0b001, "fcvtzu", fp_to_uint>;
1872 let isCodeGenOnly = 1 in {
1873 defm FCVTZS_Int : FPToInteger<0b11, 0b000, "fcvtzs", int_arm64_neon_fcvtzs>;
1874 defm FCVTZU_Int : FPToInteger<0b11, 0b001, "fcvtzu", int_arm64_neon_fcvtzu>;
1877 //===----------------------------------------------------------------------===//
1878 // Scaled integer to floating point conversion instructions.
1879 //===----------------------------------------------------------------------===//
1881 defm SCVTF : IntegerToFP<0, "scvtf", sint_to_fp>;
1882 defm UCVTF : IntegerToFP<1, "ucvtf", uint_to_fp>;
1884 //===----------------------------------------------------------------------===//
1885 // Unscaled integer to floating point conversion instruction.
1886 //===----------------------------------------------------------------------===//
1888 defm FMOV : UnscaledConversion<"fmov">;
1890 def : Pat<(f32 (fpimm0)), (FMOVWSr WZR)>, Requires<[NoZCZ]>;
1891 def : Pat<(f64 (fpimm0)), (FMOVXDr XZR)>, Requires<[NoZCZ]>;
1893 def : Pat<(v8i8 (bitconvert GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
1894 def : Pat<(v4i16 (bitconvert GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
1895 def : Pat<(v2i32 (bitconvert GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
1896 def : Pat<(v1i64 (bitconvert GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
1897 def : Pat<(v2f32 (bitconvert GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
1898 def : Pat<(v1f64 (bitconvert GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
1899 def : Pat<(v1i64 (scalar_to_vector GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
1900 def : Pat<(v1f64 (scalar_to_vector GPR64:$Xn)), (FMOVXDr GPR64:$Xn)>;
1901 def : Pat<(v1f64 (scalar_to_vector (f64 FPR64:$Xn))), (v1f64 FPR64:$Xn)>;
1903 def : Pat<(i64 (bitconvert (v8i8 V64:$Vn))), (FMOVDXr V64:$Vn)>;
1904 def : Pat<(i64 (bitconvert (v4i16 V64:$Vn))), (FMOVDXr V64:$Vn)>;
1905 def : Pat<(i64 (bitconvert (v2i32 V64:$Vn))), (FMOVDXr V64:$Vn)>;
1906 def : Pat<(i64 (bitconvert (v1i64 V64:$Vn))), (FMOVDXr V64:$Vn)>;
1907 def : Pat<(i64 (bitconvert (v2f32 V64:$Vn))), (FMOVDXr V64:$Vn)>;
1908 def : Pat<(i64 (bitconvert (v1f64 V64:$Vn))), (FMOVDXr V64:$Vn)>;
1910 def : Pat<(f32 (bitconvert (i32 GPR32:$Xn))), (COPY_TO_REGCLASS GPR32:$Xn,
1912 def : Pat<(i32 (bitconvert (f32 FPR32:$Xn))), (COPY_TO_REGCLASS FPR32:$Xn,
1914 def : Pat<(f64 (bitconvert (i64 GPR64:$Xn))), (COPY_TO_REGCLASS GPR64:$Xn,
1916 def : Pat<(i64 (bitconvert (f64 FPR64:$Xn))), (COPY_TO_REGCLASS FPR64:$Xn,
1919 //===----------------------------------------------------------------------===//
1920 // Floating point conversion instruction.
1921 //===----------------------------------------------------------------------===//
1923 defm FCVT : FPConversion<"fcvt">;
1925 def : Pat<(f32_to_f16 FPR32:$Rn),
1926 (i32 (COPY_TO_REGCLASS
1927 (f32 (SUBREG_TO_REG (i32 0), (FCVTHSr FPR32:$Rn), hsub)),
1931 //===----------------------------------------------------------------------===//
1932 // Floating point single operand instructions.
1933 //===----------------------------------------------------------------------===//
1935 defm FABS : SingleOperandFPData<0b0001, "fabs", fabs>;
1936 defm FMOV : SingleOperandFPData<0b0000, "fmov">;
1937 defm FNEG : SingleOperandFPData<0b0010, "fneg", fneg>;
1938 defm FRINTA : SingleOperandFPData<0b1100, "frinta", frnd>;
1939 defm FRINTI : SingleOperandFPData<0b1111, "frinti", fnearbyint>;
1940 defm FRINTM : SingleOperandFPData<0b1010, "frintm", ffloor>;
1941 defm FRINTN : SingleOperandFPData<0b1000, "frintn", int_arm64_neon_frintn>;
1942 defm FRINTP : SingleOperandFPData<0b1001, "frintp", fceil>;
1944 def : Pat<(v1f64 (int_arm64_neon_frintn (v1f64 FPR64:$Rn))),
1945 (FRINTNDr FPR64:$Rn)>;
1947 // FRINTX is inserted to set the flags as required by FENV_ACCESS ON behavior
1948 // in the C spec. Setting hasSideEffects ensures it is not DCE'd.
1949 // <rdar://problem/13715968>
1950 // TODO: We should really model the FPSR flags correctly. This is really ugly.
1951 let hasSideEffects = 1 in {
1952 defm FRINTX : SingleOperandFPData<0b1110, "frintx", frint>;
1955 defm FRINTZ : SingleOperandFPData<0b1011, "frintz", ftrunc>;
1957 let SchedRW = [WriteFDiv] in {
1958 defm FSQRT : SingleOperandFPData<0b0011, "fsqrt", fsqrt>;
1961 //===----------------------------------------------------------------------===//
1962 // Floating point two operand instructions.
1963 //===----------------------------------------------------------------------===//
1965 defm FADD : TwoOperandFPData<0b0010, "fadd", fadd>;
1966 let SchedRW = [WriteFDiv] in {
1967 defm FDIV : TwoOperandFPData<0b0001, "fdiv", fdiv>;
1969 defm FMAXNM : TwoOperandFPData<0b0110, "fmaxnm", int_arm64_neon_fmaxnm>;
1970 defm FMAX : TwoOperandFPData<0b0100, "fmax", ARM64fmax>;
1971 defm FMINNM : TwoOperandFPData<0b0111, "fminnm", int_arm64_neon_fminnm>;
1972 defm FMIN : TwoOperandFPData<0b0101, "fmin", ARM64fmin>;
1973 let SchedRW = [WriteFMul] in {
1974 defm FMUL : TwoOperandFPData<0b0000, "fmul", fmul>;
1975 defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", fmul>;
1977 defm FSUB : TwoOperandFPData<0b0011, "fsub", fsub>;
1979 def : Pat<(v1f64 (ARM64fmax (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
1980 (FMAXDrr FPR64:$Rn, FPR64:$Rm)>;
1981 def : Pat<(v1f64 (ARM64fmin (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
1982 (FMINDrr FPR64:$Rn, FPR64:$Rm)>;
1983 def : Pat<(v1f64 (int_arm64_neon_fmaxnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
1984 (FMAXNMDrr FPR64:$Rn, FPR64:$Rm)>;
1985 def : Pat<(v1f64 (int_arm64_neon_fminnm (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
1986 (FMINNMDrr FPR64:$Rn, FPR64:$Rm)>;
1988 //===----------------------------------------------------------------------===//
1989 // Floating point three operand instructions.
1990 //===----------------------------------------------------------------------===//
1992 defm FMADD : ThreeOperandFPData<0, 0, "fmadd", fma>;
1993 defm FMSUB : ThreeOperandFPData<0, 1, "fmsub",
1994 TriOpFrag<(fma node:$LHS, (fneg node:$MHS), node:$RHS)> >;
1995 defm FNMADD : ThreeOperandFPData<1, 0, "fnmadd",
1996 TriOpFrag<(fneg (fma node:$LHS, node:$MHS, node:$RHS))> >;
1997 defm FNMSUB : ThreeOperandFPData<1, 1, "fnmsub",
1998 TriOpFrag<(fma node:$LHS, node:$MHS, (fneg node:$RHS))> >;
2000 //===----------------------------------------------------------------------===//
2001 // Floating point comparison instructions.
2002 //===----------------------------------------------------------------------===//
2004 defm FCMPE : FPComparison<1, "fcmpe">;
2005 defm FCMP : FPComparison<0, "fcmp", ARM64fcmp>;
2007 //===----------------------------------------------------------------------===//
2008 // Floating point conditional comparison instructions.
2009 //===----------------------------------------------------------------------===//
2011 defm FCCMPE : FPCondComparison<1, "fccmpe">;
2012 defm FCCMP : FPCondComparison<0, "fccmp">;
2014 //===----------------------------------------------------------------------===//
2015 // Floating point conditional select instruction.
2016 //===----------------------------------------------------------------------===//
2018 defm FCSEL : FPCondSelect<"fcsel">;
2020 // CSEL instructions providing f128 types need to be handled by a
2021 // pseudo-instruction since the eventual code will need to introduce basic
2022 // blocks and control flow.
2023 def F128CSEL : Pseudo<(outs FPR128:$Rd),
2024 (ins FPR128:$Rn, FPR128:$Rm, ccode:$cond),
2025 [(set (f128 FPR128:$Rd),
2026 (ARM64csel FPR128:$Rn, FPR128:$Rm,
2027 (i32 imm:$cond), CPSR))]> {
2029 let usesCustomInserter = 1;
2033 //===----------------------------------------------------------------------===//
2034 // Floating point immediate move.
2035 //===----------------------------------------------------------------------===//
2037 let isReMaterializable = 1 in {
2038 defm FMOV : FPMoveImmediate<"fmov">;
2041 //===----------------------------------------------------------------------===//
2042 // Advanced SIMD two vector instructions.
2043 //===----------------------------------------------------------------------===//
2045 defm ABS : SIMDTwoVectorBHSD<0, 0b01011, "abs", int_arm64_neon_abs>;
2046 defm CLS : SIMDTwoVectorBHS<0, 0b00100, "cls", int_arm64_neon_cls>;
2047 defm CLZ : SIMDTwoVectorBHS<1, 0b00100, "clz", ctlz>;
2048 defm CMEQ : SIMDCmpTwoVector<0, 0b01001, "cmeq", ARM64cmeqz>;
2049 defm CMGE : SIMDCmpTwoVector<1, 0b01000, "cmge", ARM64cmgez>;
2050 defm CMGT : SIMDCmpTwoVector<0, 0b01000, "cmgt", ARM64cmgtz>;
2051 defm CMLE : SIMDCmpTwoVector<1, 0b01001, "cmle", ARM64cmlez>;
2052 defm CMLT : SIMDCmpTwoVector<0, 0b01010, "cmlt", ARM64cmltz>;
2053 defm CNT : SIMDTwoVectorB<0, 0b00, 0b00101, "cnt", ctpop>;
2054 defm FABS : SIMDTwoVectorFP<0, 1, 0b01111, "fabs", fabs>;
2056 defm FCMEQ : SIMDFPCmpTwoVector<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2057 defm FCMGE : SIMDFPCmpTwoVector<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2058 defm FCMGT : SIMDFPCmpTwoVector<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2059 defm FCMLE : SIMDFPCmpTwoVector<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2060 defm FCMLT : SIMDFPCmpTwoVector<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2061 defm FCVTAS : SIMDTwoVectorFPToInt<0,0,0b11100, "fcvtas",int_arm64_neon_fcvtas>;
2062 defm FCVTAU : SIMDTwoVectorFPToInt<1,0,0b11100, "fcvtau",int_arm64_neon_fcvtau>;
2063 defm FCVTL : SIMDFPWidenTwoVector<0, 0, 0b10111, "fcvtl">;
2064 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (v4i16 V64:$Rn))),
2065 (FCVTLv4i16 V64:$Rn)>;
2066 def : Pat<(v4f32 (int_arm64_neon_vcvthf2fp (extract_subvector (v8i16 V128:$Rn),
2068 (FCVTLv8i16 V128:$Rn)>;
2069 def : Pat<(v2f64 (fextend (v2f32 V64:$Rn))), (FCVTLv2i32 V64:$Rn)>;
2070 def : Pat<(v2f64 (fextend (v2f32 (extract_subvector (v4f32 V128:$Rn),
2072 (FCVTLv4i32 V128:$Rn)>;
2074 defm FCVTMS : SIMDTwoVectorFPToInt<0,0,0b11011, "fcvtms",int_arm64_neon_fcvtms>;
2075 defm FCVTMU : SIMDTwoVectorFPToInt<1,0,0b11011, "fcvtmu",int_arm64_neon_fcvtmu>;
2076 defm FCVTNS : SIMDTwoVectorFPToInt<0,0,0b11010, "fcvtns",int_arm64_neon_fcvtns>;
2077 defm FCVTNU : SIMDTwoVectorFPToInt<1,0,0b11010, "fcvtnu",int_arm64_neon_fcvtnu>;
2078 defm FCVTN : SIMDFPNarrowTwoVector<0, 0, 0b10110, "fcvtn">;
2079 def : Pat<(v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn))),
2080 (FCVTNv4i16 V128:$Rn)>;
2081 def : Pat<(concat_vectors V64:$Rd,
2082 (v4i16 (int_arm64_neon_vcvtfp2hf (v4f32 V128:$Rn)))),
2083 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2084 def : Pat<(v2f32 (fround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
2085 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fround (v2f64 V128:$Rn)))),
2086 (FCVTNv4i32 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
2087 defm FCVTPS : SIMDTwoVectorFPToInt<0,1,0b11010, "fcvtps",int_arm64_neon_fcvtps>;
2088 defm FCVTPU : SIMDTwoVectorFPToInt<1,1,0b11010, "fcvtpu",int_arm64_neon_fcvtpu>;
2089 defm FCVTXN : SIMDFPInexactCvtTwoVector<1, 0, 0b10110, "fcvtxn",
2090 int_arm64_neon_fcvtxn>;
2091 defm FCVTZS : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs", fp_to_sint>;
2092 defm FCVTZU : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu", fp_to_uint>;
2093 let isCodeGenOnly = 1 in {
2094 defm FCVTZS_Int : SIMDTwoVectorFPToInt<0, 1, 0b11011, "fcvtzs",
2095 int_arm64_neon_fcvtzs>;
2096 defm FCVTZU_Int : SIMDTwoVectorFPToInt<1, 1, 0b11011, "fcvtzu",
2097 int_arm64_neon_fcvtzu>;
2099 defm FNEG : SIMDTwoVectorFP<1, 1, 0b01111, "fneg", fneg>;
2100 defm FRECPE : SIMDTwoVectorFP<0, 1, 0b11101, "frecpe", int_arm64_neon_frecpe>;
2101 defm FRINTA : SIMDTwoVectorFP<1, 0, 0b11000, "frinta", frnd>;
2102 defm FRINTI : SIMDTwoVectorFP<1, 1, 0b11001, "frinti", fnearbyint>;
2103 defm FRINTM : SIMDTwoVectorFP<0, 0, 0b11001, "frintm", ffloor>;
2104 defm FRINTN : SIMDTwoVectorFP<0, 0, 0b11000, "frintn", int_arm64_neon_frintn>;
2105 defm FRINTP : SIMDTwoVectorFP<0, 1, 0b11000, "frintp", fceil>;
2106 defm FRINTX : SIMDTwoVectorFP<1, 0, 0b11001, "frintx", frint>;
2107 defm FRINTZ : SIMDTwoVectorFP<0, 1, 0b11001, "frintz", ftrunc>;
2108 defm FRSQRTE: SIMDTwoVectorFP<1, 1, 0b11101, "frsqrte", int_arm64_neon_frsqrte>;
2109 defm FSQRT : SIMDTwoVectorFP<1, 1, 0b11111, "fsqrt", fsqrt>;
2110 defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg",
2111 UnOpFrag<(sub immAllZerosV, node:$LHS)> >;
2112 defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>;
2113 // Aliases for MVN -> NOT.
2114 def : InstAlias<"mvn.8b $Vd, $Vn", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2115 def : InstAlias<"mvn.16b $Vd, $Vn", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2116 def : InstAlias<"mvn $Vd.8b, $Vn.8b", (NOTv8i8 V64:$Vd, V64:$Vn)>;
2117 def : InstAlias<"mvn $Vd.16b, $Vn.16b", (NOTv16i8 V128:$Vd, V128:$Vn)>;
2119 def : Pat<(ARM64neg (v8i8 V64:$Rn)), (NEGv8i8 V64:$Rn)>;
2120 def : Pat<(ARM64neg (v16i8 V128:$Rn)), (NEGv16i8 V128:$Rn)>;
2121 def : Pat<(ARM64neg (v4i16 V64:$Rn)), (NEGv4i16 V64:$Rn)>;
2122 def : Pat<(ARM64neg (v8i16 V128:$Rn)), (NEGv8i16 V128:$Rn)>;
2123 def : Pat<(ARM64neg (v2i32 V64:$Rn)), (NEGv2i32 V64:$Rn)>;
2124 def : Pat<(ARM64neg (v4i32 V128:$Rn)), (NEGv4i32 V128:$Rn)>;
2125 def : Pat<(ARM64neg (v2i64 V128:$Rn)), (NEGv2i64 V128:$Rn)>;
2127 def : Pat<(ARM64not (v8i8 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2128 def : Pat<(ARM64not (v16i8 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2129 def : Pat<(ARM64not (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2130 def : Pat<(ARM64not (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2131 def : Pat<(ARM64not (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2132 def : Pat<(ARM64not (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2133 def : Pat<(ARM64not (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2135 def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2136 def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2137 def : Pat<(vnot (v2i32 V64:$Rn)), (NOTv8i8 V64:$Rn)>;
2138 def : Pat<(vnot (v4i32 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2139 def : Pat<(vnot (v2i64 V128:$Rn)), (NOTv16i8 V128:$Rn)>;
2141 defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_arm64_neon_rbit>;
2142 defm REV16 : SIMDTwoVectorB<0, 0b00, 0b00001, "rev16", ARM64rev16>;
2143 defm REV32 : SIMDTwoVectorBH<1, 0b00000, "rev32", ARM64rev32>;
2144 defm REV64 : SIMDTwoVectorBHS<0, 0b00000, "rev64", ARM64rev64>;
2145 defm SADALP : SIMDLongTwoVectorTied<0, 0b00110, "sadalp",
2146 BinOpFrag<(add node:$LHS, (int_arm64_neon_saddlp node:$RHS))> >;
2147 defm SADDLP : SIMDLongTwoVector<0, 0b00010, "saddlp", int_arm64_neon_saddlp>;
2148 defm SCVTF : SIMDTwoVectorIntToFP<0, 0, 0b11101, "scvtf", sint_to_fp>;
2149 defm SHLL : SIMDVectorLShiftLongBySizeBHS;
2150 defm SQABS : SIMDTwoVectorBHSD<0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2151 defm SQNEG : SIMDTwoVectorBHSD<1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2152 defm SQXTN : SIMDMixedTwoVector<0, 0b10100, "sqxtn", int_arm64_neon_sqxtn>;
2153 defm SQXTUN : SIMDMixedTwoVector<1, 0b10010, "sqxtun", int_arm64_neon_sqxtun>;
2154 defm SUQADD : SIMDTwoVectorBHSDTied<0, 0b00011, "suqadd",int_arm64_neon_suqadd>;
2155 defm UADALP : SIMDLongTwoVectorTied<1, 0b00110, "uadalp",
2156 BinOpFrag<(add node:$LHS, (int_arm64_neon_uaddlp node:$RHS))> >;
2157 defm UADDLP : SIMDLongTwoVector<1, 0b00010, "uaddlp",
2158 int_arm64_neon_uaddlp>;
2159 defm UCVTF : SIMDTwoVectorIntToFP<1, 0, 0b11101, "ucvtf", uint_to_fp>;
2160 defm UQXTN : SIMDMixedTwoVector<1, 0b10100, "uqxtn", int_arm64_neon_uqxtn>;
2161 defm URECPE : SIMDTwoVectorS<0, 1, 0b11100, "urecpe", int_arm64_neon_urecpe>;
2162 defm URSQRTE: SIMDTwoVectorS<1, 1, 0b11100, "ursqrte", int_arm64_neon_ursqrte>;
2163 defm USQADD : SIMDTwoVectorBHSDTied<1, 0b00011, "usqadd",int_arm64_neon_usqadd>;
2164 defm XTN : SIMDMixedTwoVector<0, 0b10010, "xtn", trunc>;
2166 def : Pat<(v2f32 (ARM64rev64 V64:$Rn)), (REV64v2i32 V64:$Rn)>;
2167 def : Pat<(v4f32 (ARM64rev64 V128:$Rn)), (REV64v4i32 V128:$Rn)>;
2169 // Patterns for vector long shift (by element width). These need to match all
2170 // three of zext, sext and anyext so it's easier to pull the patterns out of the
2172 multiclass SIMDVectorLShiftLongBySizeBHSPats<SDPatternOperator ext> {
2173 def : Pat<(ARM64vshl (v8i16 (ext (v8i8 V64:$Rn))), (i32 8)),
2174 (SHLLv8i8 V64:$Rn)>;
2175 def : Pat<(ARM64vshl (v8i16 (ext (extract_high_v16i8 V128:$Rn))), (i32 8)),
2176 (SHLLv16i8 V128:$Rn)>;
2177 def : Pat<(ARM64vshl (v4i32 (ext (v4i16 V64:$Rn))), (i32 16)),
2178 (SHLLv4i16 V64:$Rn)>;
2179 def : Pat<(ARM64vshl (v4i32 (ext (extract_high_v8i16 V128:$Rn))), (i32 16)),
2180 (SHLLv8i16 V128:$Rn)>;
2181 def : Pat<(ARM64vshl (v2i64 (ext (v2i32 V64:$Rn))), (i32 32)),
2182 (SHLLv2i32 V64:$Rn)>;
2183 def : Pat<(ARM64vshl (v2i64 (ext (extract_high_v4i32 V128:$Rn))), (i32 32)),
2184 (SHLLv4i32 V128:$Rn)>;
2187 defm : SIMDVectorLShiftLongBySizeBHSPats<anyext>;
2188 defm : SIMDVectorLShiftLongBySizeBHSPats<zext>;
2189 defm : SIMDVectorLShiftLongBySizeBHSPats<sext>;
2191 //===----------------------------------------------------------------------===//
2192 // Advanced SIMD three vector instructions.
2193 //===----------------------------------------------------------------------===//
2195 defm ADD : SIMDThreeSameVector<0, 0b10000, "add", add>;
2196 defm ADDP : SIMDThreeSameVector<0, 0b10111, "addp", int_arm64_neon_addp>;
2197 defm CMEQ : SIMDThreeSameVector<1, 0b10001, "cmeq", ARM64cmeq>;
2198 defm CMGE : SIMDThreeSameVector<0, 0b00111, "cmge", ARM64cmge>;
2199 defm CMGT : SIMDThreeSameVector<0, 0b00110, "cmgt", ARM64cmgt>;
2200 defm CMHI : SIMDThreeSameVector<1, 0b00110, "cmhi", ARM64cmhi>;
2201 defm CMHS : SIMDThreeSameVector<1, 0b00111, "cmhs", ARM64cmhs>;
2202 defm CMTST : SIMDThreeSameVector<0, 0b10001, "cmtst", ARM64cmtst>;
2203 defm FABD : SIMDThreeSameVectorFP<1,1,0b11010,"fabd", int_arm64_neon_fabd>;
2204 defm FACGE : SIMDThreeSameVectorFPCmp<1,0,0b11101,"facge",int_arm64_neon_facge>;
2205 defm FACGT : SIMDThreeSameVectorFPCmp<1,1,0b11101,"facgt",int_arm64_neon_facgt>;
2206 defm FADDP : SIMDThreeSameVectorFP<1,0,0b11010,"faddp",int_arm64_neon_addp>;
2207 defm FADD : SIMDThreeSameVectorFP<0,0,0b11010,"fadd", fadd>;
2208 defm FCMEQ : SIMDThreeSameVectorFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2209 defm FCMGE : SIMDThreeSameVectorFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2210 defm FCMGT : SIMDThreeSameVectorFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2211 defm FDIV : SIMDThreeSameVectorFP<1,0,0b11111,"fdiv", fdiv>;
2212 defm FMAXNMP : SIMDThreeSameVectorFP<1,0,0b11000,"fmaxnmp", int_arm64_neon_fmaxnmp>;
2213 defm FMAXNM : SIMDThreeSameVectorFP<0,0,0b11000,"fmaxnm", int_arm64_neon_fmaxnm>;
2214 defm FMAXP : SIMDThreeSameVectorFP<1,0,0b11110,"fmaxp", int_arm64_neon_fmaxp>;
2215 defm FMAX : SIMDThreeSameVectorFP<0,0,0b11110,"fmax", ARM64fmax>;
2216 defm FMINNMP : SIMDThreeSameVectorFP<1,1,0b11000,"fminnmp", int_arm64_neon_fminnmp>;
2217 defm FMINNM : SIMDThreeSameVectorFP<0,1,0b11000,"fminnm", int_arm64_neon_fminnm>;
2218 defm FMINP : SIMDThreeSameVectorFP<1,1,0b11110,"fminp", int_arm64_neon_fminp>;
2219 defm FMIN : SIMDThreeSameVectorFP<0,1,0b11110,"fmin", ARM64fmin>;
2221 // NOTE: The operands of the PatFrag are reordered on FMLA/FMLS because the
2222 // instruction expects the addend first, while the fma intrinsic puts it last.
2223 defm FMLA : SIMDThreeSameVectorFPTied<0, 0, 0b11001, "fmla",
2224 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
2225 defm FMLS : SIMDThreeSameVectorFPTied<0, 1, 0b11001, "fmls",
2226 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
2228 // The following def pats catch the case where the LHS of an FMA is negated.
2229 // The TriOpFrag above catches the case where the middle operand is negated.
2230 def : Pat<(v2f32 (fma (fneg V64:$Rn), V64:$Rm, V64:$Rd)),
2231 (FMLSv2f32 V64:$Rd, V64:$Rn, V64:$Rm)>;
2233 def : Pat<(v4f32 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2234 (FMLSv4f32 V128:$Rd, V128:$Rn, V128:$Rm)>;
2236 def : Pat<(v2f64 (fma (fneg V128:$Rn), V128:$Rm, V128:$Rd)),
2237 (FMLSv2f64 V128:$Rd, V128:$Rn, V128:$Rm)>;
2239 defm FMULX : SIMDThreeSameVectorFP<0,0,0b11011,"fmulx", int_arm64_neon_fmulx>;
2240 defm FMUL : SIMDThreeSameVectorFP<1,0,0b11011,"fmul", fmul>;
2241 defm FRECPS : SIMDThreeSameVectorFP<0,0,0b11111,"frecps", int_arm64_neon_frecps>;
2242 defm FRSQRTS : SIMDThreeSameVectorFP<0,1,0b11111,"frsqrts", int_arm64_neon_frsqrts>;
2243 defm FSUB : SIMDThreeSameVectorFP<0,1,0b11010,"fsub", fsub>;
2244 defm MLA : SIMDThreeSameVectorBHSTied<0, 0b10010, "mla",
2245 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))> >;
2246 defm MLS : SIMDThreeSameVectorBHSTied<1, 0b10010, "mls",
2247 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))> >;
2248 defm MUL : SIMDThreeSameVectorBHS<0, 0b10011, "mul", mul>;
2249 defm PMUL : SIMDThreeSameVectorB<1, 0b10011, "pmul", int_arm64_neon_pmul>;
2250 defm SABA : SIMDThreeSameVectorBHSTied<0, 0b01111, "saba",
2251 TriOpFrag<(add node:$LHS, (int_arm64_neon_sabd node:$MHS, node:$RHS))> >;
2252 defm SABD : SIMDThreeSameVectorBHS<0,0b01110,"sabd", int_arm64_neon_sabd>;
2253 defm SHADD : SIMDThreeSameVectorBHS<0,0b00000,"shadd", int_arm64_neon_shadd>;
2254 defm SHSUB : SIMDThreeSameVectorBHS<0,0b00100,"shsub", int_arm64_neon_shsub>;
2255 defm SMAXP : SIMDThreeSameVectorBHS<0,0b10100,"smaxp", int_arm64_neon_smaxp>;
2256 defm SMAX : SIMDThreeSameVectorBHS<0,0b01100,"smax", int_arm64_neon_smax>;
2257 defm SMINP : SIMDThreeSameVectorBHS<0,0b10101,"sminp", int_arm64_neon_sminp>;
2258 defm SMIN : SIMDThreeSameVectorBHS<0,0b01101,"smin", int_arm64_neon_smin>;
2259 defm SQADD : SIMDThreeSameVector<0,0b00001,"sqadd", int_arm64_neon_sqadd>;
2260 defm SQDMULH : SIMDThreeSameVectorHS<0,0b10110,"sqdmulh",int_arm64_neon_sqdmulh>;
2261 defm SQRDMULH : SIMDThreeSameVectorHS<1,0b10110,"sqrdmulh",int_arm64_neon_sqrdmulh>;
2262 defm SQRSHL : SIMDThreeSameVector<0,0b01011,"sqrshl", int_arm64_neon_sqrshl>;
2263 defm SQSHL : SIMDThreeSameVector<0,0b01001,"sqshl", int_arm64_neon_sqshl>;
2264 defm SQSUB : SIMDThreeSameVector<0,0b00101,"sqsub", int_arm64_neon_sqsub>;
2265 defm SRHADD : SIMDThreeSameVectorBHS<0,0b00010,"srhadd",int_arm64_neon_srhadd>;
2266 defm SRSHL : SIMDThreeSameVector<0,0b01010,"srshl", int_arm64_neon_srshl>;
2267 defm SSHL : SIMDThreeSameVector<0,0b01000,"sshl", int_arm64_neon_sshl>;
2268 defm SUB : SIMDThreeSameVector<1,0b10000,"sub", sub>;
2269 defm UABA : SIMDThreeSameVectorBHSTied<1, 0b01111, "uaba",
2270 TriOpFrag<(add node:$LHS, (int_arm64_neon_uabd node:$MHS, node:$RHS))> >;
2271 defm UABD : SIMDThreeSameVectorBHS<1,0b01110,"uabd", int_arm64_neon_uabd>;
2272 defm UHADD : SIMDThreeSameVectorBHS<1,0b00000,"uhadd", int_arm64_neon_uhadd>;
2273 defm UHSUB : SIMDThreeSameVectorBHS<1,0b00100,"uhsub", int_arm64_neon_uhsub>;
2274 defm UMAXP : SIMDThreeSameVectorBHS<1,0b10100,"umaxp", int_arm64_neon_umaxp>;
2275 defm UMAX : SIMDThreeSameVectorBHS<1,0b01100,"umax", int_arm64_neon_umax>;
2276 defm UMINP : SIMDThreeSameVectorBHS<1,0b10101,"uminp", int_arm64_neon_uminp>;
2277 defm UMIN : SIMDThreeSameVectorBHS<1,0b01101,"umin", int_arm64_neon_umin>;
2278 defm UQADD : SIMDThreeSameVector<1,0b00001,"uqadd", int_arm64_neon_uqadd>;
2279 defm UQRSHL : SIMDThreeSameVector<1,0b01011,"uqrshl", int_arm64_neon_uqrshl>;
2280 defm UQSHL : SIMDThreeSameVector<1,0b01001,"uqshl", int_arm64_neon_uqshl>;
2281 defm UQSUB : SIMDThreeSameVector<1,0b00101,"uqsub", int_arm64_neon_uqsub>;
2282 defm URHADD : SIMDThreeSameVectorBHS<1,0b00010,"urhadd", int_arm64_neon_urhadd>;
2283 defm URSHL : SIMDThreeSameVector<1,0b01010,"urshl", int_arm64_neon_urshl>;
2284 defm USHL : SIMDThreeSameVector<1,0b01000,"ushl", int_arm64_neon_ushl>;
2286 defm AND : SIMDLogicalThreeVector<0, 0b00, "and", and>;
2287 defm BIC : SIMDLogicalThreeVector<0, 0b01, "bic",
2288 BinOpFrag<(and node:$LHS, (vnot node:$RHS))> >;
2289 defm BIF : SIMDLogicalThreeVector<1, 0b11, "bif">;
2290 defm BIT : SIMDLogicalThreeVectorTied<1, 0b10, "bit", ARM64bit>;
2291 defm BSL : SIMDLogicalThreeVectorTied<1, 0b01, "bsl",
2292 TriOpFrag<(or (and node:$LHS, node:$MHS), (and (vnot node:$LHS), node:$RHS))>>;
2293 defm EOR : SIMDLogicalThreeVector<1, 0b00, "eor", xor>;
2294 defm ORN : SIMDLogicalThreeVector<0, 0b11, "orn",
2295 BinOpFrag<(or node:$LHS, (vnot node:$RHS))> >;
2296 defm ORR : SIMDLogicalThreeVector<0, 0b10, "orr", or>;
2298 // FIXME: the .16b and .8b variantes should be emitted by the
2299 // AsmWriter. TableGen's AsmWriter-generator doesn't deal with variant syntaxes
2300 // in aliases yet though.
2301 def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}",
2302 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2303 def : InstAlias<"{mov\t$dst.8h, $src.8h|mov.8h\t$dst, $src}",
2304 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2305 def : InstAlias<"{mov\t$dst.4s, $src.4s|mov.4s\t$dst, $src}",
2306 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2307 def : InstAlias<"{mov\t$dst.2d, $src.2d|mov.2d\t$dst, $src}",
2308 (ORRv16i8 V128:$dst, V128:$src, V128:$src), 0>;
2310 def : InstAlias<"{mov\t$dst.8b, $src.8b|mov.8b\t$dst, $src}",
2311 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2312 def : InstAlias<"{mov\t$dst.4h, $src.4h|mov.4h\t$dst, $src}",
2313 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2314 def : InstAlias<"{mov\t$dst.2s, $src.2s|mov.2s\t$dst, $src}",
2315 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2316 def : InstAlias<"{mov\t$dst.1d, $src.1d|mov.1d\t$dst, $src}",
2317 (ORRv8i8 V64:$dst, V64:$src, V64:$src), 0>;
2319 def : InstAlias<"{cmls\t$dst.8b, $src1.8b, $src2.8b" #
2320 "|cmls.8b\t$dst, $src1, $src2}",
2321 (CMHSv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2322 def : InstAlias<"{cmls\t$dst.16b, $src1.16b, $src2.16b" #
2323 "|cmls.16b\t$dst, $src1, $src2}",
2324 (CMHSv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2325 def : InstAlias<"{cmls\t$dst.4h, $src1.4h, $src2.4h" #
2326 "|cmls.4h\t$dst, $src1, $src2}",
2327 (CMHSv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2328 def : InstAlias<"{cmls\t$dst.8h, $src1.8h, $src2.8h" #
2329 "|cmls.8h\t$dst, $src1, $src2}",
2330 (CMHSv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2331 def : InstAlias<"{cmls\t$dst.2s, $src1.2s, $src2.2s" #
2332 "|cmls.2s\t$dst, $src1, $src2}",
2333 (CMHSv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2334 def : InstAlias<"{cmls\t$dst.4s, $src1.4s, $src2.4s" #
2335 "|cmls.4s\t$dst, $src1, $src2}",
2336 (CMHSv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2337 def : InstAlias<"{cmls\t$dst.2d, $src1.2d, $src2.2d" #
2338 "|cmls.2d\t$dst, $src1, $src2}",
2339 (CMHSv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2341 def : InstAlias<"{cmlo\t$dst.8b, $src1.8b, $src2.8b" #
2342 "|cmlo.8b\t$dst, $src1, $src2}",
2343 (CMHIv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2344 def : InstAlias<"{cmlo\t$dst.16b, $src1.16b, $src2.16b" #
2345 "|cmlo.16b\t$dst, $src1, $src2}",
2346 (CMHIv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2347 def : InstAlias<"{cmlo\t$dst.4h, $src1.4h, $src2.4h" #
2348 "|cmlo.4h\t$dst, $src1, $src2}",
2349 (CMHIv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2350 def : InstAlias<"{cmlo\t$dst.8h, $src1.8h, $src2.8h" #
2351 "|cmlo.8h\t$dst, $src1, $src2}",
2352 (CMHIv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2353 def : InstAlias<"{cmlo\t$dst.2s, $src1.2s, $src2.2s" #
2354 "|cmlo.2s\t$dst, $src1, $src2}",
2355 (CMHIv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2356 def : InstAlias<"{cmlo\t$dst.4s, $src1.4s, $src2.4s" #
2357 "|cmlo.4s\t$dst, $src1, $src2}",
2358 (CMHIv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2359 def : InstAlias<"{cmlo\t$dst.2d, $src1.2d, $src2.2d" #
2360 "|cmlo.2d\t$dst, $src1, $src2}",
2361 (CMHIv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2363 def : InstAlias<"{cmle\t$dst.8b, $src1.8b, $src2.8b" #
2364 "|cmle.8b\t$dst, $src1, $src2}",
2365 (CMGEv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2366 def : InstAlias<"{cmle\t$dst.16b, $src1.16b, $src2.16b" #
2367 "|cmle.16b\t$dst, $src1, $src2}",
2368 (CMGEv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2369 def : InstAlias<"{cmle\t$dst.4h, $src1.4h, $src2.4h" #
2370 "|cmle.4h\t$dst, $src1, $src2}",
2371 (CMGEv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2372 def : InstAlias<"{cmle\t$dst.8h, $src1.8h, $src2.8h" #
2373 "|cmle.8h\t$dst, $src1, $src2}",
2374 (CMGEv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2375 def : InstAlias<"{cmle\t$dst.2s, $src1.2s, $src2.2s" #
2376 "|cmle.2s\t$dst, $src1, $src2}",
2377 (CMGEv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2378 def : InstAlias<"{cmle\t$dst.4s, $src1.4s, $src2.4s" #
2379 "|cmle.4s\t$dst, $src1, $src2}",
2380 (CMGEv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2381 def : InstAlias<"{cmle\t$dst.2d, $src1.2d, $src2.2d" #
2382 "|cmle.2d\t$dst, $src1, $src2}",
2383 (CMGEv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2385 def : InstAlias<"{cmlt\t$dst.8b, $src1.8b, $src2.8b" #
2386 "|cmlt.8b\t$dst, $src1, $src2}",
2387 (CMGTv8i8 V64:$dst, V64:$src2, V64:$src1), 0>;
2388 def : InstAlias<"{cmlt\t$dst.16b, $src1.16b, $src2.16b" #
2389 "|cmlt.16b\t$dst, $src1, $src2}",
2390 (CMGTv16i8 V128:$dst, V128:$src2, V128:$src1), 0>;
2391 def : InstAlias<"{cmlt\t$dst.4h, $src1.4h, $src2.4h" #
2392 "|cmlt.4h\t$dst, $src1, $src2}",
2393 (CMGTv4i16 V64:$dst, V64:$src2, V64:$src1), 0>;
2394 def : InstAlias<"{cmlt\t$dst.8h, $src1.8h, $src2.8h" #
2395 "|cmlt.8h\t$dst, $src1, $src2}",
2396 (CMGTv8i16 V128:$dst, V128:$src2, V128:$src1), 0>;
2397 def : InstAlias<"{cmlt\t$dst.2s, $src1.2s, $src2.2s" #
2398 "|cmlt.2s\t$dst, $src1, $src2}",
2399 (CMGTv2i32 V64:$dst, V64:$src2, V64:$src1), 0>;
2400 def : InstAlias<"{cmlt\t$dst.4s, $src1.4s, $src2.4s" #
2401 "|cmlt.4s\t$dst, $src1, $src2}",
2402 (CMGTv4i32 V128:$dst, V128:$src2, V128:$src1), 0>;
2403 def : InstAlias<"{cmlt\t$dst.2d, $src1.2d, $src2.2d" #
2404 "|cmlt.2d\t$dst, $src1, $src2}",
2405 (CMGTv2i64 V128:$dst, V128:$src2, V128:$src1), 0>;
2407 def : InstAlias<"{fcmle\t$dst.2s, $src1.2s, $src2.2s" #
2408 "|fcmle.2s\t$dst, $src1, $src2}",
2409 (FCMGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2410 def : InstAlias<"{fcmle\t$dst.4s, $src1.4s, $src2.4s" #
2411 "|fcmle.4s\t$dst, $src1, $src2}",
2412 (FCMGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2413 def : InstAlias<"{fcmle\t$dst.2d, $src1.2d, $src2.2d" #
2414 "|fcmle.2d\t$dst, $src1, $src2}",
2415 (FCMGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2417 def : InstAlias<"{fcmlt\t$dst.2s, $src1.2s, $src2.2s" #
2418 "|fcmlt.2s\t$dst, $src1, $src2}",
2419 (FCMGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2420 def : InstAlias<"{fcmlt\t$dst.4s, $src1.4s, $src2.4s" #
2421 "|fcmlt.4s\t$dst, $src1, $src2}",
2422 (FCMGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2423 def : InstAlias<"{fcmlt\t$dst.2d, $src1.2d, $src2.2d" #
2424 "|fcmlt.2d\t$dst, $src1, $src2}",
2425 (FCMGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2427 def : InstAlias<"{facle\t$dst.2s, $src1.2s, $src2.2s" #
2428 "|facle.2s\t$dst, $src1, $src2}",
2429 (FACGEv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2430 def : InstAlias<"{facle\t$dst.4s, $src1.4s, $src2.4s" #
2431 "|facle.4s\t$dst, $src1, $src2}",
2432 (FACGEv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2433 def : InstAlias<"{facle\t$dst.2d, $src1.2d, $src2.2d" #
2434 "|facle.2d\t$dst, $src1, $src2}",
2435 (FACGEv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2437 def : InstAlias<"{faclt\t$dst.2s, $src1.2s, $src2.2s" #
2438 "|faclt.2s\t$dst, $src1, $src2}",
2439 (FACGTv2f32 V64:$dst, V64:$src2, V64:$src1), 0>;
2440 def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" #
2441 "|faclt.4s\t$dst, $src1, $src2}",
2442 (FACGTv4f32 V128:$dst, V128:$src2, V128:$src1), 0>;
2443 def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" #
2444 "|faclt.2d\t$dst, $src1, $src2}",
2445 (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>;
2447 //===----------------------------------------------------------------------===//
2448 // Advanced SIMD three scalar instructions.
2449 //===----------------------------------------------------------------------===//
2451 defm ADD : SIMDThreeScalarD<0, 0b10000, "add", add>;
2452 defm CMEQ : SIMDThreeScalarD<1, 0b10001, "cmeq", ARM64cmeq>;
2453 defm CMGE : SIMDThreeScalarD<0, 0b00111, "cmge", ARM64cmge>;
2454 defm CMGT : SIMDThreeScalarD<0, 0b00110, "cmgt", ARM64cmgt>;
2455 defm CMHI : SIMDThreeScalarD<1, 0b00110, "cmhi", ARM64cmhi>;
2456 defm CMHS : SIMDThreeScalarD<1, 0b00111, "cmhs", ARM64cmhs>;
2457 defm CMTST : SIMDThreeScalarD<0, 0b10001, "cmtst", ARM64cmtst>;
2458 defm FABD : SIMDThreeScalarSD<1, 1, 0b11010, "fabd", int_arm64_sisd_fabd>;
2459 def : Pat<(v1f64 (int_arm64_neon_fabd (v1f64 FPR64:$Rn), (v1f64 FPR64:$Rm))),
2460 (FABD64 FPR64:$Rn, FPR64:$Rm)>;
2461 defm FACGE : SIMDThreeScalarFPCmp<1, 0, 0b11101, "facge",
2462 int_arm64_neon_facge>;
2463 defm FACGT : SIMDThreeScalarFPCmp<1, 1, 0b11101, "facgt",
2464 int_arm64_neon_facgt>;
2465 defm FCMEQ : SIMDThreeScalarFPCmp<0, 0, 0b11100, "fcmeq", ARM64fcmeq>;
2466 defm FCMGE : SIMDThreeScalarFPCmp<1, 0, 0b11100, "fcmge", ARM64fcmge>;
2467 defm FCMGT : SIMDThreeScalarFPCmp<1, 1, 0b11100, "fcmgt", ARM64fcmgt>;
2468 defm FMULX : SIMDThreeScalarSD<0, 0, 0b11011, "fmulx", int_arm64_neon_fmulx>;
2469 defm FRECPS : SIMDThreeScalarSD<0, 0, 0b11111, "frecps", int_arm64_neon_frecps>;
2470 defm FRSQRTS : SIMDThreeScalarSD<0, 1, 0b11111, "frsqrts", int_arm64_neon_frsqrts>;
2471 defm SQADD : SIMDThreeScalarBHSD<0, 0b00001, "sqadd", int_arm64_neon_sqadd>;
2472 defm SQDMULH : SIMDThreeScalarHS< 0, 0b10110, "sqdmulh", int_arm64_neon_sqdmulh>;
2473 defm SQRDMULH : SIMDThreeScalarHS< 1, 0b10110, "sqrdmulh", int_arm64_neon_sqrdmulh>;
2474 defm SQRSHL : SIMDThreeScalarBHSD<0, 0b01011, "sqrshl",int_arm64_neon_sqrshl>;
2475 defm SQSHL : SIMDThreeScalarBHSD<0, 0b01001, "sqshl", int_arm64_neon_sqshl>;
2476 defm SQSUB : SIMDThreeScalarBHSD<0, 0b00101, "sqsub", int_arm64_neon_sqsub>;
2477 defm SRSHL : SIMDThreeScalarD< 0, 0b01010, "srshl", int_arm64_neon_srshl>;
2478 defm SSHL : SIMDThreeScalarD< 0, 0b01000, "sshl", int_arm64_neon_sshl>;
2479 defm SUB : SIMDThreeScalarD< 1, 0b10000, "sub", sub>;
2480 defm UQADD : SIMDThreeScalarBHSD<1, 0b00001, "uqadd", int_arm64_neon_uqadd>;
2481 defm UQRSHL : SIMDThreeScalarBHSD<1, 0b01011, "uqrshl",int_arm64_neon_uqrshl>;
2482 defm UQSHL : SIMDThreeScalarBHSD<1, 0b01001, "uqshl", int_arm64_neon_uqshl>;
2483 defm UQSUB : SIMDThreeScalarBHSD<1, 0b00101, "uqsub", int_arm64_neon_uqsub>;
2484 defm URSHL : SIMDThreeScalarD< 1, 0b01010, "urshl", int_arm64_neon_urshl>;
2485 defm USHL : SIMDThreeScalarD< 1, 0b01000, "ushl", int_arm64_neon_ushl>;
2487 def : InstAlias<"cmls $dst, $src1, $src2",
2488 (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2489 def : InstAlias<"cmle $dst, $src1, $src2",
2490 (CMGEv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2491 def : InstAlias<"cmlo $dst, $src1, $src2",
2492 (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2493 def : InstAlias<"cmlt $dst, $src1, $src2",
2494 (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2495 def : InstAlias<"fcmle $dst, $src1, $src2",
2496 (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2497 def : InstAlias<"fcmle $dst, $src1, $src2",
2498 (FCMGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2499 def : InstAlias<"fcmlt $dst, $src1, $src2",
2500 (FCMGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2501 def : InstAlias<"fcmlt $dst, $src1, $src2",
2502 (FCMGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2503 def : InstAlias<"facle $dst, $src1, $src2",
2504 (FACGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2505 def : InstAlias<"facle $dst, $src1, $src2",
2506 (FACGE64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2507 def : InstAlias<"faclt $dst, $src1, $src2",
2508 (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1)>;
2509 def : InstAlias<"faclt $dst, $src1, $src2",
2510 (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1)>;
2512 //===----------------------------------------------------------------------===//
2513 // Advanced SIMD three scalar instructions (mixed operands).
2514 //===----------------------------------------------------------------------===//
2515 defm SQDMULL : SIMDThreeScalarMixedHS<0, 0b11010, "sqdmull",
2516 int_arm64_neon_sqdmulls_scalar>;
2517 defm SQDMLAL : SIMDThreeScalarMixedTiedHS<0, 0b10010, "sqdmlal">;
2518 defm SQDMLSL : SIMDThreeScalarMixedTiedHS<0, 0b10110, "sqdmlsl">;
2520 //===----------------------------------------------------------------------===//
2521 // Advanced SIMD two scalar instructions.
2522 //===----------------------------------------------------------------------===//
2524 defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", int_arm64_neon_abs>;
2525 defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", ARM64cmeqz>;
2526 defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", ARM64cmgez>;
2527 defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", ARM64cmgtz>;
2528 defm CMLE : SIMDCmpTwoScalarD< 1, 0b01001, "cmle", ARM64cmlez>;
2529 defm CMLT : SIMDCmpTwoScalarD< 0, 0b01010, "cmlt", ARM64cmltz>;
2530 defm FCMEQ : SIMDCmpTwoScalarSD<0, 1, 0b01101, "fcmeq", ARM64fcmeqz>;
2531 defm FCMGE : SIMDCmpTwoScalarSD<1, 1, 0b01100, "fcmge", ARM64fcmgez>;
2532 defm FCMGT : SIMDCmpTwoScalarSD<0, 1, 0b01100, "fcmgt", ARM64fcmgtz>;
2533 defm FCMLE : SIMDCmpTwoScalarSD<1, 1, 0b01101, "fcmle", ARM64fcmlez>;
2534 defm FCMLT : SIMDCmpTwoScalarSD<0, 1, 0b01110, "fcmlt", ARM64fcmltz>;
2535 defm FCVTAS : SIMDTwoScalarSD< 0, 0, 0b11100, "fcvtas">;
2536 defm FCVTAU : SIMDTwoScalarSD< 1, 0, 0b11100, "fcvtau">;
2537 defm FCVTMS : SIMDTwoScalarSD< 0, 0, 0b11011, "fcvtms">;
2538 defm FCVTMU : SIMDTwoScalarSD< 1, 0, 0b11011, "fcvtmu">;
2539 defm FCVTNS : SIMDTwoScalarSD< 0, 0, 0b11010, "fcvtns">;
2540 defm FCVTNU : SIMDTwoScalarSD< 1, 0, 0b11010, "fcvtnu">;
2541 defm FCVTPS : SIMDTwoScalarSD< 0, 1, 0b11010, "fcvtps">;
2542 defm FCVTPU : SIMDTwoScalarSD< 1, 1, 0b11010, "fcvtpu">;
2543 def FCVTXNv1i64 : SIMDInexactCvtTwoScalar<0b10110, "fcvtxn">;
2544 defm FCVTZS : SIMDTwoScalarSD< 0, 1, 0b11011, "fcvtzs">;
2545 defm FCVTZU : SIMDTwoScalarSD< 1, 1, 0b11011, "fcvtzu">;
2546 defm FRECPE : SIMDTwoScalarSD< 0, 1, 0b11101, "frecpe">;
2547 defm FRECPX : SIMDTwoScalarSD< 0, 1, 0b11111, "frecpx">;
2548 defm FRSQRTE : SIMDTwoScalarSD< 1, 1, 0b11101, "frsqrte">;
2549 defm NEG : SIMDTwoScalarD< 1, 0b01011, "neg">;
2550 defm SCVTF : SIMDTwoScalarCVTSD< 0, 0, 0b11101, "scvtf", ARM64sitof>;
2551 defm SQABS : SIMDTwoScalarBHSD< 0, 0b00111, "sqabs", int_arm64_neon_sqabs>;
2552 defm SQNEG : SIMDTwoScalarBHSD< 1, 0b00111, "sqneg", int_arm64_neon_sqneg>;
2553 defm SQXTN : SIMDTwoScalarMixedBHS< 0, 0b10100, "sqxtn", int_arm64_neon_scalar_sqxtn>;
2554 defm SQXTUN : SIMDTwoScalarMixedBHS< 1, 0b10010, "sqxtun", int_arm64_neon_scalar_sqxtun>;
2555 defm SUQADD : SIMDTwoScalarBHSDTied< 0, 0b00011, "suqadd",
2556 int_arm64_neon_suqadd>;
2557 defm UCVTF : SIMDTwoScalarCVTSD< 1, 0, 0b11101, "ucvtf", ARM64uitof>;
2558 defm UQXTN : SIMDTwoScalarMixedBHS<1, 0b10100, "uqxtn", int_arm64_neon_scalar_uqxtn>;
2559 defm USQADD : SIMDTwoScalarBHSDTied< 1, 0b00011, "usqadd",
2560 int_arm64_neon_usqadd>;
2562 def : Pat<(v1i64 (int_arm64_neon_fcvtas (v1f64 FPR64:$Rn))),
2563 (FCVTASv1i64 FPR64:$Rn)>;
2564 def : Pat<(v1i64 (int_arm64_neon_fcvtau (v1f64 FPR64:$Rn))),
2565 (FCVTAUv1i64 FPR64:$Rn)>;
2566 def : Pat<(v1i64 (int_arm64_neon_fcvtms (v1f64 FPR64:$Rn))),
2567 (FCVTMSv1i64 FPR64:$Rn)>;
2568 def : Pat<(v1i64 (int_arm64_neon_fcvtmu (v1f64 FPR64:$Rn))),
2569 (FCVTMUv1i64 FPR64:$Rn)>;
2570 def : Pat<(v1i64 (int_arm64_neon_fcvtns (v1f64 FPR64:$Rn))),
2571 (FCVTNSv1i64 FPR64:$Rn)>;
2572 def : Pat<(v1i64 (int_arm64_neon_fcvtnu (v1f64 FPR64:$Rn))),
2573 (FCVTNUv1i64 FPR64:$Rn)>;
2574 def : Pat<(v1i64 (int_arm64_neon_fcvtps (v1f64 FPR64:$Rn))),
2575 (FCVTPSv1i64 FPR64:$Rn)>;
2576 def : Pat<(v1i64 (int_arm64_neon_fcvtpu (v1f64 FPR64:$Rn))),
2577 (FCVTPUv1i64 FPR64:$Rn)>;
2578 def : Pat<(v1f64 (int_arm64_neon_frecpe (v1f64 FPR64:$Rn))),
2579 (FRECPEv1i64 FPR64:$Rn)>;
2580 def : Pat<(v1f64 (int_arm64_neon_frsqrte (v1f64 FPR64:$Rn))),
2581 (FRSQRTEv1i64 FPR64:$Rn)>;
2583 // If an integer is about to be converted to a floating point value,
2584 // just load it on the floating point unit.
2585 // Here are the patterns for 8 and 16-bits to float.
2587 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2588 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2589 (LDRBro ro_indexed8:$addr), bsub))>;
2590 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2591 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2592 (LDRBui am_indexed8:$addr), bsub))>;
2593 def : Pat <(f32 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2594 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2595 (LDURBi am_unscaled8:$addr), bsub))>;
2596 // 16-bits -> float.
2597 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2598 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2599 (LDRHro ro_indexed16:$addr), hsub))>;
2600 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2601 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2602 (LDRHui am_indexed16:$addr), hsub))>;
2603 def : Pat <(f32 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2604 (UCVTFv1i32 (INSERT_SUBREG (f32 (IMPLICIT_DEF)),
2605 (LDURHi am_unscaled16:$addr), hsub))>;
2606 // 32-bits are handled in target specific dag combine:
2607 // performIntToFpCombine.
2608 // 64-bits integer to 32-bits floating point, not possible with
2609 // UCVTF on floating point registers (both source and destination
2610 // must have the same size).
2612 // Here are the patterns for 8, 16, 32, and 64-bits to double.
2613 // 8-bits -> double.
2614 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 ro_indexed8:$addr)))),
2615 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2616 (LDRBro ro_indexed8:$addr), bsub))>;
2617 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_indexed8:$addr)))),
2618 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2619 (LDRBui am_indexed8:$addr), bsub))>;
2620 def : Pat <(f64 (uint_to_fp (i32 (zextloadi8 am_unscaled8:$addr)))),
2621 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2622 (LDURBi am_unscaled8:$addr), bsub))>;
2623 // 16-bits -> double.
2624 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 ro_indexed16:$addr)))),
2625 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2626 (LDRHro ro_indexed16:$addr), hsub))>;
2627 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_indexed16:$addr)))),
2628 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2629 (LDRHui am_indexed16:$addr), hsub))>;
2630 def : Pat <(f64 (uint_to_fp (i32 (zextloadi16 am_unscaled16:$addr)))),
2631 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2632 (LDURHi am_unscaled16:$addr), hsub))>;
2633 // 32-bits -> double.
2634 def : Pat <(f64 (uint_to_fp (i32 (load ro_indexed32:$addr)))),
2635 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2636 (LDRSro ro_indexed32:$addr), ssub))>;
2637 def : Pat <(f64 (uint_to_fp (i32 (load am_indexed32:$addr)))),
2638 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2639 (LDRSui am_indexed32:$addr), ssub))>;
2640 def : Pat <(f64 (uint_to_fp (i32 (load am_unscaled32:$addr)))),
2641 (UCVTFv1i64 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
2642 (LDURSi am_unscaled32:$addr), ssub))>;
2643 // 64-bits -> double are handled in target specific dag combine:
2644 // performIntToFpCombine.
2646 //===----------------------------------------------------------------------===//
2647 // Advanced SIMD three different-sized vector instructions.
2648 //===----------------------------------------------------------------------===//
2650 defm ADDHN : SIMDNarrowThreeVectorBHS<0,0b0100,"addhn", int_arm64_neon_addhn>;
2651 defm SUBHN : SIMDNarrowThreeVectorBHS<0,0b0110,"subhn", int_arm64_neon_subhn>;
2652 defm RADDHN : SIMDNarrowThreeVectorBHS<1,0b0100,"raddhn",int_arm64_neon_raddhn>;
2653 defm RSUBHN : SIMDNarrowThreeVectorBHS<1,0b0110,"rsubhn",int_arm64_neon_rsubhn>;
2654 defm PMULL : SIMDDifferentThreeVectorBD<0,0b1110,"pmull",int_arm64_neon_pmull>;
2655 defm SABAL : SIMDLongThreeVectorTiedBHSabal<0,0b0101,"sabal",
2656 int_arm64_neon_sabd>;
2657 defm SABDL : SIMDLongThreeVectorBHSabdl<0, 0b0111, "sabdl",
2658 int_arm64_neon_sabd>;
2659 defm SADDL : SIMDLongThreeVectorBHS< 0, 0b0000, "saddl",
2660 BinOpFrag<(add (sext node:$LHS), (sext node:$RHS))>>;
2661 defm SADDW : SIMDWideThreeVectorBHS< 0, 0b0001, "saddw",
2662 BinOpFrag<(add node:$LHS, (sext node:$RHS))>>;
2663 defm SMLAL : SIMDLongThreeVectorTiedBHS<0, 0b1000, "smlal",
2664 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2665 defm SMLSL : SIMDLongThreeVectorTiedBHS<0, 0b1010, "smlsl",
2666 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
2667 defm SMULL : SIMDLongThreeVectorBHS<0, 0b1100, "smull", int_arm64_neon_smull>;
2668 defm SQDMLAL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1001, "sqdmlal",
2669 int_arm64_neon_sqadd>;
2670 defm SQDMLSL : SIMDLongThreeVectorSQDMLXTiedHS<0, 0b1011, "sqdmlsl",
2671 int_arm64_neon_sqsub>;
2672 defm SQDMULL : SIMDLongThreeVectorHS<0, 0b1101, "sqdmull",
2673 int_arm64_neon_sqdmull>;
2674 defm SSUBL : SIMDLongThreeVectorBHS<0, 0b0010, "ssubl",
2675 BinOpFrag<(sub (sext node:$LHS), (sext node:$RHS))>>;
2676 defm SSUBW : SIMDWideThreeVectorBHS<0, 0b0011, "ssubw",
2677 BinOpFrag<(sub node:$LHS, (sext node:$RHS))>>;
2678 defm UABAL : SIMDLongThreeVectorTiedBHSabal<1, 0b0101, "uabal",
2679 int_arm64_neon_uabd>;
2680 defm UABDL : SIMDLongThreeVectorBHSabdl<1, 0b0111, "uabdl",
2681 int_arm64_neon_uabd>;
2682 defm UADDL : SIMDLongThreeVectorBHS<1, 0b0000, "uaddl",
2683 BinOpFrag<(add (zext node:$LHS), (zext node:$RHS))>>;
2684 defm UADDW : SIMDWideThreeVectorBHS<1, 0b0001, "uaddw",
2685 BinOpFrag<(add node:$LHS, (zext node:$RHS))>>;
2686 defm UMLAL : SIMDLongThreeVectorTiedBHS<1, 0b1000, "umlal",
2687 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2688 defm UMLSL : SIMDLongThreeVectorTiedBHS<1, 0b1010, "umlsl",
2689 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
2690 defm UMULL : SIMDLongThreeVectorBHS<1, 0b1100, "umull", int_arm64_neon_umull>;
2691 defm USUBL : SIMDLongThreeVectorBHS<1, 0b0010, "usubl",
2692 BinOpFrag<(sub (zext node:$LHS), (zext node:$RHS))>>;
2693 defm USUBW : SIMDWideThreeVectorBHS< 1, 0b0011, "usubw",
2694 BinOpFrag<(sub node:$LHS, (zext node:$RHS))>>;
2696 // CodeGen patterns for addhn and subhn instructions, which can actually be
2697 // written in LLVM IR without too much difficulty.
2700 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm), (i32 8))))),
2701 (ADDHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2702 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2704 (ADDHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2705 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2707 (ADDHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2708 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2709 (trunc (v8i16 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2711 (ADDHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2712 V128:$Rn, V128:$Rm)>;
2713 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2714 (trunc (v4i32 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2716 (ADDHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2717 V128:$Rn, V128:$Rm)>;
2718 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2719 (trunc (v2i64 (ARM64vlshr (add V128:$Rn, V128:$Rm),
2721 (ADDHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2722 V128:$Rn, V128:$Rm)>;
2725 def : Pat<(v8i8 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm), (i32 8))))),
2726 (SUBHNv8i16_v8i8 V128:$Rn, V128:$Rm)>;
2727 def : Pat<(v4i16 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2729 (SUBHNv4i32_v4i16 V128:$Rn, V128:$Rm)>;
2730 def : Pat<(v2i32 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2732 (SUBHNv2i64_v2i32 V128:$Rn, V128:$Rm)>;
2733 def : Pat<(concat_vectors (v8i8 V64:$Rd),
2734 (trunc (v8i16 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2736 (SUBHNv8i16_v16i8 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2737 V128:$Rn, V128:$Rm)>;
2738 def : Pat<(concat_vectors (v4i16 V64:$Rd),
2739 (trunc (v4i32 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2741 (SUBHNv4i32_v8i16 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2742 V128:$Rn, V128:$Rm)>;
2743 def : Pat<(concat_vectors (v2i32 V64:$Rd),
2744 (trunc (v2i64 (ARM64vlshr (sub V128:$Rn, V128:$Rm),
2746 (SUBHNv2i64_v4i32 (SUBREG_TO_REG (i32 0), V64:$Rd, dsub),
2747 V128:$Rn, V128:$Rm)>;
2749 //----------------------------------------------------------------------------
2750 // AdvSIMD bitwise extract from vector instruction.
2751 //----------------------------------------------------------------------------
2753 defm EXT : SIMDBitwiseExtract<"ext">;
2755 def : Pat<(v4i16 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2756 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2757 def : Pat<(v8i16 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2758 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2759 def : Pat<(v2i32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2760 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2761 def : Pat<(v2f32 (ARM64ext V64:$Rn, V64:$Rm, (i32 imm:$imm))),
2762 (EXTv8i8 V64:$Rn, V64:$Rm, imm:$imm)>;
2763 def : Pat<(v4i32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2764 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2765 def : Pat<(v4f32 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2766 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2767 def : Pat<(v2i64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2768 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2769 def : Pat<(v2f64 (ARM64ext V128:$Rn, V128:$Rm, (i32 imm:$imm))),
2770 (EXTv16i8 V128:$Rn, V128:$Rm, imm:$imm)>;
2772 // We use EXT to handle extract_subvector to copy the upper 64-bits of a
2774 def : Pat<(v8i8 (extract_subvector V128:$Rn, (i64 8))),
2775 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2776 def : Pat<(v4i16 (extract_subvector V128:$Rn, (i64 4))),
2777 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2778 def : Pat<(v2i32 (extract_subvector V128:$Rn, (i64 2))),
2779 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2780 def : Pat<(v1i64 (extract_subvector V128:$Rn, (i64 1))),
2781 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2782 def : Pat<(v2f32 (extract_subvector V128:$Rn, (i64 2))),
2783 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2784 def : Pat<(v1f64 (extract_subvector V128:$Rn, (i64 1))),
2785 (EXTRACT_SUBREG (EXTv16i8 V128:$Rn, V128:$Rn, 8), dsub)>;
2788 //----------------------------------------------------------------------------
2789 // AdvSIMD zip vector
2790 //----------------------------------------------------------------------------
2792 defm TRN1 : SIMDZipVector<0b010, "trn1", ARM64trn1>;
2793 defm TRN2 : SIMDZipVector<0b110, "trn2", ARM64trn2>;
2794 defm UZP1 : SIMDZipVector<0b001, "uzp1", ARM64uzp1>;
2795 defm UZP2 : SIMDZipVector<0b101, "uzp2", ARM64uzp2>;
2796 defm ZIP1 : SIMDZipVector<0b011, "zip1", ARM64zip1>;
2797 defm ZIP2 : SIMDZipVector<0b111, "zip2", ARM64zip2>;
2799 //----------------------------------------------------------------------------
2800 // AdvSIMD TBL/TBX instructions
2801 //----------------------------------------------------------------------------
2803 defm TBL : SIMDTableLookup< 0, "tbl">;
2804 defm TBX : SIMDTableLookupTied<1, "tbx">;
2806 def : Pat<(v8i8 (int_arm64_neon_tbl1 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
2807 (TBLv8i8One VecListOne128:$Rn, V64:$Ri)>;
2808 def : Pat<(v16i8 (int_arm64_neon_tbl1 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
2809 (TBLv16i8One V128:$Ri, V128:$Rn)>;
2811 def : Pat<(v8i8 (int_arm64_neon_tbx1 (v8i8 V64:$Rd),
2812 (v16i8 VecListOne128:$Rn), (v8i8 V64:$Ri))),
2813 (TBXv8i8One V64:$Rd, VecListOne128:$Rn, V64:$Ri)>;
2814 def : Pat<(v16i8 (int_arm64_neon_tbx1 (v16i8 V128:$Rd),
2815 (v16i8 V128:$Ri), (v16i8 V128:$Rn))),
2816 (TBXv16i8One V128:$Rd, V128:$Ri, V128:$Rn)>;
2819 //----------------------------------------------------------------------------
2820 // AdvSIMD scalar CPY instruction
2821 //----------------------------------------------------------------------------
2823 defm CPY : SIMDScalarCPY<"cpy">;
2825 //----------------------------------------------------------------------------
2826 // AdvSIMD scalar pairwise instructions
2827 //----------------------------------------------------------------------------
2829 defm ADDP : SIMDPairwiseScalarD<0, 0b11011, "addp">;
2830 defm FADDP : SIMDPairwiseScalarSD<1, 0, 0b01101, "faddp">;
2831 defm FMAXNMP : SIMDPairwiseScalarSD<1, 0, 0b01100, "fmaxnmp">;
2832 defm FMAXP : SIMDPairwiseScalarSD<1, 0, 0b01111, "fmaxp">;
2833 defm FMINNMP : SIMDPairwiseScalarSD<1, 1, 0b01100, "fminnmp">;
2834 defm FMINP : SIMDPairwiseScalarSD<1, 1, 0b01111, "fminp">;
2835 def : Pat<(i64 (int_arm64_neon_saddv (v2i64 V128:$Rn))),
2836 (ADDPv2i64p V128:$Rn)>;
2837 def : Pat<(i64 (int_arm64_neon_uaddv (v2i64 V128:$Rn))),
2838 (ADDPv2i64p V128:$Rn)>;
2839 def : Pat<(f32 (int_arm64_neon_faddv (v2f32 V64:$Rn))),
2840 (FADDPv2i32p V64:$Rn)>;
2841 def : Pat<(f32 (int_arm64_neon_faddv (v4f32 V128:$Rn))),
2842 (FADDPv2i32p (EXTRACT_SUBREG (FADDPv4f32 V128:$Rn, V128:$Rn), dsub))>;
2843 def : Pat<(f64 (int_arm64_neon_faddv (v2f64 V128:$Rn))),
2844 (FADDPv2i64p V128:$Rn)>;
2845 def : Pat<(f64 (int_arm64_neon_fmaxnmv (v2f64 V128:$Rn))),
2846 (FMAXNMPv2i64p V128:$Rn)>;
2847 def : Pat<(f64 (int_arm64_neon_fmaxv (v2f64 V128:$Rn))),
2848 (FMAXPv2i64p V128:$Rn)>;
2849 def : Pat<(f64 (int_arm64_neon_fminnmv (v2f64 V128:$Rn))),
2850 (FMINNMPv2i64p V128:$Rn)>;
2851 def : Pat<(f64 (int_arm64_neon_fminv (v2f64 V128:$Rn))),
2852 (FMINPv2i64p V128:$Rn)>;
2854 //----------------------------------------------------------------------------
2855 // AdvSIMD INS/DUP instructions
2856 //----------------------------------------------------------------------------
2858 def DUPv8i8gpr : SIMDDupFromMain<0, 0b00001, ".8b", v8i8, V64, GPR32>;
2859 def DUPv16i8gpr : SIMDDupFromMain<1, 0b00001, ".16b", v16i8, V128, GPR32>;
2860 def DUPv4i16gpr : SIMDDupFromMain<0, 0b00010, ".4h", v4i16, V64, GPR32>;
2861 def DUPv8i16gpr : SIMDDupFromMain<1, 0b00010, ".8h", v8i16, V128, GPR32>;
2862 def DUPv2i32gpr : SIMDDupFromMain<0, 0b00100, ".2s", v2i32, V64, GPR32>;
2863 def DUPv4i32gpr : SIMDDupFromMain<1, 0b00100, ".4s", v4i32, V128, GPR32>;
2864 def DUPv2i64gpr : SIMDDupFromMain<1, 0b01000, ".2d", v2i64, V128, GPR64>;
2866 def DUPv2i64lane : SIMDDup64FromElement;
2867 def DUPv2i32lane : SIMDDup32FromElement<0, ".2s", v2i32, V64>;
2868 def DUPv4i32lane : SIMDDup32FromElement<1, ".4s", v4i32, V128>;
2869 def DUPv4i16lane : SIMDDup16FromElement<0, ".4h", v4i16, V64>;
2870 def DUPv8i16lane : SIMDDup16FromElement<1, ".8h", v8i16, V128>;
2871 def DUPv8i8lane : SIMDDup8FromElement <0, ".8b", v8i8, V64>;
2872 def DUPv16i8lane : SIMDDup8FromElement <1, ".16b", v16i8, V128>;
2874 def : Pat<(v2f32 (ARM64dup (f32 FPR32:$Rn))),
2875 (v2f32 (DUPv2i32lane
2876 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
2878 def : Pat<(v4f32 (ARM64dup (f32 FPR32:$Rn))),
2879 (v4f32 (DUPv4i32lane
2880 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rn, ssub),
2882 def : Pat<(v2f64 (ARM64dup (f64 FPR64:$Rn))),
2883 (v2f64 (DUPv2i64lane
2884 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rn, dsub),
2887 def : Pat<(v2f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
2888 (DUPv2i32lane V128:$Rn, VectorIndexS:$imm)>;
2889 def : Pat<(v4f32 (ARM64duplane32 (v4f32 V128:$Rn), VectorIndexS:$imm)),
2890 (DUPv4i32lane V128:$Rn, VectorIndexS:$imm)>;
2891 def : Pat<(v2f64 (ARM64duplane64 (v2f64 V128:$Rn), VectorIndexD:$imm)),
2892 (DUPv2i64lane V128:$Rn, VectorIndexD:$imm)>;
2897 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
2898 (i32 (SMOVvi8to32 V128:$Rn, VectorIndexB:$idx))>;
2899 def : Pat<(sext_inreg (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx), i8),
2900 (i64 (SMOVvi8to64 V128:$Rn, VectorIndexB:$idx))>;
2901 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
2902 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
2903 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
2904 (i64 (SMOVvi16to64 V128:$Rn, VectorIndexH:$idx))>;
2905 def : Pat<(sext_inreg (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),i16),
2906 (i32 (SMOVvi16to32 V128:$Rn, VectorIndexH:$idx))>;
2907 def : Pat<(sext (i32 (vector_extract (v4i32 V128:$Rn), VectorIndexS:$idx))),
2908 (i64 (SMOVvi32to64 V128:$Rn, VectorIndexS:$idx))>;
2910 // Extracting i8 or i16 elements will have the zero-extend transformed to
2911 // an 'and' mask by type legalization since neither i8 nor i16 are legal types
2912 // for ARM64. Match these patterns here since UMOV already zeroes out the high
2913 // bits of the destination register.
2914 def : Pat<(and (vector_extract (v16i8 V128:$Rn), VectorIndexB:$idx),
2916 (i32 (UMOVvi8 V128:$Rn, VectorIndexB:$idx))>;
2917 def : Pat<(and (vector_extract (v8i16 V128:$Rn), VectorIndexH:$idx),
2919 (i32 (UMOVvi16 V128:$Rn, VectorIndexH:$idx))>;
2923 def : Pat<(v16i8 (scalar_to_vector GPR32:$Rn)),
2924 (INSvi8gpr (v16i8 (IMPLICIT_DEF)), (i64 0), GPR32:$Rn)>;
2925 def : Pat<(v8i8 (scalar_to_vector GPR32:$Rn)),
2927 (INSvi8gpr (v16i8 (IMPLICIT_DEF)), (i64 0), GPR32:$Rn), dsub)>;
2929 def : Pat<(v8i16 (scalar_to_vector GPR32:$Rn)),
2930 (INSvi16gpr (v8i16 (IMPLICIT_DEF)), (i64 0), GPR32:$Rn)>;
2931 def : Pat<(v4i16 (scalar_to_vector GPR32:$Rn)),
2933 (INSvi16gpr (v8i16 (IMPLICIT_DEF)), (i64 0), GPR32:$Rn), dsub)>;
2935 def : Pat<(v2i32 (scalar_to_vector (i32 FPR32:$Rn))),
2936 (v2i32 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
2937 (i32 FPR32:$Rn), ssub))>;
2938 def : Pat<(v4i32 (scalar_to_vector (i32 FPR32:$Rn))),
2939 (v4i32 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
2940 (i32 FPR32:$Rn), ssub))>;
2941 def : Pat<(v2i64 (scalar_to_vector (i64 FPR64:$Rn))),
2942 (v2i64 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
2943 (i64 FPR64:$Rn), dsub))>;
2945 def : Pat<(v4f32 (scalar_to_vector (f32 FPR32:$Rn))),
2946 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
2947 def : Pat<(v2f32 (scalar_to_vector (f32 FPR32:$Rn))),
2948 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), FPR32:$Rn, ssub)>;
2949 def : Pat<(v2f64 (scalar_to_vector (f64 FPR64:$Rn))),
2950 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rn, dsub)>;
2952 def : Pat<(v2f32 (vector_insert (v2f32 V64:$Rn),
2953 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
2956 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), V64:$Rn, dsub)),
2958 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
2961 def : Pat<(v4f32 (vector_insert (v4f32 V128:$Rn),
2962 (f32 FPR32:$Rm), (i64 VectorIndexS:$imm))),
2964 V128:$Rn, VectorIndexS:$imm,
2965 (v4f32 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR32:$Rm, ssub)),
2967 def : Pat<(v2f64 (vector_insert (v2f64 V128:$Rn),
2968 (f64 FPR64:$Rm), (i64 VectorIndexD:$imm))),
2970 V128:$Rn, VectorIndexD:$imm,
2971 (v2f64 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$Rm, dsub)),
2974 // Copy an element at a constant index in one vector into a constant indexed
2975 // element of another.
2976 // FIXME refactor to a shared class/dev parameterized on vector type, vector
2977 // index type and INS extension
2978 def : Pat<(v16i8 (int_arm64_neon_vcopy_lane
2979 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
2980 VectorIndexB:$idx2)),
2982 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
2984 def : Pat<(v8i16 (int_arm64_neon_vcopy_lane
2985 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
2986 VectorIndexH:$idx2)),
2988 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
2990 def : Pat<(v4i32 (int_arm64_neon_vcopy_lane
2991 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
2992 VectorIndexS:$idx2)),
2994 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
2996 def : Pat<(v2i64 (int_arm64_neon_vcopy_lane
2997 (v2i64 V128:$Vd), VectorIndexD:$idx, (v2i64 V128:$Vs),
2998 VectorIndexD:$idx2)),
3000 V128:$Vd, VectorIndexD:$idx, V128:$Vs, VectorIndexD:$idx2)
3003 // Floating point vector extractions are codegen'd as either a sequence of
3004 // subregister extractions, possibly fed by an INS if the lane number is
3005 // anything other than zero.
3006 def : Pat<(vector_extract (v2f64 V128:$Rn), 0),
3007 (f64 (EXTRACT_SUBREG V128:$Rn, dsub))>;
3008 def : Pat<(vector_extract (v4f32 V128:$Rn), 0),
3009 (f32 (EXTRACT_SUBREG V128:$Rn, ssub))>;
3010 def : Pat<(vector_extract (v2f64 V128:$Rn), VectorIndexD:$idx),
3011 (f64 (EXTRACT_SUBREG
3012 (INSvi64lane (v2f64 (IMPLICIT_DEF)), 0,
3013 V128:$Rn, VectorIndexD:$idx),
3015 def : Pat<(vector_extract (v4f32 V128:$Rn), VectorIndexS:$idx),
3016 (f32 (EXTRACT_SUBREG
3017 (INSvi32lane (v4f32 (IMPLICIT_DEF)), 0,
3018 V128:$Rn, VectorIndexS:$idx),
3021 // All concat_vectors operations are canonicalised to act on i64 vectors for
3022 // ARM64. In the general case we need an instruction, which had just as well be
3024 class ConcatPat<ValueType DstTy, ValueType SrcTy>
3025 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rd), V64:$Rn)),
3026 (INSvi64lane (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), 1,
3027 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub), 0)>;
3029 def : ConcatPat<v2i64, v1i64>;
3030 def : ConcatPat<v2f64, v1f64>;
3031 def : ConcatPat<v4i32, v2i32>;
3032 def : ConcatPat<v4f32, v2f32>;
3033 def : ConcatPat<v8i16, v4i16>;
3034 def : ConcatPat<v16i8, v8i8>;
3036 // If the high lanes are undef, though, we can just ignore them:
3037 class ConcatUndefPat<ValueType DstTy, ValueType SrcTy>
3038 : Pat<(DstTy (concat_vectors (SrcTy V64:$Rn), undef)),
3039 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rn, dsub)>;
3041 def : ConcatUndefPat<v2i64, v1i64>;
3042 def : ConcatUndefPat<v2f64, v1f64>;
3043 def : ConcatUndefPat<v4i32, v2i32>;
3044 def : ConcatUndefPat<v4f32, v2f32>;
3045 def : ConcatUndefPat<v8i16, v4i16>;
3046 def : ConcatUndefPat<v16i8, v8i8>;
3048 //----------------------------------------------------------------------------
3049 // AdvSIMD across lanes instructions
3050 //----------------------------------------------------------------------------
3052 defm ADDV : SIMDAcrossLanesBHS<0, 0b11011, "addv">;
3053 defm SMAXV : SIMDAcrossLanesBHS<0, 0b01010, "smaxv">;
3054 defm SMINV : SIMDAcrossLanesBHS<0, 0b11010, "sminv">;
3055 defm UMAXV : SIMDAcrossLanesBHS<1, 0b01010, "umaxv">;
3056 defm UMINV : SIMDAcrossLanesBHS<1, 0b11010, "uminv">;
3057 defm SADDLV : SIMDAcrossLanesHSD<0, 0b00011, "saddlv">;
3058 defm UADDLV : SIMDAcrossLanesHSD<1, 0b00011, "uaddlv">;
3059 defm FMAXNMV : SIMDAcrossLanesS<0b01100, 0, "fmaxnmv", int_arm64_neon_fmaxnmv>;
3060 def : Pat<(f32 (int_arm64_neon_fmaxnmv (v2f32 V64:$Rn))),
3061 (EXTRACT_SUBREG (FMAXNMPv2f32 V64:$Rn, V64:$Rn), ssub)>;
3062 defm FMAXV : SIMDAcrossLanesS<0b01111, 0, "fmaxv", int_arm64_neon_fmaxv>;
3063 def : Pat<(f32 (int_arm64_neon_fmaxv (v2f32 V64:$Rn))),
3064 (EXTRACT_SUBREG (FMAXPv2f32 V64:$Rn, V64:$Rn), ssub)>;
3065 defm FMINNMV : SIMDAcrossLanesS<0b01100, 1, "fminnmv", int_arm64_neon_fminnmv>;
3066 def : Pat<(f32 (int_arm64_neon_fminnmv (v2f32 V64:$Rn))),
3067 (EXTRACT_SUBREG (FMINNMPv2f32 V64:$Rn, V64:$Rn), ssub)>;
3068 defm FMINV : SIMDAcrossLanesS<0b01111, 1, "fminv", int_arm64_neon_fminv>;
3069 def : Pat<(f32 (int_arm64_neon_fminv (v2f32 V64:$Rn))),
3070 (EXTRACT_SUBREG (FMINPv2f32 V64:$Rn, V64:$Rn), ssub)>;
3072 multiclass SIMDAcrossLanesSignedIntrinsic<string baseOpc, Intrinsic intOp> {
3073 // If there is a sign extension after this intrinsic, consume it as smov already
3075 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i8 V64:$Rn))), i8)),
3077 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3078 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3080 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3082 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3083 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3085 // If there is a sign extension after this intrinsic, consume it as smov already
3087 def : Pat<(i32 (sext_inreg (i32 (intOp (v16i8 V128:$Rn))), i8)),
3089 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3090 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3092 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3094 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3095 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3097 // If there is a sign extension after this intrinsic, consume it as smov already
3099 def : Pat<(i32 (sext_inreg (i32 (intOp (v4i16 V64:$Rn))), i16)),
3101 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3102 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3104 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3106 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3107 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3109 // If there is a sign extension after this intrinsic, consume it as smov already
3111 def : Pat<(i32 (sext_inreg (i32 (intOp (v8i16 V128:$Rn))), i16)),
3113 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3114 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3116 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3118 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3119 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3122 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3123 (i32 (EXTRACT_SUBREG
3124 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3125 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3129 multiclass SIMDAcrossLanesUnsignedIntrinsic<string baseOpc, Intrinsic intOp> {
3130 // If there is a masking operation keeping only what has been actually
3131 // generated, consume it.
3132 def : Pat<(i32 (and (i32 (intOp (v8i8 V64:$Rn))), maski8_or_more)),
3133 (i32 (EXTRACT_SUBREG
3134 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3135 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3137 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3138 (i32 (EXTRACT_SUBREG
3139 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3140 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), bsub),
3142 // If there is a masking operation keeping only what has been actually
3143 // generated, consume it.
3144 def : Pat<(i32 (and (i32 (intOp (v16i8 V128:$Rn))), maski8_or_more)),
3145 (i32 (EXTRACT_SUBREG
3146 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3147 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3149 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3150 (i32 (EXTRACT_SUBREG
3151 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3152 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), bsub),
3155 // If there is a masking operation keeping only what has been actually
3156 // generated, consume it.
3157 def : Pat<(i32 (and (i32 (intOp (v4i16 V64:$Rn))), maski16_or_more)),
3158 (i32 (EXTRACT_SUBREG
3159 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3160 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3162 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3163 (i32 (EXTRACT_SUBREG
3164 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3165 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), hsub),
3167 // If there is a masking operation keeping only what has been actually
3168 // generated, consume it.
3169 def : Pat<(i32 (and (i32 (intOp (v8i16 V128:$Rn))), maski16_or_more)),
3170 (i32 (EXTRACT_SUBREG
3171 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3172 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3174 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3175 (i32 (EXTRACT_SUBREG
3176 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3177 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), hsub),
3180 def : Pat<(i32 (intOp (v4i32 V128:$Rn))),
3181 (i32 (EXTRACT_SUBREG
3182 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3183 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), ssub),
3188 multiclass SIMDAcrossLanesSignedLongIntrinsic<string baseOpc, Intrinsic intOp> {
3189 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3191 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3192 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3194 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3196 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3197 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3200 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3201 (i32 (EXTRACT_SUBREG
3202 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3203 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3205 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3206 (i32 (EXTRACT_SUBREG
3207 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3208 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3211 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3212 (i64 (EXTRACT_SUBREG
3213 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3214 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3218 multiclass SIMDAcrossLanesUnsignedLongIntrinsic<string baseOpc,
3220 def : Pat<(i32 (intOp (v8i8 V64:$Rn))),
3221 (i32 (EXTRACT_SUBREG
3222 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3223 (!cast<Instruction>(!strconcat(baseOpc, "v8i8v")) V64:$Rn), hsub),
3225 def : Pat<(i32 (intOp (v16i8 V128:$Rn))),
3226 (i32 (EXTRACT_SUBREG
3227 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3228 (!cast<Instruction>(!strconcat(baseOpc, "v16i8v")) V128:$Rn), hsub),
3231 def : Pat<(i32 (intOp (v4i16 V64:$Rn))),
3232 (i32 (EXTRACT_SUBREG
3233 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3234 (!cast<Instruction>(!strconcat(baseOpc, "v4i16v")) V64:$Rn), ssub),
3236 def : Pat<(i32 (intOp (v8i16 V128:$Rn))),
3237 (i32 (EXTRACT_SUBREG
3238 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3239 (!cast<Instruction>(!strconcat(baseOpc, "v8i16v")) V128:$Rn), ssub),
3242 def : Pat<(i64 (intOp (v4i32 V128:$Rn))),
3243 (i64 (EXTRACT_SUBREG
3244 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3245 (!cast<Instruction>(!strconcat(baseOpc, "v4i32v")) V128:$Rn), dsub),
3249 defm : SIMDAcrossLanesSignedIntrinsic<"ADDV", int_arm64_neon_saddv>;
3250 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3251 def : Pat<(i32 (int_arm64_neon_saddv (v2i32 V64:$Rn))),
3252 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3254 defm : SIMDAcrossLanesUnsignedIntrinsic<"ADDV", int_arm64_neon_uaddv>;
3255 // vaddv_[su]32 is special; -> ADDP Vd.2S,Vn.2S,Vm.2S; return Vd.s[0];Vn==Vm
3256 def : Pat<(i32 (int_arm64_neon_uaddv (v2i32 V64:$Rn))),
3257 (EXTRACT_SUBREG (ADDPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3259 defm : SIMDAcrossLanesSignedIntrinsic<"SMAXV", int_arm64_neon_smaxv>;
3260 def : Pat<(i32 (int_arm64_neon_smaxv (v2i32 V64:$Rn))),
3261 (EXTRACT_SUBREG (SMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3263 defm : SIMDAcrossLanesSignedIntrinsic<"SMINV", int_arm64_neon_sminv>;
3264 def : Pat<(i32 (int_arm64_neon_sminv (v2i32 V64:$Rn))),
3265 (EXTRACT_SUBREG (SMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3267 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMAXV", int_arm64_neon_umaxv>;
3268 def : Pat<(i32 (int_arm64_neon_umaxv (v2i32 V64:$Rn))),
3269 (EXTRACT_SUBREG (UMAXPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3271 defm : SIMDAcrossLanesUnsignedIntrinsic<"UMINV", int_arm64_neon_uminv>;
3272 def : Pat<(i32 (int_arm64_neon_uminv (v2i32 V64:$Rn))),
3273 (EXTRACT_SUBREG (UMINPv2i32 V64:$Rn, V64:$Rn), ssub)>;
3275 defm : SIMDAcrossLanesSignedLongIntrinsic<"SADDLV", int_arm64_neon_saddlv>;
3276 defm : SIMDAcrossLanesUnsignedLongIntrinsic<"UADDLV", int_arm64_neon_uaddlv>;
3278 // The vaddlv_s32 intrinsic gets mapped to SADDLP.
3279 def : Pat<(i64 (int_arm64_neon_saddlv (v2i32 V64:$Rn))),
3280 (i64 (EXTRACT_SUBREG
3281 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3282 (SADDLPv2i32_v1i64 V64:$Rn), dsub),
3284 // The vaddlv_u32 intrinsic gets mapped to UADDLP.
3285 def : Pat<(i64 (int_arm64_neon_uaddlv (v2i32 V64:$Rn))),
3286 (i64 (EXTRACT_SUBREG
3287 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
3288 (UADDLPv2i32_v1i64 V64:$Rn), dsub),
3291 //------------------------------------------------------------------------------
3292 // AdvSIMD modified immediate instructions
3293 //------------------------------------------------------------------------------
3296 defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", ARM64bici>;
3298 defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", ARM64orri>;
3302 def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1111, V128, fpimm8,
3304 [(set (v2f64 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3305 def FMOVv2f32_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1111, V64, fpimm8,
3307 [(set (v2f32 V64:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3308 def FMOVv4f32_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1111, V128, fpimm8,
3310 [(set (v4f32 V128:$Rd), (ARM64fmov imm0_255:$imm8))]>;
3314 // EDIT byte mask: scalar
3315 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3316 def MOVID : SIMDModifiedImmScalarNoShift<0, 1, 0b1110, "movi",
3317 [(set FPR64:$Rd, simdimmtype10:$imm8)]>;
3318 // The movi_edit node has the immediate value already encoded, so we use
3319 // a plain imm0_255 here.
3320 def : Pat<(f64 (ARM64movi_edit imm0_255:$shift)),
3321 (MOVID imm0_255:$shift)>;
3323 def : Pat<(v1i64 immAllZerosV), (MOVID (i32 0))>;
3324 def : Pat<(v2i32 immAllZerosV), (MOVID (i32 0))>;
3325 def : Pat<(v4i16 immAllZerosV), (MOVID (i32 0))>;
3326 def : Pat<(v8i8 immAllZerosV), (MOVID (i32 0))>;
3328 def : Pat<(v1i64 immAllOnesV), (MOVID (i32 255))>;
3329 def : Pat<(v2i32 immAllOnesV), (MOVID (i32 255))>;
3330 def : Pat<(v4i16 immAllOnesV), (MOVID (i32 255))>;
3331 def : Pat<(v8i8 immAllOnesV), (MOVID (i32 255))>;
3333 // EDIT byte mask: 2d
3335 // The movi_edit node has the immediate value already encoded, so we use
3336 // a plain imm0_255 in the pattern
3337 let isReMaterializable = 1, isAsCheapAsAMove = 1 in
3338 def MOVIv2d_ns : SIMDModifiedImmVectorNoShift<1, 1, 0b1110, V128,
3341 [(set (v2i64 V128:$Rd), (ARM64movi_edit imm0_255:$imm8))]>;
3344 // Use movi.2d to materialize 0.0 if the HW does zero-cycle zeroing.
3345 // Complexity is added to break a tie with a plain MOVI.
3346 let AddedComplexity = 1 in {
3347 def : Pat<(f32 fpimm0),
3348 (f32 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), ssub))>,
3350 def : Pat<(f64 fpimm0),
3351 (f64 (EXTRACT_SUBREG (v2i64 (MOVIv2d_ns (i32 0))), dsub))>,
3355 def : Pat<(v2i64 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3356 def : Pat<(v4i32 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3357 def : Pat<(v8i16 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3358 def : Pat<(v16i8 immAllZerosV), (MOVIv2d_ns (i32 0))>;
3360 def : Pat<(v2i64 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3361 def : Pat<(v4i32 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3362 def : Pat<(v8i16 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3363 def : Pat<(v16i8 immAllOnesV), (MOVIv2d_ns (i32 255))>;
3365 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3366 defm MOVI : SIMDModifiedImmVectorShift<0, 0b10, 0b00, "movi">;
3367 def : Pat<(v2i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3368 (MOVIv2i32 imm0_255:$imm8, imm:$shift)>;
3369 def : Pat<(v4i32 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3370 (MOVIv4i32 imm0_255:$imm8, imm:$shift)>;
3371 def : Pat<(v4i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3372 (MOVIv4i16 imm0_255:$imm8, imm:$shift)>;
3373 def : Pat<(v8i16 (ARM64movi_shift imm0_255:$imm8, (i32 imm:$shift))),
3374 (MOVIv8i16 imm0_255:$imm8, imm:$shift)>;
3376 // EDIT per word: 2s & 4s with MSL shifter
3377 def MOVIv2s_msl : SIMDModifiedImmMoveMSL<0, 0, {1,1,0,?}, V64, "movi", ".2s",
3378 [(set (v2i32 V64:$Rd),
3379 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3380 def MOVIv4s_msl : SIMDModifiedImmMoveMSL<1, 0, {1,1,0,?}, V128, "movi", ".4s",
3381 [(set (v4i32 V128:$Rd),
3382 (ARM64movi_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3384 // Per byte: 8b & 16b
3385 def MOVIv8b_ns : SIMDModifiedImmVectorNoShift<0, 0, 0b1110, V64, imm0_255,
3387 [(set (v8i8 V64:$Rd), (ARM64movi imm0_255:$imm8))]>;
3388 def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0b1110, V128, imm0_255,
3390 [(set (v16i8 V128:$Rd), (ARM64movi imm0_255:$imm8))]>;
3394 // EDIT per word & halfword: 2s, 4h, 4s, & 8h
3395 defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">;
3396 def : Pat<(v2i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3397 (MVNIv2i32 imm0_255:$imm8, imm:$shift)>;
3398 def : Pat<(v4i32 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3399 (MVNIv4i32 imm0_255:$imm8, imm:$shift)>;
3400 def : Pat<(v4i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3401 (MVNIv4i16 imm0_255:$imm8, imm:$shift)>;
3402 def : Pat<(v8i16 (ARM64mvni_shift imm0_255:$imm8, (i32 imm:$shift))),
3403 (MVNIv8i16 imm0_255:$imm8, imm:$shift)>;
3405 // EDIT per word: 2s & 4s with MSL shifter
3406 def MVNIv2s_msl : SIMDModifiedImmMoveMSL<0, 1, {1,1,0,?}, V64, "mvni", ".2s",
3407 [(set (v2i32 V64:$Rd),
3408 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3409 def MVNIv4s_msl : SIMDModifiedImmMoveMSL<1, 1, {1,1,0,?}, V128, "mvni", ".4s",
3410 [(set (v4i32 V128:$Rd),
3411 (ARM64mvni_msl imm0_255:$imm8, (i32 imm:$shift)))]>;
3413 //----------------------------------------------------------------------------
3414 // AdvSIMD indexed element
3415 //----------------------------------------------------------------------------
3417 let neverHasSideEffects = 1 in {
3418 defm FMLA : SIMDFPIndexedSDTied<0, 0b0001, "fmla">;
3419 defm FMLS : SIMDFPIndexedSDTied<0, 0b0101, "fmls">;
3422 // NOTE: Operands are reordered in the FMLA/FMLS PatFrags because the
3423 // instruction expects the addend first, while the intrinsic expects it last.
3425 // On the other hand, there are quite a few valid combinatorial options due to
3426 // the commutativity of multiplication and the fact that (-x) * y = x * (-y).
3427 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3428 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)>>;
3429 defm : SIMDFPIndexedSDTiedPatterns<"FMLA",
3430 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)>>;
3432 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3433 TriOpFrag<(fma node:$MHS, (fneg node:$RHS), node:$LHS)> >;
3434 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3435 TriOpFrag<(fma node:$RHS, (fneg node:$MHS), node:$LHS)> >;
3436 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3437 TriOpFrag<(fma (fneg node:$RHS), node:$MHS, node:$LHS)> >;
3438 defm : SIMDFPIndexedSDTiedPatterns<"FMLS",
3439 TriOpFrag<(fma (fneg node:$MHS), node:$RHS, node:$LHS)> >;
3441 multiclass FMLSIndexedAfterNegPatterns<SDPatternOperator OpNode> {
3442 // 3 variants for the .2s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3444 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3445 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3446 VectorIndexS:$idx))),
3447 (FMLSv2i32_indexed V64:$Rd, V64:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3448 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3449 (v2f32 (ARM64duplane32
3450 (v4f32 (insert_subvector undef,
3451 (v2f32 (fneg V64:$Rm)),
3453 VectorIndexS:$idx)))),
3454 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3455 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3456 VectorIndexS:$idx)>;
3457 def : Pat<(v2f32 (OpNode (v2f32 V64:$Rd), (v2f32 V64:$Rn),
3458 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3459 (FMLSv2i32_indexed V64:$Rd, V64:$Rn,
3460 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3462 // 3 variants for the .4s version: DUPLANE from 128-bit, DUPLANE from 64-bit
3464 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3465 (ARM64duplane32 (v4f32 (fneg V128:$Rm)),
3466 VectorIndexS:$idx))),
3467 (FMLSv4i32_indexed V128:$Rd, V128:$Rn, V128:$Rm,
3468 VectorIndexS:$idx)>;
3469 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3470 (v4f32 (ARM64duplane32
3471 (v4f32 (insert_subvector undef,
3472 (v2f32 (fneg V64:$Rm)),
3474 VectorIndexS:$idx)))),
3475 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3476 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub),
3477 VectorIndexS:$idx)>;
3478 def : Pat<(v4f32 (OpNode (v4f32 V128:$Rd), (v4f32 V128:$Rn),
3479 (ARM64dup (f32 (fneg FPR32Op:$Rm))))),
3480 (FMLSv4i32_indexed V128:$Rd, V128:$Rn,
3481 (SUBREG_TO_REG (i32 0), FPR32Op:$Rm, ssub), (i64 0))>;
3483 // 2 variants for the .2d version: DUPLANE from 128-bit, and DUP scalar
3484 // (DUPLANE from 64-bit would be trivial).
3485 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3486 (ARM64duplane64 (v2f64 (fneg V128:$Rm)),
3487 VectorIndexD:$idx))),
3489 V128:$Rd, V128:$Rn, V128:$Rm, VectorIndexS:$idx)>;
3490 def : Pat<(v2f64 (OpNode (v2f64 V128:$Rd), (v2f64 V128:$Rn),
3491 (ARM64dup (f64 (fneg FPR64Op:$Rm))))),
3492 (FMLSv2i64_indexed V128:$Rd, V128:$Rn,
3493 (SUBREG_TO_REG (i32 0), FPR64Op:$Rm, dsub), (i64 0))>;
3495 // 2 variants for 32-bit scalar version: extract from .2s or from .4s
3496 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3497 (vector_extract (v4f32 (fneg V128:$Rm)),
3498 VectorIndexS:$idx))),
3499 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3500 V128:$Rm, VectorIndexS:$idx)>;
3501 def : Pat<(f32 (OpNode (f32 FPR32:$Rd), (f32 FPR32:$Rn),
3502 (vector_extract (v2f32 (fneg V64:$Rm)),
3503 VectorIndexS:$idx))),
3504 (FMLSv1i32_indexed FPR32:$Rd, FPR32:$Rn,
3505 (SUBREG_TO_REG (i32 0), V64:$Rm, dsub), VectorIndexS:$idx)>;
3507 // 1 variant for 64-bit scalar version: extract from .1d or from .2d
3508 def : Pat<(f64 (OpNode (f64 FPR64:$Rd), (f64 FPR64:$Rn),
3509 (vector_extract (v2f64 (fneg V128:$Rm)),
3510 VectorIndexS:$idx))),
3511 (FMLSv1i64_indexed FPR64:$Rd, FPR64:$Rn,
3512 V128:$Rm, VectorIndexS:$idx)>;
3515 defm : FMLSIndexedAfterNegPatterns<
3516 TriOpFrag<(fma node:$RHS, node:$MHS, node:$LHS)> >;
3517 defm : FMLSIndexedAfterNegPatterns<
3518 TriOpFrag<(fma node:$MHS, node:$RHS, node:$LHS)> >;
3520 defm FMULX : SIMDFPIndexedSD<1, 0b1001, "fmulx", int_arm64_neon_fmulx>;
3521 defm FMUL : SIMDFPIndexedSD<0, 0b1001, "fmul", fmul>;
3523 def : Pat<(v2f32 (fmul V64:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3524 (FMULv2i32_indexed V64:$Rn,
3525 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3527 def : Pat<(v4f32 (fmul V128:$Rn, (ARM64dup (f32 FPR32:$Rm)))),
3528 (FMULv4i32_indexed V128:$Rn,
3529 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR32:$Rm, ssub),
3531 def : Pat<(v2f64 (fmul V128:$Rn, (ARM64dup (f64 FPR64:$Rm)))),
3532 (FMULv2i64_indexed V128:$Rn,
3533 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$Rm, dsub),
3536 defm SQDMULH : SIMDIndexedHS<0, 0b1100, "sqdmulh", int_arm64_neon_sqdmulh>;
3537 defm SQRDMULH : SIMDIndexedHS<0, 0b1101, "sqrdmulh", int_arm64_neon_sqrdmulh>;
3538 defm MLA : SIMDVectorIndexedHSTied<1, 0b0000, "mla",
3539 TriOpFrag<(add node:$LHS, (mul node:$MHS, node:$RHS))>>;
3540 defm MLS : SIMDVectorIndexedHSTied<1, 0b0100, "mls",
3541 TriOpFrag<(sub node:$LHS, (mul node:$MHS, node:$RHS))>>;
3542 defm MUL : SIMDVectorIndexedHS<0, 0b1000, "mul", mul>;
3543 defm SMLAL : SIMDVectorIndexedLongSDTied<0, 0b0010, "smlal",
3544 TriOpFrag<(add node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3545 defm SMLSL : SIMDVectorIndexedLongSDTied<0, 0b0110, "smlsl",
3546 TriOpFrag<(sub node:$LHS, (int_arm64_neon_smull node:$MHS, node:$RHS))>>;
3547 defm SMULL : SIMDVectorIndexedLongSD<0, 0b1010, "smull",
3548 int_arm64_neon_smull>;
3549 defm SQDMLAL : SIMDIndexedLongSQDMLXSDTied<0, 0b0011, "sqdmlal",
3550 int_arm64_neon_sqadd>;
3551 defm SQDMLSL : SIMDIndexedLongSQDMLXSDTied<0, 0b0111, "sqdmlsl",
3552 int_arm64_neon_sqsub>;
3553 defm SQDMULL : SIMDIndexedLongSD<0, 0b1011, "sqdmull", int_arm64_neon_sqdmull>;
3554 defm UMLAL : SIMDVectorIndexedLongSDTied<1, 0b0010, "umlal",
3555 TriOpFrag<(add node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3556 defm UMLSL : SIMDVectorIndexedLongSDTied<1, 0b0110, "umlsl",
3557 TriOpFrag<(sub node:$LHS, (int_arm64_neon_umull node:$MHS, node:$RHS))>>;
3558 defm UMULL : SIMDVectorIndexedLongSD<1, 0b1010, "umull",
3559 int_arm64_neon_umull>;
3561 // A scalar sqdmull with the second operand being a vector lane can be
3562 // handled directly with the indexed instruction encoding.
3563 def : Pat<(int_arm64_neon_sqdmulls_scalar (i32 FPR32:$Rn),
3564 (vector_extract (v4i32 V128:$Vm),
3565 VectorIndexS:$idx)),
3566 (SQDMULLv1i64_indexed FPR32:$Rn, V128:$Vm, VectorIndexS:$idx)>;
3568 //----------------------------------------------------------------------------
3569 // AdvSIMD scalar shift instructions
3570 //----------------------------------------------------------------------------
3571 defm FCVTZS : SIMDScalarRShiftSD<0, 0b11111, "fcvtzs">;
3572 defm FCVTZU : SIMDScalarRShiftSD<1, 0b11111, "fcvtzu">;
3573 defm SCVTF : SIMDScalarRShiftSD<0, 0b11100, "scvtf">;
3574 defm UCVTF : SIMDScalarRShiftSD<1, 0b11100, "ucvtf">;
3575 // Codegen patterns for the above. We don't put these directly on the
3576 // instructions because TableGen's type inference can't handle the truth.
3577 // Having the same base pattern for fp <--> int totally freaks it out.
3578 def : Pat<(int_arm64_neon_vcvtfp2fxs FPR32:$Rn, vecshiftR32:$imm),
3579 (FCVTZSs FPR32:$Rn, vecshiftR32:$imm)>;
3580 def : Pat<(int_arm64_neon_vcvtfp2fxu FPR32:$Rn, vecshiftR32:$imm),
3581 (FCVTZUs FPR32:$Rn, vecshiftR32:$imm)>;
3582 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxs (f64 FPR64:$Rn), vecshiftR64:$imm)),
3583 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3584 def : Pat<(i64 (int_arm64_neon_vcvtfp2fxu (f64 FPR64:$Rn), vecshiftR64:$imm)),
3585 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3586 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxs (v1f64 FPR64:$Rn),
3588 (FCVTZSd FPR64:$Rn, vecshiftR64:$imm)>;
3589 def : Pat<(v1i64 (int_arm64_neon_vcvtfp2fxu (v1f64 FPR64:$Rn),
3591 (FCVTZUd FPR64:$Rn, vecshiftR64:$imm)>;
3592 def : Pat<(int_arm64_neon_vcvtfxs2fp FPR32:$Rn, vecshiftR32:$imm),
3593 (SCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3594 def : Pat<(int_arm64_neon_vcvtfxu2fp FPR32:$Rn, vecshiftR32:$imm),
3595 (UCVTFs FPR32:$Rn, vecshiftR32:$imm)>;
3596 def : Pat<(f64 (int_arm64_neon_vcvtfxs2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3597 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3598 def : Pat<(f64 (int_arm64_neon_vcvtfxu2fp (i64 FPR64:$Rn), vecshiftR64:$imm)),
3599 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3600 def : Pat<(v1f64 (int_arm64_neon_vcvtfxs2fp (v1i64 FPR64:$Rn),
3602 (SCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3603 def : Pat<(v1f64 (int_arm64_neon_vcvtfxu2fp (v1i64 FPR64:$Rn),
3605 (UCVTFd FPR64:$Rn, vecshiftR64:$imm)>;
3607 defm SHL : SIMDScalarLShiftD< 0, 0b01010, "shl", ARM64vshl>;
3608 defm SLI : SIMDScalarLShiftDTied<1, 0b01010, "sli">;
3609 defm SQRSHRN : SIMDScalarRShiftBHS< 0, 0b10011, "sqrshrn",
3610 int_arm64_neon_sqrshrn>;
3611 defm SQRSHRUN : SIMDScalarRShiftBHS< 1, 0b10001, "sqrshrun",
3612 int_arm64_neon_sqrshrun>;
3613 defm SQSHLU : SIMDScalarLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3614 defm SQSHL : SIMDScalarLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3615 defm SQSHRN : SIMDScalarRShiftBHS< 0, 0b10010, "sqshrn",
3616 int_arm64_neon_sqshrn>;
3617 defm SQSHRUN : SIMDScalarRShiftBHS< 1, 0b10000, "sqshrun",
3618 int_arm64_neon_sqshrun>;
3619 defm SRI : SIMDScalarRShiftDTied< 1, 0b01000, "sri">;
3620 defm SRSHR : SIMDScalarRShiftD< 0, 0b00100, "srshr", ARM64srshri>;
3621 defm SRSRA : SIMDScalarRShiftDTied< 0, 0b00110, "srsra",
3622 TriOpFrag<(add node:$LHS,
3623 (ARM64srshri node:$MHS, node:$RHS))>>;
3624 defm SSHR : SIMDScalarRShiftD< 0, 0b00000, "sshr", ARM64vashr>;
3625 defm SSRA : SIMDScalarRShiftDTied< 0, 0b00010, "ssra",
3626 TriOpFrag<(add node:$LHS,
3627 (ARM64vashr node:$MHS, node:$RHS))>>;
3628 defm UQRSHRN : SIMDScalarRShiftBHS< 1, 0b10011, "uqrshrn",
3629 int_arm64_neon_uqrshrn>;
3630 defm UQSHL : SIMDScalarLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3631 defm UQSHRN : SIMDScalarRShiftBHS< 1, 0b10010, "uqshrn",
3632 int_arm64_neon_uqshrn>;
3633 defm URSHR : SIMDScalarRShiftD< 1, 0b00100, "urshr", ARM64urshri>;
3634 defm URSRA : SIMDScalarRShiftDTied< 1, 0b00110, "ursra",
3635 TriOpFrag<(add node:$LHS,
3636 (ARM64urshri node:$MHS, node:$RHS))>>;
3637 defm USHR : SIMDScalarRShiftD< 1, 0b00000, "ushr", ARM64vlshr>;
3638 defm USRA : SIMDScalarRShiftDTied< 1, 0b00010, "usra",
3639 TriOpFrag<(add node:$LHS,
3640 (ARM64vlshr node:$MHS, node:$RHS))>>;
3642 //----------------------------------------------------------------------------
3643 // AdvSIMD vector shift instructions
3644 //----------------------------------------------------------------------------
3645 defm FCVTZS:SIMDVectorRShiftSD<0, 0b11111, "fcvtzs", int_arm64_neon_vcvtfp2fxs>;
3646 defm FCVTZU:SIMDVectorRShiftSD<1, 0b11111, "fcvtzu", int_arm64_neon_vcvtfp2fxu>;
3647 defm SCVTF: SIMDVectorRShiftSDToFP<0, 0b11100, "scvtf",
3648 int_arm64_neon_vcvtfxs2fp>;
3649 defm RSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10001, "rshrn",
3650 int_arm64_neon_rshrn>;
3651 defm SHL : SIMDVectorLShiftBHSD<0, 0b01010, "shl", ARM64vshl>;
3652 defm SHRN : SIMDVectorRShiftNarrowBHS<0, 0b10000, "shrn",
3653 BinOpFrag<(trunc (ARM64vashr node:$LHS, node:$RHS))>>;
3654 defm SLI : SIMDVectorLShiftBHSDTied<1, 0b01010, "sli", int_arm64_neon_vsli>;
3655 def : Pat<(v1i64 (int_arm64_neon_vsli (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3656 (i32 vecshiftL64:$imm))),
3657 (SLId FPR64:$Rd, FPR64:$Rn, vecshiftL64:$imm)>;
3658 defm SQRSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10011, "sqrshrn",
3659 int_arm64_neon_sqrshrn>;
3660 defm SQRSHRUN: SIMDVectorRShiftNarrowBHS<1, 0b10001, "sqrshrun",
3661 int_arm64_neon_sqrshrun>;
3662 defm SQSHLU : SIMDVectorLShiftBHSD<1, 0b01100, "sqshlu", ARM64sqshlui>;
3663 defm SQSHL : SIMDVectorLShiftBHSD<0, 0b01110, "sqshl", ARM64sqshli>;
3664 defm SQSHRN : SIMDVectorRShiftNarrowBHS<0, 0b10010, "sqshrn",
3665 int_arm64_neon_sqshrn>;
3666 defm SQSHRUN : SIMDVectorRShiftNarrowBHS<1, 0b10000, "sqshrun",
3667 int_arm64_neon_sqshrun>;
3668 defm SRI : SIMDVectorRShiftBHSDTied<1, 0b01000, "sri", int_arm64_neon_vsri>;
3669 def : Pat<(v1i64 (int_arm64_neon_vsri (v1i64 FPR64:$Rd), (v1i64 FPR64:$Rn),
3670 (i32 vecshiftR64:$imm))),
3671 (SRId FPR64:$Rd, FPR64:$Rn, vecshiftR64:$imm)>;
3672 defm SRSHR : SIMDVectorRShiftBHSD<0, 0b00100, "srshr", ARM64srshri>;
3673 defm SRSRA : SIMDVectorRShiftBHSDTied<0, 0b00110, "srsra",
3674 TriOpFrag<(add node:$LHS,
3675 (ARM64srshri node:$MHS, node:$RHS))> >;
3676 defm SSHLL : SIMDVectorLShiftLongBHSD<0, 0b10100, "sshll",
3677 BinOpFrag<(ARM64vshl (sext node:$LHS), node:$RHS)>>;
3679 defm SSHR : SIMDVectorRShiftBHSD<0, 0b00000, "sshr", ARM64vashr>;
3680 defm SSRA : SIMDVectorRShiftBHSDTied<0, 0b00010, "ssra",
3681 TriOpFrag<(add node:$LHS, (ARM64vashr node:$MHS, node:$RHS))>>;
3682 defm UCVTF : SIMDVectorRShiftSDToFP<1, 0b11100, "ucvtf",
3683 int_arm64_neon_vcvtfxu2fp>;
3684 defm UQRSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10011, "uqrshrn",
3685 int_arm64_neon_uqrshrn>;
3686 defm UQSHL : SIMDVectorLShiftBHSD<1, 0b01110, "uqshl", ARM64uqshli>;
3687 defm UQSHRN : SIMDVectorRShiftNarrowBHS<1, 0b10010, "uqshrn",
3688 int_arm64_neon_uqshrn>;
3689 defm URSHR : SIMDVectorRShiftBHSD<1, 0b00100, "urshr", ARM64urshri>;
3690 defm URSRA : SIMDVectorRShiftBHSDTied<1, 0b00110, "ursra",
3691 TriOpFrag<(add node:$LHS,
3692 (ARM64urshri node:$MHS, node:$RHS))> >;
3693 defm USHLL : SIMDVectorLShiftLongBHSD<1, 0b10100, "ushll",
3694 BinOpFrag<(ARM64vshl (zext node:$LHS), node:$RHS)>>;
3695 defm USHR : SIMDVectorRShiftBHSD<1, 0b00000, "ushr", ARM64vlshr>;
3696 defm USRA : SIMDVectorRShiftBHSDTied<1, 0b00010, "usra",
3697 TriOpFrag<(add node:$LHS, (ARM64vlshr node:$MHS, node:$RHS))> >;
3699 // SHRN patterns for when a logical right shift was used instead of arithmetic
3700 // (the immediate guarantees no sign bits actually end up in the result so it
3702 def : Pat<(v8i8 (trunc (ARM64vlshr (v8i16 V128:$Rn), vecshiftR16Narrow:$imm))),
3703 (SHRNv8i8_shift V128:$Rn, vecshiftR16Narrow:$imm)>;
3704 def : Pat<(v4i16 (trunc (ARM64vlshr (v4i32 V128:$Rn), vecshiftR32Narrow:$imm))),
3705 (SHRNv4i16_shift V128:$Rn, vecshiftR32Narrow:$imm)>;
3706 def : Pat<(v2i32 (trunc (ARM64vlshr (v2i64 V128:$Rn), vecshiftR64Narrow:$imm))),
3707 (SHRNv2i32_shift V128:$Rn, vecshiftR64Narrow:$imm)>;
3709 def : Pat<(v16i8 (concat_vectors (v8i8 V64:$Rd),
3710 (trunc (ARM64vlshr (v8i16 V128:$Rn),
3711 vecshiftR16Narrow:$imm)))),
3712 (SHRNv16i8_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3713 V128:$Rn, vecshiftR16Narrow:$imm)>;
3714 def : Pat<(v8i16 (concat_vectors (v4i16 V64:$Rd),
3715 (trunc (ARM64vlshr (v4i32 V128:$Rn),
3716 vecshiftR32Narrow:$imm)))),
3717 (SHRNv8i16_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3718 V128:$Rn, vecshiftR32Narrow:$imm)>;
3719 def : Pat<(v4i32 (concat_vectors (v2i32 V64:$Rd),
3720 (trunc (ARM64vlshr (v2i64 V128:$Rn),
3721 vecshiftR64Narrow:$imm)))),
3722 (SHRNv4i32_shift (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub),
3723 V128:$Rn, vecshiftR32Narrow:$imm)>;
3725 // Vector sign and zero extensions are implemented with SSHLL and USSHLL.
3726 // Anyexts are implemented as zexts.
3727 def : Pat<(v8i16 (sext (v8i8 V64:$Rn))), (SSHLLv8i8_shift V64:$Rn, (i32 0))>;
3728 def : Pat<(v8i16 (zext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
3729 def : Pat<(v8i16 (anyext (v8i8 V64:$Rn))), (USHLLv8i8_shift V64:$Rn, (i32 0))>;
3730 def : Pat<(v4i32 (sext (v4i16 V64:$Rn))), (SSHLLv4i16_shift V64:$Rn, (i32 0))>;
3731 def : Pat<(v4i32 (zext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
3732 def : Pat<(v4i32 (anyext (v4i16 V64:$Rn))), (USHLLv4i16_shift V64:$Rn, (i32 0))>;
3733 def : Pat<(v2i64 (sext (v2i32 V64:$Rn))), (SSHLLv2i32_shift V64:$Rn, (i32 0))>;
3734 def : Pat<(v2i64 (zext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
3735 def : Pat<(v2i64 (anyext (v2i32 V64:$Rn))), (USHLLv2i32_shift V64:$Rn, (i32 0))>;
3736 // Also match an extend from the upper half of a 128 bit source register.
3737 def : Pat<(v8i16 (anyext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3738 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
3739 def : Pat<(v8i16 (zext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3740 (USHLLv16i8_shift V128:$Rn, (i32 0))>;
3741 def : Pat<(v8i16 (sext (v8i8 (extract_subvector V128:$Rn, (i64 8)) ))),
3742 (SSHLLv16i8_shift V128:$Rn, (i32 0))>;
3743 def : Pat<(v4i32 (anyext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3744 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
3745 def : Pat<(v4i32 (zext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3746 (USHLLv8i16_shift V128:$Rn, (i32 0))>;
3747 def : Pat<(v4i32 (sext (v4i16 (extract_subvector V128:$Rn, (i64 4)) ))),
3748 (SSHLLv8i16_shift V128:$Rn, (i32 0))>;
3749 def : Pat<(v2i64 (anyext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3750 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
3751 def : Pat<(v2i64 (zext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3752 (USHLLv4i32_shift V128:$Rn, (i32 0))>;
3753 def : Pat<(v2i64 (sext (v2i32 (extract_subvector V128:$Rn, (i64 2)) ))),
3754 (SSHLLv4i32_shift V128:$Rn, (i32 0))>;
3756 // Vector shift sxtl aliases
3757 def : InstAlias<"sxtl.8h $dst, $src1",
3758 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3759 def : InstAlias<"sxtl $dst.8h, $src1.8b",
3760 (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3761 def : InstAlias<"sxtl.4s $dst, $src1",
3762 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3763 def : InstAlias<"sxtl $dst.4s, $src1.4h",
3764 (SSHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3765 def : InstAlias<"sxtl.2d $dst, $src1",
3766 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3767 def : InstAlias<"sxtl $dst.2d, $src1.2s",
3768 (SSHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3770 // Vector shift sxtl2 aliases
3771 def : InstAlias<"sxtl2.8h $dst, $src1",
3772 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3773 def : InstAlias<"sxtl2 $dst.8h, $src1.16b",
3774 (SSHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3775 def : InstAlias<"sxtl2.4s $dst, $src1",
3776 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3777 def : InstAlias<"sxtl2 $dst.4s, $src1.8h",
3778 (SSHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3779 def : InstAlias<"sxtl2.2d $dst, $src1",
3780 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
3781 def : InstAlias<"sxtl2 $dst.2d, $src1.4s",
3782 (SSHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
3784 // Vector shift uxtl aliases
3785 def : InstAlias<"uxtl.8h $dst, $src1",
3786 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3787 def : InstAlias<"uxtl $dst.8h, $src1.8b",
3788 (USHLLv8i8_shift V128:$dst, V64:$src1, 0)>;
3789 def : InstAlias<"uxtl.4s $dst, $src1",
3790 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3791 def : InstAlias<"uxtl $dst.4s, $src1.4h",
3792 (USHLLv4i16_shift V128:$dst, V64:$src1, 0)>;
3793 def : InstAlias<"uxtl.2d $dst, $src1",
3794 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3795 def : InstAlias<"uxtl $dst.2d, $src1.2s",
3796 (USHLLv2i32_shift V128:$dst, V64:$src1, 0)>;
3798 // Vector shift uxtl2 aliases
3799 def : InstAlias<"uxtl2.8h $dst, $src1",
3800 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3801 def : InstAlias<"uxtl2 $dst.8h, $src1.16b",
3802 (USHLLv16i8_shift V128:$dst, V128:$src1, 0)>;
3803 def : InstAlias<"uxtl2.4s $dst, $src1",
3804 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3805 def : InstAlias<"uxtl2 $dst.4s, $src1.8h",
3806 (USHLLv8i16_shift V128:$dst, V128:$src1, 0)>;
3807 def : InstAlias<"uxtl2.2d $dst, $src1",
3808 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
3809 def : InstAlias<"uxtl2 $dst.2d, $src1.4s",
3810 (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>;
3812 // If an integer is about to be converted to a floating point value,
3813 // just load it on the floating point unit.
3814 // These patterns are more complex because floating point loads do not
3815 // support sign extension.
3816 // The sign extension has to be explicitly added and is only supported for
3817 // one step: byte-to-half, half-to-word, word-to-doubleword.
3818 // SCVTF GPR -> FPR is 9 cycles.
3819 // SCVTF FPR -> FPR is 4 cyclces.
3820 // (sign extension with lengthen) SXTL FPR -> FPR is 2 cycles.
3821 // Therefore, we can do 2 sign extensions and one SCVTF FPR -> FPR
3822 // and still being faster.
3823 // However, this is not good for code size.
3824 // 8-bits -> float. 2 sizes step-up.
3825 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 ro_indexed8:$addr)))),
3826 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3831 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3832 (LDRBro ro_indexed8:$addr),
3837 ssub)))>, Requires<[NotForCodeSize]>;
3838 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_indexed8:$addr)))),
3839 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3844 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3845 (LDRBui am_indexed8:$addr),
3850 ssub)))>, Requires<[NotForCodeSize]>;
3851 def : Pat <(f32 (sint_to_fp (i32 (sextloadi8 am_unscaled8:$addr)))),
3852 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3857 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3858 (LDURBi am_unscaled8:$addr),
3863 ssub)))>, Requires<[NotForCodeSize]>;
3864 // 16-bits -> float. 1 size step-up.
3865 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
3866 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3868 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3869 (LDRHro ro_indexed16:$addr),
3872 ssub)))>, Requires<[NotForCodeSize]>;
3873 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
3874 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3876 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3877 (LDRHui am_indexed16:$addr),
3880 ssub)))>, Requires<[NotForCodeSize]>;
3881 def : Pat <(f32 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
3882 (SCVTFv1i32 (f32 (EXTRACT_SUBREG
3884 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3885 (LDURHi am_unscaled16:$addr),
3888 ssub)))>, Requires<[NotForCodeSize]>;
3889 // 32-bits to 32-bits are handled in target specific dag combine:
3890 // performIntToFpCombine.
3891 // 64-bits integer to 32-bits floating point, not possible with
3892 // SCVTF on floating point registers (both source and destination
3893 // must have the same size).
3895 // Here are the patterns for 8, 16, 32, and 64-bits to double.
3896 // 8-bits -> double. 3 size step-up: give up.
3897 // 16-bits -> double. 2 size step.
3898 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 ro_indexed16:$addr)))),
3899 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
3904 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3905 (LDRHro ro_indexed16:$addr),
3910 dsub)))>, Requires<[NotForCodeSize]>;
3911 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_indexed16:$addr)))),
3912 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
3917 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3918 (LDRHui am_indexed16:$addr),
3923 dsub)))>, Requires<[NotForCodeSize]>;
3924 def : Pat <(f64 (sint_to_fp (i32 (sextloadi16 am_unscaled16:$addr)))),
3925 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
3930 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3931 (LDURHi am_unscaled16:$addr),
3936 dsub)))>, Requires<[NotForCodeSize]>;
3937 // 32-bits -> double. 1 size step-up.
3938 def : Pat <(f64 (sint_to_fp (i32 (load ro_indexed32:$addr)))),
3939 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
3941 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3942 (LDRSro ro_indexed32:$addr),
3945 dsub)))>, Requires<[NotForCodeSize]>;
3946 def : Pat <(f64 (sint_to_fp (i32 (load am_indexed32:$addr)))),
3947 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
3949 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3950 (LDRSui am_indexed32:$addr),
3953 dsub)))>, Requires<[NotForCodeSize]>;
3954 def : Pat <(f64 (sint_to_fp (i32 (load am_unscaled32:$addr)))),
3955 (SCVTFv1i64 (f64 (EXTRACT_SUBREG
3957 (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
3958 (LDURSi am_unscaled32:$addr),
3961 dsub)))>, Requires<[NotForCodeSize]>;
3962 // 64-bits -> double are handled in target specific dag combine:
3963 // performIntToFpCombine.
3966 //----------------------------------------------------------------------------
3967 // AdvSIMD Load-Store Structure
3968 //----------------------------------------------------------------------------
3969 defm LD1 : SIMDLd1Multiple<"ld1">;
3970 defm LD2 : SIMDLd2Multiple<"ld2">;
3971 defm LD3 : SIMDLd3Multiple<"ld3">;
3972 defm LD4 : SIMDLd4Multiple<"ld4">;
3974 defm ST1 : SIMDSt1Multiple<"st1">;
3975 defm ST2 : SIMDSt2Multiple<"st2">;
3976 defm ST3 : SIMDSt3Multiple<"st3">;
3977 defm ST4 : SIMDSt4Multiple<"st4">;
3979 class Ld1Pat<ValueType ty, Instruction INST>
3980 : Pat<(ty (load am_simdnoindex:$vaddr)), (INST am_simdnoindex:$vaddr)>;
3982 def : Ld1Pat<v16i8, LD1Onev16b>;
3983 def : Ld1Pat<v8i16, LD1Onev8h>;
3984 def : Ld1Pat<v4i32, LD1Onev4s>;
3985 def : Ld1Pat<v2i64, LD1Onev2d>;
3986 def : Ld1Pat<v8i8, LD1Onev8b>;
3987 def : Ld1Pat<v4i16, LD1Onev4h>;
3988 def : Ld1Pat<v2i32, LD1Onev2s>;
3989 def : Ld1Pat<v1i64, LD1Onev1d>;
3991 class St1Pat<ValueType ty, Instruction INST>
3992 : Pat<(store ty:$Vt, am_simdnoindex:$vaddr),
3993 (INST ty:$Vt, am_simdnoindex:$vaddr)>;
3995 def : St1Pat<v16i8, ST1Onev16b>;
3996 def : St1Pat<v8i16, ST1Onev8h>;
3997 def : St1Pat<v4i32, ST1Onev4s>;
3998 def : St1Pat<v2i64, ST1Onev2d>;
3999 def : St1Pat<v8i8, ST1Onev8b>;
4000 def : St1Pat<v4i16, ST1Onev4h>;
4001 def : St1Pat<v2i32, ST1Onev2s>;
4002 def : St1Pat<v1i64, ST1Onev1d>;
4008 defm LD1R : SIMDLdR<0, 0b110, 0, "ld1r", "One", 1, 2, 4, 8>;
4009 defm LD2R : SIMDLdR<1, 0b110, 0, "ld2r", "Two", 2, 4, 8, 16>;
4010 defm LD3R : SIMDLdR<0, 0b111, 0, "ld3r", "Three", 3, 6, 12, 24>;
4011 defm LD4R : SIMDLdR<1, 0b111, 0, "ld4r", "Four", 4, 8, 16, 32>;
4012 let mayLoad = 1, neverHasSideEffects = 1 in {
4013 defm LD1 : SIMDLdSingleBTied<0, 0b000, "ld1", VecListOneb, GPR64pi1>;
4014 defm LD1 : SIMDLdSingleHTied<0, 0b010, 0, "ld1", VecListOneh, GPR64pi2>;
4015 defm LD1 : SIMDLdSingleSTied<0, 0b100, 0b00, "ld1", VecListOnes, GPR64pi4>;
4016 defm LD1 : SIMDLdSingleDTied<0, 0b100, 0b01, "ld1", VecListOned, GPR64pi8>;
4017 defm LD2 : SIMDLdSingleBTied<1, 0b000, "ld2", VecListTwob, GPR64pi2>;
4018 defm LD2 : SIMDLdSingleHTied<1, 0b010, 0, "ld2", VecListTwoh, GPR64pi4>;
4019 defm LD2 : SIMDLdSingleSTied<1, 0b100, 0b00, "ld2", VecListTwos, GPR64pi8>;
4020 defm LD2 : SIMDLdSingleDTied<1, 0b100, 0b01, "ld2", VecListTwod, GPR64pi16>;
4021 defm LD3 : SIMDLdSingleBTied<0, 0b001, "ld3", VecListThreeb, GPR64pi3>;
4022 defm LD3 : SIMDLdSingleHTied<0, 0b011, 0, "ld3", VecListThreeh, GPR64pi6>;
4023 defm LD3 : SIMDLdSingleSTied<0, 0b101, 0b00, "ld3", VecListThrees, GPR64pi12>;
4024 defm LD3 : SIMDLdSingleDTied<0, 0b101, 0b01, "ld3", VecListThreed, GPR64pi24>;
4025 defm LD4 : SIMDLdSingleBTied<1, 0b001, "ld4", VecListFourb, GPR64pi4>;
4026 defm LD4 : SIMDLdSingleHTied<1, 0b011, 0, "ld4", VecListFourh, GPR64pi8>;
4027 defm LD4 : SIMDLdSingleSTied<1, 0b101, 0b00, "ld4", VecListFours, GPR64pi16>;
4028 defm LD4 : SIMDLdSingleDTied<1, 0b101, 0b01, "ld4", VecListFourd, GPR64pi32>;
4031 def : Pat<(v8i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4032 (LD1Rv8b am_simdnoindex:$vaddr)>;
4033 def : Pat<(v16i8 (ARM64dup (i32 (extloadi8 am_simdnoindex:$vaddr)))),
4034 (LD1Rv16b am_simdnoindex:$vaddr)>;
4035 def : Pat<(v4i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4036 (LD1Rv4h am_simdnoindex:$vaddr)>;
4037 def : Pat<(v8i16 (ARM64dup (i32 (extloadi16 am_simdnoindex:$vaddr)))),
4038 (LD1Rv8h am_simdnoindex:$vaddr)>;
4039 def : Pat<(v2i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4040 (LD1Rv2s am_simdnoindex:$vaddr)>;
4041 def : Pat<(v4i32 (ARM64dup (i32 (load am_simdnoindex:$vaddr)))),
4042 (LD1Rv4s am_simdnoindex:$vaddr)>;
4043 def : Pat<(v2i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4044 (LD1Rv2d am_simdnoindex:$vaddr)>;
4045 def : Pat<(v1i64 (ARM64dup (i64 (load am_simdnoindex:$vaddr)))),
4046 (LD1Rv1d am_simdnoindex:$vaddr)>;
4047 // Grab the floating point version too
4048 def : Pat<(v2f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4049 (LD1Rv2s am_simdnoindex:$vaddr)>;
4050 def : Pat<(v4f32 (ARM64dup (f32 (load am_simdnoindex:$vaddr)))),
4051 (LD1Rv4s am_simdnoindex:$vaddr)>;
4052 def : Pat<(v2f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4053 (LD1Rv2d am_simdnoindex:$vaddr)>;
4054 def : Pat<(v1f64 (ARM64dup (f64 (load am_simdnoindex:$vaddr)))),
4055 (LD1Rv1d am_simdnoindex:$vaddr)>;
4057 def : Pat<(vector_insert (v16i8 VecListOne128:$Rd),
4058 (i32 (extloadi8 am_simdnoindex:$vaddr)), VectorIndexB:$idx),
4059 (LD1i8 VecListOne128:$Rd, VectorIndexB:$idx, am_simdnoindex:$vaddr)>;
4060 def : Pat<(vector_insert (v8i16 VecListOne128:$Rd),
4061 (i32 (extloadi16 am_simdnoindex:$vaddr)), VectorIndexH:$idx),
4062 (LD1i16 VecListOne128:$Rd, VectorIndexH:$idx, am_simdnoindex:$vaddr)>;
4063 def : Pat<(vector_insert (v4i32 VecListOne128:$Rd),
4064 (i32 (load am_simdnoindex:$vaddr)), VectorIndexS:$idx),
4065 (LD1i32 VecListOne128:$Rd, VectorIndexS:$idx, am_simdnoindex:$vaddr)>;
4066 def : Pat<(vector_insert (v2i64 VecListOne128:$Rd),
4067 (i64 (load am_simdnoindex:$vaddr)), VectorIndexD:$idx),
4068 (LD1i64 VecListOne128:$Rd, VectorIndexD:$idx, am_simdnoindex:$vaddr)>;
4071 defm LD1 : SIMDLdSt1SingleAliases<"ld1">;
4072 defm LD2 : SIMDLdSt2SingleAliases<"ld2">;
4073 defm LD3 : SIMDLdSt3SingleAliases<"ld3">;
4074 defm LD4 : SIMDLdSt4SingleAliases<"ld4">;
4077 let AddedComplexity = 8 in {
4078 defm ST1 : SIMDStSingleB<0, 0b000, "st1", VecListOneb,
4080 (i32 (vector_extract (v16i8 VecListOneb:$Vt), VectorIndexB:$idx)),
4081 am_simdnoindex:$vaddr)], GPR64pi1>;
4082 defm ST1 : SIMDStSingleH<0, 0b010, 0, "st1", VecListOneh,
4084 (i32 (vector_extract (v8i16 VecListOneh:$Vt), VectorIndexH:$idx)),
4085 am_simdnoindex:$vaddr)], GPR64pi2>;
4086 defm ST1 : SIMDStSingleS<0, 0b100, 0b00, "st1", VecListOnes,
4088 (i32 (vector_extract (v4i32 VecListOnes:$Vt), VectorIndexS:$idx)),
4089 am_simdnoindex:$vaddr)], GPR64pi4>;
4090 defm ST1 : SIMDStSingleD<0, 0b100, 0b01, "st1", VecListOned,
4092 (i64 (vector_extract (v2i64 VecListOned:$Vt), VectorIndexD:$idx)),
4093 am_simdnoindex:$vaddr)], GPR64pi8>;
4096 let mayStore = 1, neverHasSideEffects = 1 in {
4097 defm ST2 : SIMDStSingleB<1, 0b000, "st2", VecListTwob, [], GPR64pi2>;
4098 defm ST2 : SIMDStSingleH<1, 0b010, 0, "st2", VecListTwoh, [], GPR64pi4>;
4099 defm ST2 : SIMDStSingleS<1, 0b100, 0b00, "st2", VecListTwos, [], GPR64pi8>;
4100 defm ST2 : SIMDStSingleD<1, 0b100, 0b01, "st2", VecListTwod, [], GPR64pi16>;
4101 defm ST3 : SIMDStSingleB<0, 0b001, "st3", VecListThreeb, [], GPR64pi3>;
4102 defm ST3 : SIMDStSingleH<0, 0b011, 0, "st3", VecListThreeh, [], GPR64pi6>;
4103 defm ST3 : SIMDStSingleS<0, 0b101, 0b00, "st3", VecListThrees, [], GPR64pi12>;
4104 defm ST3 : SIMDStSingleD<0, 0b101, 0b01, "st3", VecListThreed, [], GPR64pi24>;
4105 defm ST4 : SIMDStSingleB<1, 0b001, "st4", VecListFourb, [], GPR64pi4>;
4106 defm ST4 : SIMDStSingleH<1, 0b011, 0, "st4", VecListFourh, [], GPR64pi8>;
4107 defm ST4 : SIMDStSingleS<1, 0b101, 0b00, "st4", VecListFours, [], GPR64pi16>;
4108 defm ST4 : SIMDStSingleD<1, 0b101, 0b01, "st4", VecListFourd, [], GPR64pi32>;
4111 defm ST1 : SIMDLdSt1SingleAliases<"st1">;
4112 defm ST2 : SIMDLdSt2SingleAliases<"st2">;
4113 defm ST3 : SIMDLdSt3SingleAliases<"st3">;
4114 defm ST4 : SIMDLdSt4SingleAliases<"st4">;
4116 //----------------------------------------------------------------------------
4117 // Crypto extensions
4118 //----------------------------------------------------------------------------
4120 def AESErr : AESTiedInst<0b0100, "aese", int_arm64_crypto_aese>;
4121 def AESDrr : AESTiedInst<0b0101, "aesd", int_arm64_crypto_aesd>;
4122 def AESMCrr : AESInst< 0b0110, "aesmc", int_arm64_crypto_aesmc>;
4123 def AESIMCrr : AESInst< 0b0111, "aesimc", int_arm64_crypto_aesimc>;
4125 def SHA1Crrr : SHATiedInstQSV<0b000, "sha1c", int_arm64_crypto_sha1c>;
4126 def SHA1Prrr : SHATiedInstQSV<0b001, "sha1p", int_arm64_crypto_sha1p>;
4127 def SHA1Mrrr : SHATiedInstQSV<0b010, "sha1m", int_arm64_crypto_sha1m>;
4128 def SHA1SU0rrr : SHATiedInstVVV<0b011, "sha1su0", int_arm64_crypto_sha1su0>;
4129 def SHA256Hrrr : SHATiedInstQQV<0b100, "sha256h", int_arm64_crypto_sha256h>;
4130 def SHA256H2rrr : SHATiedInstQQV<0b101, "sha256h2",int_arm64_crypto_sha256h2>;
4131 def SHA256SU1rrr :SHATiedInstVVV<0b110, "sha256su1",int_arm64_crypto_sha256su1>;
4133 def SHA1Hrr : SHAInstSS< 0b0000, "sha1h", int_arm64_crypto_sha1h>;
4134 def SHA1SU1rr : SHATiedInstVV<0b0001, "sha1su1", int_arm64_crypto_sha1su1>;
4135 def SHA256SU0rr : SHATiedInstVV<0b0010, "sha256su0",int_arm64_crypto_sha256su0>;
4137 //----------------------------------------------------------------------------
4139 //----------------------------------------------------------------------------
4140 // FIXME: Like for X86, these should go in their own separate .td file.
4142 // Any instruction that defines a 32-bit result leaves the high half of the
4143 // register. Truncate can be lowered to EXTRACT_SUBREG. CopyFromReg may
4144 // be copying from a truncate. But any other 32-bit operation will zero-extend
4146 // FIXME: X86 also checks for CMOV here. Do we need something similar?
4147 def def32 : PatLeaf<(i32 GPR32:$src), [{
4148 return N->getOpcode() != ISD::TRUNCATE &&
4149 N->getOpcode() != TargetOpcode::EXTRACT_SUBREG &&
4150 N->getOpcode() != ISD::CopyFromReg;
4153 // In the case of a 32-bit def that is known to implicitly zero-extend,
4154 // we can use a SUBREG_TO_REG.
4155 def : Pat<(i64 (zext def32:$src)), (SUBREG_TO_REG (i64 0), GPR32:$src, sub_32)>;
4157 // For an anyext, we don't care what the high bits are, so we can perform an
4158 // INSERT_SUBREF into an IMPLICIT_DEF.
4159 def : Pat<(i64 (anyext GPR32:$src)),
4160 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32)>;
4162 // When we need to explicitly zero-extend, we use an unsigned bitfield move
4163 // instruction (UBFM) on the enclosing super-reg.
4164 def : Pat<(i64 (zext GPR32:$src)),
4165 (UBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4167 // To sign extend, we use a signed bitfield move instruction (SBFM) on the
4168 // containing super-reg.
4169 def : Pat<(i64 (sext GPR32:$src)),
4170 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$src, sub_32), 0, 31)>;
4171 def : Pat<(i64 (sext_inreg GPR64:$src, i32)), (SBFMXri GPR64:$src, 0, 31)>;
4172 def : Pat<(i64 (sext_inreg GPR64:$src, i16)), (SBFMXri GPR64:$src, 0, 15)>;
4173 def : Pat<(i64 (sext_inreg GPR64:$src, i8)), (SBFMXri GPR64:$src, 0, 7)>;
4174 def : Pat<(i64 (sext_inreg GPR64:$src, i1)), (SBFMXri GPR64:$src, 0, 0)>;
4175 def : Pat<(i32 (sext_inreg GPR32:$src, i16)), (SBFMWri GPR32:$src, 0, 15)>;
4176 def : Pat<(i32 (sext_inreg GPR32:$src, i8)), (SBFMWri GPR32:$src, 0, 7)>;
4177 def : Pat<(i32 (sext_inreg GPR32:$src, i1)), (SBFMWri GPR32:$src, 0, 0)>;
4179 def : Pat<(shl (sext_inreg GPR32:$Rn, i8), (i32 imm0_31:$imm)),
4180 (SBFMWri GPR32:$Rn, (i32 (i32shift_a imm0_31:$imm)),
4181 (i32 (i32shift_sext_i8 imm0_31:$imm)))>;
4182 def : Pat<(shl (sext_inreg GPR64:$Rn, i8), (i64 imm0_63:$imm)),
4183 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4184 (i64 (i64shift_sext_i8 imm0_63:$imm)))>;
4186 def : Pat<(shl (sext_inreg GPR32:$Rn, i16), (i32 imm0_31:$imm)),
4187 (SBFMWri GPR32:$Rn, (i32 (i32shift_a imm0_31:$imm)),
4188 (i32 (i32shift_sext_i16 imm0_31:$imm)))>;
4189 def : Pat<(shl (sext_inreg GPR64:$Rn, i16), (i64 imm0_63:$imm)),
4190 (SBFMXri GPR64:$Rn, (i64 (i64shift_a imm0_63:$imm)),
4191 (i64 (i64shift_sext_i16 imm0_63:$imm)))>;
4193 def : Pat<(shl (i64 (sext GPR32:$Rn)), (i64 imm0_63:$imm)),
4194 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4195 (i64 (i64shift_a imm0_63:$imm)),
4196 (i64 (i64shift_sext_i32 imm0_63:$imm)))>;
4198 // sra patterns have an AddedComplexity of 10, so make sure we have a higher
4199 // AddedComplexity for the following patterns since we want to match sext + sra
4200 // patterns before we attempt to match a single sra node.
4201 let AddedComplexity = 20 in {
4202 // We support all sext + sra combinations which preserve at least one bit of the
4203 // original value which is to be sign extended. E.g. we support shifts up to
4205 def : Pat<(sra (sext_inreg GPR32:$Rn, i8), (i32 imm0_7:$imm)),
4206 (SBFMWri GPR32:$Rn, (i32 imm0_7:$imm), 7)>;
4207 def : Pat<(sra (sext_inreg GPR64:$Rn, i8), (i64 imm0_7x:$imm)),
4208 (SBFMXri GPR64:$Rn, (i64 imm0_7x:$imm), 7)>;
4210 def : Pat<(sra (sext_inreg GPR32:$Rn, i16), (i32 imm0_15:$imm)),
4211 (SBFMWri GPR32:$Rn, (i32 imm0_15:$imm), 15)>;
4212 def : Pat<(sra (sext_inreg GPR64:$Rn, i16), (i64 imm0_15x:$imm)),
4213 (SBFMXri GPR64:$Rn, (i64 imm0_15x:$imm), 15)>;
4215 def : Pat<(sra (i64 (sext GPR32:$Rn)), (i64 imm0_31x:$imm)),
4216 (SBFMXri (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPR32:$Rn, sub_32),
4217 (i64 imm0_31x:$imm), 31)>;
4218 } // AddedComplexity = 20
4220 // To truncate, we can simply extract from a subregister.
4221 def : Pat<(i32 (trunc GPR64sp:$src)),
4222 (i32 (EXTRACT_SUBREG GPR64sp:$src, sub_32))>;
4224 // __builtin_trap() uses the BRK instruction on ARM64.
4225 def : Pat<(trap), (BRK 1)>;
4227 // Conversions within AdvSIMD types in the same register size are free.
4229 def : Pat<(v1i64 (bitconvert (v2i32 FPR64:$src))), (v1i64 FPR64:$src)>;
4230 def : Pat<(v1i64 (bitconvert (v4i16 FPR64:$src))), (v1i64 FPR64:$src)>;
4231 def : Pat<(v1i64 (bitconvert (v8i8 FPR64:$src))), (v1i64 FPR64:$src)>;
4232 def : Pat<(v1i64 (bitconvert (f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4233 def : Pat<(v1i64 (bitconvert (v2f32 FPR64:$src))), (v1i64 FPR64:$src)>;
4234 def : Pat<(v1i64 (bitconvert (v1f64 FPR64:$src))), (v1i64 FPR64:$src)>;
4236 def : Pat<(v2i32 (bitconvert (v1i64 FPR64:$src))), (v2i32 FPR64:$src)>;
4237 def : Pat<(v2i32 (bitconvert (v4i16 FPR64:$src))), (v2i32 FPR64:$src)>;
4238 def : Pat<(v2i32 (bitconvert (v8i8 FPR64:$src))), (v2i32 FPR64:$src)>;
4239 def : Pat<(v2i32 (bitconvert (f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4240 def : Pat<(v2i32 (bitconvert (v2f32 FPR64:$src))), (v2i32 FPR64:$src)>;
4241 def : Pat<(v2i32 (bitconvert (v1f64 FPR64:$src))), (v2i32 FPR64:$src)>;
4243 def : Pat<(v4i16 (bitconvert (v1i64 FPR64:$src))), (v4i16 FPR64:$src)>;
4244 def : Pat<(v4i16 (bitconvert (v2i32 FPR64:$src))), (v4i16 FPR64:$src)>;
4245 def : Pat<(v4i16 (bitconvert (v8i8 FPR64:$src))), (v4i16 FPR64:$src)>;
4246 def : Pat<(v4i16 (bitconvert (f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4247 def : Pat<(v4i16 (bitconvert (v2f32 FPR64:$src))), (v4i16 FPR64:$src)>;
4248 def : Pat<(v4i16 (bitconvert (v1f64 FPR64:$src))), (v4i16 FPR64:$src)>;
4250 def : Pat<(v8i8 (bitconvert (v1i64 FPR64:$src))), (v8i8 FPR64:$src)>;
4251 def : Pat<(v8i8 (bitconvert (v2i32 FPR64:$src))), (v8i8 FPR64:$src)>;
4252 def : Pat<(v8i8 (bitconvert (v4i16 FPR64:$src))), (v8i8 FPR64:$src)>;
4253 def : Pat<(v8i8 (bitconvert (f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4254 def : Pat<(v8i8 (bitconvert (v2f32 FPR64:$src))), (v8i8 FPR64:$src)>;
4255 def : Pat<(v8i8 (bitconvert (v1f64 FPR64:$src))), (v8i8 FPR64:$src)>;
4257 def : Pat<(f64 (bitconvert (v1i64 FPR64:$src))), (f64 FPR64:$src)>;
4258 def : Pat<(f64 (bitconvert (v2i32 FPR64:$src))), (f64 FPR64:$src)>;
4259 def : Pat<(f64 (bitconvert (v4i16 FPR64:$src))), (f64 FPR64:$src)>;
4260 def : Pat<(f64 (bitconvert (v8i8 FPR64:$src))), (f64 FPR64:$src)>;
4261 def : Pat<(f64 (bitconvert (v2f32 FPR64:$src))), (f64 FPR64:$src)>;
4262 def : Pat<(f64 (bitconvert (v1f64 FPR64:$src))), (f64 FPR64:$src)>;
4264 def : Pat<(v1f64 (bitconvert (v1i64 FPR64:$src))), (v1f64 FPR64:$src)>;
4265 def : Pat<(v1f64 (bitconvert (v2i32 FPR64:$src))), (v1f64 FPR64:$src)>;
4266 def : Pat<(v1f64 (bitconvert (v4i16 FPR64:$src))), (v1f64 FPR64:$src)>;
4267 def : Pat<(v1f64 (bitconvert (v8i8 FPR64:$src))), (v1f64 FPR64:$src)>;
4268 def : Pat<(v1f64 (bitconvert (f64 FPR64:$src))), (v1f64 FPR64:$src)>;
4269 def : Pat<(v1f64 (bitconvert (v2f32 FPR64:$src))), (v1f64 FPR64:$src)>;
4271 def : Pat<(v2f32 (bitconvert (f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4272 def : Pat<(v2f32 (bitconvert (v1i64 FPR64:$src))), (v2f32 FPR64:$src)>;
4273 def : Pat<(v2f32 (bitconvert (v2i32 FPR64:$src))), (v2f32 FPR64:$src)>;
4274 def : Pat<(v2f32 (bitconvert (v4i16 FPR64:$src))), (v2f32 FPR64:$src)>;
4275 def : Pat<(v2f32 (bitconvert (v8i8 FPR64:$src))), (v2f32 FPR64:$src)>;
4276 def : Pat<(v2f32 (bitconvert (v1f64 FPR64:$src))), (v2f32 FPR64:$src)>;
4279 def : Pat<(f128 (bitconvert (v2i64 FPR128:$src))), (f128 FPR128:$src)>;
4280 def : Pat<(f128 (bitconvert (v4i32 FPR128:$src))), (f128 FPR128:$src)>;
4281 def : Pat<(f128 (bitconvert (v8i16 FPR128:$src))), (f128 FPR128:$src)>;
4282 def : Pat<(f128 (bitconvert (v2f64 FPR128:$src))), (f128 FPR128:$src)>;
4283 def : Pat<(f128 (bitconvert (v4f32 FPR128:$src))), (f128 FPR128:$src)>;
4285 def : Pat<(v2f64 (bitconvert (f128 FPR128:$src))), (v2f64 FPR128:$src)>;
4286 def : Pat<(v2f64 (bitconvert (v4i32 FPR128:$src))), (v2f64 FPR128:$src)>;
4287 def : Pat<(v2f64 (bitconvert (v8i16 FPR128:$src))), (v2f64 FPR128:$src)>;
4288 def : Pat<(v2f64 (bitconvert (v16i8 FPR128:$src))), (v2f64 FPR128:$src)>;
4289 def : Pat<(v2f64 (bitconvert (v2i64 FPR128:$src))), (v2f64 FPR128:$src)>;
4290 def : Pat<(v2f64 (bitconvert (v4f32 FPR128:$src))), (v2f64 FPR128:$src)>;
4292 def : Pat<(v4f32 (bitconvert (f128 FPR128:$src))), (v4f32 FPR128:$src)>;
4293 def : Pat<(v4f32 (bitconvert (v4i32 FPR128:$src))), (v4f32 FPR128:$src)>;
4294 def : Pat<(v4f32 (bitconvert (v8i16 FPR128:$src))), (v4f32 FPR128:$src)>;
4295 def : Pat<(v4f32 (bitconvert (v16i8 FPR128:$src))), (v4f32 FPR128:$src)>;
4296 def : Pat<(v4f32 (bitconvert (v2i64 FPR128:$src))), (v4f32 FPR128:$src)>;
4297 def : Pat<(v4f32 (bitconvert (v2f64 FPR128:$src))), (v4f32 FPR128:$src)>;
4299 def : Pat<(v2i64 (bitconvert (f128 FPR128:$src))), (v2i64 FPR128:$src)>;
4300 def : Pat<(v2i64 (bitconvert (v4i32 FPR128:$src))), (v2i64 FPR128:$src)>;
4301 def : Pat<(v2i64 (bitconvert (v8i16 FPR128:$src))), (v2i64 FPR128:$src)>;
4302 def : Pat<(v2i64 (bitconvert (v16i8 FPR128:$src))), (v2i64 FPR128:$src)>;
4303 def : Pat<(v2i64 (bitconvert (v2f64 FPR128:$src))), (v2i64 FPR128:$src)>;
4304 def : Pat<(v2i64 (bitconvert (v4f32 FPR128:$src))), (v2i64 FPR128:$src)>;
4306 def : Pat<(v4i32 (bitconvert (f128 FPR128:$src))), (v4i32 FPR128:$src)>;
4307 def : Pat<(v4i32 (bitconvert (v2i64 FPR128:$src))), (v4i32 FPR128:$src)>;
4308 def : Pat<(v4i32 (bitconvert (v8i16 FPR128:$src))), (v4i32 FPR128:$src)>;
4309 def : Pat<(v4i32 (bitconvert (v16i8 FPR128:$src))), (v4i32 FPR128:$src)>;
4310 def : Pat<(v4i32 (bitconvert (v2f64 FPR128:$src))), (v4i32 FPR128:$src)>;
4311 def : Pat<(v4i32 (bitconvert (v4f32 FPR128:$src))), (v4i32 FPR128:$src)>;
4313 def : Pat<(v8i16 (bitconvert (f128 FPR128:$src))), (v8i16 FPR128:$src)>;
4314 def : Pat<(v8i16 (bitconvert (v2i64 FPR128:$src))), (v8i16 FPR128:$src)>;
4315 def : Pat<(v8i16 (bitconvert (v4i32 FPR128:$src))), (v8i16 FPR128:$src)>;
4316 def : Pat<(v8i16 (bitconvert (v16i8 FPR128:$src))), (v8i16 FPR128:$src)>;
4317 def : Pat<(v8i16 (bitconvert (v2f64 FPR128:$src))), (v8i16 FPR128:$src)>;
4318 def : Pat<(v8i16 (bitconvert (v4f32 FPR128:$src))), (v8i16 FPR128:$src)>;
4320 def : Pat<(v16i8 (bitconvert (f128 FPR128:$src))), (v16i8 FPR128:$src)>;
4321 def : Pat<(v16i8 (bitconvert (v2i64 FPR128:$src))), (v16i8 FPR128:$src)>;
4322 def : Pat<(v16i8 (bitconvert (v4i32 FPR128:$src))), (v16i8 FPR128:$src)>;
4323 def : Pat<(v16i8 (bitconvert (v8i16 FPR128:$src))), (v16i8 FPR128:$src)>;
4324 def : Pat<(v16i8 (bitconvert (v2f64 FPR128:$src))), (v16i8 FPR128:$src)>;
4325 def : Pat<(v16i8 (bitconvert (v4f32 FPR128:$src))), (v16i8 FPR128:$src)>;
4327 def : Pat<(v8i8 (extract_subvector (v16i8 FPR128:$Rn), (i64 1))),
4328 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4329 def : Pat<(v4i16 (extract_subvector (v8i16 FPR128:$Rn), (i64 1))),
4330 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4331 def : Pat<(v2i32 (extract_subvector (v4i32 FPR128:$Rn), (i64 1))),
4332 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4333 def : Pat<(v1i64 (extract_subvector (v2i64 FPR128:$Rn), (i64 1))),
4334 (EXTRACT_SUBREG (DUPv2i64lane FPR128:$Rn, 1), dsub)>;
4336 // A 64-bit subvector insert to the first 128-bit vector position
4337 // is a subregister copy that needs no instruction.
4338 def : Pat<(insert_subvector undef, (v1i64 FPR64:$src), (i32 0)),
4339 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4340 def : Pat<(insert_subvector undef, (v1f64 FPR64:$src), (i32 0)),
4341 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4342 def : Pat<(insert_subvector undef, (v2i32 FPR64:$src), (i32 0)),
4343 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4344 def : Pat<(insert_subvector undef, (v2f32 FPR64:$src), (i32 0)),
4345 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4346 def : Pat<(insert_subvector undef, (v4i16 FPR64:$src), (i32 0)),
4347 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4348 def : Pat<(insert_subvector undef, (v8i8 FPR64:$src), (i32 0)),
4349 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)), FPR64:$src, dsub)>;
4351 // Use pair-wise add instructions when summing up the lanes for v2f64, v2i64
4353 def : Pat<(i64 (add (vector_extract (v2i64 FPR128:$Rn), (i64 0)),
4354 (vector_extract (v2i64 FPR128:$Rn), (i64 1)))),
4355 (i64 (ADDPv2i64p (v2i64 FPR128:$Rn)))>;
4356 def : Pat<(f64 (fadd (vector_extract (v2f64 FPR128:$Rn), (i64 0)),
4357 (vector_extract (v2f64 FPR128:$Rn), (i64 1)))),
4358 (f64 (FADDPv2i64p (v2f64 FPR128:$Rn)))>;
4359 // vector_extract on 64-bit vectors gets promoted to a 128 bit vector,
4360 // so we match on v4f32 here, not v2f32. This will also catch adding
4361 // the low two lanes of a true v4f32 vector.
4362 def : Pat<(fadd (vector_extract (v4f32 FPR128:$Rn), (i64 0)),
4363 (vector_extract (v4f32 FPR128:$Rn), (i64 1))),
4364 (f32 (FADDPv2i32p (EXTRACT_SUBREG FPR128:$Rn, dsub)))>;
4366 // Scalar 64-bit shifts in FPR64 registers.
4367 def : Pat<(i64 (int_arm64_neon_sshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4368 (SSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4369 def : Pat<(i64 (int_arm64_neon_ushl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4370 (USHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4371 def : Pat<(i64 (int_arm64_neon_srshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4372 (SRSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4373 def : Pat<(i64 (int_arm64_neon_urshl (i64 FPR64:$Rn), (i64 FPR64:$Rm))),
4374 (URSHLv1i64 FPR64:$Rn, FPR64:$Rm)>;
4376 // Tail call return handling. These are all compiler pseudo-instructions,
4377 // so no encoding information or anything like that.
4378 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [SP] in {
4379 def TCRETURNdi : Pseudo<(outs), (ins i64imm:$dst), []>;
4380 def TCRETURNri : Pseudo<(outs), (ins tcGPR64:$dst), []>;
4383 def : Pat<(ARM64tcret tcGPR64:$dst), (TCRETURNri tcGPR64:$dst)>;
4384 def : Pat<(ARM64tcret (i64 tglobaladdr:$dst)), (TCRETURNdi texternalsym:$dst)>;
4385 def : Pat<(ARM64tcret (i64 texternalsym:$dst)), (TCRETURNdi texternalsym:$dst)>;
4387 include "ARM64InstrAtomics.td"