1 //===- ARM64RegisterInfo.cpp - ARM64 Register Information -----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM64 implementation of the TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARM64RegisterInfo.h"
15 #include "ARM64FrameLowering.h"
16 #include "ARM64InstrInfo.h"
17 #include "ARM64Subtarget.h"
18 #include "MCTargetDesc/ARM64AddressingModes.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/raw_ostream.h"
27 #include "llvm/Target/TargetFrameLowering.h"
28 #include "llvm/Target/TargetOptions.h"
30 #define GET_REGINFO_TARGET_DESC
31 #include "ARM64GenRegisterInfo.inc"
35 ARM64RegisterInfo::ARM64RegisterInfo(const ARM64InstrInfo *tii,
36 const ARM64Subtarget *sti)
37 : ARM64GenRegisterInfo(ARM64::LR), TII(tii), STI(sti) {}
40 ARM64RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
41 assert(MF && "Invalid MachineFunction pointer.");
42 if (MF->getFunction()->getCallingConv() == CallingConv::AnyReg)
43 return CSR_ARM64_AllRegs_SaveList;
45 return CSR_ARM64_AAPCS_SaveList;
49 ARM64RegisterInfo::getCallPreservedMask(CallingConv::ID CC) const {
50 if (CC == CallingConv::AnyReg)
51 return CSR_ARM64_AllRegs_RegMask;
53 return CSR_ARM64_AAPCS_RegMask;
56 const uint32_t *ARM64RegisterInfo::getTLSCallPreservedMask() const {
57 if (STI->isTargetDarwin())
58 return CSR_ARM64_TLS_Darwin_RegMask;
60 assert(STI->isTargetELF() && "only expect Darwin or ELF TLS");
61 return CSR_ARM64_TLS_ELF_RegMask;
65 ARM64RegisterInfo::getThisReturnPreservedMask(CallingConv::ID) const {
66 // This should return a register mask that is the same as that returned by
67 // getCallPreservedMask but that additionally preserves the register used for
68 // the first i64 argument (which must also be the register used to return a
69 // single i64 return value)
71 // In case that the calling convention does not use the same register for
72 // both, the function should return NULL (does not currently apply)
73 return CSR_ARM64_AAPCS_ThisReturn_RegMask;
76 BitVector ARM64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
77 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
79 // FIXME: avoid re-calculating this every time.
80 BitVector Reserved(getNumRegs());
81 Reserved.set(ARM64::SP);
82 Reserved.set(ARM64::XZR);
83 Reserved.set(ARM64::WSP);
84 Reserved.set(ARM64::WZR);
86 if (TFI->hasFP(MF) || STI->isTargetDarwin()) {
87 Reserved.set(ARM64::FP);
88 Reserved.set(ARM64::W29);
91 if (STI->isTargetDarwin()) {
92 Reserved.set(ARM64::X18); // Platform register
93 Reserved.set(ARM64::W18);
96 if (hasBasePointer(MF)) {
97 Reserved.set(ARM64::X19);
98 Reserved.set(ARM64::W19);
104 bool ARM64RegisterInfo::isReservedReg(const MachineFunction &MF,
105 unsigned Reg) const {
106 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
118 return STI->isTargetDarwin();
121 return TFI->hasFP(MF) || STI->isTargetDarwin();
124 return hasBasePointer(MF);
130 const TargetRegisterClass *
131 ARM64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
132 unsigned Kind) const {
133 return &ARM64::GPR64RegClass;
136 const TargetRegisterClass *
137 ARM64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
138 if (RC == &ARM64::CCRRegClass)
139 return NULL; // Can't copy CPSR.
143 unsigned ARM64RegisterInfo::getBaseRegister() const { return ARM64::X19; }
145 bool ARM64RegisterInfo::hasBasePointer(const MachineFunction &MF) const {
146 const MachineFrameInfo *MFI = MF.getFrameInfo();
148 // In the presence of variable sized objects, if the fixed stack size is
149 // large enough that referencing from the FP won't result in things being
150 // in range relatively often, we can use a base pointer to allow access
151 // from the other direction like the SP normally works.
152 if (MFI->hasVarSizedObjects()) {
153 // Conservatively estimate whether the negative offset from the frame
154 // pointer will be sufficient to reach. If a function has a smallish
155 // frame, it's less likely to have lots of spills and callee saved
156 // space, so it's all more likely to be within range of the frame pointer.
157 // If it's wrong, we'll materialize the constant and still get to the
158 // object; it's just suboptimal. Negative offsets use the unscaled
159 // load/store instructions, which have a 9-bit signed immediate.
160 if (MFI->getLocalFrameSize() < 256)
168 unsigned ARM64RegisterInfo::getFrameRegister(const MachineFunction &MF) const {
169 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
171 return TFI->hasFP(MF) ? ARM64::FP : ARM64::SP;
175 ARM64RegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
179 bool ARM64RegisterInfo::requiresVirtualBaseRegisters(const MachineFunction &MF)
185 ARM64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
186 const MachineFrameInfo *MFI = MF.getFrameInfo();
187 // ARM64FrameLowering::resolveFrameIndexReference() can always fall back
188 // to the stack pointer, so only put the emergency spill slot next to the
189 // FP when there's no better way to access it (SP or base pointer).
190 return MFI->hasVarSizedObjects() && !hasBasePointer(MF);
193 bool ARM64RegisterInfo::requiresFrameIndexScavenging(const MachineFunction &MF)
198 bool ARM64RegisterInfo::cannotEliminateFrame(const MachineFunction &MF) const {
199 const MachineFrameInfo *MFI = MF.getFrameInfo();
200 // Only consider eliminating leaf frames.
201 if (MFI->hasCalls() || (MF.getTarget().Options.DisableFramePointerElim(MF) &&
202 MFI->adjustsStack()))
204 return MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
207 /// needsFrameBaseReg - Returns true if the instruction's frame index
208 /// reference would be better served by a base register other than FP
209 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
210 /// references it should create new base registers for.
211 bool ARM64RegisterInfo::needsFrameBaseReg(MachineInstr *MI,
212 int64_t Offset) const {
213 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
214 assert(i < MI->getNumOperands() &&
215 "Instr doesn't have FrameIndex operand!");
217 // It's the load/store FI references that cause issues, as it can be difficult
218 // to materialize the offset if it won't fit in the literal field. Estimate
219 // based on the size of the local frame and some conservative assumptions
220 // about the rest of the stack frame (note, this is pre-regalloc, so
221 // we don't know everything for certain yet) whether this offset is likely
222 // to be out of range of the immediate. Return true if so.
224 // We only generate virtual base registers for loads and stores, so
225 // return false for everything else.
226 if (!MI->mayLoad() && !MI->mayStore())
229 // Without a virtual base register, if the function has variable sized
230 // objects, all fixed-size local references will be via the frame pointer,
231 // Approximate the offset and see if it's legal for the instruction.
232 // Note that the incoming offset is based on the SP value at function entry,
233 // so it'll be negative.
234 MachineFunction &MF = *MI->getParent()->getParent();
235 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
236 MachineFrameInfo *MFI = MF.getFrameInfo();
238 // Estimate an offset from the frame pointer.
239 // Conservatively assume all GPR callee-saved registers get pushed.
240 // FP, LR, X19-X28, D8-D15. 64-bits each.
241 int64_t FPOffset = Offset - 16 * 20;
242 // Estimate an offset from the stack pointer.
243 // The incoming offset is relating to the SP at the start of the function,
244 // but when we access the local it'll be relative to the SP after local
245 // allocation, so adjust our SP-relative offset by that allocation size.
246 Offset += MFI->getLocalFrameSize();
247 // Assume that we'll have at least some spill slots allocated.
248 // FIXME: This is a total SWAG number. We should run some statistics
249 // and pick a real one.
250 Offset += 128; // 128 bytes of spill slots
252 // If there is a frame pointer, try using it.
253 // The FP is only available if there is no dynamic realignment. We
254 // don't know for sure yet whether we'll need that, so we guess based
255 // on whether there are any local variables that would trigger it.
256 if (TFI->hasFP(MF) && isFrameOffsetLegal(MI, FPOffset))
259 // If we can reference via the stack pointer or base pointer, try that.
260 // FIXME: This (and the code that resolves the references) can be improved
261 // to only disallow SP relative references in the live range of
262 // the VLA(s). In practice, it's unclear how much difference that
263 // would make, but it may be worth doing.
264 if (isFrameOffsetLegal(MI, Offset))
267 // The offset likely isn't legal; we want to allocate a virtual base register.
271 bool ARM64RegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
272 int64_t Offset) const {
273 assert(Offset <= INT_MAX && "Offset too big to fit in int.");
274 assert(MI && "Unable to get the legal offset for nil instruction.");
275 int SaveOffset = Offset;
276 return isARM64FrameOffsetLegal(*MI, SaveOffset) & ARM64FrameOffsetIsLegal;
279 /// Insert defining instruction(s) for BaseReg to be a pointer to FrameIdx
280 /// at the beginning of the basic block.
281 void ARM64RegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
284 int64_t Offset) const {
285 MachineBasicBlock::iterator Ins = MBB->begin();
286 DebugLoc DL; // Defaults to "unknown"
287 if (Ins != MBB->end())
288 DL = Ins->getDebugLoc();
290 const MCInstrDesc &MCID = TII->get(ARM64::ADDXri);
291 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
292 const MachineFunction &MF = *MBB->getParent();
293 MRI.constrainRegClass(BaseReg, TII->getRegClass(MCID, 0, this, MF));
294 unsigned Shifter = ARM64_AM::getShifterImm(ARM64_AM::LSL, 0);
296 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
297 .addFrameIndex(FrameIdx)
302 void ARM64RegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
303 int64_t Offset) const {
304 int Off = Offset; // ARM doesn't need the general 64-bit offsets
307 while (!MI.getOperand(i).isFI()) {
309 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
311 bool Done = rewriteARM64FrameIndex(MI, i, BaseReg, Off, TII);
312 assert(Done && "Unable to resolve frame index!");
316 void ARM64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
317 int SPAdj, unsigned FIOperandNum,
318 RegScavenger *RS) const {
319 assert(SPAdj == 0 && "Unexpected");
321 MachineInstr &MI = *II;
322 MachineBasicBlock &MBB = *MI.getParent();
323 MachineFunction &MF = *MBB.getParent();
324 const ARM64FrameLowering *TFI = static_cast<const ARM64FrameLowering *>(
325 MF.getTarget().getFrameLowering());
327 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
331 // Special handling of dbg_value, stackmap and patchpoint instructions.
332 if (MI.isDebugValue() || MI.getOpcode() == TargetOpcode::STACKMAP ||
333 MI.getOpcode() == TargetOpcode::PATCHPOINT) {
334 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg,
336 Offset += MI.getOperand(FIOperandNum + 1).getImm();
337 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
338 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
342 // Modify MI as necessary to handle as much of 'Offset' as possible
343 Offset = TFI->resolveFrameIndexReference(MF, FrameIndex, FrameReg);
344 if (rewriteARM64FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII))
347 assert((!RS || !RS->isScavengingFrameIndex(FrameIndex)) &&
348 "Emergency spill slot is out of reach");
350 // If we get here, the immediate doesn't fit into the instruction. We folded
351 // as much as possible above. Handle the rest, providing a register that is
353 unsigned ScratchReg =
354 MF.getRegInfo().createVirtualRegister(&ARM64::GPR64RegClass);
355 emitFrameOffset(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg, Offset, TII);
356 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false, true);
361 unsigned ARM64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
362 MachineFunction &MF) const {
363 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
365 switch (RC->getID()) {
368 case ARM64::GPR32RegClassID:
369 case ARM64::GPR32spRegClassID:
370 case ARM64::GPR32allRegClassID:
371 case ARM64::GPR64spRegClassID:
372 case ARM64::GPR64allRegClassID:
373 case ARM64::GPR64RegClassID:
374 case ARM64::GPR32commonRegClassID:
375 case ARM64::GPR64commonRegClassID:
376 return 32 - 1 // XZR/SP
377 - (TFI->hasFP(MF) || STI->isTargetDarwin()) // FP
378 - STI->isTargetDarwin() // X18 reserved as platform register
379 - hasBasePointer(MF); // X19
380 case ARM64::FPR8RegClassID:
381 case ARM64::FPR16RegClassID:
382 case ARM64::FPR32RegClassID:
383 case ARM64::FPR64RegClassID:
384 case ARM64::FPR128RegClassID:
387 case ARM64::DDRegClassID:
388 case ARM64::DDDRegClassID:
389 case ARM64::DDDDRegClassID:
390 case ARM64::QQRegClassID:
391 case ARM64::QQQRegClassID:
392 case ARM64::QQQQRegClassID:
395 case ARM64::FPR128_loRegClassID: