1 //===- ARM64RegisterInfo.td - Describe the ARM64 Regisers --*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
14 class ARM64Reg<bits<16> enc, string n, list<Register> subregs = [],
15 list<string> altNames = []>
16 : Register<n, altNames> {
18 let Namespace = "ARM64";
19 let SubRegs = subregs;
22 let Namespace = "ARM64" in {
23 def sub_32 : SubRegIndex<32>;
25 def bsub : SubRegIndex<8>;
26 def hsub : SubRegIndex<16>;
27 def ssub : SubRegIndex<32>;
28 def dsub : SubRegIndex<32>;
29 def qhisub : SubRegIndex<64>;
30 def qsub : SubRegIndex<64>;
31 // Note: Code depends on these having consecutive numbers
32 def dsub0 : SubRegIndex<64>;
33 def dsub1 : SubRegIndex<64>;
34 def dsub2 : SubRegIndex<64>;
35 def dsub3 : SubRegIndex<64>;
36 // Note: Code depends on these having consecutive numbers
37 def qsub0 : SubRegIndex<128>;
38 def qsub1 : SubRegIndex<128>;
39 def qsub2 : SubRegIndex<128>;
40 def qsub3 : SubRegIndex<128>;
43 let Namespace = "ARM64" in {
44 def vreg : RegAltNameIndex;
45 def vlist1 : RegAltNameIndex;
48 //===----------------------------------------------------------------------===//
50 //===----------------------------------------------------------------------===//
51 def W0 : ARM64Reg<0, "w0" >, DwarfRegNum<[0]>;
52 def W1 : ARM64Reg<1, "w1" >, DwarfRegNum<[1]>;
53 def W2 : ARM64Reg<2, "w2" >, DwarfRegNum<[2]>;
54 def W3 : ARM64Reg<3, "w3" >, DwarfRegNum<[3]>;
55 def W4 : ARM64Reg<4, "w4" >, DwarfRegNum<[4]>;
56 def W5 : ARM64Reg<5, "w5" >, DwarfRegNum<[5]>;
57 def W6 : ARM64Reg<6, "w6" >, DwarfRegNum<[6]>;
58 def W7 : ARM64Reg<7, "w7" >, DwarfRegNum<[7]>;
59 def W8 : ARM64Reg<8, "w8" >, DwarfRegNum<[8]>;
60 def W9 : ARM64Reg<9, "w9" >, DwarfRegNum<[9]>;
61 def W10 : ARM64Reg<10, "w10">, DwarfRegNum<[10]>;
62 def W11 : ARM64Reg<11, "w11">, DwarfRegNum<[11]>;
63 def W12 : ARM64Reg<12, "w12">, DwarfRegNum<[12]>;
64 def W13 : ARM64Reg<13, "w13">, DwarfRegNum<[13]>;
65 def W14 : ARM64Reg<14, "w14">, DwarfRegNum<[14]>;
66 def W15 : ARM64Reg<15, "w15">, DwarfRegNum<[15]>;
67 def W16 : ARM64Reg<16, "w16">, DwarfRegNum<[16]>;
68 def W17 : ARM64Reg<17, "w17">, DwarfRegNum<[17]>;
69 def W18 : ARM64Reg<18, "w18">, DwarfRegNum<[18]>;
70 def W19 : ARM64Reg<19, "w19">, DwarfRegNum<[19]>;
71 def W20 : ARM64Reg<20, "w20">, DwarfRegNum<[20]>;
72 def W21 : ARM64Reg<21, "w21">, DwarfRegNum<[21]>;
73 def W22 : ARM64Reg<22, "w22">, DwarfRegNum<[22]>;
74 def W23 : ARM64Reg<23, "w23">, DwarfRegNum<[23]>;
75 def W24 : ARM64Reg<24, "w24">, DwarfRegNum<[24]>;
76 def W25 : ARM64Reg<25, "w25">, DwarfRegNum<[25]>;
77 def W26 : ARM64Reg<26, "w26">, DwarfRegNum<[26]>;
78 def W27 : ARM64Reg<27, "w27">, DwarfRegNum<[27]>;
79 def W28 : ARM64Reg<28, "w28">, DwarfRegNum<[28]>;
80 def W29 : ARM64Reg<29, "w29">, DwarfRegNum<[29]>;
81 def W30 : ARM64Reg<30, "w30">, DwarfRegNum<[30]>;
82 def WSP : ARM64Reg<31, "wsp">, DwarfRegNum<[31]>;
83 def WZR : ARM64Reg<31, "wzr">, DwarfRegAlias<WSP>;
85 let SubRegIndices = [sub_32] in {
86 def X0 : ARM64Reg<0, "x0", [W0]>, DwarfRegAlias<W0>;
87 def X1 : ARM64Reg<1, "x1", [W1]>, DwarfRegAlias<W1>;
88 def X2 : ARM64Reg<2, "x2", [W2]>, DwarfRegAlias<W2>;
89 def X3 : ARM64Reg<3, "x3", [W3]>, DwarfRegAlias<W3>;
90 def X4 : ARM64Reg<4, "x4", [W4]>, DwarfRegAlias<W4>;
91 def X5 : ARM64Reg<5, "x5", [W5]>, DwarfRegAlias<W5>;
92 def X6 : ARM64Reg<6, "x6", [W6]>, DwarfRegAlias<W6>;
93 def X7 : ARM64Reg<7, "x7", [W7]>, DwarfRegAlias<W7>;
94 def X8 : ARM64Reg<8, "x8", [W8]>, DwarfRegAlias<W8>;
95 def X9 : ARM64Reg<9, "x9", [W9]>, DwarfRegAlias<W9>;
96 def X10 : ARM64Reg<10, "x10", [W10]>, DwarfRegAlias<W10>;
97 def X11 : ARM64Reg<11, "x11", [W11]>, DwarfRegAlias<W11>;
98 def X12 : ARM64Reg<12, "x12", [W12]>, DwarfRegAlias<W12>;
99 def X13 : ARM64Reg<13, "x13", [W13]>, DwarfRegAlias<W13>;
100 def X14 : ARM64Reg<14, "x14", [W14]>, DwarfRegAlias<W14>;
101 def X15 : ARM64Reg<15, "x15", [W15]>, DwarfRegAlias<W15>;
102 def X16 : ARM64Reg<16, "x16", [W16]>, DwarfRegAlias<W16>;
103 def X17 : ARM64Reg<17, "x17", [W17]>, DwarfRegAlias<W17>;
104 def X18 : ARM64Reg<18, "x18", [W18]>, DwarfRegAlias<W18>;
105 def X19 : ARM64Reg<19, "x19", [W19]>, DwarfRegAlias<W19>;
106 def X20 : ARM64Reg<20, "x20", [W20]>, DwarfRegAlias<W20>;
107 def X21 : ARM64Reg<21, "x21", [W21]>, DwarfRegAlias<W21>;
108 def X22 : ARM64Reg<22, "x22", [W22]>, DwarfRegAlias<W22>;
109 def X23 : ARM64Reg<23, "x23", [W23]>, DwarfRegAlias<W23>;
110 def X24 : ARM64Reg<24, "x24", [W24]>, DwarfRegAlias<W24>;
111 def X25 : ARM64Reg<25, "x25", [W25]>, DwarfRegAlias<W25>;
112 def X26 : ARM64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>;
113 def X27 : ARM64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>;
114 def X28 : ARM64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>;
115 def FP : ARM64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>;
116 def LR : ARM64Reg<30, "x30", [W30]>, DwarfRegAlias<W30>;
117 def SP : ARM64Reg<31, "sp", [WSP]>, DwarfRegAlias<WSP>;
118 def XZR : ARM64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>;
121 // Condition code register.
122 def NZCV : ARM64Reg<0, "nzcv">;
124 // GPR register classes with the intersections of GPR32/GPR32sp and
125 // GPR64/GPR64sp for use by the coalescer.
126 def GPR32common : RegisterClass<"ARM64", [i32], 32, (sequence "W%u", 0, 30)> {
127 let AltOrders = [(rotl GPR32common, 8)];
128 let AltOrderSelect = [{ return 1; }];
130 def GPR64common : RegisterClass<"ARM64", [i64], 64,
131 (add (sequence "X%u", 0, 28), FP, LR)> {
132 let AltOrders = [(rotl GPR64common, 8)];
133 let AltOrderSelect = [{ return 1; }];
135 // GPR register classes which exclude SP/WSP.
136 def GPR32 : RegisterClass<"ARM64", [i32], 32, (add GPR32common, WZR)> {
137 let AltOrders = [(rotl GPR32, 8)];
138 let AltOrderSelect = [{ return 1; }];
140 def GPR64 : RegisterClass<"ARM64", [i64], 64, (add GPR64common, XZR)> {
141 let AltOrders = [(rotl GPR64, 8)];
142 let AltOrderSelect = [{ return 1; }];
145 // GPR register classes which include SP/WSP.
146 def GPR32sp : RegisterClass<"ARM64", [i32], 32, (add GPR32common, WSP)> {
147 let AltOrders = [(rotl GPR32sp, 8)];
148 let AltOrderSelect = [{ return 1; }];
150 def GPR64sp : RegisterClass<"ARM64", [i64], 64, (add GPR64common, SP)> {
151 let AltOrders = [(rotl GPR64sp, 8)];
152 let AltOrderSelect = [{ return 1; }];
155 def GPR32sponly : RegisterClass<"ARM64", [i32], 32, (add WSP)>;
156 def GPR64sponly : RegisterClass<"ARM64", [i64], 64, (add SP)>;
158 // GPR register classes which include WZR/XZR AND SP/WSP. This is not a
159 // constraint used by any instructions, it is used as a common super-class.
160 def GPR32all : RegisterClass<"ARM64", [i32], 32, (add GPR32common, WZR, WSP)>;
161 def GPR64all : RegisterClass<"ARM64", [i64], 64, (add GPR64common, XZR, SP)>;
163 // For tail calls, we can't use callee-saved registers, as they are restored
164 // to the saved value before the tail call, which would clobber a call address.
165 // This is for indirect tail calls to store the address of the destination.
166 def tcGPR64 : RegisterClass<"ARM64", [i64], 64, (sub GPR64common, X19, X20, X21,
167 X22, X23, X24, X25, X26,
170 // GPR register classes for post increment amount of vector load/store that
171 // has alternate printing when Rm=31 and prints a constant immediate value
172 // equal to the total number of bytes transferred.
174 // FIXME: TableGen *should* be able to do these itself now. There appears to be
175 // a bug in counting how many operands a Post-indexed MCInst should have which
176 // means the aliases don't trigger.
177 def GPR64pi1 : RegisterOperand<GPR64, "printPostIncOperand<1>">;
178 def GPR64pi2 : RegisterOperand<GPR64, "printPostIncOperand<2>">;
179 def GPR64pi3 : RegisterOperand<GPR64, "printPostIncOperand<3>">;
180 def GPR64pi4 : RegisterOperand<GPR64, "printPostIncOperand<4>">;
181 def GPR64pi6 : RegisterOperand<GPR64, "printPostIncOperand<6>">;
182 def GPR64pi8 : RegisterOperand<GPR64, "printPostIncOperand<8>">;
183 def GPR64pi12 : RegisterOperand<GPR64, "printPostIncOperand<12>">;
184 def GPR64pi16 : RegisterOperand<GPR64, "printPostIncOperand<16>">;
185 def GPR64pi24 : RegisterOperand<GPR64, "printPostIncOperand<24>">;
186 def GPR64pi32 : RegisterOperand<GPR64, "printPostIncOperand<32>">;
187 def GPR64pi48 : RegisterOperand<GPR64, "printPostIncOperand<48>">;
188 def GPR64pi64 : RegisterOperand<GPR64, "printPostIncOperand<64>">;
190 // Condition code regclass.
191 def CCR : RegisterClass<"ARM64", [i32], 32, (add NZCV)> {
192 let CopyCost = -1; // Don't allow copying of status registers.
194 // CCR is not allocatable.
195 let isAllocatable = 0;
198 //===----------------------------------------------------------------------===//
199 // Floating Point Scalar Registers
200 //===----------------------------------------------------------------------===//
202 def B0 : ARM64Reg<0, "b0">, DwarfRegNum<[64]>;
203 def B1 : ARM64Reg<1, "b1">, DwarfRegNum<[65]>;
204 def B2 : ARM64Reg<2, "b2">, DwarfRegNum<[66]>;
205 def B3 : ARM64Reg<3, "b3">, DwarfRegNum<[67]>;
206 def B4 : ARM64Reg<4, "b4">, DwarfRegNum<[68]>;
207 def B5 : ARM64Reg<5, "b5">, DwarfRegNum<[69]>;
208 def B6 : ARM64Reg<6, "b6">, DwarfRegNum<[70]>;
209 def B7 : ARM64Reg<7, "b7">, DwarfRegNum<[71]>;
210 def B8 : ARM64Reg<8, "b8">, DwarfRegNum<[72]>;
211 def B9 : ARM64Reg<9, "b9">, DwarfRegNum<[73]>;
212 def B10 : ARM64Reg<10, "b10">, DwarfRegNum<[74]>;
213 def B11 : ARM64Reg<11, "b11">, DwarfRegNum<[75]>;
214 def B12 : ARM64Reg<12, "b12">, DwarfRegNum<[76]>;
215 def B13 : ARM64Reg<13, "b13">, DwarfRegNum<[77]>;
216 def B14 : ARM64Reg<14, "b14">, DwarfRegNum<[78]>;
217 def B15 : ARM64Reg<15, "b15">, DwarfRegNum<[79]>;
218 def B16 : ARM64Reg<16, "b16">, DwarfRegNum<[80]>;
219 def B17 : ARM64Reg<17, "b17">, DwarfRegNum<[81]>;
220 def B18 : ARM64Reg<18, "b18">, DwarfRegNum<[82]>;
221 def B19 : ARM64Reg<19, "b19">, DwarfRegNum<[83]>;
222 def B20 : ARM64Reg<20, "b20">, DwarfRegNum<[84]>;
223 def B21 : ARM64Reg<21, "b21">, DwarfRegNum<[85]>;
224 def B22 : ARM64Reg<22, "b22">, DwarfRegNum<[86]>;
225 def B23 : ARM64Reg<23, "b23">, DwarfRegNum<[87]>;
226 def B24 : ARM64Reg<24, "b24">, DwarfRegNum<[88]>;
227 def B25 : ARM64Reg<25, "b25">, DwarfRegNum<[89]>;
228 def B26 : ARM64Reg<26, "b26">, DwarfRegNum<[90]>;
229 def B27 : ARM64Reg<27, "b27">, DwarfRegNum<[91]>;
230 def B28 : ARM64Reg<28, "b28">, DwarfRegNum<[92]>;
231 def B29 : ARM64Reg<29, "b29">, DwarfRegNum<[93]>;
232 def B30 : ARM64Reg<30, "b30">, DwarfRegNum<[94]>;
233 def B31 : ARM64Reg<31, "b31">, DwarfRegNum<[95]>;
235 let SubRegIndices = [bsub] in {
236 def H0 : ARM64Reg<0, "h0", [B0]>, DwarfRegAlias<B0>;
237 def H1 : ARM64Reg<1, "h1", [B1]>, DwarfRegAlias<B1>;
238 def H2 : ARM64Reg<2, "h2", [B2]>, DwarfRegAlias<B2>;
239 def H3 : ARM64Reg<3, "h3", [B3]>, DwarfRegAlias<B3>;
240 def H4 : ARM64Reg<4, "h4", [B4]>, DwarfRegAlias<B4>;
241 def H5 : ARM64Reg<5, "h5", [B5]>, DwarfRegAlias<B5>;
242 def H6 : ARM64Reg<6, "h6", [B6]>, DwarfRegAlias<B6>;
243 def H7 : ARM64Reg<7, "h7", [B7]>, DwarfRegAlias<B7>;
244 def H8 : ARM64Reg<8, "h8", [B8]>, DwarfRegAlias<B8>;
245 def H9 : ARM64Reg<9, "h9", [B9]>, DwarfRegAlias<B9>;
246 def H10 : ARM64Reg<10, "h10", [B10]>, DwarfRegAlias<B10>;
247 def H11 : ARM64Reg<11, "h11", [B11]>, DwarfRegAlias<B11>;
248 def H12 : ARM64Reg<12, "h12", [B12]>, DwarfRegAlias<B12>;
249 def H13 : ARM64Reg<13, "h13", [B13]>, DwarfRegAlias<B13>;
250 def H14 : ARM64Reg<14, "h14", [B14]>, DwarfRegAlias<B14>;
251 def H15 : ARM64Reg<15, "h15", [B15]>, DwarfRegAlias<B15>;
252 def H16 : ARM64Reg<16, "h16", [B16]>, DwarfRegAlias<B16>;
253 def H17 : ARM64Reg<17, "h17", [B17]>, DwarfRegAlias<B17>;
254 def H18 : ARM64Reg<18, "h18", [B18]>, DwarfRegAlias<B18>;
255 def H19 : ARM64Reg<19, "h19", [B19]>, DwarfRegAlias<B19>;
256 def H20 : ARM64Reg<20, "h20", [B20]>, DwarfRegAlias<B20>;
257 def H21 : ARM64Reg<21, "h21", [B21]>, DwarfRegAlias<B21>;
258 def H22 : ARM64Reg<22, "h22", [B22]>, DwarfRegAlias<B22>;
259 def H23 : ARM64Reg<23, "h23", [B23]>, DwarfRegAlias<B23>;
260 def H24 : ARM64Reg<24, "h24", [B24]>, DwarfRegAlias<B24>;
261 def H25 : ARM64Reg<25, "h25", [B25]>, DwarfRegAlias<B25>;
262 def H26 : ARM64Reg<26, "h26", [B26]>, DwarfRegAlias<B26>;
263 def H27 : ARM64Reg<27, "h27", [B27]>, DwarfRegAlias<B27>;
264 def H28 : ARM64Reg<28, "h28", [B28]>, DwarfRegAlias<B28>;
265 def H29 : ARM64Reg<29, "h29", [B29]>, DwarfRegAlias<B29>;
266 def H30 : ARM64Reg<30, "h30", [B30]>, DwarfRegAlias<B30>;
267 def H31 : ARM64Reg<31, "h31", [B31]>, DwarfRegAlias<B31>;
270 let SubRegIndices = [hsub] in {
271 def S0 : ARM64Reg<0, "s0", [H0]>, DwarfRegAlias<B0>;
272 def S1 : ARM64Reg<1, "s1", [H1]>, DwarfRegAlias<B1>;
273 def S2 : ARM64Reg<2, "s2", [H2]>, DwarfRegAlias<B2>;
274 def S3 : ARM64Reg<3, "s3", [H3]>, DwarfRegAlias<B3>;
275 def S4 : ARM64Reg<4, "s4", [H4]>, DwarfRegAlias<B4>;
276 def S5 : ARM64Reg<5, "s5", [H5]>, DwarfRegAlias<B5>;
277 def S6 : ARM64Reg<6, "s6", [H6]>, DwarfRegAlias<B6>;
278 def S7 : ARM64Reg<7, "s7", [H7]>, DwarfRegAlias<B7>;
279 def S8 : ARM64Reg<8, "s8", [H8]>, DwarfRegAlias<B8>;
280 def S9 : ARM64Reg<9, "s9", [H9]>, DwarfRegAlias<B9>;
281 def S10 : ARM64Reg<10, "s10", [H10]>, DwarfRegAlias<B10>;
282 def S11 : ARM64Reg<11, "s11", [H11]>, DwarfRegAlias<B11>;
283 def S12 : ARM64Reg<12, "s12", [H12]>, DwarfRegAlias<B12>;
284 def S13 : ARM64Reg<13, "s13", [H13]>, DwarfRegAlias<B13>;
285 def S14 : ARM64Reg<14, "s14", [H14]>, DwarfRegAlias<B14>;
286 def S15 : ARM64Reg<15, "s15", [H15]>, DwarfRegAlias<B15>;
287 def S16 : ARM64Reg<16, "s16", [H16]>, DwarfRegAlias<B16>;
288 def S17 : ARM64Reg<17, "s17", [H17]>, DwarfRegAlias<B17>;
289 def S18 : ARM64Reg<18, "s18", [H18]>, DwarfRegAlias<B18>;
290 def S19 : ARM64Reg<19, "s19", [H19]>, DwarfRegAlias<B19>;
291 def S20 : ARM64Reg<20, "s20", [H20]>, DwarfRegAlias<B20>;
292 def S21 : ARM64Reg<21, "s21", [H21]>, DwarfRegAlias<B21>;
293 def S22 : ARM64Reg<22, "s22", [H22]>, DwarfRegAlias<B22>;
294 def S23 : ARM64Reg<23, "s23", [H23]>, DwarfRegAlias<B23>;
295 def S24 : ARM64Reg<24, "s24", [H24]>, DwarfRegAlias<B24>;
296 def S25 : ARM64Reg<25, "s25", [H25]>, DwarfRegAlias<B25>;
297 def S26 : ARM64Reg<26, "s26", [H26]>, DwarfRegAlias<B26>;
298 def S27 : ARM64Reg<27, "s27", [H27]>, DwarfRegAlias<B27>;
299 def S28 : ARM64Reg<28, "s28", [H28]>, DwarfRegAlias<B28>;
300 def S29 : ARM64Reg<29, "s29", [H29]>, DwarfRegAlias<B29>;
301 def S30 : ARM64Reg<30, "s30", [H30]>, DwarfRegAlias<B30>;
302 def S31 : ARM64Reg<31, "s31", [H31]>, DwarfRegAlias<B31>;
305 let SubRegIndices = [ssub], RegAltNameIndices = [vreg, vlist1] in {
306 def D0 : ARM64Reg<0, "d0", [S0], ["v0", ""]>, DwarfRegAlias<B0>;
307 def D1 : ARM64Reg<1, "d1", [S1], ["v1", ""]>, DwarfRegAlias<B1>;
308 def D2 : ARM64Reg<2, "d2", [S2], ["v2", ""]>, DwarfRegAlias<B2>;
309 def D3 : ARM64Reg<3, "d3", [S3], ["v3", ""]>, DwarfRegAlias<B3>;
310 def D4 : ARM64Reg<4, "d4", [S4], ["v4", ""]>, DwarfRegAlias<B4>;
311 def D5 : ARM64Reg<5, "d5", [S5], ["v5", ""]>, DwarfRegAlias<B5>;
312 def D6 : ARM64Reg<6, "d6", [S6], ["v6", ""]>, DwarfRegAlias<B6>;
313 def D7 : ARM64Reg<7, "d7", [S7], ["v7", ""]>, DwarfRegAlias<B7>;
314 def D8 : ARM64Reg<8, "d8", [S8], ["v8", ""]>, DwarfRegAlias<B8>;
315 def D9 : ARM64Reg<9, "d9", [S9], ["v9", ""]>, DwarfRegAlias<B9>;
316 def D10 : ARM64Reg<10, "d10", [S10], ["v10", ""]>, DwarfRegAlias<B10>;
317 def D11 : ARM64Reg<11, "d11", [S11], ["v11", ""]>, DwarfRegAlias<B11>;
318 def D12 : ARM64Reg<12, "d12", [S12], ["v12", ""]>, DwarfRegAlias<B12>;
319 def D13 : ARM64Reg<13, "d13", [S13], ["v13", ""]>, DwarfRegAlias<B13>;
320 def D14 : ARM64Reg<14, "d14", [S14], ["v14", ""]>, DwarfRegAlias<B14>;
321 def D15 : ARM64Reg<15, "d15", [S15], ["v15", ""]>, DwarfRegAlias<B15>;
322 def D16 : ARM64Reg<16, "d16", [S16], ["v16", ""]>, DwarfRegAlias<B16>;
323 def D17 : ARM64Reg<17, "d17", [S17], ["v17", ""]>, DwarfRegAlias<B17>;
324 def D18 : ARM64Reg<18, "d18", [S18], ["v18", ""]>, DwarfRegAlias<B18>;
325 def D19 : ARM64Reg<19, "d19", [S19], ["v19", ""]>, DwarfRegAlias<B19>;
326 def D20 : ARM64Reg<20, "d20", [S20], ["v20", ""]>, DwarfRegAlias<B20>;
327 def D21 : ARM64Reg<21, "d21", [S21], ["v21", ""]>, DwarfRegAlias<B21>;
328 def D22 : ARM64Reg<22, "d22", [S22], ["v22", ""]>, DwarfRegAlias<B22>;
329 def D23 : ARM64Reg<23, "d23", [S23], ["v23", ""]>, DwarfRegAlias<B23>;
330 def D24 : ARM64Reg<24, "d24", [S24], ["v24", ""]>, DwarfRegAlias<B24>;
331 def D25 : ARM64Reg<25, "d25", [S25], ["v25", ""]>, DwarfRegAlias<B25>;
332 def D26 : ARM64Reg<26, "d26", [S26], ["v26", ""]>, DwarfRegAlias<B26>;
333 def D27 : ARM64Reg<27, "d27", [S27], ["v27", ""]>, DwarfRegAlias<B27>;
334 def D28 : ARM64Reg<28, "d28", [S28], ["v28", ""]>, DwarfRegAlias<B28>;
335 def D29 : ARM64Reg<29, "d29", [S29], ["v29", ""]>, DwarfRegAlias<B29>;
336 def D30 : ARM64Reg<30, "d30", [S30], ["v30", ""]>, DwarfRegAlias<B30>;
337 def D31 : ARM64Reg<31, "d31", [S31], ["v31", ""]>, DwarfRegAlias<B31>;
340 let SubRegIndices = [dsub], RegAltNameIndices = [vreg, vlist1] in {
341 def Q0 : ARM64Reg<0, "q0", [D0], ["v0", ""]>, DwarfRegAlias<B0>;
342 def Q1 : ARM64Reg<1, "q1", [D1], ["v1", ""]>, DwarfRegAlias<B1>;
343 def Q2 : ARM64Reg<2, "q2", [D2], ["v2", ""]>, DwarfRegAlias<B2>;
344 def Q3 : ARM64Reg<3, "q3", [D3], ["v3", ""]>, DwarfRegAlias<B3>;
345 def Q4 : ARM64Reg<4, "q4", [D4], ["v4", ""]>, DwarfRegAlias<B4>;
346 def Q5 : ARM64Reg<5, "q5", [D5], ["v5", ""]>, DwarfRegAlias<B5>;
347 def Q6 : ARM64Reg<6, "q6", [D6], ["v6", ""]>, DwarfRegAlias<B6>;
348 def Q7 : ARM64Reg<7, "q7", [D7], ["v7", ""]>, DwarfRegAlias<B7>;
349 def Q8 : ARM64Reg<8, "q8", [D8], ["v8", ""]>, DwarfRegAlias<B8>;
350 def Q9 : ARM64Reg<9, "q9", [D9], ["v9", ""]>, DwarfRegAlias<B9>;
351 def Q10 : ARM64Reg<10, "q10", [D10], ["v10", ""]>, DwarfRegAlias<B10>;
352 def Q11 : ARM64Reg<11, "q11", [D11], ["v11", ""]>, DwarfRegAlias<B11>;
353 def Q12 : ARM64Reg<12, "q12", [D12], ["v12", ""]>, DwarfRegAlias<B12>;
354 def Q13 : ARM64Reg<13, "q13", [D13], ["v13", ""]>, DwarfRegAlias<B13>;
355 def Q14 : ARM64Reg<14, "q14", [D14], ["v14", ""]>, DwarfRegAlias<B14>;
356 def Q15 : ARM64Reg<15, "q15", [D15], ["v15", ""]>, DwarfRegAlias<B15>;
357 def Q16 : ARM64Reg<16, "q16", [D16], ["v16", ""]>, DwarfRegAlias<B16>;
358 def Q17 : ARM64Reg<17, "q17", [D17], ["v17", ""]>, DwarfRegAlias<B17>;
359 def Q18 : ARM64Reg<18, "q18", [D18], ["v18", ""]>, DwarfRegAlias<B18>;
360 def Q19 : ARM64Reg<19, "q19", [D19], ["v19", ""]>, DwarfRegAlias<B19>;
361 def Q20 : ARM64Reg<20, "q20", [D20], ["v20", ""]>, DwarfRegAlias<B20>;
362 def Q21 : ARM64Reg<21, "q21", [D21], ["v21", ""]>, DwarfRegAlias<B21>;
363 def Q22 : ARM64Reg<22, "q22", [D22], ["v22", ""]>, DwarfRegAlias<B22>;
364 def Q23 : ARM64Reg<23, "q23", [D23], ["v23", ""]>, DwarfRegAlias<B23>;
365 def Q24 : ARM64Reg<24, "q24", [D24], ["v24", ""]>, DwarfRegAlias<B24>;
366 def Q25 : ARM64Reg<25, "q25", [D25], ["v25", ""]>, DwarfRegAlias<B25>;
367 def Q26 : ARM64Reg<26, "q26", [D26], ["v26", ""]>, DwarfRegAlias<B26>;
368 def Q27 : ARM64Reg<27, "q27", [D27], ["v27", ""]>, DwarfRegAlias<B27>;
369 def Q28 : ARM64Reg<28, "q28", [D28], ["v28", ""]>, DwarfRegAlias<B28>;
370 def Q29 : ARM64Reg<29, "q29", [D29], ["v29", ""]>, DwarfRegAlias<B29>;
371 def Q30 : ARM64Reg<30, "q30", [D30], ["v30", ""]>, DwarfRegAlias<B30>;
372 def Q31 : ARM64Reg<31, "q31", [D31], ["v31", ""]>, DwarfRegAlias<B31>;
375 def FPR8 : RegisterClass<"ARM64", [untyped], 8, (sequence "B%u", 0, 31)> {
378 def FPR16 : RegisterClass<"ARM64", [f16], 16, (sequence "H%u", 0, 31)> {
381 def FPR32 : RegisterClass<"ARM64", [f32, i32], 32,(sequence "S%u", 0, 31)>;
382 def FPR64 : RegisterClass<"ARM64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
384 64, (sequence "D%u", 0, 31)>;
385 // We don't (yet) have an f128 legal type, so don't use that here. We
386 // normalize 128-bit vectors to v2f64 for arg passing and such, so use
388 def FPR128 : RegisterClass<"ARM64",
389 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64, f128],
390 128, (sequence "Q%u", 0, 31)>;
392 // The lower 16 vector registers. Some instructions can only take registers
394 def FPR128_lo : RegisterClass<"ARM64",
395 [v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
396 128, (trunc FPR128, 16)>;
398 // Pairs, triples, and quads of 64-bit vector registers.
399 def DSeqPairs : RegisterTuples<[dsub0, dsub1], [(rotl FPR64, 0), (rotl FPR64, 1)]>;
400 def DSeqTriples : RegisterTuples<[dsub0, dsub1, dsub2],
401 [(rotl FPR64, 0), (rotl FPR64, 1),
403 def DSeqQuads : RegisterTuples<[dsub0, dsub1, dsub2, dsub3],
404 [(rotl FPR64, 0), (rotl FPR64, 1),
405 (rotl FPR64, 2), (rotl FPR64, 3)]>;
406 def DD : RegisterClass<"ARM64", [untyped], 64, (add DSeqPairs)> {
409 def DDD : RegisterClass<"ARM64", [untyped], 64, (add DSeqTriples)> {
412 def DDDD : RegisterClass<"ARM64", [untyped], 64, (add DSeqQuads)> {
416 // Pairs, triples, and quads of 128-bit vector registers.
417 def QSeqPairs : RegisterTuples<[qsub0, qsub1], [(rotl FPR128, 0), (rotl FPR128, 1)]>;
418 def QSeqTriples : RegisterTuples<[qsub0, qsub1, qsub2],
419 [(rotl FPR128, 0), (rotl FPR128, 1),
421 def QSeqQuads : RegisterTuples<[qsub0, qsub1, qsub2, qsub3],
422 [(rotl FPR128, 0), (rotl FPR128, 1),
423 (rotl FPR128, 2), (rotl FPR128, 3)]>;
424 def QQ : RegisterClass<"ARM64", [untyped], 128, (add QSeqPairs)> {
427 def QQQ : RegisterClass<"ARM64", [untyped], 128, (add QSeqTriples)> {
430 def QQQQ : RegisterClass<"ARM64", [untyped], 128, (add QSeqQuads)> {
435 // Vector operand versions of the FP registers. Alternate name printing and
436 // assmebler matching.
437 def VectorRegAsmOperand : AsmOperandClass { let Name = "VectorReg"; }
438 let ParserMatchClass = VectorRegAsmOperand in {
439 def V64 : RegisterOperand<FPR64, "printVRegOperand">;
440 def V128 : RegisterOperand<FPR128, "printVRegOperand">;
443 def VectorRegLoAsmOperand : AsmOperandClass { let Name = "VectorRegLo"; }
444 def V128_lo : RegisterOperand<FPR128_lo, "printVRegOperand"> {
445 let ParserMatchClass = VectorRegLoAsmOperand;
448 class TypedVecListAsmOperand<int count, int regsize, int lanes, string kind>
450 let Name = "TypedVectorList" # count # "_" # lanes # kind;
453 = "isTypedVectorList<" # count # ", " # lanes # ", '" # kind # "'>";
454 let RenderMethod = "addVectorList" # regsize # "Operands<" # count # ">";
457 class TypedVecListRegOperand<RegisterClass Reg, int lanes, string kind>
458 : RegisterOperand<Reg, "printTypedVectorList<" # lanes # ", '"
461 multiclass VectorList<int count, RegisterClass Reg64, RegisterClass Reg128> {
462 // With implicit types (probably on instruction instead). E.g. { v0, v1 }
463 def _64AsmOperand : AsmOperandClass {
464 let Name = NAME # "64";
465 let PredicateMethod = "isImplicitlyTypedVectorList<" # count # ">";
466 let RenderMethod = "addVectorList64Operands<" # count # ">";
469 def "64" : RegisterOperand<Reg64, "printImplicitlyTypedVectorList"> {
470 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_64AsmOperand");
473 def _128AsmOperand : AsmOperandClass {
474 let Name = NAME # "128";
475 let PredicateMethod = "isImplicitlyTypedVectorList<" # count # ">";
476 let RenderMethod = "addVectorList128Operands<" # count # ">";
479 def "128" : RegisterOperand<Reg128, "printImplicitlyTypedVectorList"> {
480 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_128AsmOperand");
483 // 64-bit register lists with explicit type.
486 def _8bAsmOperand : TypedVecListAsmOperand<count, 64, 8, "b">;
487 def "8b" : TypedVecListRegOperand<Reg64, 8, "b"> {
488 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_8bAsmOperand");
492 def _4hAsmOperand : TypedVecListAsmOperand<count, 64, 4, "h">;
493 def "4h" : TypedVecListRegOperand<Reg64, 4, "h"> {
494 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_4hAsmOperand");
498 def _2sAsmOperand : TypedVecListAsmOperand<count, 64, 2, "s">;
499 def "2s" : TypedVecListRegOperand<Reg64, 2, "s"> {
500 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_2sAsmOperand");
504 def _1dAsmOperand : TypedVecListAsmOperand<count, 64, 1, "d">;
505 def "1d" : TypedVecListRegOperand<Reg64, 1, "d"> {
506 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_1dAsmOperand");
509 // 128-bit register lists with explicit type
511 // { v0.16b, v1.16b }
512 def _16bAsmOperand : TypedVecListAsmOperand<count, 128, 16, "b">;
513 def "16b" : TypedVecListRegOperand<Reg128, 16, "b"> {
514 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_16bAsmOperand");
518 def _8hAsmOperand : TypedVecListAsmOperand<count, 128, 8, "h">;
519 def "8h" : TypedVecListRegOperand<Reg128, 8, "h"> {
520 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_8hAsmOperand");
524 def _4sAsmOperand : TypedVecListAsmOperand<count, 128, 4, "s">;
525 def "4s" : TypedVecListRegOperand<Reg128, 4, "s"> {
526 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_4sAsmOperand");
530 def _2dAsmOperand : TypedVecListAsmOperand<count, 128, 2, "d">;
531 def "2d" : TypedVecListRegOperand<Reg128, 2, "d"> {
532 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_2dAsmOperand");
536 def _bAsmOperand : TypedVecListAsmOperand<count, 128, 0, "b">;
537 def "b" : TypedVecListRegOperand<Reg128, 0, "b"> {
538 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_bAsmOperand");
542 def _hAsmOperand : TypedVecListAsmOperand<count, 128, 0, "h">;
543 def "h" : TypedVecListRegOperand<Reg128, 0, "h"> {
544 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_hAsmOperand");
548 def _sAsmOperand : TypedVecListAsmOperand<count, 128, 0, "s">;
549 def "s" : TypedVecListRegOperand<Reg128, 0, "s"> {
550 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_sAsmOperand");
554 def _dAsmOperand : TypedVecListAsmOperand<count, 128, 0, "d">;
555 def "d" : TypedVecListRegOperand<Reg128, 0, "d"> {
556 let ParserMatchClass = !cast<AsmOperandClass>(NAME # "_dAsmOperand");
562 defm VecListOne : VectorList<1, FPR64, FPR128>;
563 defm VecListTwo : VectorList<2, DD, QQ>;
564 defm VecListThree : VectorList<3, DDD, QQQ>;
565 defm VecListFour : VectorList<4, DDDD, QQQQ>;
568 // Register operand versions of the scalar FP registers.
569 def FPR16Op : RegisterOperand<FPR16, "printOperand">;
570 def FPR32Op : RegisterOperand<FPR32, "printOperand">;
571 def FPR64Op : RegisterOperand<FPR64, "printOperand">;
572 def FPR128Op : RegisterOperand<FPR128, "printOperand">;