1 //=- ARM64SchedA53.td - ARM Cortex-A53 Scheduling Definitions -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the itinerary class data for the ARM Cortex A53 processors.
12 //===----------------------------------------------------------------------===//
14 // ===---------------------------------------------------------------------===//
15 // The following definitions describe the simpler per-operand machine model.
16 // This works with MachineScheduler. See MCSchedModel.h for details.
18 // Cortex-A53 machine model for scheduling and other instruction cost heuristics.
19 def CortexA53Model : SchedMachineModel {
20 let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
21 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
22 let MinLatency = 1 ; // OperandCycles are interpreted as MinLatency.
23 let LoadLatency = 2; // Optimistic load latency assuming bypass.
24 // This is overriden by OperandCycles if the
25 // Itineraries are queried instead.
26 let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
27 // Specification - Instruction Timings"
32 //===----------------------------------------------------------------------===//
33 // Define each kind of processor resource and number available.
35 // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
36 // Cortex-A53 is in-order.
38 def A53UnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
39 def A53UnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
40 def A53UnitDiv : ProcResource<1> { let BufferSize = 0; } // Int Division
41 def A53UnitLdSt : ProcResource<1> { let BufferSize = 0; } // Load/Store
42 def A53UnitB : ProcResource<1> { let BufferSize = 0; } // Branch
43 def A53UnitFPALU : ProcResource<1> { let BufferSize = 0; } // FP ALU
44 def A53UnitFPMDS : ProcResource<1> { let BufferSize = 0; } // FP Mult/Div/Sqrt
47 //===----------------------------------------------------------------------===//
48 // Subtarget-specific SchedWrite types which both map the ProcResources and
51 let SchedModel = CortexA53Model in {
53 // ALU - These are reduced to 1 despite a true latency of 4 in order to easily
54 // model forwarding logic. Once forwarding is properly modelled, then
55 // they'll be corrected.
56 def : WriteRes<WriteImm, [A53UnitALU]> { let Latency = 1; }
57 def : WriteRes<WriteI, [A53UnitALU]> { let Latency = 1; }
58 def : WriteRes<WriteISReg, [A53UnitALU]> { let Latency = 1; }
59 def : WriteRes<WriteIEReg, [A53UnitALU]> { let Latency = 1; }
60 def : WriteRes<WriteExtr, [A53UnitALU]> { let Latency = 1; }
61 def : WriteRes<WriteIS, [A53UnitALU]> { let Latency = 1; }
62 def : WriteRes<WriteAdr, [A53UnitALU]> { let Latency = 1; }
65 def : WriteRes<WriteIM32, [A53UnitMAC]> { let Latency = 4; }
66 def : WriteRes<WriteIM64, [A53UnitMAC]> { let Latency = 4; }
69 def : WriteRes<WriteID32, [A53UnitDiv]> { let Latency = 4; }
70 def : WriteRes<WriteID64, [A53UnitDiv]> { let Latency = 4; }
73 def : WriteRes<WriteLD, [A53UnitLdSt]> { let Latency = 4; }
74 def : WriteRes<WriteLDIdx, [A53UnitLdSt]> { let Latency = 4; }
75 def : WriteRes<WriteLDHi, [A53UnitLdSt]> { let Latency = 4; }
76 def : WriteRes<WriteVLD, [A53UnitLdSt]> { let Latency = 4; }
79 def : WriteRes<WriteST, [A53UnitLdSt]> { let Latency = 4; }
80 def : WriteRes<WriteSTP, [A53UnitLdSt]> { let Latency = 4; }
81 def : WriteRes<WriteSTIdx, [A53UnitLdSt]> { let Latency = 4; }
82 def : WriteRes<WriteSTX, [A53UnitLdSt]> { let Latency = 4; }
83 def : WriteRes<WriteVST, [A53UnitLdSt]> { let Latency = 4; }
86 def : WriteRes<WriteBr, [A53UnitB]>;
87 def : WriteRes<WriteBrReg, [A53UnitB]>;
88 def : WriteRes<WriteSys, [A53UnitB]>;
89 def : WriteRes<WriteBarrier, [A53UnitB]>;
90 def : WriteRes<WriteHint, [A53UnitB]>;
93 def : WriteRes<WriteF, [A53UnitFPALU]> { let Latency = 6; }
94 def : WriteRes<WriteFCmp, [A53UnitFPALU]> { let Latency = 6; }
95 def : WriteRes<WriteFCvt, [A53UnitFPALU]> { let Latency = 6; }
96 def : WriteRes<WriteFCopy, [A53UnitFPALU]> { let Latency = 6; }
97 def : WriteRes<WriteFImm, [A53UnitFPALU]> { let Latency = 6; }
98 def : WriteRes<WriteV, [A53UnitFPALU]> { let Latency = 6; }
101 def : WriteRes<WriteFMul, [A53UnitFPMDS]> { let Latency = 6; }
102 def : WriteRes<WriteFDiv, [A53UnitFPMDS]> { let Latency = 33;
103 let ResourceCycles = [29]; }
104 def A53WriteFDiv : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 33;
105 let ResourceCycles = [29]; }
106 def A53WriteFSqrt : SchedWriteRes<[A53UnitFPMDS]> { let Latency = 32;
107 let ResourceCycles = [28]; }
109 //===----------------------------------------------------------------------===//
110 // Subtarget-specific SchedRead types.
112 // While there is no forwarding information defined for these SchedRead types,
113 // they are still used by some instruction via a SchedRW list and so these zero
114 // SchedReadAdvances are required.
116 def : ReadAdvance<ReadExtrHi, 0>;
117 def : ReadAdvance<ReadAdrBase, 0>;
118 def : ReadAdvance<ReadVLD, 0>;
120 //===----------------------------------------------------------------------===//
121 // Subtarget-specific InstRWs.
123 def : InstRW<[WriteI], (instrs COPY)>;
124 def : InstRW<[WriteLD], (instregex "LD[1-4]")>;
125 def : InstRW<[WriteST], (instregex "ST[1-4]")>;
126 def : InstRW<[A53WriteFDiv], (instregex "^FDIV")>;
127 def : InstRW<[A53WriteFSqrt], (instregex ".*SQRT.*")>;