1 //===-- ARMSchedule.td - ARM Scheduling Definitions --------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // Define TII for use in SchedVariant Predicates.
11 // const MachineInstr *MI and const TargetSchedModel *SchedModel
12 // are defined by default.
13 def : PredicateProlog<[{
14 const ARM64InstrInfo *TII =
15 static_cast<const ARM64InstrInfo*>(SchedModel->getInstrInfo());
19 // ARM64 Scheduler Definitions
21 def WriteImm : SchedWrite; // MOVN, MOVZ
22 // TODO: Provide variants for MOV32/64imm Pseudos that dynamically
23 // select the correct sequence of WriteImms.
25 def WriteI : SchedWrite; // ALU
26 def WriteISReg : SchedWrite; // ALU of Shifted-Reg
27 def WriteIEReg : SchedWrite; // ALU of Extended-Reg
28 def WriteExtr : SchedWrite; // EXTR shifts a reg pair
29 def ReadExtrHi : SchedRead; // Read the high reg of the EXTR pair
30 def WriteIS : SchedWrite; // Shift/Scale
31 def WriteID32 : SchedWrite; // 32-bit Divide
32 def WriteID64 : SchedWrite; // 64-bit Divide
33 def WriteIM32 : SchedWrite; // 32-bit Multiply
34 def WriteIM64 : SchedWrite; // 64-bit Multiply
35 def WriteBr : SchedWrite; // Branch
36 def WriteBrReg : SchedWrite; // Indirect Branch
38 def WriteLD : SchedWrite; // Load from base addr plus immediate offset
39 def WriteST : SchedWrite; // Store to base addr plus immediate offset
40 def WriteSTP : SchedWrite; // Store a register pair.
41 def WriteAdr : SchedWrite; // Address pre/post increment.
43 def WriteLDIdx : SchedWrite; // Load from a register index (maybe scaled).
44 def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled).
45 def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST.
47 // ScaledIdxPred is true if a WriteLDIdx operand will be
48 // scaled. Subtargets can use this to dynamically select resources and
49 // latency for WriteLDIdx and ReadAdrBase.
50 def ScaledIdxPred : SchedPredicate<[{TII->isScaledAddr(MI)}]>;
52 // Serialized two-level address load.
54 def WriteLDAdr : WriteSequence<[WriteAdr, WriteLD]>;
56 // Serialized two-level address lookup.
57 // EXAMPLE: MOVaddr...
58 def WriteAdrAdr : WriteSequence<[WriteAdr, WriteAdr]>;
60 // The second register of a load-pair.
61 // LDP,LDPSW,LDNP,LDXP,LDAXP
62 def WriteLDHi : SchedWrite;
64 // Store-exclusive is a store followed by a dependent load.
65 def WriteSTX : WriteSequence<[WriteST, WriteLD]>;
67 def WriteSys : SchedWrite; // Long, variable latency system ops.
68 def WriteBarrier : SchedWrite; // Memory barrier.
69 def WriteHint : SchedWrite; // Hint instruction.
71 def WriteF : SchedWrite; // General floating-point ops.
72 def WriteFCmp : SchedWrite; // Floating-point compare.
73 def WriteFCvt : SchedWrite; // Float conversion.
74 def WriteFCopy : SchedWrite; // Float-int register copy.
75 def WriteFImm : SchedWrite; // Floating-point immediate.
76 def WriteFMul : SchedWrite; // Floating-point multiply.
77 def WriteFDiv : SchedWrite; // Floating-point division.
79 def WriteV : SchedWrite; // Vector ops.
80 def WriteVLD : SchedWrite; // Vector loads.
81 def WriteVST : SchedWrite; // Vector stores.
83 // Read the unwritten lanes of the VLD's destination registers.
84 def ReadVLD : SchedRead;
86 // Sequential vector load and shuffle.
87 def WriteVLDShuffle : WriteSequence<[WriteVLD, WriteV]>;
88 def WriteVLDPairShuffle : WriteSequence<[WriteVLD, WriteV, WriteV]>;
90 // Store a shuffled vector.
91 def WriteVSTShuffle : WriteSequence<[WriteV, WriteVST]>;
92 def WriteVSTPairShuffle : WriteSequence<[WriteV, WriteV, WriteVST]>;