1 //===-- ARM64Subtarget.cpp - ARM64 Subtarget Information --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the ARM64 specific subclass of TargetSubtarget.
12 //===----------------------------------------------------------------------===//
14 #include "ARM64InstrInfo.h"
15 #include "ARM64Subtarget.h"
16 #include "llvm/ADT/SmallVector.h"
17 #include "llvm/CodeGen/MachineScheduler.h"
18 #include "llvm/IR/GlobalValue.h"
19 #include "llvm/Support/TargetRegistry.h"
21 #define GET_SUBTARGETINFO_CTOR
22 #define GET_SUBTARGETINFO_TARGET_DESC
23 #include "ARM64GenSubtargetInfo.inc"
27 ARM64Subtarget::ARM64Subtarget(const std::string &TT, const std::string &CPU,
28 const std::string &FS)
29 : ARM64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others),
30 HasFPARMv8(false), HasNEON(false), HasCrypto(false),
31 HasZeroCycleRegMove(false), HasZeroCycleZeroing(false),
32 CPUString(CPU), TargetTriple(TT) {
33 // Determine default and user-specified characteristics
35 if (CPUString.empty())
36 CPUString = "generic";
38 ParseSubtargetFeatures(CPUString, FS);
41 /// ClassifyGlobalReference - Find the target operand flags that describe
42 /// how a global value should be referenced for the current subtarget.
44 ARM64Subtarget::ClassifyGlobalReference(const GlobalValue *GV,
45 const TargetMachine &TM) const {
47 // Determine whether this is a reference to a definition or a declaration.
48 // Materializable GVs (in JIT lazy compilation mode) do not require an extra
50 bool isDecl = GV->hasAvailableExternallyLinkage();
51 if (GV->isDeclaration() && !GV->isMaterializable())
54 // MachO large model always goes via a GOT, simply to get a single 8-byte
55 // absolute relocation on all global addresses.
56 if (TM.getCodeModel() == CodeModel::Large && isTargetMachO())
57 return ARM64II::MO_GOT;
59 // The small code mode's direct accesses use ADRP, which cannot necessarily
60 // produce the value 0 (if the code is above 4GB). Therefore they must use the
62 if (TM.getCodeModel() == CodeModel::Small && GV->isWeakForLinker() && isDecl)
63 return ARM64II::MO_GOT;
65 // If symbol visibility is hidden, the extra load is not needed if
66 // the symbol is definitely defined in the current translation unit.
68 // The handling of non-hidden symbols in PIC mode is rather target-dependent:
69 // + On MachO, if the symbol is defined in this module the GOT can be
71 // + On ELF, the R_AARCH64_COPY relocation means that even symbols actually
72 // defined could end up in unexpected places. Use a GOT.
73 if (TM.getRelocationModel() != Reloc::Static && GV->hasDefaultVisibility()) {
75 return (isDecl || GV->isWeakForLinker()) ? ARM64II::MO_GOT
76 : ARM64II::MO_NO_FLAG;
78 return ARM64II::MO_GOT;
81 return ARM64II::MO_NO_FLAG;
84 /// This function returns the name of a function which has an interface
85 /// like the non-standard bzero function, if such a function exists on
86 /// the current subtarget and it is considered prefereable over
87 /// memset with zero passed as the second argument. Otherwise it
89 const char *ARM64Subtarget::getBZeroEntry() const {
90 // At the moment, always prefer bzero.
94 void ARM64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
95 MachineInstr *begin, MachineInstr *end,
96 unsigned NumRegionInstrs) const {
97 // LNT run (at least on Cyclone) showed reasonably significant gains for
98 // bi-directional scheduling. 253.perlbmk.
99 Policy.OnlyTopDown = false;
100 Policy.OnlyBottomUp = false;