1 //===-- ARM64TargetMachine.h - Define TargetMachine for ARM64 ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file declares the ARM64 specific subclass of TargetMachine.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARM64TARGETMACHINE_H
15 #define ARM64TARGETMACHINE_H
17 #include "ARM64InstrInfo.h"
18 #include "ARM64ISelLowering.h"
19 #include "ARM64Subtarget.h"
20 #include "ARM64FrameLowering.h"
21 #include "ARM64SelectionDAGInfo.h"
22 #include "llvm/IR/DataLayout.h"
23 #include "llvm/Target/TargetMachine.h"
24 #include "llvm/MC/MCStreamer.h"
28 class ARM64TargetMachine : public LLVMTargetMachine {
30 ARM64Subtarget Subtarget;
34 ARM64InstrInfo InstrInfo;
35 ARM64TargetLowering TLInfo;
36 ARM64FrameLowering FrameLowering;
37 ARM64SelectionDAGInfo TSInfo;
40 ARM64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS,
41 const TargetOptions &Options, Reloc::Model RM,
42 CodeModel::Model CM, CodeGenOpt::Level OL,
45 const ARM64Subtarget *getSubtargetImpl() const override { return &Subtarget; }
46 const ARM64TargetLowering *getTargetLowering() const override {
49 const DataLayout *getDataLayout() const override { return &DL; }
50 const ARM64FrameLowering *getFrameLowering() const override {
51 return &FrameLowering;
53 const ARM64InstrInfo *getInstrInfo() const override { return &InstrInfo; }
54 const ARM64RegisterInfo *getRegisterInfo() const override {
55 return &InstrInfo.getRegisterInfo();
57 const ARM64SelectionDAGInfo *getSelectionDAGInfo() const override {
61 // Pass Pipeline Configuration
62 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
64 /// \brief Register ARM64 analysis passes with a pass manager.
65 void addAnalysisPasses(PassManagerBase &PM) override;
68 // ARM64leTargetMachine - ARM64 little endian target machine.
70 class ARM64leTargetMachine : public ARM64TargetMachine {
71 virtual void anchor();
73 ARM64leTargetMachine(const Target &T, StringRef TT,
74 StringRef CPU, StringRef FS, const TargetOptions &Options,
75 Reloc::Model RM, CodeModel::Model CM,
76 CodeGenOpt::Level OL);
79 // ARM64beTargetMachine - ARM64 big endian target machine.
81 class ARM64beTargetMachine : public ARM64TargetMachine {
82 virtual void anchor();
84 ARM64beTargetMachine(const Target &T, StringRef TT,
85 StringRef CPU, StringRef FS, const TargetOptions &Options,
86 Reloc::Model RM, CodeModel::Model CM,
87 CodeGenOpt::Level OL);
90 } // end namespace llvm