1 //===-- ARM64InstPrinter.cpp - Convert ARM64 MCInst to assembly syntax ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM64 MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "asm-printer"
15 #include "ARM64InstPrinter.h"
16 #include "MCTargetDesc/ARM64AddressingModes.h"
17 #include "MCTargetDesc/ARM64BaseInfo.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Format.h"
23 #include "llvm/Support/raw_ostream.h"
26 #define GET_INSTRUCTION_NAME
27 #define PRINT_ALIAS_INSTR
28 #include "ARM64GenAsmWriter.inc"
29 #define GET_INSTRUCTION_NAME
30 #define PRINT_ALIAS_INSTR
31 #include "ARM64GenAsmWriter1.inc"
33 ARM64InstPrinter::ARM64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
34 const MCRegisterInfo &MRI,
35 const MCSubtargetInfo &STI)
36 : MCInstPrinter(MAI, MII, MRI) {
37 // Initialize the set of available features.
38 setAvailableFeatures(STI.getFeatureBits());
41 ARM64AppleInstPrinter::ARM64AppleInstPrinter(const MCAsmInfo &MAI,
42 const MCInstrInfo &MII,
43 const MCRegisterInfo &MRI,
44 const MCSubtargetInfo &STI)
45 : ARM64InstPrinter(MAI, MII, MRI, STI) {}
47 void ARM64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
48 // This is for .cfi directives.
49 OS << getRegisterName(RegNo);
52 void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
54 // Check for special encodings and print the cannonical alias instead.
56 unsigned Opcode = MI->getOpcode();
58 if (Opcode == ARM64::SYS || Opcode == ARM64::SYSxt)
59 if (printSysAlias(MI, O)) {
60 printAnnotation(O, Annot);
64 // TBZ/TBNZ should print the register operand as a Wreg if the bit
66 if ((Opcode == ARM64::TBNZ || Opcode == ARM64::TBZ) &&
67 MI->getOperand(1).getImm() < 32) {
69 unsigned Reg = MI->getOperand(0).getReg();
70 newMI.getOperand(0).setReg(getWRegFromXReg(Reg));
71 printInstruction(&newMI, O);
72 printAnnotation(O, Annot);
76 // SBFM/UBFM should print to a nicer aliased form if possible.
77 if (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri ||
78 Opcode == ARM64::UBFMXri || Opcode == ARM64::UBFMWri) {
79 const MCOperand &Op0 = MI->getOperand(0);
80 const MCOperand &Op1 = MI->getOperand(1);
81 const MCOperand &Op2 = MI->getOperand(2);
82 const MCOperand &Op3 = MI->getOperand(3);
84 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
85 bool IsSigned = (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri);
86 const char *AsmMnemonic = 0;
88 switch (Op3.getImm()) {
92 AsmMnemonic = IsSigned ? "sxtb" : "uxtb";
95 AsmMnemonic = IsSigned ? "sxth" : "uxth";
98 AsmMnemonic = IsSigned ? "sxtw" : "uxtw";
103 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
104 << ", " << getRegisterName(Op1.getReg());
105 printAnnotation(O, Annot);
110 // All immediate shifts are aliases, implemented using the Bitfield
111 // instruction. In all cases the immediate shift amount shift must be in
112 // the range 0 to (reg.size -1).
113 if (Op2.isImm() && Op3.isImm()) {
114 const char *AsmMnemonic = 0;
116 int64_t immr = Op2.getImm();
117 int64_t imms = Op3.getImm();
118 if (Opcode == ARM64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
121 } else if (Opcode == ARM64::UBFMXri && imms != 0x3f &&
122 ((imms + 1 == immr))) {
125 } else if (Opcode == ARM64::UBFMWri && imms == 0x1f) {
128 } else if (Opcode == ARM64::UBFMXri && imms == 0x3f) {
131 } else if (Opcode == ARM64::SBFMWri && imms == 0x1f) {
134 } else if (Opcode == ARM64::SBFMXri && imms == 0x3f) {
139 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
140 << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
141 printAnnotation(O, Annot);
147 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
148 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
150 if ((Opcode == ARM64::MOVZXi || Opcode == ARM64::MOVZWi ||
151 Opcode == ARM64::MOVNXi || Opcode == ARM64::MOVNWi) &&
152 MI->getOperand(1).isExpr()) {
153 if (Opcode == ARM64::MOVZXi || Opcode == ARM64::MOVZWi)
158 O << getRegisterName(MI->getOperand(0).getReg()) << ", #"
159 << *MI->getOperand(1).getExpr();
163 if ((Opcode == ARM64::MOVKXi || Opcode == ARM64::MOVKWi) &&
164 MI->getOperand(2).isExpr()) {
165 O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
166 << *MI->getOperand(2).getExpr();
170 // ANDS WZR, Wn, #imm ==> TST Wn, #imm
171 // ANDS XZR, Xn, #imm ==> TST Xn, #imm
172 if (Opcode == ARM64::ANDSWri && MI->getOperand(0).getReg() == ARM64::WZR) {
173 O << "\ttst\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
174 printLogicalImm32(MI, 2, O);
177 if (Opcode == ARM64::ANDSXri && MI->getOperand(0).getReg() == ARM64::XZR) {
178 O << "\ttst\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
179 printLogicalImm64(MI, 2, O);
182 // ANDS WZR, Wn, Wm{, lshift #imm} ==> TST Wn{, lshift #imm}
183 // ANDS XZR, Xn, Xm{, lshift #imm} ==> TST Xn{, lshift #imm}
184 if ((Opcode == ARM64::ANDSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
185 (Opcode == ARM64::ANDSXrs && MI->getOperand(0).getReg() == ARM64::XZR)) {
186 O << "\ttst\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
187 printShiftedRegister(MI, 2, O);
191 // SUBS WZR, Wn, #imm ==> CMP Wn, #imm
192 // SUBS XZR, Xn, #imm ==> CMP Xn, #imm
193 if ((Opcode == ARM64::SUBSWri && MI->getOperand(0).getReg() == ARM64::WZR) ||
194 (Opcode == ARM64::SUBSXri && MI->getOperand(0).getReg() == ARM64::XZR)) {
195 O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
196 printAddSubImm(MI, 2, O);
199 // SUBS WZR, Wn, Wm{, lshift #imm} ==> CMP Wn, Wm{, lshift #imm}
200 // SUBS XZR, Xn, Xm{, lshift #imm} ==> CMP Xn, Xm{, lshift #imm}
201 if ((Opcode == ARM64::SUBSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
202 (Opcode == ARM64::SUBSXrs && MI->getOperand(0).getReg() == ARM64::XZR)) {
203 O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
204 printShiftedRegister(MI, 2, O);
207 // SUBS XZR, Xn, Wm, uxtb #imm ==> CMP Xn, uxtb #imm
208 // SUBS WZR, Wn, Xm, uxtb #imm ==> CMP Wn, uxtb #imm
209 if ((Opcode == ARM64::SUBSXrx && MI->getOperand(0).getReg() == ARM64::XZR) ||
210 (Opcode == ARM64::SUBSWrx && MI->getOperand(0).getReg() == ARM64::WZR)) {
211 O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
212 printExtendedRegister(MI, 2, O);
215 // SUBS XZR, Xn, Xm, uxtx #imm ==> CMP Xn, uxtb #imm
216 if (Opcode == ARM64::SUBSXrx64 && MI->getOperand(0).getReg() == ARM64::XZR) {
217 O << "\tcmp\t" << getRegisterName(MI->getOperand(1).getReg()) << ", "
218 << getRegisterName(MI->getOperand(2).getReg());
219 printExtend(MI, 3, O);
223 // ADDS WZR, Wn, #imm ==> CMN Wn, #imm
224 // ADDS XZR, Xn, #imm ==> CMN Xn, #imm
225 if ((Opcode == ARM64::ADDSWri && MI->getOperand(0).getReg() == ARM64::WZR) ||
226 (Opcode == ARM64::ADDSXri && MI->getOperand(0).getReg() == ARM64::XZR)) {
227 O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
228 printAddSubImm(MI, 2, O);
231 // ADDS WZR, Wn, Wm{, lshift #imm} ==> CMN Wn, Wm{, lshift #imm}
232 // ADDS XZR, Xn, Xm{, lshift #imm} ==> CMN Xn, Xm{, lshift #imm}
233 if ((Opcode == ARM64::ADDSWrs && MI->getOperand(0).getReg() == ARM64::WZR) ||
234 (Opcode == ARM64::ADDSXrs && MI->getOperand(0).getReg() == ARM64::XZR)) {
235 O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
236 printShiftedRegister(MI, 2, O);
239 // ADDS XZR, Xn, Wm, uxtb #imm ==> CMN Xn, uxtb #imm
240 if (Opcode == ARM64::ADDSXrx && MI->getOperand(0).getReg() == ARM64::XZR) {
241 O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", ";
242 printExtendedRegister(MI, 2, O);
245 // ADDS XZR, Xn, Xm, uxtx #imm ==> CMN Xn, uxtb #imm
246 if (Opcode == ARM64::ADDSXrx64 && MI->getOperand(0).getReg() == ARM64::XZR) {
247 O << "\tcmn\t" << getRegisterName(MI->getOperand(1).getReg()) << ", "
248 << getRegisterName(MI->getOperand(2).getReg());
249 printExtend(MI, 3, O);
253 if (!printAliasInstr(MI, O))
254 printInstruction(MI, O);
256 printAnnotation(O, Annot);
259 static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
262 case ARM64::TBXv8i8One:
263 case ARM64::TBXv8i8Two:
264 case ARM64::TBXv8i8Three:
265 case ARM64::TBXv8i8Four:
269 case ARM64::TBLv8i8One:
270 case ARM64::TBLv8i8Two:
271 case ARM64::TBLv8i8Three:
272 case ARM64::TBLv8i8Four:
276 case ARM64::TBXv16i8One:
277 case ARM64::TBXv16i8Two:
278 case ARM64::TBXv16i8Three:
279 case ARM64::TBXv16i8Four:
283 case ARM64::TBLv16i8One:
284 case ARM64::TBLv16i8Two:
285 case ARM64::TBLv16i8Three:
286 case ARM64::TBLv16i8Four:
295 struct LdStNInstrDesc {
297 const char *Mnemonic;
303 static LdStNInstrDesc LdStNInstInfo[] = {
304 { ARM64::LD1i8, "ld1", ".b", 2, 0 },
305 { ARM64::LD1i16, "ld1", ".h", 2, 0 },
306 { ARM64::LD1i32, "ld1", ".s", 2, 0 },
307 { ARM64::LD1i64, "ld1", ".d", 2, 0 },
308 { ARM64::LD1i8_POST, "ld1", ".b", 2, 1 },
309 { ARM64::LD1i16_POST, "ld1", ".h", 2, 2 },
310 { ARM64::LD1i32_POST, "ld1", ".s", 2, 4 },
311 { ARM64::LD1i64_POST, "ld1", ".d", 2, 8 },
312 { ARM64::LD1Rv16b, "ld1r", ".16b", 0, 0 },
313 { ARM64::LD1Rv8h, "ld1r", ".8h", 0, 0 },
314 { ARM64::LD1Rv4s, "ld1r", ".4s", 0, 0 },
315 { ARM64::LD1Rv2d, "ld1r", ".2d", 0, 0 },
316 { ARM64::LD1Rv8b, "ld1r", ".8b", 0, 0 },
317 { ARM64::LD1Rv4h, "ld1r", ".4h", 0, 0 },
318 { ARM64::LD1Rv2s, "ld1r", ".2s", 0, 0 },
319 { ARM64::LD1Rv1d, "ld1r", ".1d", 0, 0 },
320 { ARM64::LD1Rv16b_POST, "ld1r", ".16b", 0, 1 },
321 { ARM64::LD1Rv8h_POST, "ld1r", ".8h", 0, 2 },
322 { ARM64::LD1Rv4s_POST, "ld1r", ".4s", 0, 4 },
323 { ARM64::LD1Rv2d_POST, "ld1r", ".2d", 0, 8 },
324 { ARM64::LD1Rv8b_POST, "ld1r", ".8b", 0, 1 },
325 { ARM64::LD1Rv4h_POST, "ld1r", ".4h", 0, 2 },
326 { ARM64::LD1Rv2s_POST, "ld1r", ".2s", 0, 4 },
327 { ARM64::LD1Rv1d_POST, "ld1r", ".1d", 0, 8 },
328 { ARM64::LD1Onev16b, "ld1", ".16b", 0, 0 },
329 { ARM64::LD1Onev8h, "ld1", ".8h", 0, 0 },
330 { ARM64::LD1Onev4s, "ld1", ".4s", 0, 0 },
331 { ARM64::LD1Onev2d, "ld1", ".2d", 0, 0 },
332 { ARM64::LD1Onev8b, "ld1", ".8b", 0, 0 },
333 { ARM64::LD1Onev4h, "ld1", ".4h", 0, 0 },
334 { ARM64::LD1Onev2s, "ld1", ".2s", 0, 0 },
335 { ARM64::LD1Onev1d, "ld1", ".1d", 0, 0 },
336 { ARM64::LD1Onev16b_POST, "ld1", ".16b", 0, 16 },
337 { ARM64::LD1Onev8h_POST, "ld1", ".8h", 0, 16 },
338 { ARM64::LD1Onev4s_POST, "ld1", ".4s", 0, 16 },
339 { ARM64::LD1Onev2d_POST, "ld1", ".2d", 0, 16 },
340 { ARM64::LD1Onev8b_POST, "ld1", ".8b", 0, 8 },
341 { ARM64::LD1Onev4h_POST, "ld1", ".4h", 0, 8 },
342 { ARM64::LD1Onev2s_POST, "ld1", ".2s", 0, 8 },
343 { ARM64::LD1Onev1d_POST, "ld1", ".1d", 0, 8 },
344 { ARM64::LD1Twov16b, "ld1", ".16b", 0, 0 },
345 { ARM64::LD1Twov8h, "ld1", ".8h", 0, 0 },
346 { ARM64::LD1Twov4s, "ld1", ".4s", 0, 0 },
347 { ARM64::LD1Twov2d, "ld1", ".2d", 0, 0 },
348 { ARM64::LD1Twov8b, "ld1", ".8b", 0, 0 },
349 { ARM64::LD1Twov4h, "ld1", ".4h", 0, 0 },
350 { ARM64::LD1Twov2s, "ld1", ".2s", 0, 0 },
351 { ARM64::LD1Twov1d, "ld1", ".1d", 0, 0 },
352 { ARM64::LD1Twov16b_POST, "ld1", ".16b", 0, 32 },
353 { ARM64::LD1Twov8h_POST, "ld1", ".8h", 0, 32 },
354 { ARM64::LD1Twov4s_POST, "ld1", ".4s", 0, 32 },
355 { ARM64::LD1Twov2d_POST, "ld1", ".2d", 0, 32 },
356 { ARM64::LD1Twov8b_POST, "ld1", ".8b", 0, 16 },
357 { ARM64::LD1Twov4h_POST, "ld1", ".4h", 0, 16 },
358 { ARM64::LD1Twov2s_POST, "ld1", ".2s", 0, 16 },
359 { ARM64::LD1Twov1d_POST, "ld1", ".1d", 0, 16 },
360 { ARM64::LD1Threev16b, "ld1", ".16b", 0, 0 },
361 { ARM64::LD1Threev8h, "ld1", ".8h", 0, 0 },
362 { ARM64::LD1Threev4s, "ld1", ".4s", 0, 0 },
363 { ARM64::LD1Threev2d, "ld1", ".2d", 0, 0 },
364 { ARM64::LD1Threev8b, "ld1", ".8b", 0, 0 },
365 { ARM64::LD1Threev4h, "ld1", ".4h", 0, 0 },
366 { ARM64::LD1Threev2s, "ld1", ".2s", 0, 0 },
367 { ARM64::LD1Threev1d, "ld1", ".1d", 0, 0 },
368 { ARM64::LD1Threev16b_POST, "ld1", ".16b", 0, 48 },
369 { ARM64::LD1Threev8h_POST, "ld1", ".8h", 0, 48 },
370 { ARM64::LD1Threev4s_POST, "ld1", ".4s", 0, 48 },
371 { ARM64::LD1Threev2d_POST, "ld1", ".2d", 0, 48 },
372 { ARM64::LD1Threev8b_POST, "ld1", ".8b", 0, 24 },
373 { ARM64::LD1Threev4h_POST, "ld1", ".4h", 0, 24 },
374 { ARM64::LD1Threev2s_POST, "ld1", ".2s", 0, 24 },
375 { ARM64::LD1Threev1d_POST, "ld1", ".1d", 0, 24 },
376 { ARM64::LD1Fourv16b, "ld1", ".16b", 0, 0 },
377 { ARM64::LD1Fourv8h, "ld1", ".8h", 0, 0 },
378 { ARM64::LD1Fourv4s, "ld1", ".4s", 0, 0 },
379 { ARM64::LD1Fourv2d, "ld1", ".2d", 0, 0 },
380 { ARM64::LD1Fourv8b, "ld1", ".8b", 0, 0 },
381 { ARM64::LD1Fourv4h, "ld1", ".4h", 0, 0 },
382 { ARM64::LD1Fourv2s, "ld1", ".2s", 0, 0 },
383 { ARM64::LD1Fourv1d, "ld1", ".1d", 0, 0 },
384 { ARM64::LD1Fourv16b_POST, "ld1", ".16b", 0, 64 },
385 { ARM64::LD1Fourv8h_POST, "ld1", ".8h", 0, 64 },
386 { ARM64::LD1Fourv4s_POST, "ld1", ".4s", 0, 64 },
387 { ARM64::LD1Fourv2d_POST, "ld1", ".2d", 0, 64 },
388 { ARM64::LD1Fourv8b_POST, "ld1", ".8b", 0, 32 },
389 { ARM64::LD1Fourv4h_POST, "ld1", ".4h", 0, 32 },
390 { ARM64::LD1Fourv2s_POST, "ld1", ".2s", 0, 32 },
391 { ARM64::LD1Fourv1d_POST, "ld1", ".1d", 0, 32 },
392 { ARM64::LD2i8, "ld2", ".b", 2, 0 },
393 { ARM64::LD2i16, "ld2", ".h", 2, 0 },
394 { ARM64::LD2i32, "ld2", ".s", 2, 0 },
395 { ARM64::LD2i64, "ld2", ".d", 2, 0 },
396 { ARM64::LD2i8_POST, "ld2", ".b", 2, 2 },
397 { ARM64::LD2i16_POST, "ld2", ".h", 2, 4 },
398 { ARM64::LD2i32_POST, "ld2", ".s", 2, 8 },
399 { ARM64::LD2i64_POST, "ld2", ".d", 2, 16 },
400 { ARM64::LD2Rv16b, "ld2r", ".16b", 0, 0 },
401 { ARM64::LD2Rv8h, "ld2r", ".8h", 0, 0 },
402 { ARM64::LD2Rv4s, "ld2r", ".4s", 0, 0 },
403 { ARM64::LD2Rv2d, "ld2r", ".2d", 0, 0 },
404 { ARM64::LD2Rv8b, "ld2r", ".8b", 0, 0 },
405 { ARM64::LD2Rv4h, "ld2r", ".4h", 0, 0 },
406 { ARM64::LD2Rv2s, "ld2r", ".2s", 0, 0 },
407 { ARM64::LD2Rv1d, "ld2r", ".1d", 0, 0 },
408 { ARM64::LD2Rv16b_POST, "ld2r", ".16b", 0, 2 },
409 { ARM64::LD2Rv8h_POST, "ld2r", ".8h", 0, 4 },
410 { ARM64::LD2Rv4s_POST, "ld2r", ".4s", 0, 8 },
411 { ARM64::LD2Rv2d_POST, "ld2r", ".2d", 0, 16 },
412 { ARM64::LD2Rv8b_POST, "ld2r", ".8b", 0, 2 },
413 { ARM64::LD2Rv4h_POST, "ld2r", ".4h", 0, 4 },
414 { ARM64::LD2Rv2s_POST, "ld2r", ".2s", 0, 8 },
415 { ARM64::LD2Rv1d_POST, "ld2r", ".1d", 0, 16 },
416 { ARM64::LD2Twov16b, "ld2", ".16b", 0, 0 },
417 { ARM64::LD2Twov8h, "ld2", ".8h", 0, 0 },
418 { ARM64::LD2Twov4s, "ld2", ".4s", 0, 0 },
419 { ARM64::LD2Twov2d, "ld2", ".2d", 0, 0 },
420 { ARM64::LD2Twov8b, "ld2", ".8b", 0, 0 },
421 { ARM64::LD2Twov4h, "ld2", ".4h", 0, 0 },
422 { ARM64::LD2Twov2s, "ld2", ".2s", 0, 0 },
423 { ARM64::LD2Twov16b_POST, "ld2", ".16b", 0, 32 },
424 { ARM64::LD2Twov8h_POST, "ld2", ".8h", 0, 32 },
425 { ARM64::LD2Twov4s_POST, "ld2", ".4s", 0, 32 },
426 { ARM64::LD2Twov2d_POST, "ld2", ".2d", 0, 32 },
427 { ARM64::LD2Twov8b_POST, "ld2", ".8b", 0, 16 },
428 { ARM64::LD2Twov4h_POST, "ld2", ".4h", 0, 16 },
429 { ARM64::LD2Twov2s_POST, "ld2", ".2s", 0, 16 },
430 { ARM64::LD3i8, "ld3", ".b", 2, 0 },
431 { ARM64::LD3i16, "ld3", ".h", 2, 0 },
432 { ARM64::LD3i32, "ld3", ".s", 2, 0 },
433 { ARM64::LD3i64, "ld3", ".d", 2, 0 },
434 { ARM64::LD3i8_POST, "ld3", ".b", 2, 3 },
435 { ARM64::LD3i16_POST, "ld3", ".h", 2, 6 },
436 { ARM64::LD3i32_POST, "ld3", ".s", 2, 12 },
437 { ARM64::LD3i64_POST, "ld3", ".d", 2, 24 },
438 { ARM64::LD3Rv16b, "ld3r", ".16b", 0, 0 },
439 { ARM64::LD3Rv8h, "ld3r", ".8h", 0, 0 },
440 { ARM64::LD3Rv4s, "ld3r", ".4s", 0, 0 },
441 { ARM64::LD3Rv2d, "ld3r", ".2d", 0, 0 },
442 { ARM64::LD3Rv8b, "ld3r", ".8b", 0, 0 },
443 { ARM64::LD3Rv4h, "ld3r", ".4h", 0, 0 },
444 { ARM64::LD3Rv2s, "ld3r", ".2s", 0, 0 },
445 { ARM64::LD3Rv1d, "ld3r", ".1d", 0, 0 },
446 { ARM64::LD3Rv16b_POST, "ld3r", ".16b", 0, 3 },
447 { ARM64::LD3Rv8h_POST, "ld3r", ".8h", 0, 6 },
448 { ARM64::LD3Rv4s_POST, "ld3r", ".4s", 0, 12 },
449 { ARM64::LD3Rv2d_POST, "ld3r", ".2d", 0, 24 },
450 { ARM64::LD3Rv8b_POST, "ld3r", ".8b", 0, 3 },
451 { ARM64::LD3Rv4h_POST, "ld3r", ".4h", 0, 6 },
452 { ARM64::LD3Rv2s_POST, "ld3r", ".2s", 0, 12 },
453 { ARM64::LD3Rv1d_POST, "ld3r", ".1d", 0, 24 },
454 { ARM64::LD3Threev16b, "ld3", ".16b", 0, 0 },
455 { ARM64::LD3Threev8h, "ld3", ".8h", 0, 0 },
456 { ARM64::LD3Threev4s, "ld3", ".4s", 0, 0 },
457 { ARM64::LD3Threev2d, "ld3", ".2d", 0, 0 },
458 { ARM64::LD3Threev8b, "ld3", ".8b", 0, 0 },
459 { ARM64::LD3Threev4h, "ld3", ".4h", 0, 0 },
460 { ARM64::LD3Threev2s, "ld3", ".2s", 0, 0 },
461 { ARM64::LD3Threev16b_POST, "ld3", ".16b", 0, 48 },
462 { ARM64::LD3Threev8h_POST, "ld3", ".8h", 0, 48 },
463 { ARM64::LD3Threev4s_POST, "ld3", ".4s", 0, 48 },
464 { ARM64::LD3Threev2d_POST, "ld3", ".2d", 0, 48 },
465 { ARM64::LD3Threev8b_POST, "ld3", ".8b", 0, 24 },
466 { ARM64::LD3Threev4h_POST, "ld3", ".4h", 0, 24 },
467 { ARM64::LD3Threev2s_POST, "ld3", ".2s", 0, 24 },
468 { ARM64::LD4i8, "ld4", ".b", 2, 0 },
469 { ARM64::LD4i16, "ld4", ".h", 2, 0 },
470 { ARM64::LD4i32, "ld4", ".s", 2, 0 },
471 { ARM64::LD4i64, "ld4", ".d", 2, 0 },
472 { ARM64::LD4i8_POST, "ld4", ".b", 2, 4 },
473 { ARM64::LD4i16_POST, "ld4", ".h", 2, 8 },
474 { ARM64::LD4i32_POST, "ld4", ".s", 2, 16 },
475 { ARM64::LD4i64_POST, "ld4", ".d", 2, 32 },
476 { ARM64::LD4Rv16b, "ld4r", ".16b", 0, 0 },
477 { ARM64::LD4Rv8h, "ld4r", ".8h", 0, 0 },
478 { ARM64::LD4Rv4s, "ld4r", ".4s", 0, 0 },
479 { ARM64::LD4Rv2d, "ld4r", ".2d", 0, 0 },
480 { ARM64::LD4Rv8b, "ld4r", ".8b", 0, 0 },
481 { ARM64::LD4Rv4h, "ld4r", ".4h", 0, 0 },
482 { ARM64::LD4Rv2s, "ld4r", ".2s", 0, 0 },
483 { ARM64::LD4Rv1d, "ld4r", ".1d", 0, 0 },
484 { ARM64::LD4Rv16b_POST, "ld4r", ".16b", 0, 4 },
485 { ARM64::LD4Rv8h_POST, "ld4r", ".8h", 0, 8 },
486 { ARM64::LD4Rv4s_POST, "ld4r", ".4s", 0, 16 },
487 { ARM64::LD4Rv2d_POST, "ld4r", ".2d", 0, 32 },
488 { ARM64::LD4Rv8b_POST, "ld4r", ".8b", 0, 4 },
489 { ARM64::LD4Rv4h_POST, "ld4r", ".4h", 0, 8 },
490 { ARM64::LD4Rv2s_POST, "ld4r", ".2s", 0, 16 },
491 { ARM64::LD4Rv1d_POST, "ld4r", ".1d", 0, 32 },
492 { ARM64::LD4Fourv16b, "ld4", ".16b", 0, 0 },
493 { ARM64::LD4Fourv8h, "ld4", ".8h", 0, 0 },
494 { ARM64::LD4Fourv4s, "ld4", ".4s", 0, 0 },
495 { ARM64::LD4Fourv2d, "ld4", ".2d", 0, 0 },
496 { ARM64::LD4Fourv8b, "ld4", ".8b", 0, 0 },
497 { ARM64::LD4Fourv4h, "ld4", ".4h", 0, 0 },
498 { ARM64::LD4Fourv2s, "ld4", ".2s", 0, 0 },
499 { ARM64::LD4Fourv16b_POST, "ld4", ".16b", 0, 64 },
500 { ARM64::LD4Fourv8h_POST, "ld4", ".8h", 0, 64 },
501 { ARM64::LD4Fourv4s_POST, "ld4", ".4s", 0, 64 },
502 { ARM64::LD4Fourv2d_POST, "ld4", ".2d", 0, 64 },
503 { ARM64::LD4Fourv8b_POST, "ld4", ".8b", 0, 32 },
504 { ARM64::LD4Fourv4h_POST, "ld4", ".4h", 0, 32 },
505 { ARM64::LD4Fourv2s_POST, "ld4", ".2s", 0, 32 },
506 { ARM64::ST1i8, "st1", ".b", 1, 0 },
507 { ARM64::ST1i16, "st1", ".h", 1, 0 },
508 { ARM64::ST1i32, "st1", ".s", 1, 0 },
509 { ARM64::ST1i64, "st1", ".d", 1, 0 },
510 { ARM64::ST1i8_POST, "st1", ".b", 1, 1 },
511 { ARM64::ST1i16_POST, "st1", ".h", 1, 2 },
512 { ARM64::ST1i32_POST, "st1", ".s", 1, 4 },
513 { ARM64::ST1i64_POST, "st1", ".d", 1, 8 },
514 { ARM64::ST1Onev16b, "st1", ".16b", 0, 0 },
515 { ARM64::ST1Onev8h, "st1", ".8h", 0, 0 },
516 { ARM64::ST1Onev4s, "st1", ".4s", 0, 0 },
517 { ARM64::ST1Onev2d, "st1", ".2d", 0, 0 },
518 { ARM64::ST1Onev8b, "st1", ".8b", 0, 0 },
519 { ARM64::ST1Onev4h, "st1", ".4h", 0, 0 },
520 { ARM64::ST1Onev2s, "st1", ".2s", 0, 0 },
521 { ARM64::ST1Onev1d, "st1", ".1d", 0, 0 },
522 { ARM64::ST1Onev16b_POST, "st1", ".16b", 0, 16 },
523 { ARM64::ST1Onev8h_POST, "st1", ".8h", 0, 16 },
524 { ARM64::ST1Onev4s_POST, "st1", ".4s", 0, 16 },
525 { ARM64::ST1Onev2d_POST, "st1", ".2d", 0, 16 },
526 { ARM64::ST1Onev8b_POST, "st1", ".8b", 0, 8 },
527 { ARM64::ST1Onev4h_POST, "st1", ".4h", 0, 8 },
528 { ARM64::ST1Onev2s_POST, "st1", ".2s", 0, 8 },
529 { ARM64::ST1Onev1d_POST, "st1", ".1d", 0, 8 },
530 { ARM64::ST1Twov16b, "st1", ".16b", 0, 0 },
531 { ARM64::ST1Twov8h, "st1", ".8h", 0, 0 },
532 { ARM64::ST1Twov4s, "st1", ".4s", 0, 0 },
533 { ARM64::ST1Twov2d, "st1", ".2d", 0, 0 },
534 { ARM64::ST1Twov8b, "st1", ".8b", 0, 0 },
535 { ARM64::ST1Twov4h, "st1", ".4h", 0, 0 },
536 { ARM64::ST1Twov2s, "st1", ".2s", 0, 0 },
537 { ARM64::ST1Twov1d, "st1", ".1d", 0, 0 },
538 { ARM64::ST1Twov16b_POST, "st1", ".16b", 0, 32 },
539 { ARM64::ST1Twov8h_POST, "st1", ".8h", 0, 32 },
540 { ARM64::ST1Twov4s_POST, "st1", ".4s", 0, 32 },
541 { ARM64::ST1Twov2d_POST, "st1", ".2d", 0, 32 },
542 { ARM64::ST1Twov8b_POST, "st1", ".8b", 0, 16 },
543 { ARM64::ST1Twov4h_POST, "st1", ".4h", 0, 16 },
544 { ARM64::ST1Twov2s_POST, "st1", ".2s", 0, 16 },
545 { ARM64::ST1Twov1d_POST, "st1", ".1d", 0, 16 },
546 { ARM64::ST1Threev16b, "st1", ".16b", 0, 0 },
547 { ARM64::ST1Threev8h, "st1", ".8h", 0, 0 },
548 { ARM64::ST1Threev4s, "st1", ".4s", 0, 0 },
549 { ARM64::ST1Threev2d, "st1", ".2d", 0, 0 },
550 { ARM64::ST1Threev8b, "st1", ".8b", 0, 0 },
551 { ARM64::ST1Threev4h, "st1", ".4h", 0, 0 },
552 { ARM64::ST1Threev2s, "st1", ".2s", 0, 0 },
553 { ARM64::ST1Threev1d, "st1", ".1d", 0, 0 },
554 { ARM64::ST1Threev16b_POST, "st1", ".16b", 0, 48 },
555 { ARM64::ST1Threev8h_POST, "st1", ".8h", 0, 48 },
556 { ARM64::ST1Threev4s_POST, "st1", ".4s", 0, 48 },
557 { ARM64::ST1Threev2d_POST, "st1", ".2d", 0, 48 },
558 { ARM64::ST1Threev8b_POST, "st1", ".8b", 0, 24 },
559 { ARM64::ST1Threev4h_POST, "st1", ".4h", 0, 24 },
560 { ARM64::ST1Threev2s_POST, "st1", ".2s", 0, 24 },
561 { ARM64::ST1Threev1d_POST, "st1", ".1d", 0, 24 },
562 { ARM64::ST1Fourv16b, "st1", ".16b", 0, 0 },
563 { ARM64::ST1Fourv8h, "st1", ".8h", 0, 0 },
564 { ARM64::ST1Fourv4s, "st1", ".4s", 0, 0 },
565 { ARM64::ST1Fourv2d, "st1", ".2d", 0, 0 },
566 { ARM64::ST1Fourv8b, "st1", ".8b", 0, 0 },
567 { ARM64::ST1Fourv4h, "st1", ".4h", 0, 0 },
568 { ARM64::ST1Fourv2s, "st1", ".2s", 0, 0 },
569 { ARM64::ST1Fourv1d, "st1", ".1d", 0, 0 },
570 { ARM64::ST1Fourv16b_POST, "st1", ".16b", 0, 64 },
571 { ARM64::ST1Fourv8h_POST, "st1", ".8h", 0, 64 },
572 { ARM64::ST1Fourv4s_POST, "st1", ".4s", 0, 64 },
573 { ARM64::ST1Fourv2d_POST, "st1", ".2d", 0, 64 },
574 { ARM64::ST1Fourv8b_POST, "st1", ".8b", 0, 32 },
575 { ARM64::ST1Fourv4h_POST, "st1", ".4h", 0, 32 },
576 { ARM64::ST1Fourv2s_POST, "st1", ".2s", 0, 32 },
577 { ARM64::ST1Fourv1d_POST, "st1", ".1d", 0, 32 },
578 { ARM64::ST2i8, "st2", ".b", 1, 0 },
579 { ARM64::ST2i16, "st2", ".h", 1, 0 },
580 { ARM64::ST2i32, "st2", ".s", 1, 0 },
581 { ARM64::ST2i64, "st2", ".d", 1, 0 },
582 { ARM64::ST2i8_POST, "st2", ".b", 1, 2 },
583 { ARM64::ST2i16_POST, "st2", ".h", 1, 4 },
584 { ARM64::ST2i32_POST, "st2", ".s", 1, 8 },
585 { ARM64::ST2i64_POST, "st2", ".d", 1, 16 },
586 { ARM64::ST2Twov16b, "st2", ".16b", 0, 0 },
587 { ARM64::ST2Twov8h, "st2", ".8h", 0, 0 },
588 { ARM64::ST2Twov4s, "st2", ".4s", 0, 0 },
589 { ARM64::ST2Twov2d, "st2", ".2d", 0, 0 },
590 { ARM64::ST2Twov8b, "st2", ".8b", 0, 0 },
591 { ARM64::ST2Twov4h, "st2", ".4h", 0, 0 },
592 { ARM64::ST2Twov2s, "st2", ".2s", 0, 0 },
593 { ARM64::ST2Twov16b_POST, "st2", ".16b", 0, 32 },
594 { ARM64::ST2Twov8h_POST, "st2", ".8h", 0, 32 },
595 { ARM64::ST2Twov4s_POST, "st2", ".4s", 0, 32 },
596 { ARM64::ST2Twov2d_POST, "st2", ".2d", 0, 32 },
597 { ARM64::ST2Twov8b_POST, "st2", ".8b", 0, 16 },
598 { ARM64::ST2Twov4h_POST, "st2", ".4h", 0, 16 },
599 { ARM64::ST2Twov2s_POST, "st2", ".2s", 0, 16 },
600 { ARM64::ST3i8, "st3", ".b", 1, 0 },
601 { ARM64::ST3i16, "st3", ".h", 1, 0 },
602 { ARM64::ST3i32, "st3", ".s", 1, 0 },
603 { ARM64::ST3i64, "st3", ".d", 1, 0 },
604 { ARM64::ST3i8_POST, "st3", ".b", 1, 3 },
605 { ARM64::ST3i16_POST, "st3", ".h", 1, 6 },
606 { ARM64::ST3i32_POST, "st3", ".s", 1, 12 },
607 { ARM64::ST3i64_POST, "st3", ".d", 1, 24 },
608 { ARM64::ST3Threev16b, "st3", ".16b", 0, 0 },
609 { ARM64::ST3Threev8h, "st3", ".8h", 0, 0 },
610 { ARM64::ST3Threev4s, "st3", ".4s", 0, 0 },
611 { ARM64::ST3Threev2d, "st3", ".2d", 0, 0 },
612 { ARM64::ST3Threev8b, "st3", ".8b", 0, 0 },
613 { ARM64::ST3Threev4h, "st3", ".4h", 0, 0 },
614 { ARM64::ST3Threev2s, "st3", ".2s", 0, 0 },
615 { ARM64::ST3Threev16b_POST, "st3", ".16b", 0, 48 },
616 { ARM64::ST3Threev8h_POST, "st3", ".8h", 0, 48 },
617 { ARM64::ST3Threev4s_POST, "st3", ".4s", 0, 48 },
618 { ARM64::ST3Threev2d_POST, "st3", ".2d", 0, 48 },
619 { ARM64::ST3Threev8b_POST, "st3", ".8b", 0, 24 },
620 { ARM64::ST3Threev4h_POST, "st3", ".4h", 0, 24 },
621 { ARM64::ST3Threev2s_POST, "st3", ".2s", 0, 24 },
622 { ARM64::ST4i8, "st4", ".b", 1, 0 },
623 { ARM64::ST4i16, "st4", ".h", 1, 0 },
624 { ARM64::ST4i32, "st4", ".s", 1, 0 },
625 { ARM64::ST4i64, "st4", ".d", 1, 0 },
626 { ARM64::ST4i8_POST, "st4", ".b", 1, 4 },
627 { ARM64::ST4i16_POST, "st4", ".h", 1, 8 },
628 { ARM64::ST4i32_POST, "st4", ".s", 1, 16 },
629 { ARM64::ST4i64_POST, "st4", ".d", 1, 32 },
630 { ARM64::ST4Fourv16b, "st4", ".16b", 0, 0 },
631 { ARM64::ST4Fourv8h, "st4", ".8h", 0, 0 },
632 { ARM64::ST4Fourv4s, "st4", ".4s", 0, 0 },
633 { ARM64::ST4Fourv2d, "st4", ".2d", 0, 0 },
634 { ARM64::ST4Fourv8b, "st4", ".8b", 0, 0 },
635 { ARM64::ST4Fourv4h, "st4", ".4h", 0, 0 },
636 { ARM64::ST4Fourv2s, "st4", ".2s", 0, 0 },
637 { ARM64::ST4Fourv16b_POST, "st4", ".16b", 0, 64 },
638 { ARM64::ST4Fourv8h_POST, "st4", ".8h", 0, 64 },
639 { ARM64::ST4Fourv4s_POST, "st4", ".4s", 0, 64 },
640 { ARM64::ST4Fourv2d_POST, "st4", ".2d", 0, 64 },
641 { ARM64::ST4Fourv8b_POST, "st4", ".8b", 0, 32 },
642 { ARM64::ST4Fourv4h_POST, "st4", ".4h", 0, 32 },
643 { ARM64::ST4Fourv2s_POST, "st4", ".2s", 0, 32 },
646 static LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
648 for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx)
649 if (LdStNInstInfo[Idx].Opcode == Opcode)
650 return &LdStNInstInfo[Idx];
655 void ARM64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
657 unsigned Opcode = MI->getOpcode();
658 StringRef Layout, Mnemonic;
661 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
662 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
663 << getRegisterName(MI->getOperand(0).getReg(), ARM64::vreg) << ", ";
665 unsigned ListOpNum = IsTbx ? 2 : 1;
666 printVectorList(MI, ListOpNum, O, "");
669 << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), ARM64::vreg);
670 printAnnotation(O, Annot);
674 if (LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
675 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
677 // Now onto the operands: first a vector list with possible lane
678 // specifier. E.g. { v0 }[2]
679 printVectorList(MI, 0, O, "");
681 if (LdStDesc->LaneOperand != 0)
682 O << '[' << MI->getOperand(LdStDesc->LaneOperand).getImm() << ']';
684 // Next the address: [xN]
685 unsigned AddrOpNum = LdStDesc->LaneOperand + 1;
686 unsigned AddrReg = MI->getOperand(AddrOpNum).getReg();
687 O << ", [" << getRegisterName(AddrReg) << ']';
689 // Finally, there might be a post-indexed offset.
690 if (LdStDesc->NaturalOffset != 0) {
691 unsigned Reg = MI->getOperand(AddrOpNum + 1).getReg();
692 if (Reg != ARM64::XZR)
693 O << ", " << getRegisterName(Reg);
695 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
696 O << ", #" << LdStDesc->NaturalOffset;
700 printAnnotation(O, Annot);
704 ARM64InstPrinter::printInst(MI, O, Annot);
707 bool ARM64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
709 unsigned Opcode = MI->getOpcode();
710 assert((Opcode == ARM64::SYS || Opcode == ARM64::SYSxt) &&
711 "Invalid opcode for SYS alias!");
715 const MCOperand &Op1 = MI->getOperand(0);
716 const MCOperand &Cn = MI->getOperand(1);
717 const MCOperand &Cm = MI->getOperand(2);
718 const MCOperand &Op2 = MI->getOperand(3);
720 unsigned Op1Val = Op1.getImm();
721 unsigned CnVal = Cn.getImm();
722 unsigned CmVal = Cm.getImm();
723 unsigned Op2Val = Op2.getImm();
732 if (Op1Val == 0 && Op2Val == 0)
736 if (Op1Val == 0 && Op2Val == 0)
738 else if (Op1Val == 3 && Op2Val == 1)
744 if (Op1Val == 3 && Op2Val == 1)
748 if (Op1Val == 0 && Op2Val == 1)
750 if (Op1Val == 0 && Op2Val == 2)
754 if (Op1Val == 3 && Op2Val == 1)
756 else if (Op1Val == 0 && Op2Val == 2)
760 if (Op1Val == 3 && Op2Val == 1)
764 if (Op1Val == 3 && Op2Val == 1)
766 else if (Op1Val == 0 && Op2Val == 2)
779 case 0: Asm = "at\ts1e1r"; break;
780 case 1: Asm = "at\ts1e1w"; break;
781 case 2: Asm = "at\ts1e0r"; break;
782 case 3: Asm = "at\ts1e0w"; break;
789 case 0: Asm = "at\ts1e2r"; break;
790 case 1: Asm = "at\ts1e2w"; break;
791 case 4: Asm = "at\ts12e1r"; break;
792 case 5: Asm = "at\ts12e1w"; break;
793 case 6: Asm = "at\ts12e0r"; break;
794 case 7: Asm = "at\ts12e0w"; break;
801 case 0: Asm = "at\ts1e3r"; break;
802 case 1: Asm = "at\ts1e3w"; break;
808 } else if (CnVal == 8) {
821 case 0: Asm = "tlbi\tvmalle1is"; break;
822 case 1: Asm = "tlbi\tvae1is"; break;
823 case 2: Asm = "tlbi\taside1is"; break;
824 case 3: Asm = "tlbi\tvaae1is"; break;
825 case 5: Asm = "tlbi\tvale1is"; break;
826 case 7: Asm = "tlbi\tvaale1is"; break;
833 case 0: Asm = "tlbi\talle2is"; break;
834 case 1: Asm = "tlbi\tvae2is"; break;
835 case 4: Asm = "tlbi\talle1is"; break;
836 case 5: Asm = "tlbi\tvale2is"; break;
837 case 6: Asm = "tlbi\tvmalls12e1is"; break;
844 case 0: Asm = "tlbi\talle3is"; break;
845 case 1: Asm = "tlbi\tvae3is"; break;
846 case 5: Asm = "tlbi\tvale3is"; break;
859 case 1: Asm = "tlbi\tipas2e1"; break;
860 case 5: Asm = "tlbi\tipas2le1"; break;
873 case 0: Asm = "tlbi\tvmalle1"; break;
874 case 1: Asm = "tlbi\tvae1"; break;
875 case 2: Asm = "tlbi\taside1"; break;
876 case 3: Asm = "tlbi\tvaae1"; break;
877 case 5: Asm = "tlbi\tvale1"; break;
878 case 7: Asm = "tlbi\tvaale1"; break;
885 case 0: Asm = "tlbi\talle2"; break;
886 case 1: Asm = "tlbi\tvae2"; break;
887 case 4: Asm = "tlbi\talle1"; break;
888 case 5: Asm = "tlbi\tvale2"; break;
889 case 6: Asm = "tlbi\tvmalls12e1"; break;
896 case 0: Asm = "tlbi\talle3"; break;
897 case 1: Asm = "tlbi\tvae3"; break;
898 case 5: Asm = "tlbi\tvale3"; break;
908 if (MI->getNumOperands() == 5)
909 O << ", " << getRegisterName(MI->getOperand(4).getReg());
915 void ARM64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
917 const MCOperand &Op = MI->getOperand(OpNo);
919 unsigned Reg = Op.getReg();
920 O << getRegisterName(Reg);
921 } else if (Op.isImm()) {
922 O << '#' << Op.getImm();
924 assert(Op.isExpr() && "unknown operand kind in printOperand");
929 void ARM64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
930 unsigned Imm, raw_ostream &O) {
931 const MCOperand &Op = MI->getOperand(OpNo);
933 unsigned Reg = Op.getReg();
934 if (Reg == ARM64::XZR)
937 O << getRegisterName(Reg);
939 assert("unknown operand kind in printPostIncOperand64");
942 void ARM64InstPrinter::printPostIncOperand1(const MCInst *MI, unsigned OpNo,
944 printPostIncOperand(MI, OpNo, 1, O);
947 void ARM64InstPrinter::printPostIncOperand2(const MCInst *MI, unsigned OpNo,
949 printPostIncOperand(MI, OpNo, 2, O);
952 void ARM64InstPrinter::printPostIncOperand3(const MCInst *MI, unsigned OpNo,
954 printPostIncOperand(MI, OpNo, 3, O);
957 void ARM64InstPrinter::printPostIncOperand4(const MCInst *MI, unsigned OpNo,
959 printPostIncOperand(MI, OpNo, 4, O);
962 void ARM64InstPrinter::printPostIncOperand6(const MCInst *MI, unsigned OpNo,
964 printPostIncOperand(MI, OpNo, 6, O);
967 void ARM64InstPrinter::printPostIncOperand8(const MCInst *MI, unsigned OpNo,
969 printPostIncOperand(MI, OpNo, 8, O);
972 void ARM64InstPrinter::printPostIncOperand12(const MCInst *MI, unsigned OpNo,
974 printPostIncOperand(MI, OpNo, 12, O);
977 void ARM64InstPrinter::printPostIncOperand16(const MCInst *MI, unsigned OpNo,
979 printPostIncOperand(MI, OpNo, 16, O);
982 void ARM64InstPrinter::printPostIncOperand24(const MCInst *MI, unsigned OpNo,
984 printPostIncOperand(MI, OpNo, 24, O);
987 void ARM64InstPrinter::printPostIncOperand32(const MCInst *MI, unsigned OpNo,
989 printPostIncOperand(MI, OpNo, 32, O);
992 void ARM64InstPrinter::printPostIncOperand48(const MCInst *MI, unsigned OpNo,
994 printPostIncOperand(MI, OpNo, 48, O);
997 void ARM64InstPrinter::printPostIncOperand64(const MCInst *MI, unsigned OpNo,
999 printPostIncOperand(MI, OpNo, 64, O);
1002 void ARM64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
1004 const MCOperand &Op = MI->getOperand(OpNo);
1005 assert(Op.isReg() && "Non-register vreg operand!");
1006 unsigned Reg = Op.getReg();
1007 O << getRegisterName(Reg, ARM64::vreg);
1010 void ARM64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
1012 const MCOperand &Op = MI->getOperand(OpNo);
1013 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
1014 O << "c" << Op.getImm();
1017 void ARM64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
1019 const MCOperand &MO = MI->getOperand(OpNum);
1021 unsigned Val = (MO.getImm() & 0xfff);
1022 assert(Val == MO.getImm() && "Add/sub immediate out of range!");
1024 ARM64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
1025 O << '#' << (Val << Shift);
1026 // Distinguish "0, lsl #12" from "0, lsl #0".
1027 if (Val == 0 && Shift != 0)
1028 printShifter(MI, OpNum + 1, O);
1030 assert(MO.isExpr() && "Unexpected operand type!");
1032 printShifter(MI, OpNum + 1, O);
1036 void ARM64InstPrinter::printLogicalImm32(const MCInst *MI, unsigned OpNum,
1038 uint64_t Val = MI->getOperand(OpNum).getImm();
1040 O.write_hex(ARM64_AM::decodeLogicalImmediate(Val, 32));
1043 void ARM64InstPrinter::printLogicalImm64(const MCInst *MI, unsigned OpNum,
1045 uint64_t Val = MI->getOperand(OpNum).getImm();
1047 O.write_hex(ARM64_AM::decodeLogicalImmediate(Val, 64));
1050 void ARM64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
1052 unsigned Val = MI->getOperand(OpNum).getImm();
1053 // LSL #0 should not be printed.
1054 if (ARM64_AM::getShiftType(Val) == ARM64_AM::LSL &&
1055 ARM64_AM::getShiftValue(Val) == 0)
1057 O << ", " << ARM64_AM::getShiftName(ARM64_AM::getShiftType(Val)) << " #"
1058 << ARM64_AM::getShiftValue(Val);
1061 void ARM64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
1063 O << getRegisterName(MI->getOperand(OpNum).getReg());
1064 printShifter(MI, OpNum + 1, O);
1067 void ARM64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
1069 O << getRegisterName(MI->getOperand(OpNum).getReg());
1070 printExtend(MI, OpNum + 1, O);
1073 void ARM64InstPrinter::printExtend(const MCInst *MI, unsigned OpNum,
1075 unsigned Val = MI->getOperand(OpNum).getImm();
1076 ARM64_AM::ExtendType ExtType = ARM64_AM::getArithExtendType(Val);
1077 unsigned ShiftVal = ARM64_AM::getArithShiftValue(Val);
1079 // If the destination or first source register operand is [W]SP, print
1080 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1082 if (ExtType == ARM64_AM::UXTW || ExtType == ARM64_AM::UXTX) {
1083 unsigned Dest = MI->getOperand(0).getReg();
1084 unsigned Src1 = MI->getOperand(1).getReg();
1085 if (Dest == ARM64::SP || Dest == ARM64::WSP || Src1 == ARM64::SP ||
1086 Src1 == ARM64::WSP) {
1088 O << ", lsl #" << ShiftVal;
1092 O << ", " << ARM64_AM::getExtendName(ExtType);
1094 O << " #" << ShiftVal;
1097 void ARM64InstPrinter::printDotCondCode(const MCInst *MI, unsigned OpNum,
1099 ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
1100 if (CC != ARM64CC::AL)
1101 O << '.' << ARM64CC::getCondCodeName(CC);
1104 void ARM64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1106 ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
1107 O << ARM64CC::getCondCodeName(CC);
1110 void ARM64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1112 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
1115 void ARM64InstPrinter::printImmScale4(const MCInst *MI, unsigned OpNum,
1117 O << '#' << 4 * MI->getOperand(OpNum).getImm();
1120 void ARM64InstPrinter::printImmScale8(const MCInst *MI, unsigned OpNum,
1122 O << '#' << 8 * MI->getOperand(OpNum).getImm();
1125 void ARM64InstPrinter::printImmScale16(const MCInst *MI, unsigned OpNum,
1127 O << '#' << 16 * MI->getOperand(OpNum).getImm();
1130 void ARM64InstPrinter::printAMIndexed(const MCInst *MI, unsigned OpNum,
1131 unsigned Scale, raw_ostream &O) {
1132 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1133 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
1135 if (MO1.getImm() != 0)
1136 O << ", #" << (MO1.getImm() * Scale);
1138 assert(MO1.isExpr() && "Unexpected operand type!");
1139 O << ", " << *MO1.getExpr();
1144 void ARM64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1146 unsigned prfop = MI->getOperand(OpNum).getImm();
1147 if (ARM64_AM::isNamedPrefetchOp(prfop))
1148 O << ARM64_AM::getPrefetchOpName((ARM64_AM::PrefetchOp)prfop);
1153 void ARM64InstPrinter::printMemoryPostIndexed32(const MCInst *MI,
1156 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
1157 << 4 * MI->getOperand(OpNum + 1).getImm();
1160 void ARM64InstPrinter::printMemoryPostIndexed64(const MCInst *MI,
1163 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
1164 << 8 * MI->getOperand(OpNum + 1).getImm();
1167 void ARM64InstPrinter::printMemoryPostIndexed128(const MCInst *MI,
1170 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
1171 << 16 * MI->getOperand(OpNum + 1).getImm();
1174 void ARM64InstPrinter::printMemoryPostIndexed(const MCInst *MI, unsigned OpNum,
1176 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']' << ", #"
1177 << MI->getOperand(OpNum + 1).getImm();
1180 void ARM64InstPrinter::printMemoryRegOffset(const MCInst *MI, unsigned OpNum,
1181 raw_ostream &O, int LegalShiftAmt) {
1182 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ", "
1183 << getRegisterName(MI->getOperand(OpNum + 1).getReg());
1185 unsigned Val = MI->getOperand(OpNum + 2).getImm();
1186 ARM64_AM::ExtendType ExtType = ARM64_AM::getMemExtendType(Val);
1187 bool DoShift = ARM64_AM::getMemDoShift(Val);
1189 if (ExtType == ARM64_AM::UXTX) {
1193 O << ", " << ARM64_AM::getExtendName(ExtType);
1196 O << " #" << LegalShiftAmt;
1201 void ARM64InstPrinter::printMemoryRegOffset8(const MCInst *MI, unsigned OpNum,
1203 printMemoryRegOffset(MI, OpNum, O, 0);
1206 void ARM64InstPrinter::printMemoryRegOffset16(const MCInst *MI, unsigned OpNum,
1208 printMemoryRegOffset(MI, OpNum, O, 1);
1211 void ARM64InstPrinter::printMemoryRegOffset32(const MCInst *MI, unsigned OpNum,
1213 printMemoryRegOffset(MI, OpNum, O, 2);
1216 void ARM64InstPrinter::printMemoryRegOffset64(const MCInst *MI, unsigned OpNum,
1218 printMemoryRegOffset(MI, OpNum, O, 3);
1221 void ARM64InstPrinter::printMemoryRegOffset128(const MCInst *MI, unsigned OpNum,
1223 printMemoryRegOffset(MI, OpNum, O, 4);
1226 void ARM64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1228 const MCOperand &MO = MI->getOperand(OpNum);
1231 // FIXME: Should this ever happen?
1234 O << ARM64_AM::getFPImmFloat(MO.getImm());
1237 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1241 assert(0 && "Vector register expected!");
1242 case ARM64::Q0: Reg = ARM64::Q1; break;
1243 case ARM64::Q1: Reg = ARM64::Q2; break;
1244 case ARM64::Q2: Reg = ARM64::Q3; break;
1245 case ARM64::Q3: Reg = ARM64::Q4; break;
1246 case ARM64::Q4: Reg = ARM64::Q5; break;
1247 case ARM64::Q5: Reg = ARM64::Q6; break;
1248 case ARM64::Q6: Reg = ARM64::Q7; break;
1249 case ARM64::Q7: Reg = ARM64::Q8; break;
1250 case ARM64::Q8: Reg = ARM64::Q9; break;
1251 case ARM64::Q9: Reg = ARM64::Q10; break;
1252 case ARM64::Q10: Reg = ARM64::Q11; break;
1253 case ARM64::Q11: Reg = ARM64::Q12; break;
1254 case ARM64::Q12: Reg = ARM64::Q13; break;
1255 case ARM64::Q13: Reg = ARM64::Q14; break;
1256 case ARM64::Q14: Reg = ARM64::Q15; break;
1257 case ARM64::Q15: Reg = ARM64::Q16; break;
1258 case ARM64::Q16: Reg = ARM64::Q17; break;
1259 case ARM64::Q17: Reg = ARM64::Q18; break;
1260 case ARM64::Q18: Reg = ARM64::Q19; break;
1261 case ARM64::Q19: Reg = ARM64::Q20; break;
1262 case ARM64::Q20: Reg = ARM64::Q21; break;
1263 case ARM64::Q21: Reg = ARM64::Q22; break;
1264 case ARM64::Q22: Reg = ARM64::Q23; break;
1265 case ARM64::Q23: Reg = ARM64::Q24; break;
1266 case ARM64::Q24: Reg = ARM64::Q25; break;
1267 case ARM64::Q25: Reg = ARM64::Q26; break;
1268 case ARM64::Q26: Reg = ARM64::Q27; break;
1269 case ARM64::Q27: Reg = ARM64::Q28; break;
1270 case ARM64::Q28: Reg = ARM64::Q29; break;
1271 case ARM64::Q29: Reg = ARM64::Q30; break;
1272 case ARM64::Q30: Reg = ARM64::Q31; break;
1273 // Vector lists can wrap around.
1282 void ARM64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1283 raw_ostream &O, StringRef LayoutSuffix) {
1284 unsigned Reg = MI->getOperand(OpNum).getReg();
1288 // Work out how many registers there are in the list (if there is an actual
1290 unsigned NumRegs = 1;
1291 if (MRI.getRegClass(ARM64::DDRegClassID).contains(Reg) ||
1292 MRI.getRegClass(ARM64::QQRegClassID).contains(Reg))
1294 else if (MRI.getRegClass(ARM64::DDDRegClassID).contains(Reg) ||
1295 MRI.getRegClass(ARM64::QQQRegClassID).contains(Reg))
1297 else if (MRI.getRegClass(ARM64::DDDDRegClassID).contains(Reg) ||
1298 MRI.getRegClass(ARM64::QQQQRegClassID).contains(Reg))
1301 // Now forget about the list and find out what the first register is.
1302 if (unsigned FirstReg = MRI.getSubReg(Reg, ARM64::dsub0))
1304 else if (unsigned FirstReg = MRI.getSubReg(Reg, ARM64::qsub0))
1307 // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1308 // printing (otherwise getRegisterName fails).
1309 if (MRI.getRegClass(ARM64::FPR64RegClassID).contains(Reg)) {
1310 const MCRegisterClass &FPR128RC = MRI.getRegClass(ARM64::FPR128RegClassID);
1311 Reg = MRI.getMatchingSuperReg(Reg, ARM64::dsub, &FPR128RC);
1314 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1315 O << getRegisterName(Reg, ARM64::vreg) << LayoutSuffix;
1316 if (i + 1 != NumRegs)
1323 void ARM64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1326 printVectorList(MI, OpNum, O, "");
1329 template <unsigned NumLanes, char LaneKind>
1330 void ARM64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1334 Suffix = Twine('.') + Twine(NumLanes) + Twine(LaneKind);
1336 Suffix = Twine('.') + Twine(LaneKind);
1339 printVectorList(MI, OpNum, O, Suffix.toStringRef(Buf));
1342 void ARM64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1344 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1347 void ARM64InstPrinter::printAlignedBranchTarget(const MCInst *MI,
1350 const MCOperand &Op = MI->getOperand(OpNum);
1352 // If the label has already been resolved to an immediate offset (say, when
1353 // we're running the disassembler), just print the immediate.
1355 O << "#" << (Op.getImm() << 2);
1359 // If the branch target is simply an address then print it in hex.
1360 const MCConstantExpr *BranchTarget =
1361 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1363 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
1365 O.write_hex(Address);
1367 // Otherwise, just print the expression.
1368 O << *MI->getOperand(OpNum).getExpr();
1372 void ARM64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
1374 const MCOperand &Op = MI->getOperand(OpNum);
1376 // If the label has already been resolved to an immediate offset (say, when
1377 // we're running the disassembler), just print the immediate.
1379 O << "#" << (Op.getImm() << 12);
1383 // Otherwise, just print the expression.
1384 O << *MI->getOperand(OpNum).getExpr();
1387 void ARM64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1389 unsigned Val = MI->getOperand(OpNo).getImm();
1390 const char *Name = ARM64SYS::getBarrierOptName((ARM64SYS::BarrierOption)Val);
1397 void ARM64InstPrinter::printSystemRegister(const MCInst *MI, unsigned OpNo,
1399 unsigned Val = MI->getOperand(OpNo).getImm();
1401 ARM64SYS::getSystemRegisterName((ARM64SYS::SystemRegister)Val);
1407 unsigned Op0 = 2 | ((Val >> 14) & 1);
1408 unsigned Op1 = (Val >> 11) & 7;
1409 unsigned CRn = (Val >> 7) & 0xf;
1410 unsigned CRm = (Val >> 3) & 0xf;
1411 unsigned Op2 = Val & 7;
1413 O << 'S' << Op0 << '_' << Op1 << "_C" << CRn << "_C" << CRm << '_' << Op2;
1416 void ARM64InstPrinter::printSystemCPSRField(const MCInst *MI, unsigned OpNo,
1418 unsigned Val = MI->getOperand(OpNo).getImm();
1419 const char *Name = ARM64SYS::getCPSRFieldName((ARM64SYS::CPSRField)Val);
1423 void ARM64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
1425 unsigned RawVal = MI->getOperand(OpNo).getImm();
1426 uint64_t Val = ARM64_AM::decodeAdvSIMDModImmType10(RawVal);
1427 O << format("#%#016lx", Val);