1 //===-- ARM64InstPrinter.cpp - Convert ARM64 MCInst to assembly syntax ----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM64 MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #include "ARM64InstPrinter.h"
15 #include "MCTargetDesc/ARM64AddressingModes.h"
16 #include "Utils/ARM64BaseInfo.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/StringExtras.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCExpr.h"
21 #include "llvm/MC/MCRegisterInfo.h"
22 #include "llvm/Support/Format.h"
23 #include "llvm/Support/raw_ostream.h"
26 #define DEBUG_TYPE "asm-printer"
28 #define GET_INSTRUCTION_NAME
29 #define PRINT_ALIAS_INSTR
30 #include "ARM64GenAsmWriter.inc"
31 #define GET_INSTRUCTION_NAME
32 #define PRINT_ALIAS_INSTR
33 #include "ARM64GenAsmWriter1.inc"
35 ARM64InstPrinter::ARM64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
36 const MCRegisterInfo &MRI,
37 const MCSubtargetInfo &STI)
38 : MCInstPrinter(MAI, MII, MRI) {
39 // Initialize the set of available features.
40 setAvailableFeatures(STI.getFeatureBits());
43 ARM64AppleInstPrinter::ARM64AppleInstPrinter(const MCAsmInfo &MAI,
44 const MCInstrInfo &MII,
45 const MCRegisterInfo &MRI,
46 const MCSubtargetInfo &STI)
47 : ARM64InstPrinter(MAI, MII, MRI, STI) {}
49 void ARM64InstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
50 // This is for .cfi directives.
51 OS << getRegisterName(RegNo);
54 void ARM64InstPrinter::printInst(const MCInst *MI, raw_ostream &O,
56 // Check for special encodings and print the canonical alias instead.
58 unsigned Opcode = MI->getOpcode();
60 if (Opcode == ARM64::SYSxt)
61 if (printSysAlias(MI, O)) {
62 printAnnotation(O, Annot);
66 // SBFM/UBFM should print to a nicer aliased form if possible.
67 if (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri ||
68 Opcode == ARM64::UBFMXri || Opcode == ARM64::UBFMWri) {
69 const MCOperand &Op0 = MI->getOperand(0);
70 const MCOperand &Op1 = MI->getOperand(1);
71 const MCOperand &Op2 = MI->getOperand(2);
72 const MCOperand &Op3 = MI->getOperand(3);
74 bool IsSigned = (Opcode == ARM64::SBFMXri || Opcode == ARM64::SBFMWri);
75 bool Is64Bit = (Opcode == ARM64::SBFMXri || Opcode == ARM64::UBFMXri);
76 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) {
77 const char *AsmMnemonic = nullptr;
79 switch (Op3.getImm()) {
95 // *xtw is only valid for signed 64-bit operations.
96 if (Is64Bit && IsSigned)
102 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
103 << ", " << getRegisterName(getWRegFromXReg(Op1.getReg()));
104 printAnnotation(O, Annot);
109 // All immediate shifts are aliases, implemented using the Bitfield
110 // instruction. In all cases the immediate shift amount shift must be in
111 // the range 0 to (reg.size -1).
112 if (Op2.isImm() && Op3.isImm()) {
113 const char *AsmMnemonic = nullptr;
115 int64_t immr = Op2.getImm();
116 int64_t imms = Op3.getImm();
117 if (Opcode == ARM64::UBFMWri && imms != 0x1F && ((imms + 1) == immr)) {
120 } else if (Opcode == ARM64::UBFMXri && imms != 0x3f &&
121 ((imms + 1 == immr))) {
124 } else if (Opcode == ARM64::UBFMWri && imms == 0x1f) {
127 } else if (Opcode == ARM64::UBFMXri && imms == 0x3f) {
130 } else if (Opcode == ARM64::SBFMWri && imms == 0x1f) {
133 } else if (Opcode == ARM64::SBFMXri && imms == 0x3f) {
138 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
139 << ", " << getRegisterName(Op1.getReg()) << ", #" << shift;
140 printAnnotation(O, Annot);
145 // SBFIZ/UBFIZ aliases
146 if (Op2.getImm() > Op3.getImm()) {
147 O << '\t' << (IsSigned ? "sbfiz" : "ubfiz") << '\t'
148 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
149 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1;
150 printAnnotation(O, Annot);
154 // Otherwise SBFX/UBFX is the preferred form
155 O << '\t' << (IsSigned ? "sbfx" : "ubfx") << '\t'
156 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
157 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1;
158 printAnnotation(O, Annot);
162 if (Opcode == ARM64::BFMXri || Opcode == ARM64::BFMWri) {
163 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
164 const MCOperand &Op2 = MI->getOperand(2);
165 int ImmR = MI->getOperand(3).getImm();
166 int ImmS = MI->getOperand(4).getImm();
170 int BitWidth = Opcode == ARM64::BFMXri ? 64 : 32;
171 int LSB = (BitWidth - ImmR) % BitWidth;
172 int Width = ImmS + 1;
173 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
174 << getRegisterName(Op2.getReg()) << ", #" << LSB << ", #" << Width;
175 printAnnotation(O, Annot);
180 int Width = ImmS - ImmR + 1;
181 // Otherwise BFXIL the preferred form
183 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg())
184 << ", #" << LSB << ", #" << Width;
185 printAnnotation(O, Annot);
189 // Symbolic operands for MOVZ, MOVN and MOVK already imply a shift
190 // (e.g. :gottprel_g1: is always going to be "lsl #16") so it should not be
192 if ((Opcode == ARM64::MOVZXi || Opcode == ARM64::MOVZWi ||
193 Opcode == ARM64::MOVNXi || Opcode == ARM64::MOVNWi) &&
194 MI->getOperand(1).isExpr()) {
195 if (Opcode == ARM64::MOVZXi || Opcode == ARM64::MOVZWi)
200 O << getRegisterName(MI->getOperand(0).getReg()) << ", #"
201 << *MI->getOperand(1).getExpr();
205 if ((Opcode == ARM64::MOVKXi || Opcode == ARM64::MOVKWi) &&
206 MI->getOperand(2).isExpr()) {
207 O << "\tmovk\t" << getRegisterName(MI->getOperand(0).getReg()) << ", #"
208 << *MI->getOperand(2).getExpr();
212 if (!printAliasInstr(MI, O))
213 printInstruction(MI, O);
215 printAnnotation(O, Annot);
218 static bool isTblTbxInstruction(unsigned Opcode, StringRef &Layout,
221 case ARM64::TBXv8i8One:
222 case ARM64::TBXv8i8Two:
223 case ARM64::TBXv8i8Three:
224 case ARM64::TBXv8i8Four:
228 case ARM64::TBLv8i8One:
229 case ARM64::TBLv8i8Two:
230 case ARM64::TBLv8i8Three:
231 case ARM64::TBLv8i8Four:
235 case ARM64::TBXv16i8One:
236 case ARM64::TBXv16i8Two:
237 case ARM64::TBXv16i8Three:
238 case ARM64::TBXv16i8Four:
242 case ARM64::TBLv16i8One:
243 case ARM64::TBLv16i8Two:
244 case ARM64::TBLv16i8Three:
245 case ARM64::TBLv16i8Four:
254 struct LdStNInstrDesc {
256 const char *Mnemonic;
263 static LdStNInstrDesc LdStNInstInfo[] = {
264 { ARM64::LD1i8, "ld1", ".b", 1, true, 0 },
265 { ARM64::LD1i16, "ld1", ".h", 1, true, 0 },
266 { ARM64::LD1i32, "ld1", ".s", 1, true, 0 },
267 { ARM64::LD1i64, "ld1", ".d", 1, true, 0 },
268 { ARM64::LD1i8_POST, "ld1", ".b", 2, true, 1 },
269 { ARM64::LD1i16_POST, "ld1", ".h", 2, true, 2 },
270 { ARM64::LD1i32_POST, "ld1", ".s", 2, true, 4 },
271 { ARM64::LD1i64_POST, "ld1", ".d", 2, true, 8 },
272 { ARM64::LD1Rv16b, "ld1r", ".16b", 0, false, 0 },
273 { ARM64::LD1Rv8h, "ld1r", ".8h", 0, false, 0 },
274 { ARM64::LD1Rv4s, "ld1r", ".4s", 0, false, 0 },
275 { ARM64::LD1Rv2d, "ld1r", ".2d", 0, false, 0 },
276 { ARM64::LD1Rv8b, "ld1r", ".8b", 0, false, 0 },
277 { ARM64::LD1Rv4h, "ld1r", ".4h", 0, false, 0 },
278 { ARM64::LD1Rv2s, "ld1r", ".2s", 0, false, 0 },
279 { ARM64::LD1Rv1d, "ld1r", ".1d", 0, false, 0 },
280 { ARM64::LD1Rv16b_POST, "ld1r", ".16b", 1, false, 1 },
281 { ARM64::LD1Rv8h_POST, "ld1r", ".8h", 1, false, 2 },
282 { ARM64::LD1Rv4s_POST, "ld1r", ".4s", 1, false, 4 },
283 { ARM64::LD1Rv2d_POST, "ld1r", ".2d", 1, false, 8 },
284 { ARM64::LD1Rv8b_POST, "ld1r", ".8b", 1, false, 1 },
285 { ARM64::LD1Rv4h_POST, "ld1r", ".4h", 1, false, 2 },
286 { ARM64::LD1Rv2s_POST, "ld1r", ".2s", 1, false, 4 },
287 { ARM64::LD1Rv1d_POST, "ld1r", ".1d", 1, false, 8 },
288 { ARM64::LD1Onev16b, "ld1", ".16b", 0, false, 0 },
289 { ARM64::LD1Onev8h, "ld1", ".8h", 0, false, 0 },
290 { ARM64::LD1Onev4s, "ld1", ".4s", 0, false, 0 },
291 { ARM64::LD1Onev2d, "ld1", ".2d", 0, false, 0 },
292 { ARM64::LD1Onev8b, "ld1", ".8b", 0, false, 0 },
293 { ARM64::LD1Onev4h, "ld1", ".4h", 0, false, 0 },
294 { ARM64::LD1Onev2s, "ld1", ".2s", 0, false, 0 },
295 { ARM64::LD1Onev1d, "ld1", ".1d", 0, false, 0 },
296 { ARM64::LD1Onev16b_POST, "ld1", ".16b", 1, false, 16 },
297 { ARM64::LD1Onev8h_POST, "ld1", ".8h", 1, false, 16 },
298 { ARM64::LD1Onev4s_POST, "ld1", ".4s", 1, false, 16 },
299 { ARM64::LD1Onev2d_POST, "ld1", ".2d", 1, false, 16 },
300 { ARM64::LD1Onev8b_POST, "ld1", ".8b", 1, false, 8 },
301 { ARM64::LD1Onev4h_POST, "ld1", ".4h", 1, false, 8 },
302 { ARM64::LD1Onev2s_POST, "ld1", ".2s", 1, false, 8 },
303 { ARM64::LD1Onev1d_POST, "ld1", ".1d", 1, false, 8 },
304 { ARM64::LD1Twov16b, "ld1", ".16b", 0, false, 0 },
305 { ARM64::LD1Twov8h, "ld1", ".8h", 0, false, 0 },
306 { ARM64::LD1Twov4s, "ld1", ".4s", 0, false, 0 },
307 { ARM64::LD1Twov2d, "ld1", ".2d", 0, false, 0 },
308 { ARM64::LD1Twov8b, "ld1", ".8b", 0, false, 0 },
309 { ARM64::LD1Twov4h, "ld1", ".4h", 0, false, 0 },
310 { ARM64::LD1Twov2s, "ld1", ".2s", 0, false, 0 },
311 { ARM64::LD1Twov1d, "ld1", ".1d", 0, false, 0 },
312 { ARM64::LD1Twov16b_POST, "ld1", ".16b", 1, false, 32 },
313 { ARM64::LD1Twov8h_POST, "ld1", ".8h", 1, false, 32 },
314 { ARM64::LD1Twov4s_POST, "ld1", ".4s", 1, false, 32 },
315 { ARM64::LD1Twov2d_POST, "ld1", ".2d", 1, false, 32 },
316 { ARM64::LD1Twov8b_POST, "ld1", ".8b", 1, false, 16 },
317 { ARM64::LD1Twov4h_POST, "ld1", ".4h", 1, false, 16 },
318 { ARM64::LD1Twov2s_POST, "ld1", ".2s", 1, false, 16 },
319 { ARM64::LD1Twov1d_POST, "ld1", ".1d", 1, false, 16 },
320 { ARM64::LD1Threev16b, "ld1", ".16b", 0, false, 0 },
321 { ARM64::LD1Threev8h, "ld1", ".8h", 0, false, 0 },
322 { ARM64::LD1Threev4s, "ld1", ".4s", 0, false, 0 },
323 { ARM64::LD1Threev2d, "ld1", ".2d", 0, false, 0 },
324 { ARM64::LD1Threev8b, "ld1", ".8b", 0, false, 0 },
325 { ARM64::LD1Threev4h, "ld1", ".4h", 0, false, 0 },
326 { ARM64::LD1Threev2s, "ld1", ".2s", 0, false, 0 },
327 { ARM64::LD1Threev1d, "ld1", ".1d", 0, false, 0 },
328 { ARM64::LD1Threev16b_POST, "ld1", ".16b", 1, false, 48 },
329 { ARM64::LD1Threev8h_POST, "ld1", ".8h", 1, false, 48 },
330 { ARM64::LD1Threev4s_POST, "ld1", ".4s", 1, false, 48 },
331 { ARM64::LD1Threev2d_POST, "ld1", ".2d", 1, false, 48 },
332 { ARM64::LD1Threev8b_POST, "ld1", ".8b", 1, false, 24 },
333 { ARM64::LD1Threev4h_POST, "ld1", ".4h", 1, false, 24 },
334 { ARM64::LD1Threev2s_POST, "ld1", ".2s", 1, false, 24 },
335 { ARM64::LD1Threev1d_POST, "ld1", ".1d", 1, false, 24 },
336 { ARM64::LD1Fourv16b, "ld1", ".16b", 0, false, 0 },
337 { ARM64::LD1Fourv8h, "ld1", ".8h", 0, false, 0 },
338 { ARM64::LD1Fourv4s, "ld1", ".4s", 0, false, 0 },
339 { ARM64::LD1Fourv2d, "ld1", ".2d", 0, false, 0 },
340 { ARM64::LD1Fourv8b, "ld1", ".8b", 0, false, 0 },
341 { ARM64::LD1Fourv4h, "ld1", ".4h", 0, false, 0 },
342 { ARM64::LD1Fourv2s, "ld1", ".2s", 0, false, 0 },
343 { ARM64::LD1Fourv1d, "ld1", ".1d", 0, false, 0 },
344 { ARM64::LD1Fourv16b_POST, "ld1", ".16b", 1, false, 64 },
345 { ARM64::LD1Fourv8h_POST, "ld1", ".8h", 1, false, 64 },
346 { ARM64::LD1Fourv4s_POST, "ld1", ".4s", 1, false, 64 },
347 { ARM64::LD1Fourv2d_POST, "ld1", ".2d", 1, false, 64 },
348 { ARM64::LD1Fourv8b_POST, "ld1", ".8b", 1, false, 32 },
349 { ARM64::LD1Fourv4h_POST, "ld1", ".4h", 1, false, 32 },
350 { ARM64::LD1Fourv2s_POST, "ld1", ".2s", 1, false, 32 },
351 { ARM64::LD1Fourv1d_POST, "ld1", ".1d", 1, false, 32 },
352 { ARM64::LD2i8, "ld2", ".b", 1, true, 0 },
353 { ARM64::LD2i16, "ld2", ".h", 1, true, 0 },
354 { ARM64::LD2i32, "ld2", ".s", 1, true, 0 },
355 { ARM64::LD2i64, "ld2", ".d", 1, true, 0 },
356 { ARM64::LD2i8_POST, "ld2", ".b", 2, true, 2 },
357 { ARM64::LD2i16_POST, "ld2", ".h", 2, true, 4 },
358 { ARM64::LD2i32_POST, "ld2", ".s", 2, true, 8 },
359 { ARM64::LD2i64_POST, "ld2", ".d", 2, true, 16 },
360 { ARM64::LD2Rv16b, "ld2r", ".16b", 0, false, 0 },
361 { ARM64::LD2Rv8h, "ld2r", ".8h", 0, false, 0 },
362 { ARM64::LD2Rv4s, "ld2r", ".4s", 0, false, 0 },
363 { ARM64::LD2Rv2d, "ld2r", ".2d", 0, false, 0 },
364 { ARM64::LD2Rv8b, "ld2r", ".8b", 0, false, 0 },
365 { ARM64::LD2Rv4h, "ld2r", ".4h", 0, false, 0 },
366 { ARM64::LD2Rv2s, "ld2r", ".2s", 0, false, 0 },
367 { ARM64::LD2Rv1d, "ld2r", ".1d", 0, false, 0 },
368 { ARM64::LD2Rv16b_POST, "ld2r", ".16b", 1, false, 2 },
369 { ARM64::LD2Rv8h_POST, "ld2r", ".8h", 1, false, 4 },
370 { ARM64::LD2Rv4s_POST, "ld2r", ".4s", 1, false, 8 },
371 { ARM64::LD2Rv2d_POST, "ld2r", ".2d", 1, false, 16 },
372 { ARM64::LD2Rv8b_POST, "ld2r", ".8b", 1, false, 2 },
373 { ARM64::LD2Rv4h_POST, "ld2r", ".4h", 1, false, 4 },
374 { ARM64::LD2Rv2s_POST, "ld2r", ".2s", 1, false, 8 },
375 { ARM64::LD2Rv1d_POST, "ld2r", ".1d", 1, false, 16 },
376 { ARM64::LD2Twov16b, "ld2", ".16b", 0, false, 0 },
377 { ARM64::LD2Twov8h, "ld2", ".8h", 0, false, 0 },
378 { ARM64::LD2Twov4s, "ld2", ".4s", 0, false, 0 },
379 { ARM64::LD2Twov2d, "ld2", ".2d", 0, false, 0 },
380 { ARM64::LD2Twov8b, "ld2", ".8b", 0, false, 0 },
381 { ARM64::LD2Twov4h, "ld2", ".4h", 0, false, 0 },
382 { ARM64::LD2Twov2s, "ld2", ".2s", 0, false, 0 },
383 { ARM64::LD2Twov16b_POST, "ld2", ".16b", 1, false, 32 },
384 { ARM64::LD2Twov8h_POST, "ld2", ".8h", 1, false, 32 },
385 { ARM64::LD2Twov4s_POST, "ld2", ".4s", 1, false, 32 },
386 { ARM64::LD2Twov2d_POST, "ld2", ".2d", 1, false, 32 },
387 { ARM64::LD2Twov8b_POST, "ld2", ".8b", 1, false, 16 },
388 { ARM64::LD2Twov4h_POST, "ld2", ".4h", 1, false, 16 },
389 { ARM64::LD2Twov2s_POST, "ld2", ".2s", 1, false, 16 },
390 { ARM64::LD3i8, "ld3", ".b", 1, true, 0 },
391 { ARM64::LD3i16, "ld3", ".h", 1, true, 0 },
392 { ARM64::LD3i32, "ld3", ".s", 1, true, 0 },
393 { ARM64::LD3i64, "ld3", ".d", 1, true, 0 },
394 { ARM64::LD3i8_POST, "ld3", ".b", 2, true, 3 },
395 { ARM64::LD3i16_POST, "ld3", ".h", 2, true, 6 },
396 { ARM64::LD3i32_POST, "ld3", ".s", 2, true, 12 },
397 { ARM64::LD3i64_POST, "ld3", ".d", 2, true, 24 },
398 { ARM64::LD3Rv16b, "ld3r", ".16b", 0, false, 0 },
399 { ARM64::LD3Rv8h, "ld3r", ".8h", 0, false, 0 },
400 { ARM64::LD3Rv4s, "ld3r", ".4s", 0, false, 0 },
401 { ARM64::LD3Rv2d, "ld3r", ".2d", 0, false, 0 },
402 { ARM64::LD3Rv8b, "ld3r", ".8b", 0, false, 0 },
403 { ARM64::LD3Rv4h, "ld3r", ".4h", 0, false, 0 },
404 { ARM64::LD3Rv2s, "ld3r", ".2s", 0, false, 0 },
405 { ARM64::LD3Rv1d, "ld3r", ".1d", 0, false, 0 },
406 { ARM64::LD3Rv16b_POST, "ld3r", ".16b", 1, false, 3 },
407 { ARM64::LD3Rv8h_POST, "ld3r", ".8h", 1, false, 6 },
408 { ARM64::LD3Rv4s_POST, "ld3r", ".4s", 1, false, 12 },
409 { ARM64::LD3Rv2d_POST, "ld3r", ".2d", 1, false, 24 },
410 { ARM64::LD3Rv8b_POST, "ld3r", ".8b", 1, false, 3 },
411 { ARM64::LD3Rv4h_POST, "ld3r", ".4h", 1, false, 6 },
412 { ARM64::LD3Rv2s_POST, "ld3r", ".2s", 1, false, 12 },
413 { ARM64::LD3Rv1d_POST, "ld3r", ".1d", 1, false, 24 },
414 { ARM64::LD3Threev16b, "ld3", ".16b", 0, false, 0 },
415 { ARM64::LD3Threev8h, "ld3", ".8h", 0, false, 0 },
416 { ARM64::LD3Threev4s, "ld3", ".4s", 0, false, 0 },
417 { ARM64::LD3Threev2d, "ld3", ".2d", 0, false, 0 },
418 { ARM64::LD3Threev8b, "ld3", ".8b", 0, false, 0 },
419 { ARM64::LD3Threev4h, "ld3", ".4h", 0, false, 0 },
420 { ARM64::LD3Threev2s, "ld3", ".2s", 0, false, 0 },
421 { ARM64::LD3Threev16b_POST, "ld3", ".16b", 1, false, 48 },
422 { ARM64::LD3Threev8h_POST, "ld3", ".8h", 1, false, 48 },
423 { ARM64::LD3Threev4s_POST, "ld3", ".4s", 1, false, 48 },
424 { ARM64::LD3Threev2d_POST, "ld3", ".2d", 1, false, 48 },
425 { ARM64::LD3Threev8b_POST, "ld3", ".8b", 1, false, 24 },
426 { ARM64::LD3Threev4h_POST, "ld3", ".4h", 1, false, 24 },
427 { ARM64::LD3Threev2s_POST, "ld3", ".2s", 1, false, 24 },
428 { ARM64::LD4i8, "ld4", ".b", 1, true, 0 },
429 { ARM64::LD4i16, "ld4", ".h", 1, true, 0 },
430 { ARM64::LD4i32, "ld4", ".s", 1, true, 0 },
431 { ARM64::LD4i64, "ld4", ".d", 1, true, 0 },
432 { ARM64::LD4i8_POST, "ld4", ".b", 2, true, 4 },
433 { ARM64::LD4i16_POST, "ld4", ".h", 2, true, 8 },
434 { ARM64::LD4i32_POST, "ld4", ".s", 2, true, 16 },
435 { ARM64::LD4i64_POST, "ld4", ".d", 2, true, 32 },
436 { ARM64::LD4Rv16b, "ld4r", ".16b", 0, false, 0 },
437 { ARM64::LD4Rv8h, "ld4r", ".8h", 0, false, 0 },
438 { ARM64::LD4Rv4s, "ld4r", ".4s", 0, false, 0 },
439 { ARM64::LD4Rv2d, "ld4r", ".2d", 0, false, 0 },
440 { ARM64::LD4Rv8b, "ld4r", ".8b", 0, false, 0 },
441 { ARM64::LD4Rv4h, "ld4r", ".4h", 0, false, 0 },
442 { ARM64::LD4Rv2s, "ld4r", ".2s", 0, false, 0 },
443 { ARM64::LD4Rv1d, "ld4r", ".1d", 0, false, 0 },
444 { ARM64::LD4Rv16b_POST, "ld4r", ".16b", 1, false, 4 },
445 { ARM64::LD4Rv8h_POST, "ld4r", ".8h", 1, false, 8 },
446 { ARM64::LD4Rv4s_POST, "ld4r", ".4s", 1, false, 16 },
447 { ARM64::LD4Rv2d_POST, "ld4r", ".2d", 1, false, 32 },
448 { ARM64::LD4Rv8b_POST, "ld4r", ".8b", 1, false, 4 },
449 { ARM64::LD4Rv4h_POST, "ld4r", ".4h", 1, false, 8 },
450 { ARM64::LD4Rv2s_POST, "ld4r", ".2s", 1, false, 16 },
451 { ARM64::LD4Rv1d_POST, "ld4r", ".1d", 1, false, 32 },
452 { ARM64::LD4Fourv16b, "ld4", ".16b", 0, false, 0 },
453 { ARM64::LD4Fourv8h, "ld4", ".8h", 0, false, 0 },
454 { ARM64::LD4Fourv4s, "ld4", ".4s", 0, false, 0 },
455 { ARM64::LD4Fourv2d, "ld4", ".2d", 0, false, 0 },
456 { ARM64::LD4Fourv8b, "ld4", ".8b", 0, false, 0 },
457 { ARM64::LD4Fourv4h, "ld4", ".4h", 0, false, 0 },
458 { ARM64::LD4Fourv2s, "ld4", ".2s", 0, false, 0 },
459 { ARM64::LD4Fourv16b_POST, "ld4", ".16b", 1, false, 64 },
460 { ARM64::LD4Fourv8h_POST, "ld4", ".8h", 1, false, 64 },
461 { ARM64::LD4Fourv4s_POST, "ld4", ".4s", 1, false, 64 },
462 { ARM64::LD4Fourv2d_POST, "ld4", ".2d", 1, false, 64 },
463 { ARM64::LD4Fourv8b_POST, "ld4", ".8b", 1, false, 32 },
464 { ARM64::LD4Fourv4h_POST, "ld4", ".4h", 1, false, 32 },
465 { ARM64::LD4Fourv2s_POST, "ld4", ".2s", 1, false, 32 },
466 { ARM64::ST1i8, "st1", ".b", 0, true, 0 },
467 { ARM64::ST1i16, "st1", ".h", 0, true, 0 },
468 { ARM64::ST1i32, "st1", ".s", 0, true, 0 },
469 { ARM64::ST1i64, "st1", ".d", 0, true, 0 },
470 { ARM64::ST1i8_POST, "st1", ".b", 1, true, 1 },
471 { ARM64::ST1i16_POST, "st1", ".h", 1, true, 2 },
472 { ARM64::ST1i32_POST, "st1", ".s", 1, true, 4 },
473 { ARM64::ST1i64_POST, "st1", ".d", 1, true, 8 },
474 { ARM64::ST1Onev16b, "st1", ".16b", 0, false, 0 },
475 { ARM64::ST1Onev8h, "st1", ".8h", 0, false, 0 },
476 { ARM64::ST1Onev4s, "st1", ".4s", 0, false, 0 },
477 { ARM64::ST1Onev2d, "st1", ".2d", 0, false, 0 },
478 { ARM64::ST1Onev8b, "st1", ".8b", 0, false, 0 },
479 { ARM64::ST1Onev4h, "st1", ".4h", 0, false, 0 },
480 { ARM64::ST1Onev2s, "st1", ".2s", 0, false, 0 },
481 { ARM64::ST1Onev1d, "st1", ".1d", 0, false, 0 },
482 { ARM64::ST1Onev16b_POST, "st1", ".16b", 1, false, 16 },
483 { ARM64::ST1Onev8h_POST, "st1", ".8h", 1, false, 16 },
484 { ARM64::ST1Onev4s_POST, "st1", ".4s", 1, false, 16 },
485 { ARM64::ST1Onev2d_POST, "st1", ".2d", 1, false, 16 },
486 { ARM64::ST1Onev8b_POST, "st1", ".8b", 1, false, 8 },
487 { ARM64::ST1Onev4h_POST, "st1", ".4h", 1, false, 8 },
488 { ARM64::ST1Onev2s_POST, "st1", ".2s", 1, false, 8 },
489 { ARM64::ST1Onev1d_POST, "st1", ".1d", 1, false, 8 },
490 { ARM64::ST1Twov16b, "st1", ".16b", 0, false, 0 },
491 { ARM64::ST1Twov8h, "st1", ".8h", 0, false, 0 },
492 { ARM64::ST1Twov4s, "st1", ".4s", 0, false, 0 },
493 { ARM64::ST1Twov2d, "st1", ".2d", 0, false, 0 },
494 { ARM64::ST1Twov8b, "st1", ".8b", 0, false, 0 },
495 { ARM64::ST1Twov4h, "st1", ".4h", 0, false, 0 },
496 { ARM64::ST1Twov2s, "st1", ".2s", 0, false, 0 },
497 { ARM64::ST1Twov1d, "st1", ".1d", 0, false, 0 },
498 { ARM64::ST1Twov16b_POST, "st1", ".16b", 1, false, 32 },
499 { ARM64::ST1Twov8h_POST, "st1", ".8h", 1, false, 32 },
500 { ARM64::ST1Twov4s_POST, "st1", ".4s", 1, false, 32 },
501 { ARM64::ST1Twov2d_POST, "st1", ".2d", 1, false, 32 },
502 { ARM64::ST1Twov8b_POST, "st1", ".8b", 1, false, 16 },
503 { ARM64::ST1Twov4h_POST, "st1", ".4h", 1, false, 16 },
504 { ARM64::ST1Twov2s_POST, "st1", ".2s", 1, false, 16 },
505 { ARM64::ST1Twov1d_POST, "st1", ".1d", 1, false, 16 },
506 { ARM64::ST1Threev16b, "st1", ".16b", 0, false, 0 },
507 { ARM64::ST1Threev8h, "st1", ".8h", 0, false, 0 },
508 { ARM64::ST1Threev4s, "st1", ".4s", 0, false, 0 },
509 { ARM64::ST1Threev2d, "st1", ".2d", 0, false, 0 },
510 { ARM64::ST1Threev8b, "st1", ".8b", 0, false, 0 },
511 { ARM64::ST1Threev4h, "st1", ".4h", 0, false, 0 },
512 { ARM64::ST1Threev2s, "st1", ".2s", 0, false, 0 },
513 { ARM64::ST1Threev1d, "st1", ".1d", 0, false, 0 },
514 { ARM64::ST1Threev16b_POST, "st1", ".16b", 1, false, 48 },
515 { ARM64::ST1Threev8h_POST, "st1", ".8h", 1, false, 48 },
516 { ARM64::ST1Threev4s_POST, "st1", ".4s", 1, false, 48 },
517 { ARM64::ST1Threev2d_POST, "st1", ".2d", 1, false, 48 },
518 { ARM64::ST1Threev8b_POST, "st1", ".8b", 1, false, 24 },
519 { ARM64::ST1Threev4h_POST, "st1", ".4h", 1, false, 24 },
520 { ARM64::ST1Threev2s_POST, "st1", ".2s", 1, false, 24 },
521 { ARM64::ST1Threev1d_POST, "st1", ".1d", 1, false, 24 },
522 { ARM64::ST1Fourv16b, "st1", ".16b", 0, false, 0 },
523 { ARM64::ST1Fourv8h, "st1", ".8h", 0, false, 0 },
524 { ARM64::ST1Fourv4s, "st1", ".4s", 0, false, 0 },
525 { ARM64::ST1Fourv2d, "st1", ".2d", 0, false, 0 },
526 { ARM64::ST1Fourv8b, "st1", ".8b", 0, false, 0 },
527 { ARM64::ST1Fourv4h, "st1", ".4h", 0, false, 0 },
528 { ARM64::ST1Fourv2s, "st1", ".2s", 0, false, 0 },
529 { ARM64::ST1Fourv1d, "st1", ".1d", 0, false, 0 },
530 { ARM64::ST1Fourv16b_POST, "st1", ".16b", 1, false, 64 },
531 { ARM64::ST1Fourv8h_POST, "st1", ".8h", 1, false, 64 },
532 { ARM64::ST1Fourv4s_POST, "st1", ".4s", 1, false, 64 },
533 { ARM64::ST1Fourv2d_POST, "st1", ".2d", 1, false, 64 },
534 { ARM64::ST1Fourv8b_POST, "st1", ".8b", 1, false, 32 },
535 { ARM64::ST1Fourv4h_POST, "st1", ".4h", 1, false, 32 },
536 { ARM64::ST1Fourv2s_POST, "st1", ".2s", 1, false, 32 },
537 { ARM64::ST1Fourv1d_POST, "st1", ".1d", 1, false, 32 },
538 { ARM64::ST2i8, "st2", ".b", 0, true, 0 },
539 { ARM64::ST2i16, "st2", ".h", 0, true, 0 },
540 { ARM64::ST2i32, "st2", ".s", 0, true, 0 },
541 { ARM64::ST2i64, "st2", ".d", 0, true, 0 },
542 { ARM64::ST2i8_POST, "st2", ".b", 1, true, 2 },
543 { ARM64::ST2i16_POST, "st2", ".h", 1, true, 4 },
544 { ARM64::ST2i32_POST, "st2", ".s", 1, true, 8 },
545 { ARM64::ST2i64_POST, "st2", ".d", 1, true, 16 },
546 { ARM64::ST2Twov16b, "st2", ".16b", 0, false, 0 },
547 { ARM64::ST2Twov8h, "st2", ".8h", 0, false, 0 },
548 { ARM64::ST2Twov4s, "st2", ".4s", 0, false, 0 },
549 { ARM64::ST2Twov2d, "st2", ".2d", 0, false, 0 },
550 { ARM64::ST2Twov8b, "st2", ".8b", 0, false, 0 },
551 { ARM64::ST2Twov4h, "st2", ".4h", 0, false, 0 },
552 { ARM64::ST2Twov2s, "st2", ".2s", 0, false, 0 },
553 { ARM64::ST2Twov16b_POST, "st2", ".16b", 1, false, 32 },
554 { ARM64::ST2Twov8h_POST, "st2", ".8h", 1, false, 32 },
555 { ARM64::ST2Twov4s_POST, "st2", ".4s", 1, false, 32 },
556 { ARM64::ST2Twov2d_POST, "st2", ".2d", 1, false, 32 },
557 { ARM64::ST2Twov8b_POST, "st2", ".8b", 1, false, 16 },
558 { ARM64::ST2Twov4h_POST, "st2", ".4h", 1, false, 16 },
559 { ARM64::ST2Twov2s_POST, "st2", ".2s", 1, false, 16 },
560 { ARM64::ST3i8, "st3", ".b", 0, true, 0 },
561 { ARM64::ST3i16, "st3", ".h", 0, true, 0 },
562 { ARM64::ST3i32, "st3", ".s", 0, true, 0 },
563 { ARM64::ST3i64, "st3", ".d", 0, true, 0 },
564 { ARM64::ST3i8_POST, "st3", ".b", 1, true, 3 },
565 { ARM64::ST3i16_POST, "st3", ".h", 1, true, 6 },
566 { ARM64::ST3i32_POST, "st3", ".s", 1, true, 12 },
567 { ARM64::ST3i64_POST, "st3", ".d", 1, true, 24 },
568 { ARM64::ST3Threev16b, "st3", ".16b", 0, false, 0 },
569 { ARM64::ST3Threev8h, "st3", ".8h", 0, false, 0 },
570 { ARM64::ST3Threev4s, "st3", ".4s", 0, false, 0 },
571 { ARM64::ST3Threev2d, "st3", ".2d", 0, false, 0 },
572 { ARM64::ST3Threev8b, "st3", ".8b", 0, false, 0 },
573 { ARM64::ST3Threev4h, "st3", ".4h", 0, false, 0 },
574 { ARM64::ST3Threev2s, "st3", ".2s", 0, false, 0 },
575 { ARM64::ST3Threev16b_POST, "st3", ".16b", 1, false, 48 },
576 { ARM64::ST3Threev8h_POST, "st3", ".8h", 1, false, 48 },
577 { ARM64::ST3Threev4s_POST, "st3", ".4s", 1, false, 48 },
578 { ARM64::ST3Threev2d_POST, "st3", ".2d", 1, false, 48 },
579 { ARM64::ST3Threev8b_POST, "st3", ".8b", 1, false, 24 },
580 { ARM64::ST3Threev4h_POST, "st3", ".4h", 1, false, 24 },
581 { ARM64::ST3Threev2s_POST, "st3", ".2s", 1, false, 24 },
582 { ARM64::ST4i8, "st4", ".b", 0, true, 0 },
583 { ARM64::ST4i16, "st4", ".h", 0, true, 0 },
584 { ARM64::ST4i32, "st4", ".s", 0, true, 0 },
585 { ARM64::ST4i64, "st4", ".d", 0, true, 0 },
586 { ARM64::ST4i8_POST, "st4", ".b", 1, true, 4 },
587 { ARM64::ST4i16_POST, "st4", ".h", 1, true, 8 },
588 { ARM64::ST4i32_POST, "st4", ".s", 1, true, 16 },
589 { ARM64::ST4i64_POST, "st4", ".d", 1, true, 32 },
590 { ARM64::ST4Fourv16b, "st4", ".16b", 0, false, 0 },
591 { ARM64::ST4Fourv8h, "st4", ".8h", 0, false, 0 },
592 { ARM64::ST4Fourv4s, "st4", ".4s", 0, false, 0 },
593 { ARM64::ST4Fourv2d, "st4", ".2d", 0, false, 0 },
594 { ARM64::ST4Fourv8b, "st4", ".8b", 0, false, 0 },
595 { ARM64::ST4Fourv4h, "st4", ".4h", 0, false, 0 },
596 { ARM64::ST4Fourv2s, "st4", ".2s", 0, false, 0 },
597 { ARM64::ST4Fourv16b_POST, "st4", ".16b", 1, false, 64 },
598 { ARM64::ST4Fourv8h_POST, "st4", ".8h", 1, false, 64 },
599 { ARM64::ST4Fourv4s_POST, "st4", ".4s", 1, false, 64 },
600 { ARM64::ST4Fourv2d_POST, "st4", ".2d", 1, false, 64 },
601 { ARM64::ST4Fourv8b_POST, "st4", ".8b", 1, false, 32 },
602 { ARM64::ST4Fourv4h_POST, "st4", ".4h", 1, false, 32 },
603 { ARM64::ST4Fourv2s_POST, "st4", ".2s", 1, false, 32 },
606 static LdStNInstrDesc *getLdStNInstrDesc(unsigned Opcode) {
608 for (Idx = 0; Idx != array_lengthof(LdStNInstInfo); ++Idx)
609 if (LdStNInstInfo[Idx].Opcode == Opcode)
610 return &LdStNInstInfo[Idx];
615 void ARM64AppleInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
617 unsigned Opcode = MI->getOpcode();
618 StringRef Layout, Mnemonic;
621 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
622 O << "\t" << (IsTbx ? "tbx" : "tbl") << Layout << '\t'
623 << getRegisterName(MI->getOperand(0).getReg(), ARM64::vreg) << ", ";
625 unsigned ListOpNum = IsTbx ? 2 : 1;
626 printVectorList(MI, ListOpNum, O, "");
629 << getRegisterName(MI->getOperand(ListOpNum + 1).getReg(), ARM64::vreg);
630 printAnnotation(O, Annot);
634 if (LdStNInstrDesc *LdStDesc = getLdStNInstrDesc(Opcode)) {
635 O << "\t" << LdStDesc->Mnemonic << LdStDesc->Layout << '\t';
637 // Now onto the operands: first a vector list with possible lane
638 // specifier. E.g. { v0 }[2]
639 int OpNum = LdStDesc->ListOperand;
640 printVectorList(MI, OpNum++, O, "");
642 if (LdStDesc->HasLane)
643 O << '[' << MI->getOperand(OpNum++).getImm() << ']';
645 // Next the address: [xN]
646 unsigned AddrReg = MI->getOperand(OpNum++).getReg();
647 O << ", [" << getRegisterName(AddrReg) << ']';
649 // Finally, there might be a post-indexed offset.
650 if (LdStDesc->NaturalOffset != 0) {
651 unsigned Reg = MI->getOperand(OpNum++).getReg();
652 if (Reg != ARM64::XZR)
653 O << ", " << getRegisterName(Reg);
655 assert(LdStDesc->NaturalOffset && "no offset on post-inc instruction?");
656 O << ", #" << LdStDesc->NaturalOffset;
660 printAnnotation(O, Annot);
664 ARM64InstPrinter::printInst(MI, O, Annot);
667 bool ARM64InstPrinter::printSysAlias(const MCInst *MI, raw_ostream &O) {
669 unsigned Opcode = MI->getOpcode();
670 assert(Opcode == ARM64::SYSxt && "Invalid opcode for SYS alias!");
673 const char *Asm = nullptr;
674 const MCOperand &Op1 = MI->getOperand(0);
675 const MCOperand &Cn = MI->getOperand(1);
676 const MCOperand &Cm = MI->getOperand(2);
677 const MCOperand &Op2 = MI->getOperand(3);
679 unsigned Op1Val = Op1.getImm();
680 unsigned CnVal = Cn.getImm();
681 unsigned CmVal = Cm.getImm();
682 unsigned Op2Val = Op2.getImm();
691 if (Op1Val == 0 && Op2Val == 0)
695 if (Op1Val == 0 && Op2Val == 0)
697 else if (Op1Val == 3 && Op2Val == 1)
703 if (Op1Val == 3 && Op2Val == 1)
707 if (Op1Val == 0 && Op2Val == 1)
709 if (Op1Val == 0 && Op2Val == 2)
713 if (Op1Val == 3 && Op2Val == 1)
715 else if (Op1Val == 0 && Op2Val == 2)
719 if (Op1Val == 3 && Op2Val == 1)
723 if (Op1Val == 3 && Op2Val == 1)
725 else if (Op1Val == 0 && Op2Val == 2)
738 case 0: Asm = "at\ts1e1r"; break;
739 case 1: Asm = "at\ts1e1w"; break;
740 case 2: Asm = "at\ts1e0r"; break;
741 case 3: Asm = "at\ts1e0w"; break;
748 case 0: Asm = "at\ts1e2r"; break;
749 case 1: Asm = "at\ts1e2w"; break;
750 case 4: Asm = "at\ts12e1r"; break;
751 case 5: Asm = "at\ts12e1w"; break;
752 case 6: Asm = "at\ts12e0r"; break;
753 case 7: Asm = "at\ts12e0w"; break;
760 case 0: Asm = "at\ts1e3r"; break;
761 case 1: Asm = "at\ts1e3w"; break;
767 } else if (CnVal == 8) {
780 case 0: Asm = "tlbi\tvmalle1is"; break;
781 case 1: Asm = "tlbi\tvae1is"; break;
782 case 2: Asm = "tlbi\taside1is"; break;
783 case 3: Asm = "tlbi\tvaae1is"; break;
784 case 5: Asm = "tlbi\tvale1is"; break;
785 case 7: Asm = "tlbi\tvaale1is"; break;
792 case 0: Asm = "tlbi\talle2is"; break;
793 case 1: Asm = "tlbi\tvae2is"; break;
794 case 4: Asm = "tlbi\talle1is"; break;
795 case 5: Asm = "tlbi\tvale2is"; break;
796 case 6: Asm = "tlbi\tvmalls12e1is"; break;
803 case 0: Asm = "tlbi\talle3is"; break;
804 case 1: Asm = "tlbi\tvae3is"; break;
805 case 5: Asm = "tlbi\tvale3is"; break;
818 case 1: Asm = "tlbi\tipas2e1is"; break;
819 case 5: Asm = "tlbi\tipas2le1is"; break;
832 case 1: Asm = "tlbi\tipas2e1"; break;
833 case 5: Asm = "tlbi\tipas2le1"; break;
846 case 0: Asm = "tlbi\tvmalle1"; break;
847 case 1: Asm = "tlbi\tvae1"; break;
848 case 2: Asm = "tlbi\taside1"; break;
849 case 3: Asm = "tlbi\tvaae1"; break;
850 case 5: Asm = "tlbi\tvale1"; break;
851 case 7: Asm = "tlbi\tvaale1"; break;
858 case 0: Asm = "tlbi\talle2"; break;
859 case 1: Asm = "tlbi\tvae2"; break;
860 case 4: Asm = "tlbi\talle1"; break;
861 case 5: Asm = "tlbi\tvale2"; break;
862 case 6: Asm = "tlbi\tvmalls12e1"; break;
869 case 0: Asm = "tlbi\talle3"; break;
870 case 1: Asm = "tlbi\tvae3"; break;
871 case 5: Asm = "tlbi\tvale3"; break;
880 unsigned Reg = MI->getOperand(4).getReg();
883 if (StringRef(Asm).lower().find("all") == StringRef::npos)
884 O << ", " << getRegisterName(Reg);
887 return Asm != nullptr;
890 void ARM64InstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
892 const MCOperand &Op = MI->getOperand(OpNo);
894 unsigned Reg = Op.getReg();
895 O << getRegisterName(Reg);
896 } else if (Op.isImm()) {
897 O << '#' << Op.getImm();
899 assert(Op.isExpr() && "unknown operand kind in printOperand");
904 void ARM64InstPrinter::printHexImm(const MCInst *MI, unsigned OpNo,
906 const MCOperand &Op = MI->getOperand(OpNo);
907 O << format("#%#llx", Op.getImm());
910 void ARM64InstPrinter::printPostIncOperand(const MCInst *MI, unsigned OpNo,
911 unsigned Imm, raw_ostream &O) {
912 const MCOperand &Op = MI->getOperand(OpNo);
914 unsigned Reg = Op.getReg();
915 if (Reg == ARM64::XZR)
918 O << getRegisterName(Reg);
920 assert(0 && "unknown operand kind in printPostIncOperand64");
923 void ARM64InstPrinter::printVRegOperand(const MCInst *MI, unsigned OpNo,
925 const MCOperand &Op = MI->getOperand(OpNo);
926 assert(Op.isReg() && "Non-register vreg operand!");
927 unsigned Reg = Op.getReg();
928 O << getRegisterName(Reg, ARM64::vreg);
931 void ARM64InstPrinter::printSysCROperand(const MCInst *MI, unsigned OpNo,
933 const MCOperand &Op = MI->getOperand(OpNo);
934 assert(Op.isImm() && "System instruction C[nm] operands must be immediates!");
935 O << "c" << Op.getImm();
938 void ARM64InstPrinter::printAddSubImm(const MCInst *MI, unsigned OpNum,
940 const MCOperand &MO = MI->getOperand(OpNum);
942 unsigned Val = (MO.getImm() & 0xfff);
943 assert(Val == MO.getImm() && "Add/sub immediate out of range!");
945 ARM64_AM::getShiftValue(MI->getOperand(OpNum + 1).getImm());
948 printShifter(MI, OpNum + 1, O);
951 *CommentStream << "=#" << (Val << Shift) << '\n';
953 assert(MO.isExpr() && "Unexpected operand type!");
955 printShifter(MI, OpNum + 1, O);
959 void ARM64InstPrinter::printLogicalImm32(const MCInst *MI, unsigned OpNum,
961 uint64_t Val = MI->getOperand(OpNum).getImm();
963 O.write_hex(ARM64_AM::decodeLogicalImmediate(Val, 32));
966 void ARM64InstPrinter::printLogicalImm64(const MCInst *MI, unsigned OpNum,
968 uint64_t Val = MI->getOperand(OpNum).getImm();
970 O.write_hex(ARM64_AM::decodeLogicalImmediate(Val, 64));
973 void ARM64InstPrinter::printShifter(const MCInst *MI, unsigned OpNum,
975 unsigned Val = MI->getOperand(OpNum).getImm();
976 // LSL #0 should not be printed.
977 if (ARM64_AM::getShiftType(Val) == ARM64_AM::LSL &&
978 ARM64_AM::getShiftValue(Val) == 0)
980 O << ", " << ARM64_AM::getShiftExtendName(ARM64_AM::getShiftType(Val)) << " #"
981 << ARM64_AM::getShiftValue(Val);
984 void ARM64InstPrinter::printShiftedRegister(const MCInst *MI, unsigned OpNum,
986 O << getRegisterName(MI->getOperand(OpNum).getReg());
987 printShifter(MI, OpNum + 1, O);
990 void ARM64InstPrinter::printExtendedRegister(const MCInst *MI, unsigned OpNum,
992 O << getRegisterName(MI->getOperand(OpNum).getReg());
993 printArithExtend(MI, OpNum + 1, O);
996 void ARM64InstPrinter::printArithExtend(const MCInst *MI, unsigned OpNum,
998 unsigned Val = MI->getOperand(OpNum).getImm();
999 ARM64_AM::ShiftExtendType ExtType = ARM64_AM::getArithExtendType(Val);
1000 unsigned ShiftVal = ARM64_AM::getArithShiftValue(Val);
1002 // If the destination or first source register operand is [W]SP, print
1003 // UXTW/UXTX as LSL, and if the shift amount is also zero, print nothing at
1005 if (ExtType == ARM64_AM::UXTW || ExtType == ARM64_AM::UXTX) {
1006 unsigned Dest = MI->getOperand(0).getReg();
1007 unsigned Src1 = MI->getOperand(1).getReg();
1008 if ( ((Dest == ARM64::SP || Src1 == ARM64::SP) &&
1009 ExtType == ARM64_AM::UXTX) ||
1010 ((Dest == ARM64::WSP || Src1 == ARM64::WSP) &&
1011 ExtType == ARM64_AM::UXTW) ) {
1013 O << ", lsl #" << ShiftVal;
1017 O << ", " << ARM64_AM::getShiftExtendName(ExtType);
1019 O << " #" << ShiftVal;
1022 void ARM64InstPrinter::printMemExtend(const MCInst *MI, unsigned OpNum,
1023 raw_ostream &O, char SrcRegKind,
1025 unsigned SignExtend = MI->getOperand(OpNum).getImm();
1026 unsigned DoShift = MI->getOperand(OpNum + 1).getImm();
1028 // sxtw, sxtx, uxtw or lsl (== uxtx)
1029 bool IsLSL = !SignExtend && SrcRegKind == 'x';
1033 O << (SignExtend ? 's' : 'u') << "xt" << SrcRegKind;
1035 if (DoShift || IsLSL)
1036 O << " #" << Log2_32(Width / 8);
1039 void ARM64InstPrinter::printCondCode(const MCInst *MI, unsigned OpNum,
1041 ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
1042 O << ARM64CC::getCondCodeName(CC);
1045 void ARM64InstPrinter::printInverseCondCode(const MCInst *MI, unsigned OpNum,
1047 ARM64CC::CondCode CC = (ARM64CC::CondCode)MI->getOperand(OpNum).getImm();
1048 O << ARM64CC::getCondCodeName(ARM64CC::getInvertedCondCode(CC));
1051 void ARM64InstPrinter::printAMNoIndex(const MCInst *MI, unsigned OpNum,
1053 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg()) << ']';
1057 void ARM64InstPrinter::printImmScale(const MCInst *MI, unsigned OpNum,
1059 O << '#' << Scale * MI->getOperand(OpNum).getImm();
1062 void ARM64InstPrinter::printUImm12Offset(const MCInst *MI, unsigned OpNum,
1063 unsigned Scale, raw_ostream &O) {
1064 const MCOperand MO = MI->getOperand(OpNum);
1066 O << "#" << (MO.getImm() * Scale);
1068 assert(MO.isExpr() && "Unexpected operand type!");
1073 void ARM64InstPrinter::printAMIndexedWB(const MCInst *MI, unsigned OpNum,
1074 unsigned Scale, raw_ostream &O) {
1075 const MCOperand MO1 = MI->getOperand(OpNum + 1);
1076 O << '[' << getRegisterName(MI->getOperand(OpNum).getReg());
1078 O << ", #" << (MO1.getImm() * Scale);
1080 assert(MO1.isExpr() && "Unexpected operand type!");
1081 O << ", " << *MO1.getExpr();
1086 void ARM64InstPrinter::printPrefetchOp(const MCInst *MI, unsigned OpNum,
1088 unsigned prfop = MI->getOperand(OpNum).getImm();
1090 StringRef Name = ARM64PRFM::PRFMMapper().toString(prfop, Valid);
1097 void ARM64InstPrinter::printFPImmOperand(const MCInst *MI, unsigned OpNum,
1099 const MCOperand &MO = MI->getOperand(OpNum);
1100 float FPImm = MO.isFPImm() ? MO.getFPImm() : ARM64_AM::getFPImmFloat(MO.getImm());
1102 // 8 decimal places are enough to perfectly represent permitted floats.
1103 O << format("#%.8f", FPImm);
1106 static unsigned getNextVectorRegister(unsigned Reg, unsigned Stride = 1) {
1110 assert(0 && "Vector register expected!");
1111 case ARM64::Q0: Reg = ARM64::Q1; break;
1112 case ARM64::Q1: Reg = ARM64::Q2; break;
1113 case ARM64::Q2: Reg = ARM64::Q3; break;
1114 case ARM64::Q3: Reg = ARM64::Q4; break;
1115 case ARM64::Q4: Reg = ARM64::Q5; break;
1116 case ARM64::Q5: Reg = ARM64::Q6; break;
1117 case ARM64::Q6: Reg = ARM64::Q7; break;
1118 case ARM64::Q7: Reg = ARM64::Q8; break;
1119 case ARM64::Q8: Reg = ARM64::Q9; break;
1120 case ARM64::Q9: Reg = ARM64::Q10; break;
1121 case ARM64::Q10: Reg = ARM64::Q11; break;
1122 case ARM64::Q11: Reg = ARM64::Q12; break;
1123 case ARM64::Q12: Reg = ARM64::Q13; break;
1124 case ARM64::Q13: Reg = ARM64::Q14; break;
1125 case ARM64::Q14: Reg = ARM64::Q15; break;
1126 case ARM64::Q15: Reg = ARM64::Q16; break;
1127 case ARM64::Q16: Reg = ARM64::Q17; break;
1128 case ARM64::Q17: Reg = ARM64::Q18; break;
1129 case ARM64::Q18: Reg = ARM64::Q19; break;
1130 case ARM64::Q19: Reg = ARM64::Q20; break;
1131 case ARM64::Q20: Reg = ARM64::Q21; break;
1132 case ARM64::Q21: Reg = ARM64::Q22; break;
1133 case ARM64::Q22: Reg = ARM64::Q23; break;
1134 case ARM64::Q23: Reg = ARM64::Q24; break;
1135 case ARM64::Q24: Reg = ARM64::Q25; break;
1136 case ARM64::Q25: Reg = ARM64::Q26; break;
1137 case ARM64::Q26: Reg = ARM64::Q27; break;
1138 case ARM64::Q27: Reg = ARM64::Q28; break;
1139 case ARM64::Q28: Reg = ARM64::Q29; break;
1140 case ARM64::Q29: Reg = ARM64::Q30; break;
1141 case ARM64::Q30: Reg = ARM64::Q31; break;
1142 // Vector lists can wrap around.
1151 void ARM64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
1152 raw_ostream &O, StringRef LayoutSuffix) {
1153 unsigned Reg = MI->getOperand(OpNum).getReg();
1157 // Work out how many registers there are in the list (if there is an actual
1159 unsigned NumRegs = 1;
1160 if (MRI.getRegClass(ARM64::DDRegClassID).contains(Reg) ||
1161 MRI.getRegClass(ARM64::QQRegClassID).contains(Reg))
1163 else if (MRI.getRegClass(ARM64::DDDRegClassID).contains(Reg) ||
1164 MRI.getRegClass(ARM64::QQQRegClassID).contains(Reg))
1166 else if (MRI.getRegClass(ARM64::DDDDRegClassID).contains(Reg) ||
1167 MRI.getRegClass(ARM64::QQQQRegClassID).contains(Reg))
1170 // Now forget about the list and find out what the first register is.
1171 if (unsigned FirstReg = MRI.getSubReg(Reg, ARM64::dsub0))
1173 else if (unsigned FirstReg = MRI.getSubReg(Reg, ARM64::qsub0))
1176 // If it's a D-reg, we need to promote it to the equivalent Q-reg before
1177 // printing (otherwise getRegisterName fails).
1178 if (MRI.getRegClass(ARM64::FPR64RegClassID).contains(Reg)) {
1179 const MCRegisterClass &FPR128RC = MRI.getRegClass(ARM64::FPR128RegClassID);
1180 Reg = MRI.getMatchingSuperReg(Reg, ARM64::dsub, &FPR128RC);
1183 for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
1184 O << getRegisterName(Reg, ARM64::vreg) << LayoutSuffix;
1185 if (i + 1 != NumRegs)
1192 void ARM64InstPrinter::printImplicitlyTypedVectorList(const MCInst *MI,
1195 printVectorList(MI, OpNum, O, "");
1198 template <unsigned NumLanes, char LaneKind>
1199 void ARM64InstPrinter::printTypedVectorList(const MCInst *MI, unsigned OpNum,
1201 std::string Suffix(".");
1203 Suffix += itostr(NumLanes) + LaneKind;
1207 printVectorList(MI, OpNum, O, Suffix);
1210 void ARM64InstPrinter::printVectorIndex(const MCInst *MI, unsigned OpNum,
1212 O << "[" << MI->getOperand(OpNum).getImm() << "]";
1215 void ARM64InstPrinter::printAlignedLabel(const MCInst *MI, unsigned OpNum,
1217 const MCOperand &Op = MI->getOperand(OpNum);
1219 // If the label has already been resolved to an immediate offset (say, when
1220 // we're running the disassembler), just print the immediate.
1222 O << "#" << (Op.getImm() << 2);
1226 // If the branch target is simply an address then print it in hex.
1227 const MCConstantExpr *BranchTarget =
1228 dyn_cast<MCConstantExpr>(MI->getOperand(OpNum).getExpr());
1230 if (BranchTarget && BranchTarget->EvaluateAsAbsolute(Address)) {
1232 O.write_hex(Address);
1234 // Otherwise, just print the expression.
1235 O << *MI->getOperand(OpNum).getExpr();
1239 void ARM64InstPrinter::printAdrpLabel(const MCInst *MI, unsigned OpNum,
1241 const MCOperand &Op = MI->getOperand(OpNum);
1243 // If the label has already been resolved to an immediate offset (say, when
1244 // we're running the disassembler), just print the immediate.
1246 O << "#" << (Op.getImm() << 12);
1250 // Otherwise, just print the expression.
1251 O << *MI->getOperand(OpNum).getExpr();
1254 void ARM64InstPrinter::printBarrierOption(const MCInst *MI, unsigned OpNo,
1256 unsigned Val = MI->getOperand(OpNo).getImm();
1257 unsigned Opcode = MI->getOpcode();
1261 if (Opcode == ARM64::ISB)
1262 Name = ARM64ISB::ISBMapper().toString(Val, Valid);
1264 Name = ARM64DB::DBarrierMapper().toString(Val, Valid);
1271 void ARM64InstPrinter::printMRSSystemRegister(const MCInst *MI, unsigned OpNo,
1273 unsigned Val = MI->getOperand(OpNo).getImm();
1276 auto Mapper = ARM64SysReg::MRSMapper(getAvailableFeatures());
1277 std::string Name = Mapper.toString(Val, Valid);
1280 O << StringRef(Name).upper();
1283 void ARM64InstPrinter::printMSRSystemRegister(const MCInst *MI, unsigned OpNo,
1285 unsigned Val = MI->getOperand(OpNo).getImm();
1288 auto Mapper = ARM64SysReg::MSRMapper(getAvailableFeatures());
1289 std::string Name = Mapper.toString(Val, Valid);
1292 O << StringRef(Name).upper();
1295 void ARM64InstPrinter::printSystemPStateField(const MCInst *MI, unsigned OpNo,
1297 unsigned Val = MI->getOperand(OpNo).getImm();
1300 StringRef Name = ARM64PState::PStateMapper().toString(Val, Valid);
1302 O << StringRef(Name.str()).upper();
1307 void ARM64InstPrinter::printSIMDType10Operand(const MCInst *MI, unsigned OpNo,
1309 unsigned RawVal = MI->getOperand(OpNo).getImm();
1310 uint64_t Val = ARM64_AM::decodeAdvSIMDModImmType10(RawVal);
1311 O << format("#%#016llx", Val);