1 //===-- ARM64InstPrinter.h - Convert ARM64 MCInst to assembly syntax ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class prints an ARM64 MCInst to a .s file.
12 //===----------------------------------------------------------------------===//
14 #ifndef ARM64INSTPRINTER_H
15 #define ARM64INSTPRINTER_H
17 #include "MCTargetDesc/ARM64MCTargetDesc.h"
18 #include "llvm/ADT/StringRef.h"
19 #include "llvm/MC/MCInstPrinter.h"
20 #include "llvm/MC/MCSubtargetInfo.h"
26 class ARM64InstPrinter : public MCInstPrinter {
28 ARM64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
29 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
31 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
32 virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
34 // Autogenerated by tblgen.
35 virtual void printInstruction(const MCInst *MI, raw_ostream &O);
36 virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O);
37 virtual StringRef getRegName(unsigned RegNo) const {
38 return getRegisterName(RegNo);
40 static const char *getRegisterName(unsigned RegNo,
41 unsigned AltIdx = ARM64::NoRegAltName);
44 bool printSysAlias(const MCInst *MI, raw_ostream &O);
46 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
47 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
49 void printPostIncOperand1(const MCInst *MI, unsigned OpNo, raw_ostream &O);
50 void printPostIncOperand2(const MCInst *MI, unsigned OpNo, raw_ostream &O);
51 void printPostIncOperand3(const MCInst *MI, unsigned OpNo, raw_ostream &O);
52 void printPostIncOperand4(const MCInst *MI, unsigned OpNo, raw_ostream &O);
53 void printPostIncOperand6(const MCInst *MI, unsigned OpNo, raw_ostream &O);
54 void printPostIncOperand8(const MCInst *MI, unsigned OpNo, raw_ostream &O);
55 void printPostIncOperand12(const MCInst *MI, unsigned OpNo, raw_ostream &O);
56 void printPostIncOperand16(const MCInst *MI, unsigned OpNo, raw_ostream &O);
57 void printPostIncOperand24(const MCInst *MI, unsigned OpNo, raw_ostream &O);
58 void printPostIncOperand32(const MCInst *MI, unsigned OpNo, raw_ostream &O);
59 void printPostIncOperand48(const MCInst *MI, unsigned OpNo, raw_ostream &O);
60 void printPostIncOperand64(const MCInst *MI, unsigned OpNo, raw_ostream &O);
61 void printVRegOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
62 void printSysCROperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
63 void printAddSubImm(const MCInst *MI, unsigned OpNum, raw_ostream &O);
64 void printLogicalImm32(const MCInst *MI, unsigned OpNum, raw_ostream &O);
65 void printLogicalImm64(const MCInst *MI, unsigned OpNum, raw_ostream &O);
66 void printShifter(const MCInst *MI, unsigned OpNum, raw_ostream &O);
67 void printShiftedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
68 void printExtendedRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
69 void printExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O);
70 void printCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
71 void printDotCondCode(const MCInst *MI, unsigned OpNum, raw_ostream &O);
72 void printAlignedBranchTarget(const MCInst *MI, unsigned OpNum,
74 void printAMIndexed(const MCInst *MI, unsigned OpNum, unsigned Scale,
76 void printAMIndexed128(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
77 printAMIndexed(MI, OpNum, 16, O);
80 void printAMIndexed64(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
81 printAMIndexed(MI, OpNum, 8, O);
84 void printAMIndexed32(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
85 printAMIndexed(MI, OpNum, 4, O);
88 void printAMIndexed16(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
89 printAMIndexed(MI, OpNum, 2, O);
92 void printAMIndexed8(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
93 printAMIndexed(MI, OpNum, 1, O);
95 void printAMUnscaled(const MCInst *MI, unsigned OpNum, raw_ostream &O) {
96 printAMIndexed(MI, OpNum, 1, O);
98 void printAMNoIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
99 void printImmScale4(const MCInst *MI, unsigned OpNum, raw_ostream &O);
100 void printImmScale8(const MCInst *MI, unsigned OpNum, raw_ostream &O);
101 void printImmScale16(const MCInst *MI, unsigned OpNum, raw_ostream &O);
102 void printPrefetchOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
103 void printMemoryPostIndexed(const MCInst *MI, unsigned OpNum, raw_ostream &O);
104 void printMemoryPostIndexed32(const MCInst *MI, unsigned OpNum,
106 void printMemoryPostIndexed64(const MCInst *MI, unsigned OpNum,
108 void printMemoryPostIndexed128(const MCInst *MI, unsigned OpNum,
110 void printMemoryRegOffset(const MCInst *MI, unsigned OpNum, raw_ostream &O,
112 void printMemoryRegOffset8(const MCInst *MI, unsigned OpNum, raw_ostream &O);
113 void printMemoryRegOffset16(const MCInst *MI, unsigned OpNum, raw_ostream &O);
114 void printMemoryRegOffset32(const MCInst *MI, unsigned OpNum, raw_ostream &O);
115 void printMemoryRegOffset64(const MCInst *MI, unsigned OpNum, raw_ostream &O);
116 void printMemoryRegOffset128(const MCInst *MI, unsigned OpNum,
119 void printFPImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
121 void printVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O,
122 StringRef LayoutSuffix);
124 /// Print a list of vector registers where the type suffix is implicit
125 /// (i.e. attached to the instruction rather than the registers).
126 void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum,
129 template <unsigned NumLanes, char LaneKind>
130 void printTypedVectorList(const MCInst *MI, unsigned OpNum, raw_ostream &O);
132 void printVectorIndex(const MCInst *MI, unsigned OpNum, raw_ostream &O);
133 void printAdrpLabel(const MCInst *MI, unsigned OpNum, raw_ostream &O);
134 void printBarrierOption(const MCInst *MI, unsigned OpNum, raw_ostream &O);
135 void printMSRSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
136 void printMRSSystemRegister(const MCInst *MI, unsigned OpNum, raw_ostream &O);
137 void printSystemCPSRField(const MCInst *MI, unsigned OpNum, raw_ostream &O);
138 void printSIMDType10Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
141 class ARM64AppleInstPrinter : public ARM64InstPrinter {
143 ARM64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
144 const MCRegisterInfo &MRI, const MCSubtargetInfo &STI);
146 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
148 virtual void printInstruction(const MCInst *MI, raw_ostream &O);
149 virtual bool printAliasInstr(const MCInst *MI, raw_ostream &O);
150 virtual StringRef getRegName(unsigned RegNo) const {
151 return getRegisterName(RegNo);
153 static const char *getRegisterName(unsigned RegNo,
154 unsigned AltIdx = ARM64::NoRegAltName);