1 //===- ARM64AddressingModes.h - ARM64 Addressing Modes ----------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the ARM64 addressing mode implementation stuff.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_ARM64_ARM64ADDRESSINGMODES_H
15 #define LLVM_TARGET_ARM64_ARM64ADDRESSINGMODES_H
17 #include "llvm/ADT/APFloat.h"
18 #include "llvm/ADT/APInt.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/MathExtras.h"
25 /// ARM64_AM - ARM64 Addressing Mode Stuff
28 //===----------------------------------------------------------------------===//
41 /// getShiftName - Get the string encoding for the shift type.
42 static inline const char *getShiftName(ARM64_AM::ShiftType ST) {
44 default: assert(false && "unhandled shift type!");
45 case ARM64_AM::LSL: return "lsl";
46 case ARM64_AM::LSR: return "lsr";
47 case ARM64_AM::ASR: return "asr";
48 case ARM64_AM::ROR: return "ror";
49 case ARM64_AM::MSL: return "msl";
54 /// getShiftType - Extract the shift type.
55 static inline ARM64_AM::ShiftType getShiftType(unsigned Imm) {
56 return ARM64_AM::ShiftType((Imm >> 6) & 0x7);
59 /// getShiftValue - Extract the shift value.
60 static inline unsigned getShiftValue(unsigned Imm) {
64 /// getShifterImm - Encode the shift type and amount:
65 /// imm: 6-bit shift amount
66 /// shifter: 000 ==> lsl
73 static inline unsigned getShifterImm(ARM64_AM::ShiftType ST, unsigned Imm) {
74 assert((Imm & 0x3f) == Imm && "Illegal shifted immedate value!");
75 return (unsigned(ST) << 6) | (Imm & 0x3f);
78 //===----------------------------------------------------------------------===//
94 /// getExtendName - Get the string encoding for the extend type.
95 static inline const char *getExtendName(ARM64_AM::ExtendType ET) {
97 default: assert(false && "unhandled extend type!");
98 case ARM64_AM::UXTB: return "uxtb";
99 case ARM64_AM::UXTH: return "uxth";
100 case ARM64_AM::UXTW: return "uxtw";
101 case ARM64_AM::UXTX: return "uxtx";
102 case ARM64_AM::SXTB: return "sxtb";
103 case ARM64_AM::SXTH: return "sxth";
104 case ARM64_AM::SXTW: return "sxtw";
105 case ARM64_AM::SXTX: return "sxtx";
110 /// getArithShiftValue - get the arithmetic shift value.
111 static inline unsigned getArithShiftValue(unsigned Imm) {
115 /// getExtendType - Extract the extend type for operands of arithmetic ops.
116 static inline ARM64_AM::ExtendType getArithExtendType(unsigned Imm) {
117 return ARM64_AM::ExtendType((Imm >> 3) & 0x7);
120 /// getArithExtendImm - Encode the extend type and shift amount for an
121 /// arithmetic instruction:
122 /// imm: 3-bit extend amount
123 /// shifter: 000 ==> uxtb
133 static inline unsigned getArithExtendImm(ARM64_AM::ExtendType ET,
135 assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!");
136 return (unsigned(ET) << 3) | (Imm & 0x7);
139 /// getMemDoShift - Extract the "do shift" flag value for load/store
141 static inline bool getMemDoShift(unsigned Imm) {
142 return (Imm & 0x1) != 0;
145 /// getExtendType - Extract the extend type for the offset operand of
147 static inline ARM64_AM::ExtendType getMemExtendType(unsigned Imm) {
148 return ARM64_AM::ExtendType((Imm >> 1) & 0x7);
151 /// getExtendImm - Encode the extend type and amount for a load/store inst:
152 /// imm: 3-bit extend amount
153 /// shifter: 000 ==> uxtb
163 static inline unsigned getMemExtendImm(ARM64_AM::ExtendType ET, bool Imm) {
164 assert((Imm & 0x7) == Imm && "Illegal shifted immedate value!");
165 return (unsigned(ET) << 1) | (Imm & 0x7);
168 //===----------------------------------------------------------------------===//
172 /// Pre-fetch operator names.
173 /// The enum values match the encoding values:
174 /// prfop<4:3> 00=preload data, 10=prepare for store
175 /// prfop<2:1> 00=target L1 cache, 01=target L2 cache, 10=target L3 cache,
176 /// prfop<0> 0=non-streaming (temporal), 1=streaming (non-temporal)
178 InvalidPrefetchOp = -1,
193 /// isNamedPrefetchOp - Check if the prefetch-op 5-bit value has a name.
194 static inline bool isNamedPrefetchOp(unsigned prfop) {
196 default: return false;
197 case ARM64_AM::PLDL1KEEP: case ARM64_AM::PLDL1STRM: case ARM64_AM::PLDL2KEEP:
198 case ARM64_AM::PLDL2STRM: case ARM64_AM::PLDL3KEEP: case ARM64_AM::PLDL3STRM:
199 case ARM64_AM::PSTL1KEEP: case ARM64_AM::PSTL1STRM: case ARM64_AM::PSTL2KEEP:
200 case ARM64_AM::PSTL2STRM: case ARM64_AM::PSTL3KEEP: case ARM64_AM::PSTL3STRM:
206 /// getPrefetchOpName - Get the string encoding for the prefetch operator.
207 static inline const char *getPrefetchOpName(ARM64_AM::PrefetchOp prfop) {
209 default: assert(false && "unhandled prefetch-op type!");
210 case ARM64_AM::PLDL1KEEP: return "pldl1keep";
211 case ARM64_AM::PLDL1STRM: return "pldl1strm";
212 case ARM64_AM::PLDL2KEEP: return "pldl2keep";
213 case ARM64_AM::PLDL2STRM: return "pldl2strm";
214 case ARM64_AM::PLDL3KEEP: return "pldl3keep";
215 case ARM64_AM::PLDL3STRM: return "pldl3strm";
216 case ARM64_AM::PSTL1KEEP: return "pstl1keep";
217 case ARM64_AM::PSTL1STRM: return "pstl1strm";
218 case ARM64_AM::PSTL2KEEP: return "pstl2keep";
219 case ARM64_AM::PSTL2STRM: return "pstl2strm";
220 case ARM64_AM::PSTL3KEEP: return "pstl3keep";
221 case ARM64_AM::PSTL3STRM: return "pstl3strm";
226 static inline uint64_t ror(uint64_t elt, unsigned size) {
227 return ((elt & 1) << (size-1)) | (elt >> 1);
230 /// processLogicalImmediate - Determine if an immediate value can be encoded
231 /// as the immediate operand of a logical instruction for the given register
232 /// size. If so, return true with "encoding" set to the encoded value in
233 /// the form N:immr:imms.
234 static inline bool processLogicalImmediate(uint64_t imm, unsigned regSize,
235 uint64_t &encoding) {
236 if (imm == 0ULL || imm == ~0ULL ||
237 (regSize != 64 && (imm >> regSize != 0 || imm == ~0U)))
241 uint64_t eltVal = imm;
243 // First, determine the element size.
244 while (size < regSize) {
245 unsigned numElts = regSize / size;
246 unsigned mask = (1ULL << size) - 1;
247 uint64_t lowestEltVal = imm & mask;
249 bool allMatched = true;
250 for (unsigned i = 1; i < numElts; ++i) {
251 uint64_t currEltVal = (imm >> (i*size)) & mask;
252 if (currEltVal != lowestEltVal) {
259 eltVal = lowestEltVal;
266 // Second, determine the rotation to make the element be: 0^m 1^n.
267 for (unsigned i = 0; i < size; ++i) {
268 eltVal = ror(eltVal, size);
269 uint32_t clz = countLeadingZeros(eltVal) - (64 - size);
270 uint32_t cto = CountTrailingOnes_64(eltVal);
272 if (clz + cto == size) {
273 // Encode in immr the number of RORs it would take to get *from* this
274 // element value to our target value, where i+1 is the number of RORs
275 // to go the opposite direction.
276 unsigned immr = size - (i + 1);
278 // If size has a 1 in the n'th bit, create a value that has zeroes in
279 // bits [0, n] and ones above that.
280 uint64_t nimms = ~(size-1) << 1;
282 // Or the CTO value into the low bits, which must be below the Nth bit
283 // bit mentioned above.
286 // Extract the seventh bit and toggle it to create the N field.
287 unsigned N = ((nimms >> 6) & 1) ^ 1;
289 encoding = (N << 12) | (immr << 6) | (nimms & 0x3f);
297 /// isLogicalImmediate - Return true if the immediate is valid for a logical
298 /// immediate instruction of the given register size. Return false otherwise.
299 static inline bool isLogicalImmediate(uint64_t imm, unsigned regSize) {
301 return processLogicalImmediate(imm, regSize, encoding);
304 /// encodeLogicalImmediate - Return the encoded immediate value for a logical
305 /// immediate instruction of the given register size.
306 static inline uint64_t encodeLogicalImmediate(uint64_t imm, unsigned regSize) {
307 uint64_t encoding = 0;
308 bool res = processLogicalImmediate(imm, regSize, encoding);
309 assert(res && "invalid logical immediate");
314 /// decodeLogicalImmediate - Decode a logical immediate value in the form
315 /// "N:immr:imms" (where the immr and imms fields are each 6 bits) into the
316 /// integer value it represents with regSize bits.
317 static inline uint64_t decodeLogicalImmediate(uint64_t val, unsigned regSize) {
318 // Extract the N, imms, and immr fields.
319 unsigned N = (val >> 12) & 1;
320 unsigned immr = (val >> 6) & 0x3f;
321 unsigned imms = val & 0x3f;
323 assert((regSize == 64 || N == 0) && "undefined logical immediate encoding");
324 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
325 assert(len >= 0 && "undefined logical immediate encoding");
326 unsigned size = (1 << len);
327 unsigned R = immr & (size - 1);
328 unsigned S = imms & (size - 1);
329 assert(S != size - 1 && "undefined logical immediate encoding");
330 uint64_t pattern = (1ULL << (S + 1)) - 1;
331 for (unsigned i = 0; i < R; ++i)
332 pattern = ror(pattern, size);
334 // Replicate the pattern to fill the regSize.
335 while (size != regSize) {
336 pattern |= (pattern << size);
342 /// isValidDecodeLogicalImmediate - Check to see if the logical immediate value
343 /// in the form "N:immr:imms" (where the immr and imms fields are each 6 bits)
344 /// is a valid encoding for an integer value with regSize bits.
345 static inline bool isValidDecodeLogicalImmediate(uint64_t val,
347 // Extract the N and imms fields needed for checking.
348 unsigned N = (val >> 12) & 1;
349 unsigned imms = val & 0x3f;
351 if (regSize == 32 && N != 0) // undefined logical immediate encoding
353 int len = 31 - countLeadingZeros((N << 6) | (~imms & 0x3f));
354 if (len < 0) // undefined logical immediate encoding
356 unsigned size = (1 << len);
357 unsigned S = imms & (size - 1);
358 if (S == size - 1) // undefined logical immediate encoding
364 //===----------------------------------------------------------------------===//
365 // Floating-point Immediates
367 static inline float getFPImmFloat(unsigned Imm) {
368 // We expect an 8-bit binary encoding of a floating-point number here.
374 uint8_t Sign = (Imm >> 7) & 0x1;
375 uint8_t Exp = (Imm >> 4) & 0x7;
376 uint8_t Mantissa = Imm & 0xf;
378 // 8-bit FP iEEEE Float Encoding
379 // abcd efgh aBbbbbbc defgh000 00000000 00000000
384 FPUnion.I |= Sign << 31;
385 FPUnion.I |= ((Exp & 0x4) != 0 ? 0 : 1) << 30;
386 FPUnion.I |= ((Exp & 0x4) != 0 ? 0x1f : 0) << 25;
387 FPUnion.I |= (Exp & 0x3) << 23;
388 FPUnion.I |= Mantissa << 19;
392 /// getFP32Imm - Return an 8-bit floating-point version of the 32-bit
393 /// floating-point value. If the value cannot be represented as an 8-bit
394 /// floating-point value, then return -1.
395 static inline int getFP32Imm(const APInt &Imm) {
396 uint32_t Sign = Imm.lshr(31).getZExtValue() & 1;
397 int32_t Exp = (Imm.lshr(23).getSExtValue() & 0xff) - 127; // -126 to 127
398 int64_t Mantissa = Imm.getZExtValue() & 0x7fffff; // 23 bits
400 // We can handle 4 bits of mantissa.
401 // mantissa = (16+UInt(e:f:g:h))/16.
402 if (Mantissa & 0x7ffff)
405 if ((Mantissa & 0xf) != Mantissa)
408 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
409 if (Exp < -3 || Exp > 4)
411 Exp = ((Exp+3) & 0x7) ^ 4;
413 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
416 static inline int getFP32Imm(const APFloat &FPImm) {
417 return getFP32Imm(FPImm.bitcastToAPInt());
420 /// getFP64Imm - Return an 8-bit floating-point version of the 64-bit
421 /// floating-point value. If the value cannot be represented as an 8-bit
422 /// floating-point value, then return -1.
423 static inline int getFP64Imm(const APInt &Imm) {
424 uint64_t Sign = Imm.lshr(63).getZExtValue() & 1;
425 int64_t Exp = (Imm.lshr(52).getSExtValue() & 0x7ff) - 1023; // -1022 to 1023
426 uint64_t Mantissa = Imm.getZExtValue() & 0xfffffffffffffULL;
428 // We can handle 4 bits of mantissa.
429 // mantissa = (16+UInt(e:f:g:h))/16.
430 if (Mantissa & 0xffffffffffffULL)
433 if ((Mantissa & 0xf) != Mantissa)
436 // We can handle 3 bits of exponent: exp == UInt(NOT(b):c:d)-3
437 if (Exp < -3 || Exp > 4)
439 Exp = ((Exp+3) & 0x7) ^ 4;
441 return ((int)Sign << 7) | (Exp << 4) | Mantissa;
444 static inline int getFP64Imm(const APFloat &FPImm) {
445 return getFP64Imm(FPImm.bitcastToAPInt());
448 //===--------------------------------------------------------------------===//
449 // AdvSIMD Modified Immediates
450 //===--------------------------------------------------------------------===//
452 // 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh
453 static inline bool isAdvSIMDModImmType1(uint64_t Imm) {
454 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
455 ((Imm & 0xffffff00ffffff00ULL) == 0);
458 static inline uint8_t encodeAdvSIMDModImmType1(uint64_t Imm) {
459 return (Imm & 0xffULL);
462 static inline uint64_t decodeAdvSIMDModImmType1(uint8_t Imm) {
463 uint64_t EncVal = Imm;
464 return (EncVal << 32) | EncVal;
467 // 0x00 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00
468 static inline bool isAdvSIMDModImmType2(uint64_t Imm) {
469 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
470 ((Imm & 0xffff00ffffff00ffULL) == 0);
473 static inline uint8_t encodeAdvSIMDModImmType2(uint64_t Imm) {
474 return (Imm & 0xff00ULL) >> 8;
477 static inline uint64_t decodeAdvSIMDModImmType2(uint8_t Imm) {
478 uint64_t EncVal = Imm;
479 return (EncVal << 40) | (EncVal << 8);
482 // 0x00 abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00
483 static inline bool isAdvSIMDModImmType3(uint64_t Imm) {
484 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
485 ((Imm & 0xff00ffffff00ffffULL) == 0);
488 static inline uint8_t encodeAdvSIMDModImmType3(uint64_t Imm) {
489 return (Imm & 0xff0000ULL) >> 16;
492 static inline uint64_t decodeAdvSIMDModImmType3(uint8_t Imm) {
493 uint64_t EncVal = Imm;
494 return (EncVal << 48) | (EncVal << 16);
497 // abcdefgh 0x00 0x00 0x00 abcdefgh 0x00 0x00 0x00
498 static inline bool isAdvSIMDModImmType4(uint64_t Imm) {
499 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
500 ((Imm & 0x00ffffff00ffffffULL) == 0);
503 static inline uint8_t encodeAdvSIMDModImmType4(uint64_t Imm) {
504 return (Imm & 0xff000000ULL) >> 24;
507 static inline uint64_t decodeAdvSIMDModImmType4(uint8_t Imm) {
508 uint64_t EncVal = Imm;
509 return (EncVal << 56) | (EncVal << 24);
512 // 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh
513 static inline bool isAdvSIMDModImmType5(uint64_t Imm) {
514 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
515 (((Imm & 0x00ff0000ULL) >> 16) == (Imm & 0x000000ffULL)) &&
516 ((Imm & 0xff00ff00ff00ff00ULL) == 0);
519 static inline uint8_t encodeAdvSIMDModImmType5(uint64_t Imm) {
520 return (Imm & 0xffULL);
523 static inline uint64_t decodeAdvSIMDModImmType5(uint8_t Imm) {
524 uint64_t EncVal = Imm;
525 return (EncVal << 48) | (EncVal << 32) | (EncVal << 16) | EncVal;
528 // abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00 abcdefgh 0x00
529 static inline bool isAdvSIMDModImmType6(uint64_t Imm) {
530 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
531 (((Imm & 0xff000000ULL) >> 16) == (Imm & 0x0000ff00ULL)) &&
532 ((Imm & 0x00ff00ff00ff00ffULL) == 0);
535 static inline uint8_t encodeAdvSIMDModImmType6(uint64_t Imm) {
536 return (Imm & 0xff00ULL) >> 8;
539 static inline uint64_t decodeAdvSIMDModImmType6(uint8_t Imm) {
540 uint64_t EncVal = Imm;
541 return (EncVal << 56) | (EncVal << 40) | (EncVal << 24) | (EncVal << 8);
544 // 0x00 0x00 abcdefgh 0xFF 0x00 0x00 abcdefgh 0xFF
545 static inline bool isAdvSIMDModImmType7(uint64_t Imm) {
546 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
547 ((Imm & 0xffff00ffffff00ffULL) == 0x000000ff000000ffULL);
550 static inline uint8_t encodeAdvSIMDModImmType7(uint64_t Imm) {
551 return (Imm & 0xff00ULL) >> 8;
554 static inline uint64_t decodeAdvSIMDModImmType7(uint8_t Imm) {
555 uint64_t EncVal = Imm;
556 return (EncVal << 40) | (EncVal << 8) | 0x000000ff000000ffULL;
559 // 0x00 abcdefgh 0xFF 0xFF 0x00 abcdefgh 0xFF 0xFF
560 static inline bool isAdvSIMDModImmType8(uint64_t Imm) {
561 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
562 ((Imm & 0xff00ffffff00ffffULL) == 0x0000ffff0000ffffULL);
565 static inline uint64_t decodeAdvSIMDModImmType8(uint8_t Imm) {
566 uint64_t EncVal = Imm;
567 return (EncVal << 48) | (EncVal << 16) | 0x0000ffff0000ffffULL;
570 static inline uint8_t encodeAdvSIMDModImmType8(uint64_t Imm) {
571 return (Imm & 0x00ff0000ULL) >> 16;
574 // abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh abcdefgh
575 static inline bool isAdvSIMDModImmType9(uint64_t Imm) {
576 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
577 ((Imm >> 48) == (Imm & 0x0000ffffULL)) &&
578 ((Imm >> 56) == (Imm & 0x000000ffULL));
581 static inline uint8_t encodeAdvSIMDModImmType9(uint64_t Imm) {
582 return (Imm & 0xffULL);
585 static inline uint64_t decodeAdvSIMDModImmType9(uint8_t Imm) {
586 uint64_t EncVal = Imm;
587 EncVal |= (EncVal << 8);
588 EncVal |= (EncVal << 16);
589 EncVal |= (EncVal << 32);
593 // aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
594 // cmode: 1110, op: 1
595 static inline bool isAdvSIMDModImmType10(uint64_t Imm) {
596 uint64_t ByteA = Imm & 0xff00000000000000ULL;
597 uint64_t ByteB = Imm & 0x00ff000000000000ULL;
598 uint64_t ByteC = Imm & 0x0000ff0000000000ULL;
599 uint64_t ByteD = Imm & 0x000000ff00000000ULL;
600 uint64_t ByteE = Imm & 0x00000000ff000000ULL;
601 uint64_t ByteF = Imm & 0x0000000000ff0000ULL;
602 uint64_t ByteG = Imm & 0x000000000000ff00ULL;
603 uint64_t ByteH = Imm & 0x00000000000000ffULL;
605 return (ByteA == 0ULL || ByteA == 0xff00000000000000ULL) &&
606 (ByteB == 0ULL || ByteB == 0x00ff000000000000ULL) &&
607 (ByteC == 0ULL || ByteC == 0x0000ff0000000000ULL) &&
608 (ByteD == 0ULL || ByteD == 0x000000ff00000000ULL) &&
609 (ByteE == 0ULL || ByteE == 0x00000000ff000000ULL) &&
610 (ByteF == 0ULL || ByteF == 0x0000000000ff0000ULL) &&
611 (ByteG == 0ULL || ByteG == 0x000000000000ff00ULL) &&
612 (ByteH == 0ULL || ByteH == 0x00000000000000ffULL);
615 static inline uint8_t encodeAdvSIMDModImmType10(uint64_t Imm) {
616 bool BitA = Imm & 0xff00000000000000ULL;
617 bool BitB = Imm & 0x00ff000000000000ULL;
618 bool BitC = Imm & 0x0000ff0000000000ULL;
619 bool BitD = Imm & 0x000000ff00000000ULL;
620 bool BitE = Imm & 0x00000000ff000000ULL;
621 bool BitF = Imm & 0x0000000000ff0000ULL;
622 bool BitG = Imm & 0x000000000000ff00ULL;
623 bool BitH = Imm & 0x00000000000000ffULL;
625 unsigned EncVal = BitA;
643 static inline uint64_t decodeAdvSIMDModImmType10(uint8_t Imm) {
645 if (Imm & 0x80) EncVal |= 0xff00000000000000ULL;
646 if (Imm & 0x40) EncVal |= 0x00ff000000000000ULL;
647 if (Imm & 0x20) EncVal |= 0x0000ff0000000000ULL;
648 if (Imm & 0x10) EncVal |= 0x000000ff00000000ULL;
649 if (Imm & 0x08) EncVal |= 0x00000000ff000000ULL;
650 if (Imm & 0x04) EncVal |= 0x0000000000ff0000ULL;
651 if (Imm & 0x02) EncVal |= 0x000000000000ff00ULL;
652 if (Imm & 0x01) EncVal |= 0x00000000000000ffULL;
656 // aBbbbbbc defgh000 0x00 0x00 aBbbbbbc defgh000 0x00 0x00
657 static inline bool isAdvSIMDModImmType11(uint64_t Imm) {
658 uint64_t BString = (Imm & 0x7E000000ULL) >> 25;
659 return ((Imm >> 32) == (Imm & 0xffffffffULL)) &&
660 (BString == 0x1f || BString == 0x20) &&
661 ((Imm & 0x0007ffff0007ffffULL) == 0);
664 static inline uint8_t encodeAdvSIMDModImmType11(uint64_t Imm) {
665 bool BitA = (Imm & 0x80000000ULL);
666 bool BitB = (Imm & 0x20000000ULL);
667 bool BitC = (Imm & 0x01000000ULL);
668 bool BitD = (Imm & 0x00800000ULL);
669 bool BitE = (Imm & 0x00400000ULL);
670 bool BitF = (Imm & 0x00200000ULL);
671 bool BitG = (Imm & 0x00100000ULL);
672 bool BitH = (Imm & 0x00080000ULL);
674 unsigned EncVal = BitA;
692 static inline uint64_t decodeAdvSIMDModImmType11(uint8_t Imm) {
694 if (Imm & 0x80) EncVal |= 0x80000000ULL;
695 if (Imm & 0x40) EncVal |= 0x3e000000ULL;
696 else EncVal |= 0x40000000ULL;
697 if (Imm & 0x20) EncVal |= 0x01000000ULL;
698 if (Imm & 0x10) EncVal |= 0x00800000ULL;
699 if (Imm & 0x08) EncVal |= 0x00400000ULL;
700 if (Imm & 0x04) EncVal |= 0x00200000ULL;
701 if (Imm & 0x02) EncVal |= 0x00100000ULL;
702 if (Imm & 0x01) EncVal |= 0x00080000ULL;
703 return (EncVal << 32) | EncVal;
706 // aBbbbbbb bbcdefgh 0x00 0x00 0x00 0x00 0x00 0x00
707 static inline bool isAdvSIMDModImmType12(uint64_t Imm) {
708 uint64_t BString = (Imm & 0x7fc0000000000000ULL) >> 54;
709 return ((BString == 0xff || BString == 0x100) &&
710 ((Imm & 0x0000ffffffffffffULL) == 0));
713 static inline uint8_t encodeAdvSIMDModImmType12(uint64_t Imm) {
714 bool BitA = (Imm & 0x8000000000000000ULL);
715 bool BitB = (Imm & 0x0040000000000000ULL);
716 bool BitC = (Imm & 0x0020000000000000ULL);
717 bool BitD = (Imm & 0x0010000000000000ULL);
718 bool BitE = (Imm & 0x0008000000000000ULL);
719 bool BitF = (Imm & 0x0004000000000000ULL);
720 bool BitG = (Imm & 0x0002000000000000ULL);
721 bool BitH = (Imm & 0x0001000000000000ULL);
723 unsigned EncVal = BitA;
741 static inline uint64_t decodeAdvSIMDModImmType12(uint8_t Imm) {
743 if (Imm & 0x80) EncVal |= 0x8000000000000000ULL;
744 if (Imm & 0x40) EncVal |= 0x3fc0000000000000ULL;
745 else EncVal |= 0x4000000000000000ULL;
746 if (Imm & 0x20) EncVal |= 0x0020000000000000ULL;
747 if (Imm & 0x10) EncVal |= 0x0010000000000000ULL;
748 if (Imm & 0x08) EncVal |= 0x0008000000000000ULL;
749 if (Imm & 0x04) EncVal |= 0x0004000000000000ULL;
750 if (Imm & 0x02) EncVal |= 0x0002000000000000ULL;
751 if (Imm & 0x01) EncVal |= 0x0001000000000000ULL;
752 return (EncVal << 32) | EncVal;
755 } // end namespace ARM64_AM
757 } // end namespace llvm