1 //===-- ARM64AsmBackend.cpp - ARM64 Assembler Backend ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "ARM64RegisterInfo.h"
12 #include "MCTargetDesc/ARM64FixupKinds.h"
13 #include "llvm/ADT/Triple.h"
14 #include "llvm/MC/MCAsmBackend.h"
15 #include "llvm/MC/MCDirectives.h"
16 #include "llvm/MC/MCFixupKindInfo.h"
17 #include "llvm/MC/MCObjectWriter.h"
18 #include "llvm/MC/MCSectionMachO.h"
19 #include "llvm/Support/ErrorHandling.h"
20 #include "llvm/Support/MachO.h"
25 class ARM64AsmBackend : public MCAsmBackend {
26 static const unsigned PCRelFlagVal =
27 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits | MCFixupKindInfo::FKF_IsPCRel;
30 ARM64AsmBackend(const Target &T) : MCAsmBackend() {}
32 unsigned getNumFixupKinds() const { return ARM64::NumTargetFixupKinds; }
34 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
35 const static MCFixupKindInfo Infos[ARM64::NumTargetFixupKinds] = {
36 // This table *must* be in the order that the fixup_* kinds are defined in
39 // Name Offset (bits) Size (bits) Flags
40 { "fixup_arm64_pcrel_adr_imm21", 0, 32, PCRelFlagVal },
41 { "fixup_arm64_pcrel_adrp_imm21", 0, 32, PCRelFlagVal },
42 { "fixup_arm64_add_imm12", 10, 12, 0 },
43 { "fixup_arm64_ldst_imm12_scale1", 10, 12, 0 },
44 { "fixup_arm64_ldst_imm12_scale2", 10, 12, 0 },
45 { "fixup_arm64_ldst_imm12_scale4", 10, 12, 0 },
46 { "fixup_arm64_ldst_imm12_scale8", 10, 12, 0 },
47 { "fixup_arm64_ldst_imm12_scale16", 10, 12, 0 },
48 { "fixup_arm64_movw", 5, 16, 0 },
49 { "fixup_arm64_pcrel_branch14", 5, 14, PCRelFlagVal },
50 { "fixup_arm64_pcrel_imm19", 5, 19, PCRelFlagVal },
51 { "fixup_arm64_pcrel_branch26", 0, 26, PCRelFlagVal },
52 { "fixup_arm64_pcrel_call26", 0, 26, PCRelFlagVal },
53 { "fixup_arm64_tlsdesc_call", 0, 0, 0 }
56 if (Kind < FirstTargetFixupKind)
57 return MCAsmBackend::getFixupKindInfo(Kind);
59 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
61 return Infos[Kind - FirstTargetFixupKind];
64 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
65 uint64_t Value, bool IsPCRel) const;
67 bool mayNeedRelaxation(const MCInst &Inst) const;
68 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
69 const MCRelaxableFragment *DF,
70 const MCAsmLayout &Layout) const;
71 void relaxInstruction(const MCInst &Inst, MCInst &Res) const;
72 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
74 void HandleAssemblerFlag(MCAssemblerFlag Flag) {}
76 unsigned getPointerSize() const { return 8; }
79 } // end anonymous namespace
81 /// \brief The number of bytes the fixup may change.
82 static unsigned getFixupKindNumBytes(unsigned Kind) {
85 assert(0 && "Unknown fixup kind!");
87 case ARM64::fixup_arm64_tlsdesc_call:
94 case ARM64::fixup_arm64_movw:
97 case ARM64::fixup_arm64_pcrel_branch14:
98 case ARM64::fixup_arm64_add_imm12:
99 case ARM64::fixup_arm64_ldst_imm12_scale1:
100 case ARM64::fixup_arm64_ldst_imm12_scale2:
101 case ARM64::fixup_arm64_ldst_imm12_scale4:
102 case ARM64::fixup_arm64_ldst_imm12_scale8:
103 case ARM64::fixup_arm64_ldst_imm12_scale16:
104 case ARM64::fixup_arm64_pcrel_imm19:
107 case ARM64::fixup_arm64_pcrel_adr_imm21:
108 case ARM64::fixup_arm64_pcrel_adrp_imm21:
109 case ARM64::fixup_arm64_pcrel_branch26:
110 case ARM64::fixup_arm64_pcrel_call26:
119 static unsigned AdrImmBits(unsigned Value) {
120 unsigned lo2 = Value & 0x3;
121 unsigned hi19 = (Value & 0x1ffffc) >> 2;
122 return (hi19 << 5) | (lo2 << 29);
125 static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
126 int64_t SignedValue = static_cast<int64_t>(Value);
129 assert(false && "Unknown fixup kind!");
130 case ARM64::fixup_arm64_pcrel_adr_imm21:
131 if (SignedValue > 2097151 || SignedValue < -2097152)
132 report_fatal_error("fixup value out of range");
133 return AdrImmBits(Value & 0x1fffffULL);
134 case ARM64::fixup_arm64_pcrel_adrp_imm21:
135 return AdrImmBits((Value & 0x1fffff000ULL) >> 12);
136 case ARM64::fixup_arm64_pcrel_imm19:
137 // Signed 21-bit immediate
138 if (SignedValue > 2097151 || SignedValue < -2097152)
139 report_fatal_error("fixup value out of range");
140 // Low two bits are not encoded.
141 return (Value >> 2) & 0x7ffff;
142 case ARM64::fixup_arm64_add_imm12:
143 case ARM64::fixup_arm64_ldst_imm12_scale1:
144 // Unsigned 12-bit immediate
146 report_fatal_error("invalid imm12 fixup value");
148 case ARM64::fixup_arm64_ldst_imm12_scale2:
149 // Unsigned 12-bit immediate which gets multiplied by 2
150 if (Value & 1 || Value >= 0x2000)
151 report_fatal_error("invalid imm12 fixup value");
153 case ARM64::fixup_arm64_ldst_imm12_scale4:
154 // Unsigned 12-bit immediate which gets multiplied by 4
155 if (Value & 3 || Value >= 0x4000)
156 report_fatal_error("invalid imm12 fixup value");
158 case ARM64::fixup_arm64_ldst_imm12_scale8:
159 // Unsigned 12-bit immediate which gets multiplied by 8
160 if (Value & 7 || Value >= 0x8000)
161 report_fatal_error("invalid imm12 fixup value");
163 case ARM64::fixup_arm64_ldst_imm12_scale16:
164 // Unsigned 12-bit immediate which gets multiplied by 16
165 if (Value & 15 || Value >= 0x10000)
166 report_fatal_error("invalid imm12 fixup value");
168 case ARM64::fixup_arm64_movw:
169 report_fatal_error("no resolvable MOVZ/MOVK fixups supported yet");
171 case ARM64::fixup_arm64_pcrel_branch14:
172 // Signed 16-bit immediate
173 if (SignedValue > 32767 || SignedValue < -32768)
174 report_fatal_error("fixup value out of range");
175 // Low two bits are not encoded (4-byte alignment assumed).
177 report_fatal_error("fixup not sufficiently aligned");
178 return (Value >> 2) & 0x3fff;
179 case ARM64::fixup_arm64_pcrel_branch26:
180 case ARM64::fixup_arm64_pcrel_call26:
181 // Signed 28-bit immediate
182 if (SignedValue > 134217727 || SignedValue < -134217728)
183 report_fatal_error("fixup value out of range");
184 // Low two bits are not encoded (4-byte alignment assumed).
186 report_fatal_error("fixup not sufficiently aligned");
187 return (Value >> 2) & 0x3ffffff;
196 void ARM64AsmBackend::applyFixup(const MCFixup &Fixup, char *Data,
197 unsigned DataSize, uint64_t Value,
198 bool IsPCRel) const {
199 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind());
201 return; // Doesn't change encoding.
202 MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
203 // Apply any target-specific value adjustments.
204 Value = adjustFixupValue(Fixup.getKind(), Value);
206 // Shift the value into position.
207 Value <<= Info.TargetOffset;
209 unsigned Offset = Fixup.getOffset();
210 assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
212 // For each byte of the fragment that the fixup touches, mask in the
213 // bits from the fixup value.
214 for (unsigned i = 0; i != NumBytes; ++i)
215 Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
218 bool ARM64AsmBackend::mayNeedRelaxation(const MCInst &Inst) const {
222 bool ARM64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
223 const MCRelaxableFragment *DF,
224 const MCAsmLayout &Layout) const {
225 // FIXME: This isn't correct for ARM64. Just moving the "generic" logic
226 // into the targets for now.
228 // Relax if the value is too big for a (signed) i8.
229 return int64_t(Value) != int64_t(int8_t(Value));
232 void ARM64AsmBackend::relaxInstruction(const MCInst &Inst, MCInst &Res) const {
233 assert(false && "ARM64AsmBackend::relaxInstruction() unimplemented");
236 bool ARM64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
237 // If the count is not 4-byte aligned, we must be writing data into the text
238 // section (otherwise we have unaligned instructions, and thus have far
239 // bigger problems), so just write zeros instead.
240 if ((Count & 3) != 0) {
241 for (uint64_t i = 0, e = (Count & 3); i != e; ++i)
245 // We are properly aligned, so write NOPs as requested.
247 for (uint64_t i = 0; i != Count; ++i)
248 OW->Write32(0xd503201f);
256 /// \brief Compact unwind encoding values.
257 enum CompactUnwindEncodings {
258 /// \brief A "frameless" leaf function, where no non-volatile registers are
259 /// saved. The return remains in LR throughout the function.
260 UNWIND_ARM64_MODE_FRAMELESS = 0x02000000,
262 /// \brief No compact unwind encoding available. Instead the low 23-bits of
263 /// the compact unwind encoding is the offset of the DWARF FDE in the
264 /// __eh_frame section. This mode is never used in object files. It is only
265 /// generated by the linker in final linked images, which have only DWARF info
267 UNWIND_ARM64_MODE_DWARF = 0x03000000,
269 /// \brief This is a standard arm64 prologue where FP/LR are immediately
270 /// pushed on the stack, then SP is copied to FP. If there are any
271 /// non-volatile register saved, they are copied into the stack fame in pairs
272 /// in a contiguous ranger right below the saved FP/LR pair. Any subset of the
273 /// five X pairs and four D pairs can be saved, but the memory layout must be
274 /// in register number order.
275 UNWIND_ARM64_MODE_FRAME = 0x04000000,
277 /// \brief Frame register pair encodings.
278 UNWIND_ARM64_FRAME_X19_X20_PAIR = 0x00000001,
279 UNWIND_ARM64_FRAME_X21_X22_PAIR = 0x00000002,
280 UNWIND_ARM64_FRAME_X23_X24_PAIR = 0x00000004,
281 UNWIND_ARM64_FRAME_X25_X26_PAIR = 0x00000008,
282 UNWIND_ARM64_FRAME_X27_X28_PAIR = 0x00000010,
283 UNWIND_ARM64_FRAME_D8_D9_PAIR = 0x00000100,
284 UNWIND_ARM64_FRAME_D10_D11_PAIR = 0x00000200,
285 UNWIND_ARM64_FRAME_D12_D13_PAIR = 0x00000400,
286 UNWIND_ARM64_FRAME_D14_D15_PAIR = 0x00000800
289 } // end CU namespace
291 // FIXME: This should be in a separate file.
292 class DarwinARM64AsmBackend : public ARM64AsmBackend {
293 const MCRegisterInfo &MRI;
295 /// \brief Encode compact unwind stack adjustment for frameless functions.
296 /// See UNWIND_ARM64_FRAMELESS_STACK_SIZE_MASK in compact_unwind_encoding.h.
297 /// The stack size always needs to be 16 byte aligned.
298 uint32_t encodeStackAdjustment(uint32_t StackSize) const {
299 return (StackSize / 16) << 12;
303 DarwinARM64AsmBackend(const Target &T, const MCRegisterInfo &MRI)
304 : ARM64AsmBackend(T), MRI(MRI) {}
306 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
307 return createARM64MachObjectWriter(OS, MachO::CPU_TYPE_ARM64,
308 MachO::CPU_SUBTYPE_ARM64_ALL);
311 virtual bool doesSectionRequireSymbols(const MCSection &Section) const {
312 // Any section for which the linker breaks things into atoms needs to
313 // preserve symbols, including assembler local symbols, to identify
314 // those atoms. These sections are:
317 // S_CSTRING_LITERALS (e.g. __cstring)
318 // S_LITERAL_POINTERS (e.g. objc selector pointers)
319 // S_16BYTE_LITERALS, S_8BYTE_LITERALS, S_4BYTE_LITERALS
326 // __DATA,__objc_classrefs
327 // __DATA,__objc_catlist
329 // FIXME: It would be better if the compiler used actual linker local
330 // symbols for each of these sections rather than preserving what
331 // are ostensibly assembler local symbols.
332 const MCSectionMachO &SMO = static_cast<const MCSectionMachO &>(Section);
333 return (SMO.getType() == MachO::S_CSTRING_LITERALS ||
334 SMO.getType() == MachO::S_4BYTE_LITERALS ||
335 SMO.getType() == MachO::S_8BYTE_LITERALS ||
336 SMO.getType() == MachO::S_16BYTE_LITERALS ||
337 SMO.getType() == MachO::S_LITERAL_POINTERS ||
338 (SMO.getSegmentName() == "__TEXT" &&
339 (SMO.getSectionName() == "__eh_frame" ||
340 SMO.getSectionName() == "__ustring")) ||
341 (SMO.getSegmentName() == "__DATA" &&
342 (SMO.getSectionName() == "__cfstring" ||
343 SMO.getSectionName() == "__objc_classrefs" ||
344 SMO.getSectionName() == "__objc_catlist")));
347 /// \brief Generate the compact unwind encoding from the CFI directives.
349 generateCompactUnwindEncoding(ArrayRef<MCCFIInstruction> Instrs) const
352 return CU::UNWIND_ARM64_MODE_FRAMELESS;
355 unsigned StackSize = 0;
357 uint32_t CompactUnwindEncoding = 0;
358 for (size_t i = 0, e = Instrs.size(); i != e; ++i) {
359 const MCCFIInstruction &Inst = Instrs[i];
361 switch (Inst.getOperation()) {
363 // Cannot handle this directive: bail out.
364 return CU::UNWIND_ARM64_MODE_DWARF;
365 case MCCFIInstruction::OpDefCfa: {
366 // Defines a frame pointer.
367 assert(getXRegFromWReg(MRI.getLLVMRegNum(Inst.getRegister(), true)) ==
369 "Invalid frame pointer!");
370 assert(i + 2 < e && "Insufficient CFI instructions to define a frame!");
372 const MCCFIInstruction &LRPush = Instrs[++i];
373 assert(LRPush.getOperation() == MCCFIInstruction::OpOffset &&
374 "Link register not pushed!");
375 const MCCFIInstruction &FPPush = Instrs[++i];
376 assert(FPPush.getOperation() == MCCFIInstruction::OpOffset &&
377 "Frame pointer not pushed!");
379 unsigned LRReg = MRI.getLLVMRegNum(LRPush.getRegister(), true);
380 unsigned FPReg = MRI.getLLVMRegNum(FPPush.getRegister(), true);
382 LRReg = getXRegFromWReg(LRReg);
383 FPReg = getXRegFromWReg(FPReg);
385 assert(LRReg == ARM64::LR && FPReg == ARM64::FP &&
386 "Pushing invalid registers for frame!");
388 // Indicate that the function has a frame.
389 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAME;
393 case MCCFIInstruction::OpDefCfaOffset: {
394 assert(StackSize == 0 && "We already have the CFA offset!");
395 StackSize = std::abs(Inst.getOffset());
398 case MCCFIInstruction::OpOffset: {
399 // Registers are saved in pairs. We expect there to be two consecutive
400 // `.cfi_offset' instructions with the appropriate registers specified.
401 unsigned Reg1 = MRI.getLLVMRegNum(Inst.getRegister(), true);
403 return CU::UNWIND_ARM64_MODE_DWARF;
405 const MCCFIInstruction &Inst2 = Instrs[++i];
406 if (Inst2.getOperation() != MCCFIInstruction::OpOffset)
407 return CU::UNWIND_ARM64_MODE_DWARF;
408 unsigned Reg2 = MRI.getLLVMRegNum(Inst2.getRegister(), true);
410 // N.B. The encodings must be in register number order, and the X
411 // registers before the D registers.
413 // X19/X20 pair = 0x00000001,
414 // X21/X22 pair = 0x00000002,
415 // X23/X24 pair = 0x00000004,
416 // X25/X26 pair = 0x00000008,
417 // X27/X28 pair = 0x00000010
418 Reg1 = getXRegFromWReg(Reg1);
419 Reg2 = getXRegFromWReg(Reg2);
421 if (Reg1 == ARM64::X19 && Reg2 == ARM64::X20 &&
422 (CompactUnwindEncoding & 0xF1E) == 0)
423 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X19_X20_PAIR;
424 else if (Reg1 == ARM64::X21 && Reg2 == ARM64::X22 &&
425 (CompactUnwindEncoding & 0xF1C) == 0)
426 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X21_X22_PAIR;
427 else if (Reg1 == ARM64::X23 && Reg2 == ARM64::X24 &&
428 (CompactUnwindEncoding & 0xF18) == 0)
429 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X23_X24_PAIR;
430 else if (Reg1 == ARM64::X25 && Reg2 == ARM64::X26 &&
431 (CompactUnwindEncoding & 0xF10) == 0)
432 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X25_X26_PAIR;
433 else if (Reg1 == ARM64::X27 && Reg2 == ARM64::X28 &&
434 (CompactUnwindEncoding & 0xF00) == 0)
435 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_X27_X28_PAIR;
437 Reg1 = getDRegFromBReg(Reg1);
438 Reg2 = getDRegFromBReg(Reg2);
440 // D8/D9 pair = 0x00000100,
441 // D10/D11 pair = 0x00000200,
442 // D12/D13 pair = 0x00000400,
443 // D14/D15 pair = 0x00000800
444 if (Reg1 == ARM64::D8 && Reg2 == ARM64::D9 &&
445 (CompactUnwindEncoding & 0xE00) == 0)
446 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D8_D9_PAIR;
447 else if (Reg1 == ARM64::D10 && Reg2 == ARM64::D11 &&
448 (CompactUnwindEncoding & 0xC00) == 0)
449 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D10_D11_PAIR;
450 else if (Reg1 == ARM64::D12 && Reg2 == ARM64::D13 &&
451 (CompactUnwindEncoding & 0x800) == 0)
452 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D12_D13_PAIR;
453 else if (Reg1 == ARM64::D14 && Reg2 == ARM64::D15)
454 CompactUnwindEncoding |= CU::UNWIND_ARM64_FRAME_D14_D15_PAIR;
456 // A pair was pushed which we cannot handle.
457 return CU::UNWIND_ARM64_MODE_DWARF;
466 // With compact unwind info we can only represent stack adjustments of up
468 if (StackSize > 65520)
469 return CU::UNWIND_ARM64_MODE_DWARF;
471 CompactUnwindEncoding |= CU::UNWIND_ARM64_MODE_FRAMELESS;
472 CompactUnwindEncoding |= encodeStackAdjustment(StackSize);
475 return CompactUnwindEncoding;
479 } // end anonymous namespace
483 class ELFARM64AsmBackend : public ARM64AsmBackend {
488 ELFARM64AsmBackend(const Target &T, uint8_t OSABI, bool IsLittleEndian)
489 : ARM64AsmBackend(T), OSABI(OSABI), IsLittleEndian(IsLittleEndian) {}
491 MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
492 return createARM64ELFObjectWriter(OS, OSABI, IsLittleEndian);
495 void processFixupValue(const MCAssembler &Asm, const MCAsmLayout &Layout,
496 const MCFixup &Fixup, const MCFragment *DF,
497 const MCValue &Target, uint64_t &Value,
498 bool &IsResolved) override;
501 void ELFARM64AsmBackend::processFixupValue(const MCAssembler &Asm,
502 const MCAsmLayout &Layout,
503 const MCFixup &Fixup,
504 const MCFragment *DF,
505 const MCValue &Target,
506 uint64_t &Value, bool &IsResolved) {
507 // The ADRP instruction adds some multiple of 0x1000 to the current PC &
508 // ~0xfff. This means that the required offset to reach a symbol can vary by
509 // up to one step depending on where the ADRP is in memory. For example:
514 // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
515 // we'll need that as an offset. At any other address "there" will be in the
516 // same page as the ADRP and the instruction should encode 0x0. Assuming the
517 // section isn't 0x1000-aligned, we therefore need to delegate this decision
518 // to the linker -- a relocation!
519 if ((uint32_t)Fixup.getKind() == ARM64::fixup_arm64_pcrel_adrp_imm21)
524 MCAsmBackend *llvm::createARM64leAsmBackend(const Target &T,
525 const MCRegisterInfo &MRI,
526 StringRef TT, StringRef CPU) {
527 Triple TheTriple(TT);
529 if (TheTriple.isOSDarwin())
530 return new DarwinARM64AsmBackend(T, MRI);
532 assert(TheTriple.isOSBinFormatELF() && "Expect either MachO or ELF target");
533 return new ELFARM64AsmBackend(T, TheTriple.getOS(), /*IsLittleEndian=*/true);
536 MCAsmBackend *llvm::createARM64beAsmBackend(const Target &T,
537 const MCRegisterInfo &MRI,
538 StringRef TT, StringRef CPU) {
539 Triple TheTriple(TT);
541 assert(TheTriple.isOSBinFormatELF() && "Big endian is only supported for ELF targets!");
542 return new ELFARM64AsmBackend(T, TheTriple.getOS(), /*IsLittleEndian=*/false);