lib/Target/Alpha/Alpha.td

   1 //===- Alpha.td - Describe the Alpha Target Machine --------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file was developed by the LLVM research group and is distributed under
   6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 // Get the target-independent interfaces which we are implementing...
  14 //
  15 include "../Target.td"
  16
  17 //Alpha is little endian
  18
  19 //===----------------------------------------------------------------------===//
  20 // Subtarget Features
  21 //===----------------------------------------------------------------------===//
  22
  23 def FeatureCIX : SubtargetFeature<"CIX", "HasCT", "true",
  24                                   "Enable CIX extentions">;
  25 def FeatureFIX : SubtargetFeature<"FIX", "HasF2I", "true",
  26                                   "Enable FIX extentions">;
  27
  28 //===----------------------------------------------------------------------===//
  29 // Register File Description
  30 //===----------------------------------------------------------------------===//
  31
  32 include "AlphaRegisterInfo.td"
  33
  34 //===----------------------------------------------------------------------===//
  35 // Schedule Description
  36 //===----------------------------------------------------------------------===//
  37
  38 include "AlphaSchedule.td"
  39
  40 //===----------------------------------------------------------------------===//
  41 // Instruction Descriptions
  42 //===----------------------------------------------------------------------===//
  43
  44 include "AlphaInstrInfo.td"
  45
  46 def AlphaInstrInfo : InstrInfo {
  47   // Define how we want to layout our target-specific information field.
  48  // let TSFlagsFields = [];
  49  // let TSFlagsShifts = [];
  50 }
  51
  52 //===----------------------------------------------------------------------===//
  53 // Alpha Processor Definitions
  54 //===----------------------------------------------------------------------===//
  55
  56 def : Processor<"generic", Alpha21264Itineraries, []>;
  57 def : Processor<"pca56"  , Alpha21264Itineraries, []>;
  58 def : Processor<"ev56"   , Alpha21264Itineraries, []>;
  59 def : Processor<"ev6"    , Alpha21264Itineraries, [FeatureFIX]>;
  60 def : Processor<"ev67"   , Alpha21264Itineraries, [FeatureFIX, FeatureCIX]>;
  61
  62 //===----------------------------------------------------------------------===//
  63 // The Alpha Target
  64 //===----------------------------------------------------------------------===//
  65
  66
  67 def Alpha : Target {
  68   // Pointers on Alpha are 64-bits in size.
  69   let PointerType = i64;
  70
  71   let CalleeSavedRegisters =
  72         //saved regs
  73         [R9, R10, R11, R12, R13, R14,
  74         //Frame pointer
  75 //      R15,
  76         //return address
  77 //      R26,
  78         //Stack Pointer
  79 //      R30,
  80          F2, F3, F4, F5, F6, F7, F8, F9];
  81
  82   // Pull in Instruction Info:
  83   let InstructionSet = AlphaInstrInfo;
  84 }