1 //===-- Alpha/AlphaCodeEmitter.cpp - Convert Alpha code to machine code ---===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the pass that transforms the Alpha machine instructions
11 // into relocatable machine code.
13 //===----------------------------------------------------------------------===//
15 #define DEBUG_TYPE "alpha-emitter"
16 #include "AlphaTargetMachine.h"
17 #include "AlphaRelocations.h"
19 #include "llvm/PassManager.h"
20 #include "llvm/CodeGen/MachineCodeEmitter.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstr.h"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/Function.h"
25 #include "llvm/Support/Debug.h"
29 class AlphaCodeEmitter : public MachineFunctionPass {
30 const AlphaInstrInfo *II;
32 MachineCodeEmitter &MCE;
34 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr
36 int getMachineOpValue(MachineInstr &MI, MachineOperand &MO);
39 explicit AlphaCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce)
40 : II(0), TM(tm), MCE(mce) {}
41 AlphaCodeEmitter(TargetMachine &tm, MachineCodeEmitter &mce,
42 const AlphaInstrInfo& ii)
43 : II(&ii), TM(tm), MCE(mce) {}
45 bool runOnMachineFunction(MachineFunction &MF);
47 virtual const char *getPassName() const {
48 return "Alpha Machine Code Emitter";
51 void emitInstruction(const MachineInstr &MI);
53 /// getBinaryCodeForInstr - This function, generated by the
54 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
55 /// machine instructions.
57 unsigned getBinaryCodeForInstr(MachineInstr &MI);
60 void emitBasicBlock(MachineBasicBlock &MBB);
65 /// createAlphaCodeEmitterPass - Return a pass that emits the collected Alpha code
66 /// to the specified MCE object.
67 FunctionPass *llvm::createAlphaCodeEmitterPass(AlphaTargetMachine &TM,
68 MachineCodeEmitter &MCE) {
69 return new AlphaCodeEmitter(TM, MCE);
72 bool AlphaCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
73 II = ((AlphaTargetMachine&)MF.getTarget()).getInstrInfo();
76 MCE.startFunction(MF);
77 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
79 } while (MCE.finishFunction(MF));
84 void AlphaCodeEmitter::emitBasicBlock(MachineBasicBlock &MBB) {
85 MCE.StartMachineBasicBlock(&MBB);
86 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
88 MachineInstr &MI = *I;
89 switch(MI.getOpcode()) {
91 MCE.emitWordLE(getBinaryCodeForInstr(*I));
104 static unsigned getAlphaRegNumber(unsigned Reg) {
106 case Alpha::R0 : case Alpha::F0 : return 0;
107 case Alpha::R1 : case Alpha::F1 : return 1;
108 case Alpha::R2 : case Alpha::F2 : return 2;
109 case Alpha::R3 : case Alpha::F3 : return 3;
110 case Alpha::R4 : case Alpha::F4 : return 4;
111 case Alpha::R5 : case Alpha::F5 : return 5;
112 case Alpha::R6 : case Alpha::F6 : return 6;
113 case Alpha::R7 : case Alpha::F7 : return 7;
114 case Alpha::R8 : case Alpha::F8 : return 8;
115 case Alpha::R9 : case Alpha::F9 : return 9;
116 case Alpha::R10 : case Alpha::F10 : return 10;
117 case Alpha::R11 : case Alpha::F11 : return 11;
118 case Alpha::R12 : case Alpha::F12 : return 12;
119 case Alpha::R13 : case Alpha::F13 : return 13;
120 case Alpha::R14 : case Alpha::F14 : return 14;
121 case Alpha::R15 : case Alpha::F15 : return 15;
122 case Alpha::R16 : case Alpha::F16 : return 16;
123 case Alpha::R17 : case Alpha::F17 : return 17;
124 case Alpha::R18 : case Alpha::F18 : return 18;
125 case Alpha::R19 : case Alpha::F19 : return 19;
126 case Alpha::R20 : case Alpha::F20 : return 20;
127 case Alpha::R21 : case Alpha::F21 : return 21;
128 case Alpha::R22 : case Alpha::F22 : return 22;
129 case Alpha::R23 : case Alpha::F23 : return 23;
130 case Alpha::R24 : case Alpha::F24 : return 24;
131 case Alpha::R25 : case Alpha::F25 : return 25;
132 case Alpha::R26 : case Alpha::F26 : return 26;
133 case Alpha::R27 : case Alpha::F27 : return 27;
134 case Alpha::R28 : case Alpha::F28 : return 28;
135 case Alpha::R29 : case Alpha::F29 : return 29;
136 case Alpha::R30 : case Alpha::F30 : return 30;
137 case Alpha::R31 : case Alpha::F31 : return 31;
139 assert(0 && "Unhandled reg");
144 int AlphaCodeEmitter::getMachineOpValue(MachineInstr &MI, MachineOperand &MO) {
146 int rv = 0; // Return value; defaults to 0 for unhandled cases
147 // or things that get fixed up later by the JIT.
149 if (MO.isRegister()) {
150 rv = getAlphaRegNumber(MO.getReg());
151 } else if (MO.isImmediate()) {
152 rv = MO.getImmedValue();
153 } else if (MO.isGlobalAddress() || MO.isExternalSymbol()
154 || MO.isConstantPoolIndex()) {
155 DOUT << MO << " is a relocated op for " << MI << "\n";
159 switch (MI.getOpcode()) {
161 Reloc = Alpha::reloc_bsr;
176 Reloc = Alpha::reloc_gprellow;
179 Reloc = Alpha::reloc_gprelhigh;
182 Reloc = Alpha::reloc_literal;
187 Reloc = Alpha::reloc_gpdist;
188 Offset = MI.getOperand(3).getImmedValue();
191 assert(0 && "unknown relocatable instruction");
194 if (MO.isGlobalAddress())
195 MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(),
196 Reloc, MO.getGlobal(), Offset,
198 else if (MO.isExternalSymbol())
199 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
200 Reloc, MO.getSymbolName(), Offset,
203 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
204 Reloc, MO.getConstantPoolIndex(),
206 } else if (MO.isMachineBasicBlock()) {
207 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
209 MO.getMachineBasicBlock()));
211 cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n";
219 #include "AlphaGenCodeEmitter.inc"