1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Constants.h"
26 #include "llvm/DerivedTypes.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
39 //===--------------------------------------------------------------------===//
40 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
41 /// instructions for SelectionDAG operations.
42 class AlphaDAGToDAGISel : public SelectionDAGISel {
43 static const int64_t IMM_LOW = -32768;
44 static const int64_t IMM_HIGH = 32767;
45 static const int64_t IMM_MULT = 65536;
46 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
47 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
49 static int64_t get_ldah16(int64_t x) {
50 int64_t y = x / IMM_MULT;
51 if (x % IMM_MULT > IMM_HIGH)
56 static int64_t get_lda16(int64_t x) {
57 return x - get_ldah16(x) * IMM_MULT;
60 /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
61 /// instruction (if not, return 0). Note that this code accepts partial
62 /// zap masks. For example (and LHS, 1) is a valid zap, as long we know
63 /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
64 /// in checking mode. If LHS is null, we assume that the mask has already
65 /// been validated before.
66 uint64_t get_zapImm(SDValue LHS, uint64_t Constant) {
67 uint64_t BitsToCheck = 0;
69 for (unsigned i = 0; i != 8; ++i) {
70 if (((Constant >> 8*i) & 0xFF) == 0) {
74 if (((Constant >> 8*i) & 0xFF) == 0xFF) {
75 // If the entire byte is set, zapnot the byte.
76 } else if (LHS.getNode() == 0) {
77 // Otherwise, if the mask was previously validated, we know its okay
78 // to zapnot this entire byte even though all the bits aren't set.
80 // Otherwise we don't know that the it's okay to zapnot this entire
81 // byte. Only do this iff we can prove that the missing bits are
82 // already null, so the bytezap doesn't need to really null them.
83 BitsToCheck |= ~Constant & (0xFF << 8*i);
88 // If there are missing bits in a byte (for example, X & 0xEF00), check to
89 // see if the missing bits (0x1000) are already known zero if not, the zap
90 // isn't okay to do, as it won't clear all the required bits.
92 !CurDAG->MaskedValueIsZero(LHS,
93 APInt(LHS.getValueSizeInBits(),
100 static uint64_t get_zapImm(uint64_t x) {
102 for(int i = 0; i != 8; ++i) {
103 if ((x & 0x00FF) == 0x00FF)
105 else if ((x & 0x00FF) != 0)
113 static uint64_t getNearPower2(uint64_t x) {
115 unsigned at = CountLeadingZeros_64(x);
116 uint64_t complow = 1 << (63 - at);
117 uint64_t comphigh = 1 << (64 - at);
118 //cerr << x << ":" << complow << ":" << comphigh << "\n";
119 if (abs(complow - x) <= abs(comphigh - x))
125 static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
126 uint64_t y = getNearPower2(x);
133 static bool isFPZ(SDValue N) {
134 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
135 return (CN && (CN->getValueAPF().isZero()));
137 static bool isFPZn(SDValue N) {
138 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
139 return (CN && CN->getValueAPF().isNegZero());
141 static bool isFPZp(SDValue N) {
142 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
143 return (CN && CN->getValueAPF().isPosZero());
147 explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
148 : SelectionDAGISel(*TM.getTargetLowering())
151 /// getI64Imm - Return a target constant with the specified value, of type
153 inline SDValue getI64Imm(int64_t Imm) {
154 return CurDAG->getTargetConstant(Imm, MVT::i64);
157 // Select - Convert the specified operand from a target-independent to a
158 // target-specific node if it hasn't already been changed.
159 SDNode *Select(SDValue Op);
161 /// InstructionSelect - This callback is invoked by
162 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
163 virtual void InstructionSelect();
165 virtual const char *getPassName() const {
166 return "Alpha DAG->DAG Pattern Instruction Selection";
169 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
170 /// inline asm expressions.
171 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
173 std::vector<SDValue> &OutOps) {
175 switch (ConstraintCode) {
176 default: return true;
183 OutOps.push_back(Op0);
187 // Include the pieces autogenerated from the target description.
188 #include "AlphaGenDAGISel.inc"
191 SDValue getGlobalBaseReg();
192 SDValue getGlobalRetAddr();
193 void SelectCALL(SDValue Op);
198 /// getGlobalBaseReg - Output the instructions required to put the
199 /// GOT address into a register.
201 SDValue AlphaDAGToDAGISel::getGlobalBaseReg() {
203 for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
204 ee = RegInfo->livein_end(); ii != ee; ++ii)
205 if (ii->first == Alpha::R29) {
209 assert(GP && "GOT PTR not in liveins");
210 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
214 /// getRASaveReg - Grab the return address
216 SDValue AlphaDAGToDAGISel::getGlobalRetAddr() {
218 for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
219 ee = RegInfo->livein_end(); ii != ee; ++ii)
220 if (ii->first == Alpha::R26) {
224 assert(RA && "RA PTR not in liveins");
225 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
229 /// InstructionSelect - This callback is invoked by
230 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
231 void AlphaDAGToDAGISel::InstructionSelect() {
234 // Select target instructions for the DAG.
236 CurDAG->RemoveDeadNodes();
239 // Select - Convert the specified operand from a target-independent to a
240 // target-specific node if it hasn't already been changed.
241 SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
242 SDNode *N = Op.getNode();
243 if (N->isMachineOpcode()) {
244 return NULL; // Already selected.
247 switch (N->getOpcode()) {
253 case ISD::FrameIndex: {
254 int FI = cast<FrameIndexSDNode>(N)->getIndex();
255 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
256 CurDAG->getTargetFrameIndex(FI, MVT::i32),
259 case ISD::GLOBAL_OFFSET_TABLE: {
260 SDValue Result = getGlobalBaseReg();
261 ReplaceUses(Op, Result);
264 case AlphaISD::GlobalRetAddr: {
265 SDValue Result = getGlobalRetAddr();
266 ReplaceUses(Op, Result);
270 case AlphaISD::DivCall: {
271 SDValue Chain = CurDAG->getEntryNode();
272 SDValue N0 = Op.getOperand(0);
273 SDValue N1 = Op.getOperand(1);
274 SDValue N2 = Op.getOperand(2);
278 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
280 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
282 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
285 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
286 Chain, Chain.getValue(1));
287 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
289 return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
292 case ISD::READCYCLECOUNTER: {
293 SDValue Chain = N->getOperand(0);
294 AddToISelQueue(Chain); //Select chain
295 return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
299 case ISD::Constant: {
300 uint64_t uval = cast<ConstantSDNode>(N)->getZExtValue();
303 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
304 Alpha::R31, MVT::i64);
305 ReplaceUses(Op, Result);
309 int64_t val = (int64_t)uval;
310 int32_t val32 = (int32_t)val;
311 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
312 val >= IMM_LOW + IMM_LOW * IMM_MULT)
313 break; //(LDAH (LDA))
314 if ((uval >> 32) == 0 && //empty upper bits
315 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
316 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
317 break; //(zext (LDAH (LDA)))
318 //Else use the constant pool
319 ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
320 SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
321 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
323 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
324 CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
326 case ISD::TargetConstantFP: {
327 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
328 bool isDouble = N->getValueType(0) == MVT::f64;
329 MVT T = isDouble ? MVT::f64 : MVT::f32;
330 if (CN->getValueAPF().isPosZero()) {
331 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
332 T, CurDAG->getRegister(Alpha::F31, T),
333 CurDAG->getRegister(Alpha::F31, T));
334 } else if (CN->getValueAPF().isNegZero()) {
335 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
336 T, CurDAG->getRegister(Alpha::F31, T),
337 CurDAG->getRegister(Alpha::F31, T));
345 if (N->getOperand(0).getNode()->getValueType(0).isFloatingPoint()) {
346 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
348 unsigned Opc = Alpha::WTF;
352 default: DEBUG(N->dump(CurDAG)); assert(0 && "Unknown FP comparison!");
353 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
354 Opc = Alpha::CMPTEQ; break;
355 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
356 Opc = Alpha::CMPTLT; break;
357 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
358 Opc = Alpha::CMPTLE; break;
359 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
360 Opc = Alpha::CMPTLT; rev = true; break;
361 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
362 Opc = Alpha::CMPTLE; rev = true; break;
363 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
364 Opc = Alpha::CMPTEQ; inv = true; break;
366 Opc = Alpha::CMPTUN; inv = true; break;
368 Opc = Alpha::CMPTUN; break;
370 SDValue tmp1 = N->getOperand(rev?1:0);
371 SDValue tmp2 = N->getOperand(rev?0:1);
372 AddToISelQueue(tmp1);
373 AddToISelQueue(tmp2);
374 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2);
376 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDValue(cmp, 0),
377 CurDAG->getRegister(Alpha::F31, MVT::f64));
379 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
380 case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
382 SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
384 cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
385 SDValue(cmp2, 0), SDValue(cmp, 0));
391 SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDValue(cmp, 0));
392 return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
393 CurDAG->getRegister(Alpha::R31, MVT::i64),
399 if (N->getValueType(0).isFloatingPoint() &&
400 (N->getOperand(0).getOpcode() != ISD::SETCC ||
401 !N->getOperand(0).getOperand(1).getValueType().isFloatingPoint())) {
402 //This should be the condition not covered by the Patterns
403 //FIXME: Don't have SelectCode die, but rather return something testable
404 // so that things like this can be caught in fall though code
406 bool isDouble = N->getValueType(0) == MVT::f64;
407 SDValue cond = N->getOperand(0);
408 SDValue TV = N->getOperand(1);
409 SDValue FV = N->getOperand(2);
410 AddToISelQueue(cond);
414 SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond);
415 return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
416 MVT::f64, FV, TV, SDValue(LD,0));
421 ConstantSDNode* SC = NULL;
422 ConstantSDNode* MC = NULL;
423 if (N->getOperand(0).getOpcode() == ISD::SRL &&
424 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
425 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
426 uint64_t sval = SC->getZExtValue();
427 uint64_t mval = MC->getZExtValue();
428 // If the result is a zap, let the autogened stuff handle it.
429 if (get_zapImm(N->getOperand(0), mval))
431 // given mask X, and shift S, we want to see if there is any zap in the
432 // mask if we play around with the botton S bits
433 uint64_t dontcare = (~0ULL) >> (64 - sval);
434 uint64_t mask = mval << sval;
436 if (get_zapImm(mask | dontcare))
437 mask = mask | dontcare;
439 if (get_zapImm(mask)) {
440 AddToISelQueue(N->getOperand(0).getOperand(0));
442 SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
443 N->getOperand(0).getOperand(0),
444 getI64Imm(get_zapImm(mask))), 0);
445 return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
454 return SelectCode(Op);
457 void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
458 //TODO: add flag stuff to prevent nondeturministic breakage!
460 SDNode *N = Op.getNode();
461 SDValue Chain = N->getOperand(0);
462 SDValue Addr = N->getOperand(1);
463 SDValue InFlag(0,0); // Null incoming flag value.
464 AddToISelQueue(Chain);
466 std::vector<SDValue> CallOperands;
467 std::vector<MVT> TypeOperands;
470 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
471 TypeOperands.push_back(N->getOperand(i).getValueType());
472 AddToISelQueue(N->getOperand(i));
473 CallOperands.push_back(N->getOperand(i));
475 int count = N->getNumOperands() - 2;
477 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
478 Alpha::R19, Alpha::R20, Alpha::R21};
479 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
480 Alpha::F19, Alpha::F20, Alpha::F21};
482 for (int i = 6; i < count; ++i) {
483 unsigned Opc = Alpha::WTF;
484 if (TypeOperands[i].isInteger()) {
486 } else if (TypeOperands[i] == MVT::f32) {
488 } else if (TypeOperands[i] == MVT::f64) {
491 assert(0 && "Unknown operand");
493 SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
494 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
496 Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
498 for (int i = 0; i < std::min(6, count); ++i) {
499 if (TypeOperands[i].isInteger()) {
500 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
501 InFlag = Chain.getValue(1);
502 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
503 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
504 InFlag = Chain.getValue(1);
506 assert(0 && "Unknown operand");
509 // Finally, once everything is in registers to pass to the call, emit the
511 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
512 SDValue GOT = getGlobalBaseReg();
513 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
514 InFlag = Chain.getValue(1);
515 Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
516 Addr.getOperand(0), Chain, InFlag), 0);
518 AddToISelQueue(Addr);
519 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
520 InFlag = Chain.getValue(1);
521 Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
524 InFlag = Chain.getValue(1);
526 std::vector<SDValue> CallResults;
528 switch (N->getValueType(0).getSimpleVT()) {
529 default: assert(0 && "Unexpected ret value!");
530 case MVT::Other: break;
532 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
533 CallResults.push_back(Chain.getValue(0));
536 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
537 CallResults.push_back(Chain.getValue(0));
540 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
541 CallResults.push_back(Chain.getValue(0));
545 CallResults.push_back(Chain);
546 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
547 ReplaceUses(Op.getValue(i), CallResults[i]);
551 /// createAlphaISelDag - This pass converts a legalized DAG into a
552 /// Alpha-specific DAG, ready for instruction scheduling.
554 FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) {
555 return new AlphaDAGToDAGISel(TM);