1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
37 //===--------------------------------------------------------------------===//
38 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
39 /// instructions for SelectionDAG operations.
40 class AlphaDAGToDAGISel : public SelectionDAGISel {
41 AlphaTargetLowering AlphaLowering;
43 static const int64_t IMM_LOW = -32768;
44 static const int64_t IMM_HIGH = 32767;
45 static const int64_t IMM_MULT = 65536;
46 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
47 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
49 static int64_t get_ldah16(int64_t x) {
50 int64_t y = x / IMM_MULT;
51 if (x % IMM_MULT > IMM_HIGH)
56 static int64_t get_lda16(int64_t x) {
57 return x - get_ldah16(x) * IMM_MULT;
60 static uint64_t get_zapImm(uint64_t x) {
61 unsigned int build = 0;
62 for(int i = 0; i < 8; ++i)
64 if ((x & 0x00FF) == 0x00FF)
66 else if ((x & 0x00FF) != 0)
73 static bool isFPZ(SDOperand N) {
74 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
75 return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
77 static bool isFPZn(SDOperand N) {
78 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
79 return (CN && CN->isExactlyValue(-0.0));
81 static bool isFPZp(SDOperand N) {
82 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
83 return (CN && CN->isExactlyValue(+0.0));
87 AlphaDAGToDAGISel(TargetMachine &TM)
88 : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
91 /// getI64Imm - Return a target constant with the specified value, of type
93 inline SDOperand getI64Imm(int64_t Imm) {
94 return CurDAG->getTargetConstant(Imm, MVT::i64);
97 // Select - Convert the specified operand from a target-independent to a
98 // target-specific node if it hasn't already been changed.
99 void Select(SDOperand &Result, SDOperand Op);
101 /// InstructionSelectBasicBlock - This callback is invoked by
102 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
103 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
105 virtual const char *getPassName() const {
106 return "Alpha DAG->DAG Pattern Instruction Selection";
109 // Include the pieces autogenerated from the target description.
110 #include "AlphaGenDAGISel.inc"
113 SDOperand getGlobalBaseReg();
114 SDOperand getRASaveReg();
115 SDOperand SelectCALL(SDOperand Op);
120 /// getGlobalBaseReg - Output the instructions required to put the
121 /// GOT address into a register.
123 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
124 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
125 AlphaLowering.getVRegGP(),
129 /// getRASaveReg - Grab the return address
131 SDOperand AlphaDAGToDAGISel::getRASaveReg() {
132 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
133 AlphaLowering.getVRegRA(),
137 /// InstructionSelectBasicBlock - This callback is invoked by
138 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
139 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
142 // Select target instructions for the DAG.
143 DAG.setRoot(SelectRoot(DAG.getRoot()));
145 DAG.RemoveDeadNodes();
147 // Emit machine code to BB.
148 ScheduleAndEmitDAG(DAG);
151 // Select - Convert the specified operand from a target-independent to a
152 // target-specific node if it hasn't already been changed.
153 void AlphaDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
155 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
156 N->getOpcode() < AlphaISD::FIRST_NUMBER) {
158 return; // Already selected.
161 // If this has already been converted, use it.
162 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
163 if (CGMI != CodeGenMap.end()) {
164 Result = CGMI->second;
168 switch (N->getOpcode()) {
171 Result = SelectCALL(Op);
174 case ISD::FrameIndex: {
175 int FI = cast<FrameIndexSDNode>(N)->getIndex();
176 Result = CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
177 CurDAG->getTargetFrameIndex(FI, MVT::i32),
181 case AlphaISD::GlobalBaseReg:
182 Result = getGlobalBaseReg();
185 case AlphaISD::DivCall: {
186 SDOperand Chain = CurDAG->getEntryNode();
187 SDOperand N0, N1, N2;
188 Select(N0, Op.getOperand(0));
189 Select(N1, Op.getOperand(1));
190 Select(N2, Op.getOperand(2));
191 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
193 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
195 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
197 Chain = CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
198 Chain, Chain.getValue(1));
199 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
201 Result = CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
205 case ISD::READCYCLECOUNTER: {
207 Select(Chain, N->getOperand(0)); //Select chain
208 Result = CurDAG->SelectNodeTo(N, Alpha::RPCC, MVT::i64, Chain);
214 Select(Chain, N->getOperand(0)); // Token chain.
217 if (N->getNumOperands() == 2) {
219 Select(Val, N->getOperand(1));
220 if (N->getOperand(1).getValueType() == MVT::i64) {
221 Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
222 InFlag = Chain.getValue(1);
223 } else if (N->getOperand(1).getValueType() == MVT::f64 ||
224 N->getOperand(1).getValueType() == MVT::f32) {
225 Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag);
226 InFlag = Chain.getValue(1);
229 Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
230 InFlag = Chain.getValue(1);
232 // Finally, select this to a ret instruction.
233 Result = CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
236 case ISD::Constant: {
237 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
240 Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31,
245 int64_t val = (int64_t)uval;
246 int32_t val32 = (int32_t)val;
247 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
248 val >= IMM_LOW + IMM_LOW * IMM_MULT)
249 break; //(LDAH (LDA))
250 if ((uval >> 32) == 0 && //empty upper bits
251 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
252 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
253 break; //(zext (LDAH (LDA)))
254 //Else use the constant pool
255 MachineConstantPool *CP = BB->getParent()->getConstantPool();
257 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
258 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
259 Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
260 Result = CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
261 CPI, Tmp, CurDAG->getEntryNode());
264 case ISD::TargetConstantFP: {
265 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
266 bool isDouble = N->getValueType(0) == MVT::f64;
267 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
268 if (CN->isExactlyValue(+0.0)) {
269 Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
270 T, CurDAG->getRegister(Alpha::F31, T),
271 CurDAG->getRegister(Alpha::F31, T));
273 } else if ( CN->isExactlyValue(-0.0)) {
274 Result = CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
275 T, CurDAG->getRegister(Alpha::F31, T),
276 CurDAG->getRegister(Alpha::F31, T));
285 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
286 unsigned Opc = Alpha::WTF;
287 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
291 default: N->dump(); assert(0 && "Unknown FP comparison!");
292 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
293 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
294 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
295 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
296 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
297 case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
299 SDOperand tmp1, tmp2;
300 Select(tmp1, N->getOperand(0));
301 Select(tmp2, N->getOperand(1));
302 SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
306 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp,
307 CurDAG->getRegister(Alpha::F31, MVT::f64));
310 if (AlphaLowering.hasITOF()) {
311 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp);
314 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
315 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
316 SDOperand ST = CurDAG->getTargetNode(Alpha::STT, MVT::Other,
317 cmp, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
318 LD = CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
319 CurDAG->getRegister(Alpha::R31, MVT::i64),
322 SDOperand FP = CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
323 CurDAG->getRegister(Alpha::R31, MVT::i64),
331 if (MVT::isFloatingPoint(N->getValueType(0)) &&
332 (N->getOperand(0).getOpcode() != ISD::SETCC ||
333 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
334 //This should be the condition not covered by the Patterns
335 //FIXME: Don't have SelectCode die, but rather return something testable
336 // so that things like this can be caught in fall though code
338 bool isDouble = N->getValueType(0) == MVT::f64;
339 SDOperand LD, cond, TV, FV;
340 Select(cond, N->getOperand(0));
341 Select(TV, N->getOperand(1));
342 Select(FV, N->getOperand(2));
344 if (AlphaLowering.hasITOF()) {
345 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
348 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
349 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
350 SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
351 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
352 LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
353 CurDAG->getRegister(Alpha::R31, MVT::i64),
356 SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
357 MVT::f64, FV, TV, LD);
365 SelectCode(Result, Op);
368 SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
369 //TODO: add flag stuff to prevent nondeturministic breakage!
373 SDOperand Addr = N->getOperand(1);
374 SDOperand InFlag; // Null incoming flag value.
375 Select(Chain, N->getOperand(0));
377 std::vector<SDOperand> CallOperands;
378 std::vector<MVT::ValueType> TypeOperands;
381 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
383 TypeOperands.push_back(N->getOperand(i).getValueType());
384 Select(Tmp, N->getOperand(i));
385 CallOperands.push_back(Tmp);
387 int count = N->getNumOperands() - 2;
389 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
390 Alpha::R19, Alpha::R20, Alpha::R21};
391 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
392 Alpha::F19, Alpha::F20, Alpha::F21};
394 for (int i = 6; i < count; ++i) {
395 unsigned Opc = Alpha::WTF;
396 if (MVT::isInteger(TypeOperands[i])) {
398 } else if (TypeOperands[i] == MVT::f32) {
400 } else if (TypeOperands[i] == MVT::f64) {
403 assert(0 && "Unknown operand");
404 Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
405 getI64Imm((i - 6) * 8),
406 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
409 for (int i = 0; i < std::min(6, count); ++i) {
410 if (MVT::isInteger(TypeOperands[i])) {
411 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
412 InFlag = Chain.getValue(1);
413 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
414 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
415 InFlag = Chain.getValue(1);
417 assert(0 && "Unknown operand");
421 // Finally, once everything is in registers to pass to the call, emit the
423 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
424 SDOperand GOT = getGlobalBaseReg();
425 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
426 InFlag = Chain.getValue(1);
427 Chain = CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
428 Addr.getOperand(0), Chain, InFlag);
431 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
432 InFlag = Chain.getValue(1);
433 Chain = CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
436 InFlag = Chain.getValue(1);
438 std::vector<SDOperand> CallResults;
440 switch (N->getValueType(0)) {
441 default: assert(0 && "Unexpected ret value!");
442 case MVT::Other: break;
444 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
445 CallResults.push_back(Chain.getValue(0));
448 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
449 CallResults.push_back(Chain.getValue(0));
452 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
453 CallResults.push_back(Chain.getValue(0));
457 CallResults.push_back(Chain);
458 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
459 CodeGenMap[Op.getValue(i)] = CallResults[i];
460 return CallResults[Op.ResNo];
464 /// createAlphaISelDag - This pass converts a legalized DAG into a
465 /// Alpha-specific DAG, ready for instruction scheduling.
467 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
468 return new AlphaDAGToDAGISel(TM);