1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/Target/TargetOptions.h"
26 #include "llvm/Constants.h"
27 #include "llvm/DerivedTypes.h"
28 #include "llvm/GlobalValue.h"
29 #include "llvm/Intrinsics.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
39 //===--------------------------------------------------------------------===//
40 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
41 /// instructions for SelectionDAG operations.
42 class AlphaDAGToDAGISel : public SelectionDAGISel {
43 AlphaTargetLowering AlphaLowering;
45 static const int64_t IMM_LOW = -32768;
46 static const int64_t IMM_HIGH = 32767;
47 static const int64_t IMM_MULT = 65536;
48 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
49 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
51 static int64_t get_ldah16(int64_t x) {
52 int64_t y = x / IMM_MULT;
53 if (x % IMM_MULT > IMM_HIGH)
58 static int64_t get_lda16(int64_t x) {
59 return x - get_ldah16(x) * IMM_MULT;
62 /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
63 /// instruction (if not, return 0). Note that this code accepts partial
64 /// zap masks. For example (and LHS, 1) is a valid zap, as long we know
65 /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
66 /// in checking mode. If LHS is null, we assume that the mask has already
67 /// been validated before.
68 uint64_t get_zapImm(SDOperand LHS, uint64_t Constant) {
69 uint64_t BitsToCheck = 0;
71 for (unsigned i = 0; i != 8; ++i) {
72 if (((Constant >> 8*i) & 0xFF) == 0) {
76 if (((Constant >> 8*i) & 0xFF) == 0xFF) {
77 // If the entire byte is set, zapnot the byte.
78 } else if (LHS.Val == 0) {
79 // Otherwise, if the mask was previously validated, we know its okay
80 // to zapnot this entire byte even though all the bits aren't set.
82 // Otherwise we don't know that the it's okay to zapnot this entire
83 // byte. Only do this iff we can prove that the missing bits are
84 // already null, so the bytezap doesn't need to really null them.
85 BitsToCheck |= ~Constant & (0xFF << 8*i);
90 // If there are missing bits in a byte (for example, X & 0xEF00), check to
91 // see if the missing bits (0x1000) are already known zero if not, the zap
92 // isn't okay to do, as it won't clear all the required bits.
94 !CurDAG->MaskedValueIsZero(LHS, BitsToCheck))
100 static uint64_t get_zapImm(uint64_t x) {
102 for(int i = 0; i != 8; ++i) {
103 if ((x & 0x00FF) == 0x00FF)
105 else if ((x & 0x00FF) != 0)
113 static uint64_t getNearPower2(uint64_t x) {
115 unsigned at = CountLeadingZeros_64(x);
116 uint64_t complow = 1 << (63 - at);
117 uint64_t comphigh = 1 << (64 - at);
118 //cerr << x << ":" << complow << ":" << comphigh << "\n";
119 if (abs(complow - x) <= abs(comphigh - x))
125 static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
126 uint64_t y = getNearPower2(x);
133 static bool isFPZ(SDOperand N) {
134 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
135 return (CN && (CN->getValueAPF().isZero()));
137 static bool isFPZn(SDOperand N) {
138 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
139 return (CN && CN->getValueAPF().isNegZero());
141 static bool isFPZp(SDOperand N) {
142 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
143 return (CN && CN->getValueAPF().isPosZero());
147 AlphaDAGToDAGISel(TargetMachine &TM)
148 : SelectionDAGISel(AlphaLowering),
149 AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
152 /// getI64Imm - Return a target constant with the specified value, of type
154 inline SDOperand getI64Imm(int64_t Imm) {
155 return CurDAG->getTargetConstant(Imm, MVT::i64);
158 // Select - Convert the specified operand from a target-independent to a
159 // target-specific node if it hasn't already been changed.
160 SDNode *Select(SDOperand Op);
162 /// InstructionSelectBasicBlock - This callback is invoked by
163 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
164 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
166 virtual const char *getPassName() const {
167 return "Alpha DAG->DAG Pattern Instruction Selection";
170 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
171 /// inline asm expressions.
172 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
174 std::vector<SDOperand> &OutOps,
177 switch (ConstraintCode) {
178 default: return true;
185 OutOps.push_back(Op0);
189 // Include the pieces autogenerated from the target description.
190 #include "AlphaGenDAGISel.inc"
193 SDOperand getGlobalBaseReg();
194 SDOperand getGlobalRetAddr();
195 void SelectCALL(SDOperand Op);
200 /// getGlobalBaseReg - Output the instructions required to put the
201 /// GOT address into a register.
203 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
205 for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
206 ee = RegInfo->livein_end(); ii != ee; ++ii)
207 if (ii->first == Alpha::R29) {
211 assert(GP && "GOT PTR not in liveins");
212 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
216 /// getRASaveReg - Grab the return address
218 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
220 for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
221 ee = RegInfo->livein_end(); ii != ee; ++ii)
222 if (ii->first == Alpha::R26) {
226 assert(RA && "RA PTR not in liveins");
227 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
231 /// InstructionSelectBasicBlock - This callback is invoked by
232 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
233 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
236 // Select target instructions for the DAG.
237 DAG.setRoot(SelectRoot(DAG.getRoot()));
238 DAG.RemoveDeadNodes();
240 // Emit machine code to BB.
241 ScheduleAndEmitDAG(DAG);
244 // Select - Convert the specified operand from a target-independent to a
245 // target-specific node if it hasn't already been changed.
246 SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
248 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
249 N->getOpcode() < AlphaISD::FIRST_NUMBER) {
250 return NULL; // Already selected.
253 switch (N->getOpcode()) {
259 case ISD::FrameIndex: {
260 int FI = cast<FrameIndexSDNode>(N)->getIndex();
261 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
262 CurDAG->getTargetFrameIndex(FI, MVT::i32),
265 case ISD::GLOBAL_OFFSET_TABLE: {
266 SDOperand Result = getGlobalBaseReg();
267 ReplaceUses(Op, Result);
270 case AlphaISD::GlobalRetAddr: {
271 SDOperand Result = getGlobalRetAddr();
272 ReplaceUses(Op, Result);
276 case AlphaISD::DivCall: {
277 SDOperand Chain = CurDAG->getEntryNode();
278 SDOperand N0 = Op.getOperand(0);
279 SDOperand N1 = Op.getOperand(1);
280 SDOperand N2 = Op.getOperand(2);
284 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
286 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
288 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
291 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
292 Chain, Chain.getValue(1));
293 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
294 SDOperand(CNode, 1));
295 return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
298 case ISD::READCYCLECOUNTER: {
299 SDOperand Chain = N->getOperand(0);
300 AddToISelQueue(Chain); //Select chain
301 return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
305 case ISD::Constant: {
306 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
309 SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
310 Alpha::R31, MVT::i64);
311 ReplaceUses(Op, Result);
315 int64_t val = (int64_t)uval;
316 int32_t val32 = (int32_t)val;
317 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
318 val >= IMM_LOW + IMM_LOW * IMM_MULT)
319 break; //(LDAH (LDA))
320 if ((uval >> 32) == 0 && //empty upper bits
321 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
322 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
323 break; //(zext (LDAH (LDA)))
324 //Else use the constant pool
325 ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
326 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
327 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
329 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
330 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
332 case ISD::TargetConstantFP: {
333 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
334 bool isDouble = N->getValueType(0) == MVT::f64;
335 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
336 if (CN->getValueAPF().isPosZero()) {
337 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
338 T, CurDAG->getRegister(Alpha::F31, T),
339 CurDAG->getRegister(Alpha::F31, T));
340 } else if (CN->getValueAPF().isNegZero()) {
341 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
342 T, CurDAG->getRegister(Alpha::F31, T),
343 CurDAG->getRegister(Alpha::F31, T));
351 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
352 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
354 unsigned Opc = Alpha::WTF;
358 default: DEBUG(N->dump(CurDAG)); assert(0 && "Unknown FP comparison!");
359 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
360 Opc = Alpha::CMPTEQ; break;
361 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
362 Opc = Alpha::CMPTLT; break;
363 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
364 Opc = Alpha::CMPTLE; break;
365 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
366 Opc = Alpha::CMPTLT; rev = true; break;
367 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
368 Opc = Alpha::CMPTLE; rev = true; break;
369 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
370 Opc = Alpha::CMPTEQ; inv = true; break;
372 Opc = Alpha::CMPTUN; inv = true; break;
374 Opc = Alpha::CMPTUN; break;
376 SDOperand tmp1 = N->getOperand(rev?1:0);
377 SDOperand tmp2 = N->getOperand(rev?0:1);
378 AddToISelQueue(tmp1);
379 AddToISelQueue(tmp2);
380 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2);
382 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
383 CurDAG->getRegister(Alpha::F31, MVT::f64));
385 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
386 case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
388 SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
390 cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
391 SDOperand(cmp2, 0), SDOperand(cmp, 0));
397 SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDOperand(cmp, 0));
398 return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
399 CurDAG->getRegister(Alpha::R31, MVT::i64),
405 if (MVT::isFloatingPoint(N->getValueType(0)) &&
406 (N->getOperand(0).getOpcode() != ISD::SETCC ||
407 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
408 //This should be the condition not covered by the Patterns
409 //FIXME: Don't have SelectCode die, but rather return something testable
410 // so that things like this can be caught in fall though code
412 bool isDouble = N->getValueType(0) == MVT::f64;
413 SDOperand cond = N->getOperand(0);
414 SDOperand TV = N->getOperand(1);
415 SDOperand FV = N->getOperand(2);
416 AddToISelQueue(cond);
420 SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond);
421 return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
422 MVT::f64, FV, TV, SDOperand(LD,0));
427 ConstantSDNode* SC = NULL;
428 ConstantSDNode* MC = NULL;
429 if (N->getOperand(0).getOpcode() == ISD::SRL &&
430 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
431 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
432 uint64_t sval = SC->getValue();
433 uint64_t mval = MC->getValue();
434 // If the result is a zap, let the autogened stuff handle it.
435 if (get_zapImm(N->getOperand(0), mval))
437 // given mask X, and shift S, we want to see if there is any zap in the
438 // mask if we play around with the botton S bits
439 uint64_t dontcare = (~0ULL) >> (64 - sval);
440 uint64_t mask = mval << sval;
442 if (get_zapImm(mask | dontcare))
443 mask = mask | dontcare;
445 if (get_zapImm(mask)) {
446 AddToISelQueue(N->getOperand(0).getOperand(0));
448 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
449 N->getOperand(0).getOperand(0),
450 getI64Imm(get_zapImm(mask))), 0);
451 return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
460 return SelectCode(Op);
463 void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
464 //TODO: add flag stuff to prevent nondeturministic breakage!
467 SDOperand Chain = N->getOperand(0);
468 SDOperand Addr = N->getOperand(1);
469 SDOperand InFlag(0,0); // Null incoming flag value.
470 AddToISelQueue(Chain);
472 std::vector<SDOperand> CallOperands;
473 std::vector<MVT::ValueType> TypeOperands;
476 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
477 TypeOperands.push_back(N->getOperand(i).getValueType());
478 AddToISelQueue(N->getOperand(i));
479 CallOperands.push_back(N->getOperand(i));
481 int count = N->getNumOperands() - 2;
483 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
484 Alpha::R19, Alpha::R20, Alpha::R21};
485 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
486 Alpha::F19, Alpha::F20, Alpha::F21};
488 for (int i = 6; i < count; ++i) {
489 unsigned Opc = Alpha::WTF;
490 if (MVT::isInteger(TypeOperands[i])) {
492 } else if (TypeOperands[i] == MVT::f32) {
494 } else if (TypeOperands[i] == MVT::f64) {
497 assert(0 && "Unknown operand");
499 SDOperand Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
500 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
502 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
504 for (int i = 0; i < std::min(6, count); ++i) {
505 if (MVT::isInteger(TypeOperands[i])) {
506 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
507 InFlag = Chain.getValue(1);
508 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
509 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
510 InFlag = Chain.getValue(1);
512 assert(0 && "Unknown operand");
515 // Finally, once everything is in registers to pass to the call, emit the
517 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
518 SDOperand GOT = getGlobalBaseReg();
519 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
520 InFlag = Chain.getValue(1);
521 Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
522 Addr.getOperand(0), Chain, InFlag), 0);
524 AddToISelQueue(Addr);
525 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
526 InFlag = Chain.getValue(1);
527 Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
530 InFlag = Chain.getValue(1);
532 std::vector<SDOperand> CallResults;
534 switch (N->getValueType(0)) {
535 default: assert(0 && "Unexpected ret value!");
536 case MVT::Other: break;
538 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
539 CallResults.push_back(Chain.getValue(0));
542 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
543 CallResults.push_back(Chain.getValue(0));
546 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
547 CallResults.push_back(Chain.getValue(0));
551 CallResults.push_back(Chain);
552 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
553 ReplaceUses(Op.getValue(i), CallResults[i]);
557 /// createAlphaISelDag - This pass converts a legalized DAG into a
558 /// Alpha-specific DAG, ready for instruction scheduling.
560 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
561 return new AlphaDAGToDAGISel(TM);