1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Constants.h"
26 #include "llvm/DerivedTypes.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/MathExtras.h"
38 //===--------------------------------------------------------------------===//
39 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
40 /// instructions for SelectionDAG operations.
41 class AlphaDAGToDAGISel : public SelectionDAGISel {
42 AlphaTargetLowering AlphaLowering;
44 static const int64_t IMM_LOW = -32768;
45 static const int64_t IMM_HIGH = 32767;
46 static const int64_t IMM_MULT = 65536;
47 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
48 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
50 static int64_t get_ldah16(int64_t x) {
51 int64_t y = x / IMM_MULT;
52 if (x % IMM_MULT > IMM_HIGH)
57 static int64_t get_lda16(int64_t x) {
58 return x - get_ldah16(x) * IMM_MULT;
61 /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
62 /// instruction (if not, return 0). Note that this code accepts partial
63 /// zap masks. For example (and LHS, 1) is a valid zap, as long we know
64 /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
65 /// in checking mode. If LHS is null, we assume that the mask has already
66 /// been validated before.
67 uint64_t get_zapImm(SDOperand LHS, uint64_t Constant) {
68 uint64_t BitsToCheck = 0;
70 for (unsigned i = 0; i != 8; ++i) {
71 if (((Constant >> 8*i) & 0xFF) == 0) {
75 if (((Constant >> 8*i) & 0xFF) == 0xFF) {
76 // If the entire byte is set, zapnot the byte.
77 } else if (LHS.Val == 0) {
78 // Otherwise, if the mask was previously validated, we know its okay
79 // to zapnot this entire byte even though all the bits aren't set.
81 // Otherwise we don't know that the it's okay to zapnot this entire
82 // byte. Only do this iff we can prove that the missing bits are
83 // already null, so the bytezap doesn't need to really null them.
84 BitsToCheck |= ~Constant & (0xFF << 8*i);
89 // If there are missing bits in a byte (for example, X & 0xEF00), check to
90 // see if the missing bits (0x1000) are already known zero if not, the zap
91 // isn't okay to do, as it won't clear all the required bits.
93 !getTargetLowering().MaskedValueIsZero(LHS, BitsToCheck))
99 static uint64_t get_zapImm(uint64_t x) {
101 for(int i = 0; i != 8; ++i) {
102 if ((x & 0x00FF) == 0x00FF)
104 else if ((x & 0x00FF) != 0)
112 static uint64_t getNearPower2(uint64_t x) {
114 unsigned at = CountLeadingZeros_64(x);
115 uint64_t complow = 1 << (63 - at);
116 uint64_t comphigh = 1 << (64 - at);
117 //cerr << x << ":" << complow << ":" << comphigh << "\n";
118 if (abs(complow - x) <= abs(comphigh - x))
124 static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
125 uint64_t y = getNearPower2(x);
132 static bool isFPZ(SDOperand N) {
133 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
134 return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
136 static bool isFPZn(SDOperand N) {
137 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
138 return (CN && CN->isExactlyValue(-0.0));
140 static bool isFPZp(SDOperand N) {
141 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
142 return (CN && CN->isExactlyValue(+0.0));
146 AlphaDAGToDAGISel(TargetMachine &TM)
147 : SelectionDAGISel(AlphaLowering),
148 AlphaLowering(*(AlphaTargetLowering*)(TM.getTargetLowering()))
151 /// getI64Imm - Return a target constant with the specified value, of type
153 inline SDOperand getI64Imm(int64_t Imm) {
154 return CurDAG->getTargetConstant(Imm, MVT::i64);
157 // Select - Convert the specified operand from a target-independent to a
158 // target-specific node if it hasn't already been changed.
159 SDNode *Select(SDOperand Op);
161 /// InstructionSelectBasicBlock - This callback is invoked by
162 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
163 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
165 virtual const char *getPassName() const {
166 return "Alpha DAG->DAG Pattern Instruction Selection";
169 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
170 /// inline asm expressions.
171 virtual bool SelectInlineAsmMemoryOperand(const SDOperand &Op,
173 std::vector<SDOperand> &OutOps,
176 switch (ConstraintCode) {
177 default: return true;
184 OutOps.push_back(Op0);
188 // Include the pieces autogenerated from the target description.
189 #include "AlphaGenDAGISel.inc"
192 SDOperand getGlobalBaseReg();
193 SDOperand getGlobalRetAddr();
194 void SelectCALL(SDOperand Op);
199 /// getGlobalBaseReg - Output the instructions required to put the
200 /// GOT address into a register.
202 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
203 MachineFunction* MF = BB->getParent();
205 for(MachineFunction::livein_iterator ii = MF->livein_begin(),
206 ee = MF->livein_end(); ii != ee; ++ii)
207 if (ii->first == Alpha::R29) {
211 assert(GP && "GOT PTR not in liveins");
212 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
216 /// getRASaveReg - Grab the return address
218 SDOperand AlphaDAGToDAGISel::getGlobalRetAddr() {
219 MachineFunction* MF = BB->getParent();
221 for(MachineFunction::livein_iterator ii = MF->livein_begin(),
222 ee = MF->livein_end(); ii != ee; ++ii)
223 if (ii->first == Alpha::R26) {
227 assert(RA && "RA PTR not in liveins");
228 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
232 /// InstructionSelectBasicBlock - This callback is invoked by
233 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
234 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
237 // Select target instructions for the DAG.
238 DAG.setRoot(SelectRoot(DAG.getRoot()));
239 DAG.RemoveDeadNodes();
241 // Emit machine code to BB.
242 ScheduleAndEmitDAG(DAG);
245 // Select - Convert the specified operand from a target-independent to a
246 // target-specific node if it hasn't already been changed.
247 SDNode *AlphaDAGToDAGISel::Select(SDOperand Op) {
249 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
250 N->getOpcode() < AlphaISD::FIRST_NUMBER) {
251 return NULL; // Already selected.
254 switch (N->getOpcode()) {
260 case ISD::FrameIndex: {
261 int FI = cast<FrameIndexSDNode>(N)->getIndex();
262 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
263 CurDAG->getTargetFrameIndex(FI, MVT::i32),
266 case ISD::GLOBAL_OFFSET_TABLE: {
267 SDOperand Result = getGlobalBaseReg();
268 ReplaceUses(Op, Result);
271 case AlphaISD::GlobalRetAddr: {
272 SDOperand Result = getGlobalRetAddr();
273 ReplaceUses(Op, Result);
277 case AlphaISD::DivCall: {
278 SDOperand Chain = CurDAG->getEntryNode();
279 SDOperand N0 = Op.getOperand(0);
280 SDOperand N1 = Op.getOperand(1);
281 SDOperand N2 = Op.getOperand(2);
285 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
287 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
289 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
292 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
293 Chain, Chain.getValue(1));
294 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
295 SDOperand(CNode, 1));
296 return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
299 case ISD::READCYCLECOUNTER: {
300 SDOperand Chain = N->getOperand(0);
301 AddToISelQueue(Chain); //Select chain
302 return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
306 case ISD::Constant: {
307 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
310 SDOperand Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
311 Alpha::R31, MVT::i64);
312 ReplaceUses(Op, Result);
316 int64_t val = (int64_t)uval;
317 int32_t val32 = (int32_t)val;
318 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
319 val >= IMM_LOW + IMM_LOW * IMM_MULT)
320 break; //(LDAH (LDA))
321 if ((uval >> 32) == 0 && //empty upper bits
322 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
323 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
324 break; //(zext (LDAH (LDA)))
325 //Else use the constant pool
326 ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
327 SDOperand CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
328 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
330 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
331 CPI, SDOperand(Tmp, 0), CurDAG->getEntryNode());
333 case ISD::TargetConstantFP: {
334 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
335 bool isDouble = N->getValueType(0) == MVT::f64;
336 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
337 if (CN->isExactlyValue(+0.0)) {
338 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
339 T, CurDAG->getRegister(Alpha::F31, T),
340 CurDAG->getRegister(Alpha::F31, T));
341 } else if ( CN->isExactlyValue(-0.0)) {
342 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
343 T, CurDAG->getRegister(Alpha::F31, T),
344 CurDAG->getRegister(Alpha::F31, T));
352 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
353 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
355 unsigned Opc = Alpha::WTF;
359 default: DEBUG(N->dump()); assert(0 && "Unknown FP comparison!");
360 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
361 Opc = Alpha::CMPTEQ; break;
362 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
363 Opc = Alpha::CMPTLT; break;
364 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
365 Opc = Alpha::CMPTLE; break;
366 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
367 Opc = Alpha::CMPTLT; rev = true; break;
368 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
369 Opc = Alpha::CMPTLE; rev = true; break;
370 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
371 Opc = Alpha::CMPTEQ; inv = true; break;
373 Opc = Alpha::CMPTUN; inv = true; break;
375 Opc = Alpha::CMPTUN; break;
377 SDOperand tmp1 = N->getOperand(rev?1:0);
378 SDOperand tmp2 = N->getOperand(rev?0:1);
379 AddToISelQueue(tmp1);
380 AddToISelQueue(tmp2);
381 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2);
383 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDOperand(cmp, 0),
384 CurDAG->getRegister(Alpha::F31, MVT::f64));
386 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
387 case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
389 SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
391 cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
392 SDOperand(cmp2, 0), SDOperand(cmp, 0));
398 SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDOperand(cmp, 0));
399 return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
400 CurDAG->getRegister(Alpha::R31, MVT::i64),
406 if (MVT::isFloatingPoint(N->getValueType(0)) &&
407 (N->getOperand(0).getOpcode() != ISD::SETCC ||
408 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
409 //This should be the condition not covered by the Patterns
410 //FIXME: Don't have SelectCode die, but rather return something testable
411 // so that things like this can be caught in fall though code
413 bool isDouble = N->getValueType(0) == MVT::f64;
414 SDOperand cond = N->getOperand(0);
415 SDOperand TV = N->getOperand(1);
416 SDOperand FV = N->getOperand(2);
417 AddToISelQueue(cond);
421 SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond);
422 return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
423 MVT::f64, FV, TV, SDOperand(LD,0));
428 ConstantSDNode* SC = NULL;
429 ConstantSDNode* MC = NULL;
430 if (N->getOperand(0).getOpcode() == ISD::SRL &&
431 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
432 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
433 uint64_t sval = SC->getValue();
434 uint64_t mval = MC->getValue();
435 // If the result is a zap, let the autogened stuff handle it.
436 if (get_zapImm(N->getOperand(0), mval))
438 // given mask X, and shift S, we want to see if there is any zap in the
439 // mask if we play around with the botton S bits
440 uint64_t dontcare = (~0ULL) >> (64 - sval);
441 uint64_t mask = mval << sval;
443 if (get_zapImm(mask | dontcare))
444 mask = mask | dontcare;
446 if (get_zapImm(mask)) {
447 AddToISelQueue(N->getOperand(0).getOperand(0));
449 SDOperand(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
450 N->getOperand(0).getOperand(0),
451 getI64Imm(get_zapImm(mask))), 0);
452 return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
461 return SelectCode(Op);
464 void AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
465 //TODO: add flag stuff to prevent nondeturministic breakage!
468 SDOperand Chain = N->getOperand(0);
469 SDOperand Addr = N->getOperand(1);
470 SDOperand InFlag(0,0); // Null incoming flag value.
471 AddToISelQueue(Chain);
473 std::vector<SDOperand> CallOperands;
474 std::vector<MVT::ValueType> TypeOperands;
477 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
478 TypeOperands.push_back(N->getOperand(i).getValueType());
479 AddToISelQueue(N->getOperand(i));
480 CallOperands.push_back(N->getOperand(i));
482 int count = N->getNumOperands() - 2;
484 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
485 Alpha::R19, Alpha::R20, Alpha::R21};
486 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
487 Alpha::F19, Alpha::F20, Alpha::F21};
489 for (int i = 6; i < count; ++i) {
490 unsigned Opc = Alpha::WTF;
491 if (MVT::isInteger(TypeOperands[i])) {
493 } else if (TypeOperands[i] == MVT::f32) {
495 } else if (TypeOperands[i] == MVT::f64) {
498 assert(0 && "Unknown operand");
500 SDOperand Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
501 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
503 Chain = SDOperand(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
505 for (int i = 0; i < std::min(6, count); ++i) {
506 if (MVT::isInteger(TypeOperands[i])) {
507 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
508 InFlag = Chain.getValue(1);
509 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
510 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
511 InFlag = Chain.getValue(1);
513 assert(0 && "Unknown operand");
516 // Finally, once everything is in registers to pass to the call, emit the
518 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
519 SDOperand GOT = getGlobalBaseReg();
520 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
521 InFlag = Chain.getValue(1);
522 Chain = SDOperand(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
523 Addr.getOperand(0), Chain, InFlag), 0);
525 AddToISelQueue(Addr);
526 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
527 InFlag = Chain.getValue(1);
528 Chain = SDOperand(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
531 InFlag = Chain.getValue(1);
533 std::vector<SDOperand> CallResults;
535 switch (N->getValueType(0)) {
536 default: assert(0 && "Unexpected ret value!");
537 case MVT::Other: break;
539 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
540 CallResults.push_back(Chain.getValue(0));
543 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
544 CallResults.push_back(Chain.getValue(0));
547 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
548 CallResults.push_back(Chain.getValue(0));
552 CallResults.push_back(Chain);
553 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
554 ReplaceUses(Op.getValue(i), CallResults[i]);
558 /// createAlphaISelDag - This pass converts a legalized DAG into a
559 /// Alpha-specific DAG, ready for instruction scheduling.
561 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
562 return new AlphaDAGToDAGISel(TM);