1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/Constants.h"
26 #include "llvm/DerivedTypes.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Intrinsics.h"
29 #include "llvm/Support/Compiler.h"
30 #include "llvm/Support/Debug.h"
31 #include "llvm/Support/MathExtras.h"
37 //===--------------------------------------------------------------------===//
38 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
39 /// instructions for SelectionDAG operations.
40 class AlphaDAGToDAGISel : public SelectionDAGISel {
41 static const int64_t IMM_LOW = -32768;
42 static const int64_t IMM_HIGH = 32767;
43 static const int64_t IMM_MULT = 65536;
44 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
45 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
47 static int64_t get_ldah16(int64_t x) {
48 int64_t y = x / IMM_MULT;
49 if (x % IMM_MULT > IMM_HIGH)
54 static int64_t get_lda16(int64_t x) {
55 return x - get_ldah16(x) * IMM_MULT;
58 /// get_zapImm - Return a zap mask if X is a valid immediate for a zapnot
59 /// instruction (if not, return 0). Note that this code accepts partial
60 /// zap masks. For example (and LHS, 1) is a valid zap, as long we know
61 /// that the bits 1-7 of LHS are already zero. If LHS is non-null, we are
62 /// in checking mode. If LHS is null, we assume that the mask has already
63 /// been validated before.
64 uint64_t get_zapImm(SDValue LHS, uint64_t Constant) {
65 uint64_t BitsToCheck = 0;
67 for (unsigned i = 0; i != 8; ++i) {
68 if (((Constant >> 8*i) & 0xFF) == 0) {
72 if (((Constant >> 8*i) & 0xFF) == 0xFF) {
73 // If the entire byte is set, zapnot the byte.
74 } else if (LHS.getNode() == 0) {
75 // Otherwise, if the mask was previously validated, we know its okay
76 // to zapnot this entire byte even though all the bits aren't set.
78 // Otherwise we don't know that the it's okay to zapnot this entire
79 // byte. Only do this iff we can prove that the missing bits are
80 // already null, so the bytezap doesn't need to really null them.
81 BitsToCheck |= ~Constant & (0xFF << 8*i);
86 // If there are missing bits in a byte (for example, X & 0xEF00), check to
87 // see if the missing bits (0x1000) are already known zero if not, the zap
88 // isn't okay to do, as it won't clear all the required bits.
90 !CurDAG->MaskedValueIsZero(LHS,
91 APInt(LHS.getValueSizeInBits(),
98 static uint64_t get_zapImm(uint64_t x) {
100 for(int i = 0; i != 8; ++i) {
101 if ((x & 0x00FF) == 0x00FF)
103 else if ((x & 0x00FF) != 0)
111 static uint64_t getNearPower2(uint64_t x) {
113 unsigned at = CountLeadingZeros_64(x);
114 uint64_t complow = 1 << (63 - at);
115 uint64_t comphigh = 1 << (64 - at);
116 //cerr << x << ":" << complow << ":" << comphigh << "\n";
117 if (abs(complow - x) <= abs(comphigh - x))
123 static bool chkRemNearPower2(uint64_t x, uint64_t r, bool swap) {
124 uint64_t y = getNearPower2(x);
131 static bool isFPZ(SDValue N) {
132 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
133 return (CN && (CN->getValueAPF().isZero()));
135 static bool isFPZn(SDValue N) {
136 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
137 return (CN && CN->getValueAPF().isNegZero());
139 static bool isFPZp(SDValue N) {
140 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
141 return (CN && CN->getValueAPF().isPosZero());
145 explicit AlphaDAGToDAGISel(AlphaTargetMachine &TM)
146 : SelectionDAGISel(*TM.getTargetLowering())
149 /// getI64Imm - Return a target constant with the specified value, of type
151 inline SDValue getI64Imm(int64_t Imm) {
152 return CurDAG->getTargetConstant(Imm, MVT::i64);
155 // Select - Convert the specified operand from a target-independent to a
156 // target-specific node if it hasn't already been changed.
157 SDNode *Select(SDValue Op);
159 /// InstructionSelect - This callback is invoked by
160 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
161 virtual void InstructionSelect();
163 virtual const char *getPassName() const {
164 return "Alpha DAG->DAG Pattern Instruction Selection";
167 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
168 /// inline asm expressions.
169 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
171 std::vector<SDValue> &OutOps) {
173 switch (ConstraintCode) {
174 default: return true;
180 OutOps.push_back(Op0);
184 // Include the pieces autogenerated from the target description.
185 #include "AlphaGenDAGISel.inc"
188 SDValue getGlobalBaseReg();
189 SDValue getGlobalRetAddr();
190 void SelectCALL(SDValue Op);
195 /// getGlobalBaseReg - Output the instructions required to put the
196 /// GOT address into a register.
198 SDValue AlphaDAGToDAGISel::getGlobalBaseReg() {
200 for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
201 ee = RegInfo->livein_end(); ii != ee; ++ii)
202 if (ii->first == Alpha::R29) {
206 assert(GP && "GOT PTR not in liveins");
207 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
211 /// getRASaveReg - Grab the return address
213 SDValue AlphaDAGToDAGISel::getGlobalRetAddr() {
215 for(MachineRegisterInfo::livein_iterator ii = RegInfo->livein_begin(),
216 ee = RegInfo->livein_end(); ii != ee; ++ii)
217 if (ii->first == Alpha::R26) {
221 assert(RA && "RA PTR not in liveins");
222 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
226 /// InstructionSelect - This callback is invoked by
227 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
228 void AlphaDAGToDAGISel::InstructionSelect() {
231 // Select target instructions for the DAG.
233 CurDAG->RemoveDeadNodes();
236 // Select - Convert the specified operand from a target-independent to a
237 // target-specific node if it hasn't already been changed.
238 SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
239 SDNode *N = Op.getNode();
240 if (N->isMachineOpcode()) {
241 return NULL; // Already selected.
244 switch (N->getOpcode()) {
250 case ISD::FrameIndex: {
251 int FI = cast<FrameIndexSDNode>(N)->getIndex();
252 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
253 CurDAG->getTargetFrameIndex(FI, MVT::i32),
256 case ISD::GLOBAL_OFFSET_TABLE: {
257 SDValue Result = getGlobalBaseReg();
258 ReplaceUses(Op, Result);
261 case AlphaISD::GlobalRetAddr: {
262 SDValue Result = getGlobalRetAddr();
263 ReplaceUses(Op, Result);
267 case AlphaISD::DivCall: {
268 SDValue Chain = CurDAG->getEntryNode();
269 SDValue N0 = Op.getOperand(0);
270 SDValue N1 = Op.getOperand(1);
271 SDValue N2 = Op.getOperand(2);
272 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, N1,
274 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, N2,
276 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, N0,
279 CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
280 Chain, Chain.getValue(1));
281 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
283 return CurDAG->SelectNodeTo(N, Alpha::BISr, MVT::i64, Chain, Chain);
286 case ISD::READCYCLECOUNTER: {
287 SDValue Chain = N->getOperand(0);
288 return CurDAG->getTargetNode(Alpha::RPCC, MVT::i64, MVT::Other,
292 case ISD::Constant: {
293 uint64_t uval = cast<ConstantSDNode>(N)->getZExtValue();
296 SDValue Result = CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
297 Alpha::R31, MVT::i64);
298 ReplaceUses(Op, Result);
302 int64_t val = (int64_t)uval;
303 int32_t val32 = (int32_t)val;
304 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
305 val >= IMM_LOW + IMM_LOW * IMM_MULT)
306 break; //(LDAH (LDA))
307 if ((uval >> 32) == 0 && //empty upper bits
308 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
309 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
310 break; //(zext (LDAH (LDA)))
311 //Else use the constant pool
312 ConstantInt *C = ConstantInt::get(Type::Int64Ty, uval);
313 SDValue CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
314 SDNode *Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI,
316 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
317 CPI, SDValue(Tmp, 0), CurDAG->getEntryNode());
319 case ISD::TargetConstantFP:
320 case ISD::ConstantFP: {
321 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
322 bool isDouble = N->getValueType(0) == MVT::f64;
323 MVT T = isDouble ? MVT::f64 : MVT::f32;
324 if (CN->getValueAPF().isPosZero()) {
325 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
326 T, CurDAG->getRegister(Alpha::F31, T),
327 CurDAG->getRegister(Alpha::F31, T));
328 } else if (CN->getValueAPF().isNegZero()) {
329 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
330 T, CurDAG->getRegister(Alpha::F31, T),
331 CurDAG->getRegister(Alpha::F31, T));
339 if (N->getOperand(0).getNode()->getValueType(0).isFloatingPoint()) {
340 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
342 unsigned Opc = Alpha::WTF;
346 default: DEBUG(N->dump(CurDAG)); assert(0 && "Unknown FP comparison!");
347 case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ:
348 Opc = Alpha::CMPTEQ; break;
349 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT:
350 Opc = Alpha::CMPTLT; break;
351 case ISD::SETLE: case ISD::SETOLE: case ISD::SETULE:
352 Opc = Alpha::CMPTLE; break;
353 case ISD::SETGT: case ISD::SETOGT: case ISD::SETUGT:
354 Opc = Alpha::CMPTLT; rev = true; break;
355 case ISD::SETGE: case ISD::SETOGE: case ISD::SETUGE:
356 Opc = Alpha::CMPTLE; rev = true; break;
357 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE:
358 Opc = Alpha::CMPTEQ; inv = true; break;
360 Opc = Alpha::CMPTUN; inv = true; break;
362 Opc = Alpha::CMPTUN; break;
364 SDValue tmp1 = N->getOperand(rev?1:0);
365 SDValue tmp2 = N->getOperand(rev?0:1);
366 SDNode *cmp = CurDAG->getTargetNode(Opc, MVT::f64, tmp1, tmp2);
368 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, SDValue(cmp, 0),
369 CurDAG->getRegister(Alpha::F31, MVT::f64));
371 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE:
372 case ISD::SETUNE: case ISD::SETUGT: case ISD::SETUGE:
374 SDNode* cmp2 = CurDAG->getTargetNode(Alpha::CMPTUN, MVT::f64,
376 cmp = CurDAG->getTargetNode(Alpha::ADDT, MVT::f64,
377 SDValue(cmp2, 0), SDValue(cmp, 0));
383 SDNode* LD = CurDAG->getTargetNode(Alpha::FTOIT, MVT::i64, SDValue(cmp, 0));
384 return CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
385 CurDAG->getRegister(Alpha::R31, MVT::i64),
391 if (N->getValueType(0).isFloatingPoint() &&
392 (N->getOperand(0).getOpcode() != ISD::SETCC ||
393 !N->getOperand(0).getOperand(1).getValueType().isFloatingPoint())) {
394 //This should be the condition not covered by the Patterns
395 //FIXME: Don't have SelectCode die, but rather return something testable
396 // so that things like this can be caught in fall though code
398 bool isDouble = N->getValueType(0) == MVT::f64;
399 SDValue cond = N->getOperand(0);
400 SDValue TV = N->getOperand(1);
401 SDValue FV = N->getOperand(2);
403 SDNode* LD = CurDAG->getTargetNode(Alpha::ITOFT, MVT::f64, cond);
404 return CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
405 MVT::f64, FV, TV, SDValue(LD,0));
410 ConstantSDNode* SC = NULL;
411 ConstantSDNode* MC = NULL;
412 if (N->getOperand(0).getOpcode() == ISD::SRL &&
413 (MC = dyn_cast<ConstantSDNode>(N->getOperand(1))) &&
414 (SC = dyn_cast<ConstantSDNode>(N->getOperand(0).getOperand(1)))) {
415 uint64_t sval = SC->getZExtValue();
416 uint64_t mval = MC->getZExtValue();
417 // If the result is a zap, let the autogened stuff handle it.
418 if (get_zapImm(N->getOperand(0), mval))
420 // given mask X, and shift S, we want to see if there is any zap in the
421 // mask if we play around with the botton S bits
422 uint64_t dontcare = (~0ULL) >> (64 - sval);
423 uint64_t mask = mval << sval;
425 if (get_zapImm(mask | dontcare))
426 mask = mask | dontcare;
428 if (get_zapImm(mask)) {
430 SDValue(CurDAG->getTargetNode(Alpha::ZAPNOTi, MVT::i64,
431 N->getOperand(0).getOperand(0),
432 getI64Imm(get_zapImm(mask))), 0);
433 return CurDAG->getTargetNode(Alpha::SRLr, MVT::i64, Z,
442 return SelectCode(Op);
445 void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
446 //TODO: add flag stuff to prevent nondeturministic breakage!
448 SDNode *N = Op.getNode();
449 SDValue Chain = N->getOperand(0);
450 SDValue Addr = N->getOperand(1);
451 SDValue InFlag(0,0); // Null incoming flag value.
453 std::vector<SDValue> CallOperands;
454 std::vector<MVT> TypeOperands;
457 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
458 TypeOperands.push_back(N->getOperand(i).getValueType());
459 CallOperands.push_back(N->getOperand(i));
461 int count = N->getNumOperands() - 2;
463 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
464 Alpha::R19, Alpha::R20, Alpha::R21};
465 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
466 Alpha::F19, Alpha::F20, Alpha::F21};
468 for (int i = 6; i < count; ++i) {
469 unsigned Opc = Alpha::WTF;
470 if (TypeOperands[i].isInteger()) {
472 } else if (TypeOperands[i] == MVT::f32) {
474 } else if (TypeOperands[i] == MVT::f64) {
477 assert(0 && "Unknown operand");
479 SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8),
480 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
482 Chain = SDValue(CurDAG->getTargetNode(Opc, MVT::Other, Ops, 4), 0);
484 for (int i = 0; i < std::min(6, count); ++i) {
485 if (TypeOperands[i].isInteger()) {
486 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
487 InFlag = Chain.getValue(1);
488 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
489 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
490 InFlag = Chain.getValue(1);
492 assert(0 && "Unknown operand");
495 // Finally, once everything is in registers to pass to the call, emit the
497 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
498 SDValue GOT = getGlobalBaseReg();
499 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
500 InFlag = Chain.getValue(1);
501 Chain = SDValue(CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
502 Addr.getOperand(0), Chain, InFlag), 0);
504 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Addr, InFlag);
505 InFlag = Chain.getValue(1);
506 Chain = SDValue(CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
509 InFlag = Chain.getValue(1);
511 std::vector<SDValue> CallResults;
513 switch (N->getValueType(0).getSimpleVT()) {
514 default: assert(0 && "Unexpected ret value!");
515 case MVT::Other: break;
517 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
518 CallResults.push_back(Chain.getValue(0));
521 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
522 CallResults.push_back(Chain.getValue(0));
525 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
526 CallResults.push_back(Chain.getValue(0));
530 CallResults.push_back(Chain);
531 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
532 ReplaceUses(Op.getValue(i), CallResults[i]);
536 /// createAlphaISelDag - This pass converts a legalized DAG into a
537 /// Alpha-specific DAG, ready for instruction scheduling.
539 FunctionPass *llvm::createAlphaISelDag(AlphaTargetMachine &TM) {
540 return new AlphaDAGToDAGISel(TM);