1 //===-- AlphaISelDAGToDAG.cpp - Alpha pattern matching inst selector ------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Andrew Lenharth and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for Alpha,
11 // converting from a legalized dag to a Alpha dag.
13 //===----------------------------------------------------------------------===//
16 #include "AlphaTargetMachine.h"
17 #include "AlphaISelLowering.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/SSARegMap.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SelectionDAGISel.h"
24 #include "llvm/Target/TargetOptions.h"
25 #include "llvm/ADT/Statistic.h"
26 #include "llvm/Constants.h"
27 #include "llvm/GlobalValue.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
36 //===--------------------------------------------------------------------===//
37 /// AlphaDAGToDAGISel - Alpha specific code to select Alpha machine
38 /// instructions for SelectionDAG operations.
39 class AlphaDAGToDAGISel : public SelectionDAGISel {
40 AlphaTargetLowering AlphaLowering;
42 static const int64_t IMM_LOW = -32768;
43 static const int64_t IMM_HIGH = 32767;
44 static const int64_t IMM_MULT = 65536;
45 static const int64_t IMM_FULLHIGH = IMM_HIGH + IMM_HIGH * IMM_MULT;
46 static const int64_t IMM_FULLLOW = IMM_LOW + IMM_LOW * IMM_MULT;
48 static int64_t get_ldah16(int64_t x) {
49 int64_t y = x / IMM_MULT;
50 if (x % IMM_MULT > IMM_HIGH)
55 static int64_t get_lda16(int64_t x) {
56 return x - get_ldah16(x) * IMM_MULT;
59 static uint64_t get_zapImm(uint64_t x) {
60 unsigned int build = 0;
61 for(int i = 0; i < 8; ++i)
63 if ((x & 0x00FF) == 0x00FF)
65 else if ((x & 0x00FF) != 0)
72 static bool isFPZ(SDOperand N) {
73 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
74 return (CN && (CN->isExactlyValue(+0.0) || CN->isExactlyValue(-0.0)));
76 static bool isFPZn(SDOperand N) {
77 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
78 return (CN && CN->isExactlyValue(-0.0));
80 static bool isFPZp(SDOperand N) {
81 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(N);
82 return (CN && CN->isExactlyValue(+0.0));
86 AlphaDAGToDAGISel(TargetMachine &TM)
87 : SelectionDAGISel(AlphaLowering), AlphaLowering(TM)
90 /// getI64Imm - Return a target constant with the specified value, of type
92 inline SDOperand getI64Imm(int64_t Imm) {
93 return CurDAG->getTargetConstant(Imm, MVT::i64);
96 // Select - Convert the specified operand from a target-independent to a
97 // target-specific node if it hasn't already been changed.
98 SDOperand Select(SDOperand Op);
100 /// InstructionSelectBasicBlock - This callback is invoked by
101 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
102 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
104 virtual const char *getPassName() const {
105 return "Alpha DAG->DAG Pattern Instruction Selection";
108 // Include the pieces autogenerated from the target description.
109 #include "AlphaGenDAGISel.inc"
112 SDOperand getGlobalBaseReg();
113 SDOperand getRASaveReg();
114 SDOperand SelectCALL(SDOperand Op);
119 /// getGlobalBaseReg - Output the instructions required to put the
120 /// GOT address into a register.
122 SDOperand AlphaDAGToDAGISel::getGlobalBaseReg() {
123 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
124 AlphaLowering.getVRegGP(),
128 /// getRASaveReg - Grab the return address
130 SDOperand AlphaDAGToDAGISel::getRASaveReg() {
131 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(),
132 AlphaLowering.getVRegRA(),
136 /// InstructionSelectBasicBlock - This callback is invoked by
137 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
138 void AlphaDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
141 // Select target instructions for the DAG.
142 DAG.setRoot(Select(DAG.getRoot()));
144 DAG.RemoveDeadNodes();
146 // Emit machine code to BB.
147 ScheduleAndEmitDAG(DAG);
150 // Select - Convert the specified operand from a target-independent to a
151 // target-specific node if it hasn't already been changed.
152 SDOperand AlphaDAGToDAGISel::Select(SDOperand Op) {
154 if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
155 N->getOpcode() < AlphaISD::FIRST_NUMBER)
156 return Op; // Already selected.
158 // If this has already been converted, use it.
159 std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
160 if (CGMI != CodeGenMap.end()) return CGMI->second;
162 switch (N->getOpcode()) {
164 case AlphaISD::CALL: return SelectCALL(Op);
166 case ISD::FrameIndex: {
167 int FI = cast<FrameIndexSDNode>(N)->getIndex();
168 return CurDAG->SelectNodeTo(N, Alpha::LDA, MVT::i64,
169 CurDAG->getTargetFrameIndex(FI, MVT::i32),
172 case AlphaISD::GlobalBaseReg:
173 return getGlobalBaseReg();
175 case AlphaISD::DivCall: {
176 SDOperand Chain = CurDAG->getEntryNode();
177 Chain = CurDAG->getCopyToReg(Chain, Alpha::R24, Select(Op.getOperand(1)),
179 Chain = CurDAG->getCopyToReg(Chain, Alpha::R25, Select(Op.getOperand(2)),
181 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Select(Op.getOperand(0)),
183 Chain = CurDAG->getTargetNode(Alpha::JSRs, MVT::Other, MVT::Flag,
184 Chain, Chain.getValue(1));
185 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R27, MVT::i64,
187 return CurDAG->SelectNodeTo(N, Alpha::BIS, MVT::i64, Chain, Chain);
190 case ISD::READCYCLECOUNTER: {
191 SDOperand Chain = Select(N->getOperand(0)); //Select chain
192 return CurDAG->SelectNodeTo(N, Alpha::RPCC, MVT::i64, Chain);
196 SDOperand Chain = Select(N->getOperand(0)); // Token chain.
199 if (N->getNumOperands() == 2) {
200 SDOperand Val = Select(N->getOperand(1));
201 if (N->getOperand(1).getValueType() == MVT::i64) {
202 Chain = CurDAG->getCopyToReg(Chain, Alpha::R0, Val, InFlag);
203 InFlag = Chain.getValue(1);
204 } else if (N->getOperand(1).getValueType() == MVT::f64 ||
205 N->getOperand(1).getValueType() == MVT::f32) {
206 Chain = CurDAG->getCopyToReg(Chain, Alpha::F0, Val, InFlag);
207 InFlag = Chain.getValue(1);
210 Chain = CurDAG->getCopyToReg(Chain, Alpha::R26, getRASaveReg(), InFlag);
211 InFlag = Chain.getValue(1);
213 // Finally, select this to a ret instruction.
214 return CurDAG->SelectNodeTo(N, Alpha::RETDAG, MVT::Other, Chain, InFlag);
216 case ISD::Constant: {
217 uint64_t uval = cast<ConstantSDNode>(N)->getValue();
220 return CurDAG->getCopyFromReg(CurDAG->getEntryNode(), Alpha::R31, MVT::i64);
222 int64_t val = (int64_t)uval;
223 int32_t val32 = (int32_t)val;
224 if (val <= IMM_HIGH + IMM_HIGH * IMM_MULT &&
225 val >= IMM_LOW + IMM_LOW * IMM_MULT)
226 break; //(LDAH (LDA))
227 if ((uval >> 32) == 0 && //empty upper bits
228 val32 <= IMM_HIGH + IMM_HIGH * IMM_MULT)
229 // val32 >= IMM_LOW + IMM_LOW * IMM_MULT) //always true
230 break; //(zext (LDAH (LDA)))
231 //Else use the constant pool
232 MachineConstantPool *CP = BB->getParent()->getConstantPool();
234 ConstantUInt::get(Type::getPrimitiveType(Type::ULongTyID) , uval);
235 SDOperand Tmp, CPI = CurDAG->getTargetConstantPool(C, MVT::i64);
236 Tmp = CurDAG->getTargetNode(Alpha::LDAHr, MVT::i64, CPI, getGlobalBaseReg());
237 return CurDAG->SelectNodeTo(N, Alpha::LDQr, MVT::i64, MVT::Other,
238 CPI, Tmp, CurDAG->getEntryNode());
240 case ISD::TargetConstantFP: {
241 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
242 bool isDouble = N->getValueType(0) == MVT::f64;
243 MVT::ValueType T = isDouble ? MVT::f64 : MVT::f32;
244 if (CN->isExactlyValue(+0.0)) {
245 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYST : Alpha::CPYSS,
246 T, CurDAG->getRegister(Alpha::F31, T),
247 CurDAG->getRegister(Alpha::F31, T));
248 } else if ( CN->isExactlyValue(-0.0)) {
249 return CurDAG->SelectNodeTo(N, isDouble ? Alpha::CPYSNT : Alpha::CPYSNS,
250 T, CurDAG->getRegister(Alpha::F31, T),
251 CurDAG->getRegister(Alpha::F31, T));
259 if (MVT::isFloatingPoint(N->getOperand(0).Val->getValueType(0))) {
260 unsigned Opc = Alpha::WTF;
261 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
265 default: N->dump(); assert(0 && "Unknown FP comparison!");
266 case ISD::SETEQ: Opc = Alpha::CMPTEQ; break;
267 case ISD::SETLT: Opc = Alpha::CMPTLT; break;
268 case ISD::SETLE: Opc = Alpha::CMPTLE; break;
269 case ISD::SETGT: Opc = Alpha::CMPTLT; rev = true; break;
270 case ISD::SETGE: Opc = Alpha::CMPTLE; rev = true; break;
271 case ISD::SETNE: Opc = Alpha::CMPTEQ; isNE = true; break;
273 SDOperand tmp1 = Select(N->getOperand(0)),
274 tmp2 = Select(N->getOperand(1));
275 SDOperand cmp = CurDAG->getTargetNode(Opc, MVT::f64,
279 cmp = CurDAG->getTargetNode(Alpha::CMPTEQ, MVT::f64, cmp,
280 CurDAG->getRegister(Alpha::F31, MVT::f64));
283 if (AlphaLowering.hasITOF()) {
284 LD = CurDAG->getNode(AlphaISD::FTOIT_, MVT::i64, cmp);
287 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
288 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
289 SDOperand ST = CurDAG->getTargetNode(Alpha::STT, MVT::Other,
290 cmp, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
291 LD = CurDAG->getTargetNode(Alpha::LDQ, MVT::i64, FI,
292 CurDAG->getRegister(Alpha::R31, MVT::i64),
295 SDOperand FP = CurDAG->getTargetNode(Alpha::CMPULT, MVT::i64,
296 CurDAG->getRegister(Alpha::R31, MVT::i64),
303 if (MVT::isFloatingPoint(N->getValueType(0)) &&
304 (N->getOperand(0).getOpcode() != ISD::SETCC ||
305 !MVT::isFloatingPoint(N->getOperand(0).getOperand(1).getValueType()))) {
306 //This should be the condition not covered by the Patterns
307 //FIXME: Don't have SelectCode die, but rather return something testable
308 // so that things like this can be caught in fall though code
310 bool isDouble = N->getValueType(0) == MVT::f64;
312 cond = Select(N->getOperand(0)),
313 TV = Select(N->getOperand(1)),
314 FV = Select(N->getOperand(2));
316 if (AlphaLowering.hasITOF()) {
317 LD = CurDAG->getNode(AlphaISD::ITOFT_, MVT::f64, cond);
320 CurDAG->getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
321 SDOperand FI = CurDAG->getFrameIndex(FrameIdx, MVT::i64);
322 SDOperand ST = CurDAG->getTargetNode(Alpha::STQ, MVT::Other,
323 cond, FI, CurDAG->getRegister(Alpha::R31, MVT::i64));
324 LD = CurDAG->getTargetNode(Alpha::LDT, MVT::f64, FI,
325 CurDAG->getRegister(Alpha::R31, MVT::i64),
328 SDOperand FP = CurDAG->getTargetNode(isDouble?Alpha::FCMOVNET:Alpha::FCMOVNES,
329 MVT::f64, FV, TV, LD);
336 return SelectCode(Op);
339 SDOperand AlphaDAGToDAGISel::SelectCALL(SDOperand Op) {
340 //TODO: add flag stuff to prevent nondeturministic breakage!
343 SDOperand Chain = Select(N->getOperand(0));
344 SDOperand Addr = N->getOperand(1);
345 SDOperand InFlag; // Null incoming flag value.
347 std::vector<SDOperand> CallOperands;
348 std::vector<MVT::ValueType> TypeOperands;
351 for(int i = 2, e = N->getNumOperands(); i < e; ++i) {
352 TypeOperands.push_back(N->getOperand(i).getValueType());
353 CallOperands.push_back(Select(N->getOperand(i)));
355 int count = N->getNumOperands() - 2;
357 static const unsigned args_int[] = {Alpha::R16, Alpha::R17, Alpha::R18,
358 Alpha::R19, Alpha::R20, Alpha::R21};
359 static const unsigned args_float[] = {Alpha::F16, Alpha::F17, Alpha::F18,
360 Alpha::F19, Alpha::F20, Alpha::F21};
362 for (int i = 6; i < count; ++i) {
363 unsigned Opc = Alpha::WTF;
364 if (MVT::isInteger(TypeOperands[i])) {
366 } else if (TypeOperands[i] == MVT::f32) {
368 } else if (TypeOperands[i] == MVT::f64) {
371 assert(0 && "Unknown operand");
372 Chain = CurDAG->getTargetNode(Opc, MVT::Other, CallOperands[i],
373 getI64Imm((i - 6) * 8),
374 CurDAG->getCopyFromReg(Chain, Alpha::R30, MVT::i64),
377 for (int i = 0; i < std::min(6, count); ++i) {
378 if (MVT::isInteger(TypeOperands[i])) {
379 Chain = CurDAG->getCopyToReg(Chain, args_int[i], CallOperands[i], InFlag);
380 InFlag = Chain.getValue(1);
381 } else if (TypeOperands[i] == MVT::f32 || TypeOperands[i] == MVT::f64) {
382 Chain = CurDAG->getCopyToReg(Chain, args_float[i], CallOperands[i], InFlag);
383 InFlag = Chain.getValue(1);
385 assert(0 && "Unknown operand");
389 // Finally, once everything is in registers to pass to the call, emit the
391 if (Addr.getOpcode() == AlphaISD::GPRelLo) {
392 SDOperand GOT = getGlobalBaseReg();
393 Chain = CurDAG->getCopyToReg(Chain, Alpha::R29, GOT, InFlag);
394 InFlag = Chain.getValue(1);
395 Chain = CurDAG->getTargetNode(Alpha::BSR, MVT::Other, MVT::Flag,
396 Addr.getOperand(0), Chain, InFlag);
398 Chain = CurDAG->getCopyToReg(Chain, Alpha::R27, Select(Addr), InFlag);
399 InFlag = Chain.getValue(1);
400 Chain = CurDAG->getTargetNode(Alpha::JSR, MVT::Other, MVT::Flag,
403 InFlag = Chain.getValue(1);
405 std::vector<SDOperand> CallResults;
407 switch (N->getValueType(0)) {
408 default: assert(0 && "Unexpected ret value!");
409 case MVT::Other: break;
411 Chain = CurDAG->getCopyFromReg(Chain, Alpha::R0, MVT::i64, InFlag).getValue(1);
412 CallResults.push_back(Chain.getValue(0));
415 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f32, InFlag).getValue(1);
416 CallResults.push_back(Chain.getValue(0));
419 Chain = CurDAG->getCopyFromReg(Chain, Alpha::F0, MVT::f64, InFlag).getValue(1);
420 CallResults.push_back(Chain.getValue(0));
424 CallResults.push_back(Chain);
425 for (unsigned i = 0, e = CallResults.size(); i != e; ++i)
426 CodeGenMap[Op.getValue(i)] = CallResults[i];
427 return CallResults[Op.ResNo];
431 /// createAlphaISelDag - This pass converts a legalized DAG into a
432 /// Alpha-specific DAG, ready for instruction scheduling.
434 FunctionPass *llvm::createAlphaISelDag(TargetMachine &TM) {
435 return new AlphaDAGToDAGISel(TM);